syslog basic querry
alfred.hitch at gmail.com
Thu Dec 29 03:20:14 UTC 2005
external circuitry you indicated is diff. from power cicruitry.
Are you trying to refer to circuitry which will reset the flash and
processor separately, the way they want it ?
I wonder if this is the way most people design their watchdig
circuitry ? any comments ? is most standard way to go about this a
processor connected reset signals ? say ixp425 if it matters as a
reference benchmark ? or power reset ? or custom external circuitry
which caters to all peripherals wishes ?
On 12/28/05, Robin Farine <robin.farine at terminus.org> wrote:
> On Wednesday December 28 2005 11:17, alfred hitch wrote:
> > I had seen long time back for example a bug with flash that
> > unless you power cycle , if flash happened to be in some read
> > mode or something it will remain so, if there was just a
> > processor reset.
> > Does flash for example has a RST pin ? If yes, then it should
> > take care of this ?
> Some processor-flash combination fails to restart when the CPU's
> reset_out pin is tied to the flash reset pin because the CPU does
> not respect the flash reset timing. The CPU tries to read
> instructions from the flash too soon after it has released its
> reset_out signal and thus reads random data from the flash.
> With such a problematic combination, an external reset circuitry is
> required. Otherwise, a power cycle is the only way out.
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