[Buildroot] FFTW optimized for ARM and NEON FPU
guillaume william brs
guillaume.bressaix at gmail.com
Tue Feb 24 03:57:08 UTC 2015
I am working on a cortex-a9 (zynq SoC, mainly zc706)
I faced fairly slow computations of FFT using this library with the
default configuration (20MFlops).
I modified package/fftw.mk to optimize the library compilation as long
as an FPU is available,
NEON in this case: this increased the number of MFlops to 500-600.
guillaume william bres-saix
NIST - Time & Frequency div.
325 Broadway, Boulder, CO 80305.
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