RFC: pagesize generalization patch

Paul Mundt lethal at linux-sh.org
Wed Aug 23 02:30:09 UTC 2006


On Wed, Aug 23, 2006 at 03:25:19AM +0200, Peter S. Mazinger wrote:
> -/* SHMLBA uses it on most of the archs (not mips) */
> -#define __getpagesize getpagesize
> +/* SHMLBA is defined by using getpagesize for all archs less mips/hppa,
> + * make it use the internal __pagesize */
> +extern size_t __pagesize attribute_hidden;
> +#define getpagesize() __pagesize
>  
That's actually not entirely true, though looking at the shm.h users, it
seems that there are a few platforms that aren't matching up with the
kernel's definition. The general rule is that on platforms with a
virtually indexed dcache SHMLBA should be the maximum of the page size
or the cache size per-way, and then only for platforms with an aliasing
dcache.

Setting this to PAGE_SIZE * 4 is sensible enough, though most aliasing
VIPT caches typically only have cacheline aliasing problems when using
a 4k page size, so opencoding it as 16k (as MIPS does) should work for
most people that are afflicted with these types of caches.

At a quick glance, we're missing a sensible SHMLBA for ARM, SH, and
SPARC, which will also have these issues.

As far as cleaning this up once and for all, we could technically use
AT_DCACHEBSIZE and AT_L1D_CACHESHAPE (masking off the lower 4 bits for
the cache ways) to do run-time calculation for the mask if we're more
interested in keeping SHMLBA tightly packed. At least for all of the
architectures that need it, the > PAGE_SIZE case is limited to a few
processors that have this problem. Having it hardcoded for a size that
gaurantees alias avoidance is obviously the simple solution, though I'm
fine with just stuffing the details into the ELF auxvt and setting a
run-time mask as well.

Preferences before I start on a patch?


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