[git commit prelink 1/1] sh: fix memcpy saving/restoring FR12-FR15 registers
Carmelo Amoroso
carmelo.amoroso at st.com
Tue Dec 14 07:08:36 UTC 2010
commit: http://git.uclibc.org/uClibc/commit/?id=640220faf25659eb4c15b78cf8869251dbadbd16
branch: http://git.uclibc.org/uClibc/commit/?id=refs/heads/prelink
This patch fixes a bug in the memcpy that doesn't save/restore
the FR12-FR15 registers (callee save registers in ST40 ABI) while
copying many cache lines with FPU in single paired precision mode
and by using all FPU registers (DR and XD).
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro at st.com>
Reviewed-by: Carmelo Amoroso <carmelo.amoroso at st.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso at st.com>
---
libc/string/sh/sh4/memcpy.S | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/libc/string/sh/sh4/memcpy.S b/libc/string/sh/sh4/memcpy.S
index 5be770a..6a229a0 100644
--- a/libc/string/sh/sh4/memcpy.S
+++ b/libc/string/sh/sh4/memcpy.S
@@ -497,6 +497,12 @@ ENTRY(memcpy)
mov r5, r6
add #-0x80, r6 ! prefetch head
+ ! store FPU (in single precision mode, do not check R15 align).
+ fmov fr12, @-r15
+ fmov fr13, @-r15
+ fmov fr14, @-r15
+ fmov fr15, @-r15
+
FPU_SET_PAIRED_PREC
mov #4, r0
@@ -553,16 +559,22 @@ ENTRY(memcpy)
bt/s 67b
pref @r6
+ RESTORE_FPSCR
+
+ ! Restore FPU callee save registers
+ fmov @r15+, fr15
+ fmov @r15+, fr14
+ fmov @r15+, fr13
+ fmov @r15+, fr12
+
! Other cache lines could be copied: so use the FPU in single paired
! precision without prefetching. No check for alignment is necessary.
mov #1, r0
cmp/ge r0, r3
- bt/s 4f
+ bt/s 3f
add #0x60, r5
- RESTORE_FPSCR
-
bra 5f
nop
--
1.7.2.2
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