[git commit 0_9_30] use newer spiffy asm constraints to get better code generation
Mike Frysinger
vapier at gentoo.org
Sat Oct 10 16:44:02 UTC 2009
commit: http://git.uclibc.org/uClibc/commit/?id=d879639aaa53549cdb6d01868cc72fca2a3047f6
branch: http://git.uclibc.org/uClibc/commit/?id=refs/heads/0_9_30
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop at gmail.com>
---
libc/sysdeps/linux/bfin/syscall.c | 26 +++++++++-----------------
1 files changed, 9 insertions(+), 17 deletions(-)
diff --git a/libc/sysdeps/linux/bfin/syscall.c b/libc/sysdeps/linux/bfin/syscall.c
index 1db8738..d68eb6e 100644
--- a/libc/sysdeps/linux/bfin/syscall.c
+++ b/libc/sysdeps/linux/bfin/syscall.c
@@ -29,24 +29,16 @@ long syscall(long sysnum, long a, long b, long c, long d, long e, long f)
int _r0 = 0;
__asm__ __volatile__ (
- "R5 = %7;"
- "R4 = %6;"
- "R3 = %5;"
- "R2 = %4;"
- "R1 = %3;"
- "R0 = %2;"
- "P0 = %1;"
"excpt 0;"
- "%0 = R0;"
- : "=r" (_r0)
- : "rm" (sysnum),
- "rm" (a),
- "rm" (b),
- "rm" (c),
- "rm" (d),
- "rm" (e),
- "rm" (f)
- : "memory","CC","R0","R1","R2","R3","R4","R5","P0");
+ : "=q0" (_r0)
+ : "qA" (sysnum),
+ "q0" (a),
+ "q1" (b),
+ "q2" (c),
+ "q3" (d),
+ "q4" (e),
+ "q5" (f)
+ : "memory", "CC");
if (_r0 >= (unsigned long) -4095) {
(*__errno_location()) = (-_r0);
--
1.6.3.3
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