The following changes since commit e79f9914b49eecf523ce469cfe146cde99f1097d: squid: bump to version 3.1.9 (2010-11-08 13:40:35 -0300) are available in the git repository at: git://repo.or.cz/buildroot-gz.git master Gustavo Zacarias (3): libmad: fix MIPS gcc 4.4+ "h" asm constraint removal ltrace: build fix toolchain: LEON SPARC only works with gcc-4.4.x Konrad Eisele (3): config: Add sparc-leon processors. Readd V7, 8 part of BR2_SPARC_TYPE. Add BR2_GCC_TARGET_CPU. Remove depricated v9 Sparc type. toolchain: Add support for --with-cpu gcc-patch: Add patch for 4.4.5 to support Sparc-leon processors CHANGES | 2 +- package/ltrace/ltrace-0.5.3-ptrace_h.patch | 12 + .../libmad-0.15.1b-mips-h-constraint-removal.patch | 72 ++++++ target/Config.in.arch | 32 ++- toolchain/gcc/4.4.5/950-sparc-leon.patch | 239 ++++++++++++++++++++ toolchain/gcc/Makefile.in | 3 + toolchain/gcc/gcc-uclibc-4.x.mk | 8 +- 7 files changed, 351 insertions(+), 17 deletions(-) create mode 100644 package/ltrace/ltrace-0.5.3-ptrace_h.patch create mode 100644 package/multimedia/libmad/libmad-0.15.1b-mips-h-constraint-removal.patch create mode 100644 toolchain/gcc/4.4.5/950-sparc-leon.patch diff --git a/CHANGES b/CHANGES index 889f787..f79dbbc 100644 --- a/CHANGES +++ b/CHANGES @@ -6,7 +6,7 @@ misc fixes + nconfig and savedefconfig targets. Toolchain: ARM cortex A9 support, experimental crosstool-ng - backend, GCC 4.5.x. + backend, GCC 4.5.x, LEON SPARC support. Fs: Squashfs 4.1 with lzo support diff --git a/package/ltrace/ltrace-0.5.3-ptrace_h.patch b/package/ltrace/ltrace-0.5.3-ptrace_h.patch new file mode 100644 index 0000000..88663f8 --- /dev/null +++ b/package/ltrace/ltrace-0.5.3-ptrace_h.patch @@ -0,0 +1,12 @@ +diff -Nura ltrace-0.5.3.orig/sysdeps/linux-gnu/events.c ltrace-0.5.3/sysdeps/linux-gnu/events.c +--- ltrace-0.5.3.orig/sysdeps/linux-gnu/events.c 2009-07-25 12:13:02.000000000 -0300 ++++ ltrace-0.5.3/sysdeps/linux-gnu/events.c 2010-11-08 15:40:58.236834364 -0300 +@@ -7,7 +7,7 @@ + #include + #include + #include +-#include ++#include + + #include "common.h" + diff --git a/package/multimedia/libmad/libmad-0.15.1b-mips-h-constraint-removal.patch b/package/multimedia/libmad/libmad-0.15.1b-mips-h-constraint-removal.patch new file mode 100644 index 0000000..0958587 --- /dev/null +++ b/package/multimedia/libmad/libmad-0.15.1b-mips-h-constraint-removal.patch @@ -0,0 +1,72 @@ +http://patchwork.openembedded.org/patch/921/ + +diff -ur libmad-0.15.1b-orig/fixed.h libmad-0.15.1b/fixed.h +--- libmad-0.15.1b-orig/fixed.h 2004-02-17 12:32:03.000000000 +1030 ++++ libmad-0.15.1b/fixed.h 2009-08-05 10:46:30.000000000 +0930 +@@ -299,6 +299,23 @@ + + # elif defined(FPM_MIPS) + ++/* Test for gcc >= maj.min, as per __GNUC_PREREQ in glibc */ ++#if defined (__GNUC__) && defined (__GNUC_MINOR__) ++#define __GNUC_PREREQ(maj, min) \ ++ ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) ++#else ++#define __GNUC_PREREQ(maj, min) 0 ++#endif ++ ++#if __GNUC_PREREQ(4,4) ++ typedef unsigned int u64_di_t __attribute__ ((mode (DI))); ++# define MAD_F_MLX(hi, lo, x, y) \ ++ do { \ ++ u64_di_t __ll = (u64_di_t) (x) * (y); \ ++ hi = __ll >> 32; \ ++ lo = __ll; \ ++ } while (0) ++#else + /* + * This MIPS version is fast and accurate; the disposition of the least + * significant bit depends on OPT_ACCURACY via mad_f_scale64(). +@@ -328,6 +345,7 @@ + : "%r" ((x) >> 12), "r" ((y) >> 16)) + # define MAD_F_MLZ(hi, lo) ((mad_fixed_t) (lo)) + # endif ++#endif /* __GNU_PREREQ(4,4) */ + + # if defined(OPT_SPEED) + # define mad_f_scale64(hi, lo) \ +diff -ur libmad-0.15.1b-orig/mad.h libmad-0.15.1b/mad.h +--- libmad-0.15.1b-orig/mad.h 2004-02-17 13:25:44.000000000 +1030 ++++ libmad-0.15.1b/mad.h 2009-08-05 10:42:40.000000000 +0930 +@@ -344,6 +344,23 @@ + + # elif defined(FPM_MIPS) + ++/* Test for gcc >= maj.min, as per __GNUC_PREREQ in glibc */ ++#if defined (__GNUC__) && defined (__GNUC_MINOR__) ++#define __GNUC_PREREQ(maj, min) \ ++ ((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min)) ++#else ++#define __GNUC_PREREQ(maj, min) 0 ++#endif ++ ++#if __GNUC_PREREQ(4,4) ++ typedef unsigned int u64_di_t __attribute__ ((mode (DI))); ++# define MAD_F_MLX(hi, lo, x, y) \ ++ do { \ ++ u64_di_t __ll = (u64_di_t) (x) * (y); \ ++ hi = __ll >> 32; \ ++ lo = __ll; \ ++ } while (0) ++#else + /* + * This MIPS version is fast and accurate; the disposition of the least + * significant bit depends on OPT_ACCURACY via mad_f_scale64(). +@@ -373,6 +390,7 @@ + : "%r" ((x) >> 12), "r" ((y) >> 16)) + # define MAD_F_MLZ(hi, lo) ((mad_fixed_t) (lo)) + # endif ++#endif /* __GNU_PREREQ(4,4) */ + + # if defined(OPT_SPEED) + # define mad_f_scale64(hi, lo) \ diff --git a/target/Config.in.arch b/target/Config.in.arch index e08ce5b..6236439 100644 --- a/target/Config.in.arch +++ b/target/Config.in.arch @@ -304,6 +304,15 @@ config BR2_sparc_cypress bool "cypress" config BR2_sparc_v8 bool "v8" +comment "LEON SPARC needs gcc = 4.4.x" +config BR2_sparc_sparchfleon + bool "hfleon" +config BR2_sparc_sparchfleonv8 + bool "hfleonv8" +config BR2_sparc_sparcsfleon + bool "sfleon" +config BR2_sparc_sparcsfleonv8 + bool "sfleonv8" config BR2_sparc_supersparc bool "supersparc" config BR2_sparc_sparclite @@ -320,20 +329,13 @@ config BR2_sparc_sparclet bool "sparclet" config BR2_sparc_tsc701 bool "tsc701" -config BR2_sparc_v9 - bool "v9" -config BR2_sparc_v9a - bool "v9a" -config BR2_sparc_v9b - bool "v9b" -config BR2_sparc_ultrasparc - bool "ultrasparc" -config BR2_sparc_ultrasparc3 - bool "ultrasparc3" -config BR2_sparc_niagara - bool "niagara" endchoice +config BR2_SPARC_TYPE + string + default V7 if BR2_sparc_v7 || BR2_sparc_cypress || BR2_sparc_sparclite || BR2_sparc_f930 || BR2_sparc_f934 || BR2_sparc_sparclite86x || BR2_sparc_sparclet || BR2_sparc_tsc701 || BR2_sparc_sparchfleon || BR2_sparc_sparcsfleon + default V8 if BR2_sparc_v8 || BR2_sparc_supersparc || BR2_sparc_hypersparc || BR2_sparc_sparchfleonv8 || BR2_sparc_sparcsfleonv8 + choice prompt "Target Architecture Variant" depends on BR2_xtensa @@ -666,3 +668,9 @@ config BR2_GCC_TARGET_ABI default ibmlongdouble if BR2_powerpc && BR2_PPC_ABI_ibmlongdouble default ieeelongdouble if BR2_powerpc && BR2_PPC_ABI_ieeelongdouble +config BR2_GCC_TARGET_CPU + string + default sparchfleon if BR2_sparc_sparchfleon + default sparchfleonv8 if BR2_sparc_sparchfleonv8 + default sparcsfleon if BR2_sparc_sparcsfleon + default sparcsfleonv8 if BR2_sparc_sparcsfleonv8 diff --git a/toolchain/gcc/4.4.5/950-sparc-leon.patch b/toolchain/gcc/4.4.5/950-sparc-leon.patch new file mode 100644 index 0000000..ad18607 --- /dev/null +++ b/toolchain/gcc/4.4.5/950-sparc-leon.patch @@ -0,0 +1,239 @@ +diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/leon.md gcc-4.4.2/gcc/config/sparc/leon.md +--- gcc-4.4.2.ori/gcc/config/sparc/leon.md 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.2/gcc/config/sparc/leon.md 2010-10-19 11:56:58.000000000 +0200 +@@ -0,0 +1,56 @@ ++;; Scheduling description for Leon. ++;; Copyright (C) 2010 Free Software Foundation, Inc. ++;; ++;; This file is part of GCC. ++;; ++;; GCC is free software; you can redistribute it and/or modify ++;; it under the terms of the GNU General Public License as published by ++;; the Free Software Foundation; either version 3, or (at your option) ++;; any later version. ++;; ++;; GCC is distributed in the hope that it will be useful, ++;; but WITHOUT ANY WARRANTY; without even the implied warranty of ++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++;; GNU General Public License for more details. ++;; ++;; You should have received a copy of the GNU General Public License ++;; along with GCC; see the file COPYING3. If not see ++;; . ++ ++ ++(define_automaton "leon") ++ ++(define_cpu_unit "leon_memory, leon_fpalu" "leon") ++(define_cpu_unit "leon_fpmds" "leon") ++(define_cpu_unit "write_buf" "leon") ++ ++(define_insn_reservation "leon_load" 1 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "load,sload,fpload")) ++ "leon_memory") ++ ++(define_insn_reservation "leon_store" 1 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "store,fpstore")) ++ "leon_memory+write_buf") ++ ++(define_insn_reservation "leon_fp_alu" 1 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "fp,fpmove")) ++ "leon_fpalu, nothing") ++ ++(define_insn_reservation "leon_fp_mult" 1 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "fpmul")) ++ "leon_fpmds, nothing") ++ ++(define_insn_reservation "leon_fp_div" 16 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "fpdivs,fpdivd")) ++ "leon_fpmds, nothing*15") ++ ++(define_insn_reservation "leon_fp_sqrt" 23 ++ (and (eq_attr "cpu" "leon") ++ (eq_attr "type" "fpsqrts,fpsqrtd")) ++ "leon_fpmds, nothing*21") ++ +diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.c gcc-4.4.2/gcc/config/sparc/sparc.c +--- gcc-4.4.2.ori/gcc/config/sparc/sparc.c 2010-10-19 11:55:17.000000000 +0200 ++++ gcc-4.4.2/gcc/config/sparc/sparc.c 2010-10-19 11:56:58.000000000 +0200 +@@ -246,6 +246,30 @@ + 0, /* shift penalty */ + }; + ++static const ++struct processor_costs leon_costs = { ++ COSTS_N_INSNS (1), /* int load */ ++ COSTS_N_INSNS (1), /* int signed load */ ++ COSTS_N_INSNS (1), /* int zeroed load */ ++ COSTS_N_INSNS (1), /* float load */ ++ COSTS_N_INSNS (1), /* fmov, fneg, fabs */ ++ COSTS_N_INSNS (1), /* fadd, fsub */ ++ COSTS_N_INSNS (1), /* fcmp */ ++ COSTS_N_INSNS (1), /* fmov, fmovr */ ++ COSTS_N_INSNS (1), /* fmul */ ++ COSTS_N_INSNS (15), /* fdivs */ ++ COSTS_N_INSNS (15), /* fdivd */ ++ COSTS_N_INSNS (23), /* fsqrts */ ++ COSTS_N_INSNS (23), /* fsqrtd */ ++ COSTS_N_INSNS (5), /* imul */ ++ COSTS_N_INSNS (5), /* imulX */ ++ 0, /* imul bit factor */ ++ COSTS_N_INSNS (5), /* idiv */ ++ COSTS_N_INSNS (5), /* idivX */ ++ COSTS_N_INSNS (1), /* movcc/movr */ ++ 0, /* shift penalty */ ++}; ++ + const struct processor_costs *sparc_costs = &cypress_costs; + + #ifdef HAVE_AS_RELAX_OPTION +@@ -651,6 +675,10 @@ + { TARGET_CPU_ultrasparc3, "ultrasparc3" }, + { TARGET_CPU_niagara, "niagara" }, + { TARGET_CPU_niagara2, "niagara2" }, ++ { TARGET_CPU_sparchfleon, "sparchfleon" }, ++ { TARGET_CPU_sparchfleonv8, "sparchfleonv8" }, ++ { TARGET_CPU_sparcsfleon, "sparcsfleon" }, ++ { TARGET_CPU_sparcsfleonv8, "sparcsfleonv8" }, + { 0, 0 } + }; + const struct cpu_default *def; +@@ -689,6 +717,11 @@ + /* UltraSPARC T1 */ + { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, + { "niagara2", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9}, ++ /* SPARC-LEON */ ++ { "sparchfleon", PROCESSOR_LEON, MASK_ISA, MASK_FPU }, ++ { "sparchfleonv8", PROCESSOR_LEON, MASK_ISA & ~(MASK_V8), MASK_V8|MASK_FPU }, ++ { "sparcsfleon", PROCESSOR_LEON, MASK_ISA | MASK_FPU, 0 }, ++ { "sparcsfleonv8", PROCESSOR_LEON, (MASK_ISA | MASK_FPU) & ~(MASK_V8), MASK_V8 }, + { 0, 0, 0, 0 } + }; + const struct cpu_table *cpu; +@@ -855,6 +888,9 @@ + case PROCESSOR_NIAGARA2: + sparc_costs = &niagara2_costs; + break; ++ case PROCESSOR_LEON: ++ sparc_costs = &leon_costs; ++ break; + }; + + #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 +diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.h gcc-4.4.2/gcc/config/sparc/sparc.h +--- gcc-4.4.2.ori/gcc/config/sparc/sparc.h 2010-10-19 11:55:17.000000000 +0200 ++++ gcc-4.4.2/gcc/config/sparc/sparc.h 2010-10-19 11:56:58.000000000 +0200 +@@ -243,6 +243,10 @@ + #define TARGET_CPU_ultrasparc3 9 + #define TARGET_CPU_niagara 10 + #define TARGET_CPU_niagara2 11 ++#define TARGET_CPU_sparchfleon 12 ++#define TARGET_CPU_sparchfleonv8 13 ++#define TARGET_CPU_sparcsfleon 14 ++#define TARGET_CPU_sparcsfleonv8 15 + + #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ +@@ -299,6 +303,26 @@ + #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" + #endif + ++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleon ++#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon" ++#define ASM_CPU32_DEFAULT_SPEC "" ++#endif ++ ++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleon ++#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D_SOFT_FLOAT" ++#define ASM_CPU32_DEFAULT_SPEC "" ++#endif ++ ++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparchfleonv8 ++#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ " ++#define ASM_CPU32_DEFAULT_SPEC "" ++#endif ++ ++#if TARGET_CPU_DEFAULT == TARGET_CPU_sparcsfleonv8 ++#define CPP_CPU32_DEFAULT_SPEC "-Dsparcleon -D__sparc_v8__ -D_SOFT_FLOAT" ++#define ASM_CPU32_DEFAULT_SPEC "" ++#endif ++ + #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc + #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" + #define ASM_CPU32_DEFAULT_SPEC "" +@@ -369,6 +393,10 @@ + %{mcpu=ultrasparc3:-D__sparc_v9__} \ + %{mcpu=niagara:-D__sparc_v9__} \ + %{mcpu=niagara2:-D__sparc_v9__} \ ++%{mcpu=sparchfleon:-Dsparcleon} \ ++%{mcpu=sparchfleonv8:-Dsparcleon -D__sparc_v8__} \ ++%{mcpu=sparcsfleon:-Dsparcleon -D_SOFT_FLOAT} \ ++%{mcpu=sparcsfleonv8:-Dsparcleon -D_SOFT_FLOAT -D__sparc_v8__} \ + %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ + " + #define CPP_ARCH32_SPEC "" +@@ -533,6 +561,7 @@ + PROCESSOR_V7, + PROCESSOR_CYPRESS, + PROCESSOR_V8, ++ PROCESSOR_LEON, + PROCESSOR_SUPERSPARC, + PROCESSOR_SPARCLITE, + PROCESSOR_F930, +diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/sparc.md gcc-4.4.2/gcc/config/sparc/sparc.md +--- gcc-4.4.2.ori/gcc/config/sparc/sparc.md 2010-10-19 11:55:17.000000000 +0200 ++++ gcc-4.4.2/gcc/config/sparc/sparc.md 2010-10-19 11:56:58.000000000 +0200 +@@ -89,6 +89,7 @@ + "v7, + cypress, + v8, ++ leon, + supersparc, + sparclite,f930,f934, + hypersparc,sparclite86x, +@@ -320,6 +321,7 @@ + (include "ultra3.md") + (include "niagara.md") + (include "niagara2.md") ++(include "leon.md") + + + ;; Operand and operator predicates and constraints +diff -Naurb gcc-4.4.2.ori/gcc/config/sparc/t-leon gcc-4.4.2/gcc/config/sparc/t-leon +--- gcc-4.4.2.ori/gcc/config/sparc/t-leon 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-4.4.2/gcc/config/sparc/t-leon 2010-10-19 11:56:58.000000000 +0200 +@@ -0,0 +1,16 @@ ++# configuration file for LEON cpu ++ ++LIB1ASMSRC = sparc/lb1spc.asm ++LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 ++ ++# We want fine grained libraries, so use the new code to build the ++# floating point emulation libraries. ++FPBIT = fp-bit.c ++DPBIT = dp-bit.c ++ ++dp-bit.c: $(srcdir)/config/fp-bit.c ++ cat $(srcdir)/config/fp-bit.c > dp-bit.c ++ ++fp-bit.c: $(srcdir)/config/fp-bit.c ++ echo '#define FLOAT' > fp-bit.c ++ cat $(srcdir)/config/fp-bit.c >> fp-bit.c +diff -Naurb gcc-4.4.2.ori/gcc/config.gcc gcc-4.4.2/gcc/config.gcc +--- gcc-4.4.2.ori/gcc/config.gcc 2010-10-19 11:55:17.000000000 +0200 ++++ gcc-4.4.2/gcc/config.gcc 2010-10-19 11:56:11.000000000 +0200 +@@ -2978,6 +2978,9 @@ + | v9 | ultrasparc | ultrasparc3 | niagara | niagara2) + # OK + ;; ++ sparchfleon | sparcsfleon | sparchfleonv8 | sparcsfleonv8 | leon) ++ tmake_file="${tmake_file} sparc/t-leon" ++ ;; + *) + echo "Unknown cpu used in --with-$which=$val" 1>&2 + exit 1 diff --git a/toolchain/gcc/Makefile.in b/toolchain/gcc/Makefile.in index b6ebca9..2e55ed0 100644 --- a/toolchain/gcc/Makefile.in +++ b/toolchain/gcc/Makefile.in @@ -37,6 +37,9 @@ endif ifneq ($(call qstrip,$(BR2_GCC_TARGET_ABI)),) GCC_WITH_ABI:=--with-abi=$(BR2_GCC_TARGET_ABI) endif +ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),) +GCC_WITH_CPU:=--with-cpu=$(BR2_GCC_TARGET_CPU) +endif # AVR32 GCC configuration ifeq ($(BR2_avr32),y) diff --git a/toolchain/gcc/gcc-uclibc-4.x.mk b/toolchain/gcc/gcc-uclibc-4.x.mk index 684dca8..af085f7 100644 --- a/toolchain/gcc/gcc-uclibc-4.x.mk +++ b/toolchain/gcc/gcc-uclibc-4.x.mk @@ -229,7 +229,7 @@ $(GCC_BUILD_DIR1)/.configured: $(GCC_DIR)/.patched $(THREADS) \ $(GCC_DECIMAL_FLOAT) \ $(SOFT_FLOAT_CONFIG_OPTION) \ - $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) \ + $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) $(GCC_WITH_CPU) \ $(EXTRA_GCC_CONFIG_OPTIONS) \ $(EXTRA_GCC1_CONFIG_OPTIONS) \ $(QUIET) \ @@ -306,7 +306,7 @@ $(GCC_BUILD_DIR2)/.configured: $(GCC_DIR)/.patched $(MULTILIB) \ $(GCC_DECIMAL_FLOAT) \ $(SOFT_FLOAT_CONFIG_OPTION) \ - $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) \ + $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) $(GCC_WITH_CPU) \ $(EXTRA_GCC_CONFIG_OPTIONS) \ $(EXTRA_GCC2_CONFIG_OPTIONS) \ $(QUIET) \ @@ -382,7 +382,7 @@ $(GCC_BUILD_DIR3)/.configured: $(GCC_SRC_DIR)/.patched $(GCC_STAGING_PREREQ) $(THREADS) \ $(GCC_DECIMAL_FLOAT) \ $(SOFT_FLOAT_CONFIG_OPTION) \ - $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) \ + $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) $(GCC_WITH_CPU) \ $(DISABLE_LARGEFILE) \ $(EXTRA_GCC_CONFIG_OPTIONS) \ $(EXTRA_GCC2_CONFIG_OPTIONS) \ @@ -516,7 +516,7 @@ $(GCC_BUILD_DIR4)/.configured: $(GCC_BUILD_DIR4)/.prepared $(THREADS) \ $(GCC_DECIMAL_FLOAT) \ $(SOFT_FLOAT_CONFIG_OPTION) \ - $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) \ + $(GCC_WITH_ABI) $(GCC_WITH_ARCH) $(GCC_WITH_TUNE) $(GCC_WITH_CPU) \ $(DISABLE_LARGEFILE) \ $(EXTRA_GCC_CONFIG_OPTIONS) \ $(EXTRA_TARGET_GCC_CONFIG_OPTIONS) \