[Buildroot] [PATCH v2] configs/digilent_genesys_zu_defconfig: add Digilent Genesys ZU board (ZynqMP SoC)

Alvaro Gamez Machado alvaro.gamez at hazent.com
Thu Aug 5 08:47:54 UTC 2021


This adds support the Digilent Genesys ZU development board.

Signed-off-by: Alvaro Gamez Machado <alvaro.gamez at hazent.com>

---
v1 -> v2:

* Clarify boot process of zynqmp on README
* Note upstream source of YYLOC patch for kernel
* Minimize psu_init_gpl.c using uboot's tool
* Explain on its file how to generate a FIT image containing an FPGA bitfile
* Explain existance of uboot environment file and add example of how to define
  a generic UIO device

Signed-off-by: Alvaro Gamez Machado <alvaro.gamez at hazent.com>
---
 ...ve-redundant-YYLOC-global-declaratio.patch |    54 +
 .../0001-uboot-add-genesys-zu.patch           |    10 +
 board/digilent/genesys-zu/GenesysZU.dts       |  1655 +
 board/digilent/genesys-zu/README.txt          |   110 +
 board/digilent/genesys-zu/genimage.cfg        |    28 +
 board/digilent/genesys-zu/image.its           |    59 +
 board/digilent/genesys-zu/kernel_defconfig    |   414 +
 board/digilent/genesys-zu/pm_cfg_obj.c        |   630 +
 board/digilent/genesys-zu/post-image.sh       |    10 +
 board/digilent/genesys-zu/psu_init_gpl.c      |   985 +
 board/digilent/genesys-zu/psu_init_gpl.h      | 37545 ++++++++++++++++
 board/digilent/genesys-zu/uboot-env.txt       |    83 +
 board/digilent/genesys-zu/uboot_defconfig     |   106 +
 configs/digilent_genesys_zu_defconfig         |    49 +
 14 files changed, 41738 insertions(+)
 create mode 100644 board/digilent/genesys-zu/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch
 create mode 100644 board/digilent/genesys-zu/0001-uboot-add-genesys-zu.patch
 create mode 100644 board/digilent/genesys-zu/GenesysZU.dts
 create mode 100644 board/digilent/genesys-zu/README.txt
 create mode 100644 board/digilent/genesys-zu/genimage.cfg
 create mode 100644 board/digilent/genesys-zu/image.its
 create mode 100644 board/digilent/genesys-zu/kernel_defconfig
 create mode 100644 board/digilent/genesys-zu/pm_cfg_obj.c
 create mode 100755 board/digilent/genesys-zu/post-image.sh
 create mode 100644 board/digilent/genesys-zu/psu_init_gpl.c
 create mode 100644 board/digilent/genesys-zu/psu_init_gpl.h
 create mode 100644 board/digilent/genesys-zu/uboot-env.txt
 create mode 100644 board/digilent/genesys-zu/uboot_defconfig
 create mode 100644 configs/digilent_genesys_zu_defconfig

diff --git a/board/digilent/genesys-zu/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch b/board/digilent/genesys-zu/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch
new file mode 100644
index 0000000000..8db0ca7953
--- /dev/null
+++ b/board/digilent/genesys-zu/0001-scripts-dtc-Remove-redundant-YYLOC-global-declaratio.patch
@@ -0,0 +1,54 @@
+From e33a814e772cdc36436c8c188d8c42d019fda639 Mon Sep 17 00:00:00 2001
+From: Dirk Mueller <dmueller at suse.com>
+Date: Tue, 14 Jan 2020 18:53:41 +0100
+Subject: [PATCH] scripts/dtc: Remove redundant YYLOC global declaration
+
+gcc 10 will default to -fno-common, which causes this error at link
+time:
+
+  (.text+0x0): multiple definition of `yylloc'; dtc-lexer.lex.o (symbol from plugin):(.text+0x0): first defined here
+
+This is because both dtc-lexer as well as dtc-parser define the same
+global symbol yyloc. Before with -fcommon those were merged into one
+defintion. The proper solution would be to to mark this as "extern",
+however that leads to:
+
+  dtc-lexer.l:26:16: error: redundant redeclaration of 'yylloc' [-Werror=redundant-decls]
+   26 | extern YYLTYPE yylloc;
+      |                ^~~~~~
+In file included from dtc-lexer.l:24:
+dtc-parser.tab.h:127:16: note: previous declaration of 'yylloc' was here
+  127 | extern YYLTYPE yylloc;
+      |                ^~~~~~
+cc1: all warnings being treated as errors
+
+which means the declaration is completely redundant and can just be
+dropped.
+
+Signed-off-by: Dirk Mueller <dmueller at suse.com>
+Signed-off-by: David Gibson <david at gibson.dropbear.id.au>
+[robh: cherry-pick from upstream]
+Cc: stable at vger.kernel.org
+Signed-off-by: Rob Herring <robh at kernel.org>
+---
+
+Patch in linux kernel upstream, commit e33a814e772cdc36436c8c188d8c42d019fda639
+
+ scripts/dtc/dtc-lexer.l | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
+index 5c6c3fd557d7..b3b7270300de 100644
+--- a/scripts/dtc/dtc-lexer.l
++++ b/scripts/dtc/dtc-lexer.l
+@@ -23,7 +23,6 @@ LINECOMMENT	"//".*\n
+ #include "srcpos.h"
+ #include "dtc-parser.tab.h"
+ 
+-YYLTYPE yylloc;
+ extern bool treesource_error;
+ 
+ /* CAUTION: this will stop working if we ever use yyless() or yyunput() */
+-- 
+2.32.0
+
diff --git a/board/digilent/genesys-zu/0001-uboot-add-genesys-zu.patch b/board/digilent/genesys-zu/0001-uboot-add-genesys-zu.patch
new file mode 100644
index 0000000000..78be6aa176
--- /dev/null
+++ b/board/digilent/genesys-zu/0001-uboot-add-genesys-zu.patch
@@ -0,0 +1,10 @@
+--- uboot-2021.04.orig/arch/arm/dts/Makefile	2021-07-05 13:58:02.688479608 +0200
++++ uboot-2021.04/arch/arm/dts/Makefile	2021-07-05 13:58:35.040572907 +0200
+@@ -291,6 +291,7 @@
+ dtb-$(CONFIG_ARCH_ZYNQMP) += \
+ 	avnet-ultra96-rev1.dtb			\
+ 	avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb	\
++	GenesysZU.dtb				\
+ 	zynqmp-a2197-revA.dtb			\
+ 	zynqmp-e-a2197-00-revA.dtb		\
+ 	zynqmp-g-a2197-00-revA.dtb		\
diff --git a/board/digilent/genesys-zu/GenesysZU.dts b/board/digilent/genesys-zu/GenesysZU.dts
new file mode 100644
index 0000000000..ddeba4b715
--- /dev/null
+++ b/board/digilent/genesys-zu/GenesysZU.dts
@@ -0,0 +1,1655 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = "/amba/ethernet at ff0b0000";
+		i2c0 = "/amba_pl at 0/i2c at 8000c000";
+		i2c1 = "/amba/i2c at ff020000";
+		i2c2 = "/amba/i2c at ff030000";
+		serial0 = "/amba/serial at ff000000";
+		serial1 = "/amba/serial at ff010000";
+		spi0 = "/amba/spi at ff0f0000";
+		spi1 = "/amba/spi at ff040000";
+	};
+
+	amba: amba {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "simple-bus";
+		ranges;
+		u-boot,dm-pre-reloc;
+
+		sata: ahci at fd0c0000 {
+			#stream-id-cells = <0x04>;
+			clocks = <0x03 0x16>;
+			compatible = "ceva,ahci-1v84";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x85 0x04>;
+			power-domains = <0x0c 0x1c>;
+			reg = <0x00 0xfd0c0000 0x00 0x2000>;
+			status = "disabled";
+		};
+
+		ams at ffa50000 {
+			#address-cells = <0x02>;
+			#io-channel-cells = <0x01>;
+			#size-cells = <0x02>;
+			clocks = <0x03 0x46>;
+			compatible = "xlnx,zynqmp-ams";
+			interrupt-names = "ams-irq";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x38 0x04>;
+			ranges;
+			reg = <0x00 0xffa50000 0x00 0x800>;
+			reg-names = "ams-base";
+			status = "okay";
+
+			ams_pl at ffa50c00 {
+				compatible = "xlnx,zynqmp-ams-pl";
+				reg = <0x00 0xffa50c00 0x00 0x400>;
+				status = "okay";
+
+				xlnx,ext-channels {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+
+					channel at 0 {
+						reg = <0x00>;
+					};
+
+					channel at 5 {
+						reg = <0x05>;
+					};
+
+					channel at 6 {
+						reg = <0x06>;
+					};
+
+					channel at 7 {
+						reg = <0x07>;
+					};
+
+					channel at 8 {
+						reg = <0x08>;
+					};
+				};
+			};
+
+			ams_ps at ffa50800 {
+				compatible = "xlnx,zynqmp-ams-ps";
+				reg = <0x00 0xffa50800 0x00 0x400>;
+				status = "okay";
+			};
+		};
+
+		can at ff060000 {
+			clock-names = "can_clk", "pclk";
+			clocks = <0x03 0x3f 0x03 0x1f>;
+			compatible = "xlnx,zynq-can-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x17 0x04>;
+			power-domains = <0x0c 0x2f>;
+			reg = <0x00 0xff060000 0x00 0x1000>;
+			rx-fifo-depth = <0x40>;
+			status = "disabled";
+			tx-fifo-depth = <0x40>;
+		};
+
+		can at ff070000 {
+			clock-names = "can_clk", "pclk";
+			clocks = <0x03 0x40 0x03 0x1f>;
+			compatible = "xlnx,zynq-can-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x18 0x04>;
+			power-domains = <0x0c 0x30>;
+			reg = <0x00 0xff070000 0x00 0x1000>;
+			rx-fifo-depth = <0x40>;
+			status = "disabled";
+			tx-fifo-depth = <0x40>;
+		};
+
+		cci at fd6e0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x01>;
+			compatible = "arm,cci-400";
+			ranges = <0x00 0x00 0xfd6e0000 0x10000>;
+			reg = <0x00 0xfd6e0000 0x00 0x9000>;
+
+			pmu at 9000 {
+				compatible = "arm,cci-400-pmu,r1";
+				interrupt-parent = <0x04>;
+				interrupts = <0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04 0x00 0x7b 0x04>;
+				reg = <0x9000 0x5000>;
+			};
+		};
+
+		dma at fd4c0000 {
+			#dma-cells = <0x01>;
+			clock-names = "axi_clk";
+			clocks = <0x03 0x14>;
+			compatible = "xlnx,dpdma";
+			dma-channels = <0x06>;
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7a 0x04>;
+			phandle = <0x19>;
+			power-domains = <0x0c 0x29>;
+			reg = <0x00 0xfd4c0000 0x00 0x1000>;
+			status = "okay";
+
+			dma-audio0channel {
+				compatible = "xlnx,audio0";
+			};
+
+			dma-audio1channel {
+				compatible = "xlnx,audio1";
+			};
+
+			dma-graphicschannel {
+				compatible = "xlnx,graphics";
+			};
+
+			dma-video0channel {
+				compatible = "xlnx,video0";
+			};
+
+			dma-video1channel {
+				compatible = "xlnx,video1";
+			};
+
+			dma-video2channel {
+				compatible = "xlnx,video2";
+			};
+		};
+
+		dma at fd500000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7c 0x04>;
+			iommus = <0x0d 0x14e8>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd500000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd510000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7d 0x04>;
+			iommus = <0x0d 0x14e9>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd510000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd520000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7e 0x04>;
+			iommus = <0x0d 0x14ea>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd520000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd530000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7f 0x04>;
+			iommus = <0x0d 0x14eb>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd530000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd540000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x80 0x04>;
+			iommus = <0x0d 0x14ec>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd540000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd550000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x81 0x04>;
+			iommus = <0x0d 0x14ed>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd550000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd560000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x82 0x04>;
+			iommus = <0x0d 0x14ee>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd560000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at fd570000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x13 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x83 0x04>;
+			iommus = <0x0d 0x14ef>;
+			power-domains = <0x0c 0x2a>;
+			reg = <0x00 0xfd570000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x80>;
+		};
+
+		dma at ffa80000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x4d 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffa80000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffa90000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x4e 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffa90000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffaa0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x4f 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffaa0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffab0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x50 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffab0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffac0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x51 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffac0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffad0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x52 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffad0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffae0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x53 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffae0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		dma at ffaf0000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_main", "clk_apb";
+			clocks = <0x03 0x44 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-dma-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x54 0x04>;
+			power-domains = <0x0c 0x2b>;
+			reg = <0x00 0xffaf0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,bus-width = <0x40>;
+		};
+
+		ethernet at ff0b0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+			clocks = <0x03 0x1f 0x03 0x68 0x03 0x2d 0x03 0x31 0x03 0x2c>;
+			compatible = "cdns,zynqmp-gem", "cdns,gem";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x39 0x04 0x00 0x39 0x04>;
+			iommus = <0x0d 0x874>;
+			phy-handle = <0x0e>;
+			phy-mode = "rgmii-id";
+			power-domains = <0x0c 0x1d>;
+			reg = <0x00 0xff0b0000 0x00 0x1000>;
+			status = "okay";
+			xlnx,ptp-enet-clock = <0x00>;
+
+			phy at 15 {
+				interrupt-parent = <0x0f>;
+				interrupts = <0x26 0x08>;
+				phandle = <0x0e>;
+				reg = <0x0f>;
+				reset-assert-us = <0x01>;
+				reset-gpios = <0x0f 0x2c 0x01>;
+				reset_deassert-us = <0xc8>;
+				ti,clk-output-sel = <0x0c>;
+				ti,fifo-depth = <0x01>;
+				ti,rx-internal-delay = <0x07>;
+				ti,tx-internal-delay = <0x05>;
+			};
+		};
+
+		ethernet at ff0c0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+			clocks = <0x03 0x1f 0x03 0x69 0x03 0x2e 0x03 0x32 0x03 0x2c>;
+			compatible = "cdns,zynqmp-gem", "cdns,gem";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x3b 0x04 0x00 0x3b 0x04>;
+			iommus = <0x0d 0x875>;
+			power-domains = <0x0c 0x1e>;
+			reg = <0x00 0xff0c0000 0x00 0x1000>;
+			status = "disabled";
+		};
+
+		ethernet at ff0d0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+			clocks = <0x03 0x1f 0x03 0x6a 0x03 0x2f 0x03 0x33 0x03 0x2c>;
+			compatible = "cdns,zynqmp-gem", "cdns,gem";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x3d 0x04 0x00 0x3d 0x04>;
+			iommus = <0x0d 0x876>;
+			power-domains = <0x0c 0x1f>;
+			reg = <0x00 0xff0d0000 0x00 0x1000>;
+			status = "disabled";
+		};
+
+		ethernet at ff0e0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
+			clocks = <0x03 0x1f 0x03 0x6b 0x03 0x30 0x03 0x34 0x03 0x2c>;
+			compatible = "cdns,zynqmp-gem", "cdns,gem";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x3f 0x04 0x00 0x3f 0x04>;
+			iommus = <0x0d 0x877>;
+			power-domains = <0x0c 0x20>;
+			reg = <0x00 0xff0e0000 0x00 0x1000>;
+			status = "disabled";
+		};
+
+		gpio at ff0a0000 {
+			#gpio-cells = <0x02>;
+			#interrupt-cells = <0x02>;
+			clocks = <0x03 0x1f>;
+			compatible = "xlnx,zynqmp-gpio-1.0";
+			emio-gpio-width = <0x20>;
+			gpio-controller;
+			gpio-line-names = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "btn1", "btn0", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "led0", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", "iic_mux_reset", "mipiA_pwup", "mipiB_pwup", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", "gpio173";
+			gpio-mask-high = <0x00>;
+			gpio-mask-low = <0x5600>;
+			interrupt-controller;
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x10 0x04>;
+			phandle = <0x0f>;
+			power-domains = <0x0c 0x2e>;
+			reg = <0x00 0xff0a0000 0x00 0x1000>;
+			status = "okay";
+		};
+
+		gpu at fd4b0000 {
+			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
+			clocks = <0x03 0x18 0x03 0x19 0x03 0x1a>;
+			compatible = "arm,mali-400", "arm,mali-utgard";
+			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04 0x00 0x84 0x04>;
+			power-domains = <0x0c 0x3a>;
+			reg = <0x00 0xfd4b0000 0x00 0x10000>;
+			status = "okay";
+			xlnx,tz-nonsecure = <0x01>;
+		};
+
+		i2c at ff020000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			clock-frequency = <0x61a80>;
+			clocks = <0x03 0x3d>;
+			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x11 0x04>;
+			power-domains = <0x0c 0x25>;
+			reg = <0x00 0xff020000 0x00 0x1000>;
+			status = "okay";
+
+			i2c-mux at 70 {
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+				compatible = "nxp,pca9548";
+				reg = <0x70>;
+				reset-gpios = <0x0f 0x4e 0x00>;
+
+				i2c at 0 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x00>;
+				};
+
+				i2c at 1 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x01>;
+				};
+
+				i2c at 2 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x02>;
+				};
+
+				i2c at 3 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x03>;
+
+					pmu at 43 {
+						#clock-cells = <0x00>;
+						compatible = "infineon,irps5401";
+						reg = <0x43>;
+					};
+
+					pmu at 44 {
+						#clock-cells = <0x00>;
+						compatible = "infineon,irps5401";
+						reg = <0x44>;
+					};
+
+					pmu at 45 {
+						#clock-cells = <0x00>;
+						compatible = "infineon,irps5401";
+						reg = <0x45>;
+					};
+				};
+
+				i2c at 4 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x04>;
+
+					eeprom at 51 {
+						compatible = "atmel,24c02";
+						pagesize = <0x01>;
+						reg = <0x51>;
+					};
+				};
+
+				i2c at 5 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x05>;
+
+					eeprom at 30 {
+						address-width = <0x10>;
+						compatible = "atmel,24c02";
+						read-only;
+						reg = <0x30>;
+						size = <0x10000>;
+					};
+				};
+
+				i2c at 6 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x06>;
+				};
+
+				i2c at 7 {
+					#address-cells = <0x01>;
+					#size-cells = <0x00>;
+					reg = <0x07>;
+				};
+			};
+		};
+
+		i2c at ff030000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			clock-frequency = <0x61a80>;
+			clocks = <0x03 0x3e>;
+			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x12 0x04>;
+			power-domains = <0x0c 0x26>;
+			reg = <0x00 0xff030000 0x00 0x1000>;
+			status = "okay";
+		};
+
+		memory-controller at fd070000 {
+			compatible = "xlnx,zynqmp-ddrc-2.40a";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x70 0x04>;
+			reg = <0x00 0xfd070000 0x00 0x30000>;
+		};
+
+		memory-controller at ff960000 {
+			compatible = "xlnx,zynqmp-ocmc-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x0a 0x04>;
+			reg = <0x00 0xff960000 0x00 0x1000>;
+		};
+
+		mmc at ff160000 {
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x03 0x36 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x30 0x04>;
+			iommus = <0x0d 0x870>;
+			power-domains = <0x0c 0x27>;
+			reg = <0x00 0xff160000 0x00 0x1000>;
+			status = "disabled";
+			u-boot,dm-pre-reloc;
+			xlnx,device_id = <0x00>;
+		};
+
+		mmc at ff170000 {
+			#stream-id-cells = <0x01>;
+			clock-frequency = <0xb2d05e0>;
+			clock-names = "clk_xin", "clk_ahb";
+			clocks = <0x03 0x37 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+			disable-wp;
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x31 0x04>;
+			iommus = <0x0d 0x871>;
+			power-domains = <0x0c 0x28>;
+			reg = <0x00 0xff170000 0x00 0x1000>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+			xlnx,device_id = <0x01>;
+			xlnx,itap-delay-sd-ddr50 = <0x32>;
+			xlnx,itap-delay-sd-hsd = <0x29>;
+			xlnx,itap-delay-sdr104 = <0x0b>;
+			xlnx,itap-delay-sdr25 = <0x2a>;
+			xlnx,itap-delay-sdr50 = <0x1e>;
+			xlnx,mio_bank = <0x01>;
+		};
+
+		nand at ff100000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "clk_sys", "clk_flash";
+			clocks = <0x03 0x3c 0x03 0x1f>;
+			compatible = "arasan,nfc-v3p10";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x0e 0x04>;
+			iommus = <0x0d 0x872>;
+			power-domains = <0x0c 0x2c>;
+			reg = <0x00 0xff100000 0x00 0x1000>;
+			status = "disabled";
+		};
+
+		pcie at fd0e0000 {
+			#address-cells = <0x03>;
+			#interrupt-cells = <0x01>;
+			#size-cells = <0x02>;
+			bus-range = <0x00 0xff>;
+			clocks = <0x03 0x17>;
+			compatible = "xlnx,nwl-pcie-2.11";
+			device_type = "pci";
+			interrupt-map = <0x00 0x00 0x00 0x01 0x11 0x01 0x00 0x00 0x00 0x02 0x11 0x02 0x00 0x00 0x00 0x03 0x11 0x03 0x00 0x00 0x00 0x04 0x11 0x04>;
+			interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+			interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x76 0x04 0x00 0x75 0x04 0x00 0x74 0x04 0x00 0x73 0x04 0x00 0x72 0x04>;
+			msi-controller;
+			msi-parent = <0x10>;
+			phandle = <0x10>;
+			power-domains = <0x0c 0x3b>;
+			ranges = <0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00>;
+			reg = <0x00 0xfd0e0000 0x00 0x1000 0x00 0xfd480000 0x00 0x1000 0x80 0x00 0x00 0x1000000>;
+			reg-names = "breg", "pcireg", "cfg";
+			status = "disabled";
+			xlnx,pcie-mode = "Root Port";
+			xlnx,tz-nonsecure = <0x00>;
+
+			legacy-interrupt-controller {
+				#address-cells = <0x00>;
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				phandle = <0x11>;
+			};
+		};
+
+		perf-monitor at fd0b0000 {
+			clocks = <0x03 0x1c>;
+			compatible = "xlnx,axi-perf-monitor";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7b 0x04>;
+			reg = <0x00 0xfd0b0000 0x00 0x10000>;
+			xlnx,enable-event-count = <0x01>;
+			xlnx,enable-event-log = <0x00>;
+			xlnx,enable-profile = <0x00>;
+			xlnx,enable-trace = <0x00>;
+			xlnx,global-count-width = <0x20>;
+			xlnx,have-sampled-metric-cnt = <0x01>;
+			xlnx,metric-count-scale = <0x01>;
+			xlnx,metric-count-width = <0x20>;
+			xlnx,metrics-sample-count-width = <0x20>;
+			xlnx,num-monitor-slots = <0x06>;
+			xlnx,num-of-counters = <0x0a>;
+		};
+
+		perf-monitor at fd490000 {
+			clocks = <0x03 0x1c>;
+			compatible = "xlnx,axi-perf-monitor";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x7b 0x04>;
+			reg = <0x00 0xfd490000 0x00 0x10000>;
+			xlnx,enable-event-count = <0x01>;
+			xlnx,enable-event-log = <0x00>;
+			xlnx,enable-profile = <0x00>;
+			xlnx,enable-trace = <0x00>;
+			xlnx,global-count-width = <0x20>;
+			xlnx,have-sampled-metric-cnt = <0x01>;
+			xlnx,metric-count-scale = <0x01>;
+			xlnx,metric-count-width = <0x20>;
+			xlnx,metrics-sample-count-width = <0x20>;
+			xlnx,num-monitor-slots = <0x01>;
+			xlnx,num-of-counters = <0x08>;
+		};
+
+		perf-monitor at ffa00000 {
+			clocks = <0x03 0x1f>;
+			compatible = "xlnx,axi-perf-monitor";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x19 0x04>;
+			reg = <0x00 0xffa00000 0x00 0x10000>;
+			xlnx,enable-event-count = <0x01>;
+			xlnx,enable-event-log = <0x01>;
+			xlnx,enable-profile = <0x00>;
+			xlnx,enable-trace = <0x00>;
+			xlnx,global-count-width = <0x20>;
+			xlnx,have-sampled-metric-cnt = <0x01>;
+			xlnx,metric-count-scale = <0x01>;
+			xlnx,metric-count-width = <0x20>;
+			xlnx,metrics-sample-count-width = <0x20>;
+			xlnx,num-monitor-slots = <0x01>;
+			xlnx,num-of-counters = <0x08>;
+		};
+
+		perf-monitor at ffa10000 {
+			clocks = <0x03 0x1f>;
+			compatible = "xlnx,axi-perf-monitor";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x19 0x04>;
+			reg = <0x00 0xffa10000 0x00 0x10000>;
+			xlnx,enable-event-count = <0x01>;
+			xlnx,enable-event-log = <0x01>;
+			xlnx,enable-profile = <0x00>;
+			xlnx,enable-trace = <0x00>;
+			xlnx,global-count-width = <0x20>;
+			xlnx,have-sampled-metric-cnt = <0x01>;
+			xlnx,metric-count-scale = <0x01>;
+			xlnx,metric-count-width = <0x20>;
+			xlnx,metrics-sample-count-width = <0x20>;
+			xlnx,num-monitor-slots = <0x01>;
+			xlnx,num-of-counters = <0x08>;
+		};
+
+		rtc at ffa60000 {
+			calibration = <0x8000>;
+			compatible = "xlnx,zynqmp-rtc";
+			interrupt-names = "alarm", "sec";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x1a 0x04 0x00 0x1b 0x04>;
+			reg = <0x00 0xffa60000 0x00 0x100>;
+			status = "okay";
+		};
+
+		serial at ff000000 {
+			clock-names = "uart_clk", "pclk";
+			clocks = <0x03 0x38 0x03 0x1f>;
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+			cts-override;
+			device_type = "serial";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x15 0x04>;
+			port-number = <0x00>;
+			power-domains = <0x0c 0x21>;
+			reg = <0x00 0xff000000 0x00 0x1000>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+		};
+
+		serial at ff010000 {
+			clock-names = "uart_clk", "pclk";
+			clocks = <0x03 0x39 0x03 0x1f>;
+			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
+			cts-override;
+			device_type = "serial";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x16 0x04>;
+			port-number = <0x01>;
+			power-domains = <0x0c 0x22>;
+			reg = <0x00 0xff010000 0x00 0x1000>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+		};
+
+		spi at ff040000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <0x03 0x3a 0x03 0x1f>;
+			compatible = "cdns,spi-r1p6";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x13 0x04>;
+			is-decoded-cs = <0x00>;
+			num-cs = <0x02>;
+			power-domains = <0x0c 0x23>;
+			reg = <0x00 0xff040000 0x00 0x1000>;
+			status = "okay";
+
+			gpio at 1 {
+				#gpio-cells = <0x02>;
+				#interrupt-cells = <0x02>;
+				#reset-cells = <0x01>;
+				compatible = "microchip,mcp23s08";
+				gpio-controller;
+				interrupt-controller;
+				interrupt-parent = <0x0f>;
+				interrupts = <0x19 0x08>;
+				microchip,spi-present-mask = <0x01>;
+				phandle = <0x14>;
+				reg = <0x01>;
+				spi-max-frequency = <0x989680>;
+			};
+
+			wilc_spi at 0 {
+				chip_en-gpios = <0x14 0x00 0x00>;
+				compatible = "microchip,wilc1000", "microchip,wilc3000";
+				irq-gpios = <0x14 0x01 0x00>;
+				reg = <0x00>;
+				reset-gpios = <0x14 0x02 0x00>;
+				spi-max-frequency = <0x2dc6c00>;
+				status = "okay";
+			};
+		};
+
+		spi at ff050000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <0x03 0x3b 0x03 0x1f>;
+			compatible = "cdns,spi-r1p6";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x14 0x04>;
+			power-domains = <0x0c 0x24>;
+			reg = <0x00 0xff050000 0x00 0x1000>;
+			status = "disabled";
+		};
+
+		spi at ff0f0000 {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			#stream-id-cells = <0x01>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <0x03 0x35 0x03 0x1f>;
+			compatible = "xlnx,zynqmp-qspi-1.0";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x0f 0x04>;
+			iommus = <0x0d 0x873>;
+			is-dual = <0x00>;
+			num-cs = <0x01>;
+			power-domains = <0x0c 0x2d>;
+			reg = <0x00 0xff0f0000 0x00 0x1000 0x00 0xc0000000 0x00 0x8000000>;
+			spi-rx-bus-width = <0x04>;
+			spi-tx-bus-width = <0x04>;
+			status = "okay";
+			u-boot,dm-pre-reloc;
+
+			flash at 0 {
+				#address-cells = <0x01>;
+				#size-cells = <0x01>;
+				compatible = "is25lp256d", "jedec,spi-nor";
+				reg = <0x00>;
+				spi-max-frequency = <0x17d7840>;
+
+				partition at 0x00000000 {
+					label = "boot";
+					reg = <0x00 0x100000>;
+				};
+
+				partition at 0x00100000 {
+					label = "bootenv";
+					reg = <0x100000 0x40000>;
+				};
+
+				partition at 0x00140000 {
+					label = "kernel";
+					reg = <0x140000 0x1600000>;
+				};
+			};
+		};
+
+		timer at ff110000 {
+			clocks = <0x03 0x1f>;
+			compatible = "cdns,ttc";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x24 0x04 0x00 0x25 0x04 0x00 0x26 0x04>;
+			power-domains = <0x0c 0x18>;
+			reg = <0x00 0xff110000 0x00 0x1000>;
+			status = "disabled";
+			timer-width = <0x20>;
+		};
+
+		timer at ff120000 {
+			clocks = <0x03 0x1f>;
+			compatible = "cdns,ttc";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x27 0x04 0x00 0x28 0x04 0x00 0x29 0x04>;
+			power-domains = <0x0c 0x19>;
+			reg = <0x00 0xff120000 0x00 0x1000>;
+			status = "disabled";
+			timer-width = <0x20>;
+		};
+
+		timer at ff130000 {
+			clocks = <0x03 0x1f>;
+			compatible = "cdns,ttc";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x2a 0x04 0x00 0x2b 0x04 0x00 0x2c 0x04>;
+			power-domains = <0x0c 0x1a>;
+			reg = <0x00 0xff130000 0x00 0x1000>;
+			status = "disabled";
+			timer-width = <0x20>;
+		};
+
+		timer at ff140000 {
+			clocks = <0x03 0x1f>;
+			compatible = "cdns,ttc";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x2d 0x04 0x00 0x2e 0x04 0x00 0x2f 0x04>;
+			power-domains = <0x0c 0x1b>;
+			reg = <0x00 0xff140000 0x00 0x1000>;
+			status = "disabled";
+			timer-width = <0x20>;
+		};
+
+		usb0 at ff9d0000 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <0x03 0x20 0x03 0x22>;
+			compatible = "xlnx,zynqmp-dwc3";
+			nvmem-cell-names = "soc_revision";
+			nvmem-cells = <0x12>;
+			power-domains = <0x0c 0x16>;
+			ranges;
+			reg = <0x00 0xff9d0000 0x00 0x100>;
+			status = "okay";
+			xlnx,tz-nonsecure = <0x01>;
+
+			dwc3 at fe200000 {
+				#stream-id-cells = <0x01>;
+				compatible = "snps,dwc3";
+				dr_mode = "host";
+				interrupt-names = "dwc_usb3", "otg", "hiber";
+				interrupt-parent = <0x04>;
+				interrupts = <0x00 0x41 0x04 0x00 0x45 0x04 0x00 0x4b 0x04>;
+				iommus = <0x0d 0x860>;
+				maximum-speed = "super-speed";
+				phy-names = "usb3-phy";
+				phys = <0x15 0x04 0x00 0x00 0x5f5e100>;
+				reg = <0x00 0xfe200000 0x00 0x40000>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,enable_guctl1_ipd_quirk;
+				snps,enable_guctl1_resume_quirk;
+				snps,quirk-frame-length-adjustment = <0x20>;
+				snps,refclk_fladj;
+				snps,usb3_lpm_capable;
+				snps,xhci-stream-quirk;
+				status = "okay";
+			};
+		};
+
+		usb1 at ff9e0000 {
+			#address-cells = <0x02>;
+			#size-cells = <0x02>;
+			clock-names = "bus_clk", "ref_clk";
+			clocks = <0x03 0x21 0x03 0x22>;
+			compatible = "xlnx,zynqmp-dwc3";
+			nvmem-cell-names = "soc_revision";
+			nvmem-cells = <0x12>;
+			power-domains = <0x0c 0x17>;
+			ranges;
+			reg = <0x00 0xff9e0000 0x00 0x100>;
+			status = "okay";
+			xlnx,tz-nonsecure = <0x00>;
+
+			dwc3 at fe300000 {
+				#stream-id-cells = <0x01>;
+				compatible = "snps,dwc3";
+				dr_mode = "host";
+				interrupt-names = "dwc_usb3", "otg", "hiber";
+				interrupt-parent = <0x04>;
+				interrupts = <0x00 0x46 0x04 0x00 0x4a 0x04 0x00 0x4c 0x04>;
+				iommus = <0x0d 0x861>;
+				maximum-speed = "high-speed";
+				reg = <0x00 0xfe300000 0x00 0x40000>;
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+				snps,enable_guctl1_ipd_quirk;
+				snps,enable_guctl1_resume_quirk;
+				snps,quirk-frame-length-adjustment = <0x20>;
+				snps,refclk_fladj;
+				snps,xhci-stream-quirk;
+				status = "okay";
+			};
+		};
+
+		watchdog at fd4d0000 {
+			clocks = <0x03 0x4b>;
+			compatible = "cdns,wdt-r1p2";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x71 0x01>;
+			reg = <0x00 0xfd4d0000 0x00 0x1000>;
+			reset-on-timeout;
+			status = "disabled";
+			timeout-sec = <0x3c>;
+		};
+
+		watchdog at ff150000 {
+			clocks = <0x03 0x70>;
+			compatible = "cdns,wdt-r1p2";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x34 0x01>;
+			reg = <0x00 0xff150000 0x00 0x1000>;
+			status = "disabled";
+			timeout-sec = <0x0a>;
+		};
+
+		zynqmp-display at fd4a0000 {
+			clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
+			clocks = <0x16 0x03 0x11 0x03 0x10>;
+			compatible = "xlnx,zynqmp-dpsub-1.7";
+			interrupt-parent = <0x04>;
+			interrupts = <0x00 0x77 0x04>;
+			phy-names = "dp-phy0", "dp-phy1";
+			phys = <0x17 0x06 0x00 0x02 0x66ff300 0x18 0x06 0x01 0x02 0x66ff300>;
+			power-domains = <0x0c 0x29>;
+			reg = <0x00 0xfd4a0000 0x00 0x1000 0x00 0xfd4aa000 0x00 0x1000 0x00 0xfd4ab000 0x00 0x1000 0x00 0xfd4ac000 0x00 0x1000>;
+			reg-names = "dp", "blend", "av_buf", "aud";
+			status = "okay";
+			xlnx,max-lanes = <0x02>;
+
+			gfx-layer {
+				dma-names = "gfx0";
+				dmas = <0x19 0x03>;
+			};
+
+			i2c-bus {
+			};
+
+			vid-layer {
+				dma-names = "vid0", "vid1", "vid2";
+				dmas = <0x19 0x00 0x19 0x01 0x19 0x02>;
+			};
+
+			zynqmp_dp_snd_card {
+				compatible = "xlnx,dp-snd-card";
+				status = "okay";
+				xlnx,dp-snd-codec = <0x1c>;
+				xlnx,dp-snd-pcm = <0x1a 0x1b>;
+			};
+
+			zynqmp_dp_snd_codec0 {
+				clock-names = "aud_clk";
+				clocks = <0x03 0x11>;
+				compatible = "xlnx,dp-snd-codec";
+				phandle = <0x1c>;
+				status = "okay";
+			};
+
+			zynqmp_dp_snd_pcm0 {
+				compatible = "xlnx,dp-snd-pcm";
+				dma-names = "tx";
+				dmas = <0x19 0x04>;
+				phandle = <0x1a>;
+				status = "okay";
+			};
+
+			zynqmp_dp_snd_pcm1 {
+				compatible = "xlnx,dp-snd-pcm";
+				dma-names = "tx";
+				dmas = <0x19 0x05>;
+				phandle = <0x1b>;
+				status = "okay";
+			};
+		};
+
+		psgtr: zynqmp_phy at fd400000 {
+			compatible = "xlnx,zynqmp-psgtr-v1.1";
+			nvmem-cell-names = "soc_revision";
+			nvmem-cells = <0x12>;
+			reg = <0x00 0xfd400000 0x00 0x40000 0x00 0xfd3d0000 0x00 0x1000>;
+			reg-names = "serdes", "siou";
+			reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst";
+			resets = <0x13 0x10 0x13 0x3b 0x13 0x3c 0x13 0x3d 0x13 0x3e 0x13 0x3f 0x13 0x40 0x13 0x03 0x13 0x1d 0x13 0x1e 0x13 0x1f 0x13 0x20>;
+			status = "okay";
+
+			lane0: lane0 {
+				#phy-cells = <0x04>;
+			};
+
+			lane1 {
+				#phy-cells = <0x04>;
+				phandle = <0x15>;
+			};
+
+			lane2 {
+				#phy-cells = <0x04>;
+				phandle = <0x18>;
+			};
+
+			lane3 {
+				#phy-cells = <0x04>;
+				phandle = <0x17>;
+			};
+		};
+	};
+
+	amba_apu at 0 {
+		#address-cells = <0x02>;
+		#size-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges = <0x00 0x00 0x00 0x00 0xffffffff>;
+
+		interrupt-controller at f9010000 {
+			#interrupt-cells = <0x03>;
+			compatible = "arm,gic-400", "arm,cortex-a15-gic";
+			interrupt-controller;
+			interrupt-parent = <0x04>;
+			interrupts = <0x01 0x09 0xf04>;
+			num_cpus = <0x02>;
+			num_interrupts = <0x60>;
+			phandle = <0x04>;
+			reg = <0x00 0xf9010000 0x10000 0x00 0xf9020000 0x20000 0x00 0xf9040000 0x20000 0x00 0xf9060000 0x20000>;
+		};
+	};
+
+	aux_ref_clk {
+		#clock-cells = <0x00>;
+		clock-frequency = <0x19bfcc0>;
+		compatible = "fixed-clock";
+		phandle = <0x09>;
+		u-boot,dm-pre-reloc;
+	};
+
+	cpu_opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+		phandle = <0x01>;
+
+		opp00 {
+			clock-latency-ns = <0x7a120>;
+			opp-hz = <0x00 0x47868bf4>;
+			opp-microvolt = <0xf4240>;
+		};
+
+		opp01 {
+			clock-latency-ns = <0x7a120>;
+			opp-hz = <0x00 0x23c345fa>;
+			opp-microvolt = <0xf4240>;
+		};
+
+		opp02 {
+			clock-latency-ns = <0x7a120>;
+			opp-hz = <0x00 0x17d783fc>;
+			opp-microvolt = <0xf4240>;
+		};
+
+		opp03 {
+			clock-latency-ns = <0x7a120>;
+			opp-hz = <0x00 0x11e1a2fd>;
+			opp-microvolt = <0xf4240>;
+		};
+	};
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		cpu at 0 {
+			clocks = <0x03 0x0a>;
+			compatible = "arm,cortex-a53", "arm,armv8";
+			cpu-idle-states = <0x02>;
+			device_type = "cpu";
+			enable-method = "psci";
+			operating-points-v2 = <0x01>;
+			reg = <0x00>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			cpu-idle-states = <0x02>;
+			device_type = "cpu";
+			enable-method = "psci";
+			operating-points-v2 = <0x01>;
+			reg = <0x01>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			cpu-idle-states = <0x02>;
+			device_type = "cpu";
+			enable-method = "psci";
+			operating-points-v2 = <0x01>;
+			reg = <0x02>;
+		};
+
+		cpu at 3 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			cpu-idle-states = <0x02>;
+			device_type = "cpu";
+			enable-method = "psci";
+			operating-points-v2 = <0x01>;
+			reg = <0x03>;
+		};
+
+		idle-states {
+			entry-method = "arm,psci";
+
+			cpu-sleep-0 {
+				arm,psci-suspend-param = <0x40000000>;
+				compatible = "arm,idle-state";
+				entry-latency-us = <0x12c>;
+				exit-latency-us = <0x258>;
+				local-timer-stop;
+				min-residency-us = <0x2710>;
+				phandle = <0x02>;
+			};
+		};
+	};
+
+	dcc {
+		compatible = "arm,dcc";
+		status = "disabled";
+		u-boot,dm-pre-reloc;
+	};
+
+	dp_aclk {
+		#clock-cells = <0x00>;
+		clock-accuracy = <0x64>;
+		clock-frequency = <0x5f5e100>;
+		compatible = "fixed-clock";
+		phandle = <0x16>;
+	};
+
+	edac {
+		compatible = "arm,cortex-a53-edac";
+	};
+
+	fclk0 {
+		clocks = <0x03 0x47>;
+		compatible = "xlnx,fclk";
+		status = "okay";
+	};
+
+	fclk1 {
+		clocks = <0x03 0x48>;
+		compatible = "xlnx,fclk";
+		status = "okay";
+	};
+
+	fclk2 {
+		clocks = <0x03 0x49>;
+		compatible = "xlnx,fclk";
+		status = "okay";
+	};
+
+	fclk3 {
+		clocks = <0x03 0x4a>;
+		compatible = "xlnx,fclk";
+		status = "okay";
+	};
+
+	firmware {
+
+		zynqmp-firmware {
+			#power-domain-cells = <0x01>;
+			compatible = "xlnx,zynqmp-firmware";
+			method = "smc";
+			phandle = <0x0c>;
+			u-boot,dm-pre-reloc;
+
+			clock-controller {
+				#clock-cells = <0x01>;
+				clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
+				clocks = <0x06 0x07 0x08 0x09 0x0a>;
+				compatible = "xlnx,zynqmp-clk";
+				phandle = <0x03>;
+				u-boot,dm-pre-reloc;
+			};
+
+			pinctrl {
+				compatible = "xlnx,zynqmp-pinctrl";
+				status = "disabled";
+			};
+
+			zynqmp_reset: reset-controller {
+				#reset-cells = <0x01>;
+				compatible = "xlnx,zynqmp-reset";
+				phandle = <0x13>;
+			};
+
+			zynqmp-power {
+				u-boot,dm-pre-reloc;
+				compatible = "xlnx,zynqmp-power";
+				interrupt-parent = <0x04>;
+				interrupts = <0x00 0x23 0x04>;
+				mbox-names = "tx", "rx";
+				mboxes = <0x05 0x00 0x05 0x01>;
+			};
+		};
+	};
+
+	fpga-full {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "fpga-region";
+		fpga-mgr = <0x0b>;
+	};
+
+	gt_crx_ref_clk {
+		#clock-cells = <0x00>;
+		clock-frequency = <0x66ff300>;
+		compatible = "fixed-clock";
+		phandle = <0x0a>;
+		u-boot,dm-pre-reloc;
+	};
+
+	nvmem_firmware {
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		compatible = "xlnx,zynqmp-nvmem-fw";
+
+		efuse_chash at 50 {
+			reg = <0x50 0x04>;
+		};
+
+		efuse_dna at c {
+			reg = <0x0c 0x0c>;
+		};
+
+		efuse_miscusr at 40 {
+			reg = <0x40 0x04>;
+		};
+
+		efuse_ppk0hash at a0 {
+			reg = <0xa0 0x30>;
+		};
+
+		efuse_ppk1hash at d0 {
+			reg = <0xd0 0x30>;
+		};
+
+		efuse_pufmisc at 54 {
+			reg = <0x54 0x04>;
+		};
+
+		efuse_sec at 58 {
+			reg = <0x58 0x04>;
+		};
+
+		efuse_spkid at 5c {
+			reg = <0x5c 0x04>;
+		};
+
+		efuse_usr0 at 20 {
+			reg = <0x20 0x04>;
+		};
+
+		efuse_usr1 at 24 {
+			reg = <0x24 0x04>;
+		};
+
+		efuse_usr2 at 28 {
+			reg = <0x28 0x04>;
+		};
+
+		efuse_usr3 at 2c {
+			reg = <0x2c 0x04>;
+		};
+
+		efuse_usr4 at 30 {
+			reg = <0x30 0x04>;
+		};
+
+		efuse_usr5 at 34 {
+			reg = <0x34 0x04>;
+		};
+
+		efuse_usr6 at 38 {
+			reg = <0x38 0x04>;
+		};
+
+		efuse_usr7 at 3c {
+			reg = <0x3c 0x04>;
+		};
+
+		soc_revision at 0 {
+			phandle = <0x12>;
+			reg = <0x00 0x04>;
+		};
+	};
+
+	pcap {
+		clock-names = "ref_clk";
+		clocks = <0x03 0x29>;
+		compatible = "xlnx,zynqmp-pcap-fpga";
+		phandle = <0x0b>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <0x04>;
+		interrupts = <0x00 0x8f 0x04 0x00 0x90 0x04 0x00 0x91 0x04 0x00 0x92 0x04>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	pss_alt_ref_clk {
+		#clock-cells = <0x00>;
+		clock-frequency = <0x00>;
+		compatible = "fixed-clock";
+		phandle = <0x08>;
+		u-boot,dm-pre-reloc;
+	};
+
+	pss_ref_clk {
+		#clock-cells = <0x00>;
+		clock-frequency = <0x1c9c380>;
+		compatible = "fixed-clock";
+		phandle = <0x06>;
+		u-boot,dm-pre-reloc;
+	};
+
+	sha384 {
+		compatible = "xlnx,zynqmp-keccak-384";
+	};
+
+	smmu at fd800000 {
+		#global-interrupts = <0x01>;
+		#iommu-cells = <0x01>;
+		compatible = "arm,mmu-500";
+		interrupt-parent = <0x04>;
+		interrupts = <0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04 0x00 0x9b 0x04>;
+		phandle = <0x0d>;
+		reg = <0x00 0xfd800000 0x00 0x20000>;
+		status = "disabled";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <0x04>;
+		interrupts = <0x01 0x0d 0xf08 0x01 0x0e 0xf08 0x01 0x0b 0xf08 0x01 0x0a 0xf08>;
+	};
+
+	video_clk {
+		#clock-cells = <0x00>;
+		clock-frequency = <0x19bfcc0>;
+		compatible = "fixed-clock";
+		phandle = <0x07>;
+		u-boot,dm-pre-reloc;
+	};
+
+	zynqmp_aes {
+		compatible = "xlnx,zynqmp-aes";
+	};
+
+	zynqmp_ipi {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		compatible = "xlnx,zynqmp-ipi-mailbox";
+		interrupt-parent = <0x04>;
+		interrupts = <0x00 0x23 0x04>;
+		ranges;
+		xlnx,ipi-id = <0x00>;
+		u-boot,dm-pre-reloc;
+
+		mailbox at ff990400 {
+			#mbox-cells = <0x01>;
+			phandle = <0x05>;
+			reg = <0x00 0xff9905c0 0x00 0x20 0x00 0xff9905e0 0x00 0x20 0x00 0xff990e80 0x00 0x20 0x00 0xff990ea0 0x00 0x20>;
+			reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region";
+			xlnx,ipi-id = <0x04>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	zynqmp_rsa {
+		compatible = "xlnx,zynqmp-rsa";
+	};
+};
+
+/ {
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x7ff00000>,
+		      <0x00000008 0x00000000 0x00000000 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		reserved_DMA: reserved_DMA {
+			reg = <0x08 0x00000000 0x00 0x10000000>;
+			no-map;
+		};
+		reserved_SG: reserved_SG {
+			reg = <0x08 0x10000000 0x00 0x10000>;
+			no-map;
+		};
+	};
+
+	chosen {
+		bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused uio_pdrv_genirq.of_id=generic-uio";
+		linux,initrd-end = <0x00 0x78fff6ca>;
+		linux,initrd-start = <0x00 0x76363000>;
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&sata {
+	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	status = "okay";
+	xlnx,tz-nonsecure-sata0 = <0x0>;
+	xlnx,tz-nonsecure-sata1 = <0x0>;
+	phy-names = "sata-phy";
+	phys = <&psgtr 1 1 1 1>;
+	resets = <&zynqmp_reset 16>;
+};
+
+&amba {
+	axi_complex_fft: axi_complex_fft at 80000000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80000000 0x00 0x10000>;
+		reg-names  = "axi_complex_fft";
+	};
+
+	axi_beamforming: axi_beamforming at 80010000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80010000 0x00 0x10000>;
+		reg-names  = "axi_beamforming";
+	};
+
+	axi_prepare_transfer_0: axi_prepare_transfer_0 at 80020000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80020000 0x00 0x10000>;
+		reg-names  = "axi_prepare_transfer_0";
+	};
+
+	axi_prepare_transfer_1: axi_prepare_transfer_1 at 80030000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80030000 0x00 0x10000>;
+		reg-names  = "axi_prepare_transfer_1";
+	};
+
+	axi_trigger_stats: axi_trigger_stats at 80040000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80040000 0x00 0x10000>;
+		reg-names  = "axi_trigger_stats";
+	};
+
+	axi_window_processing: axi_window_processing at 80050000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80050000 0x00 0x10000>;
+		reg-names  = "axi_window_processing";
+	};
+
+	axi_cancelator: axi_cancelator at 80080000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80080000 0x00 0x10000>;
+		reg-names  = "axi_cancelator";
+	};
+
+	axi_filter_downsampler_2MHz: axi_filter_downsampler_2MHz at 80090000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x80090000 0x00 0x10000>;
+		reg-names  = "axi_filter";
+	};
+
+	axi_filter_downsampler_user: axi_filter_downsampler_user at 800a0000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x800a0000 0x00 0x10000>;
+		reg-names  = "axi_filter";
+	};
+
+	axi_art_adc: axi_art_adc at 800b0000 {
+		compatible = "generic-uio";
+		reg = <0x00 0x800b0000 0x00 0x10000>;
+		reg-names  = "ADC";
+	};
+
+	axi_rtc: axi_rtc at 0x800c0000 {
+		compatible = "art,axi-art-rtc";
+		reg = <0x00 0x800c0000 0x00 0x10000>;
+		reg-names = "axi_rtc";
+	};
+
+	DMACapture_0: DMACapture_0 at 0x80060000 {
+		compatible = "generic-uio";
+		interrupt-parent = <0x04>;
+		interrupts = <0 89 1>;
+		reg = <0x08 0x00000000 0x00 0x8000000	/* 128 MB */
+		       0x08 0x10000000 0x00 0x0008000
+		       0x00 0x80060000 0x00 0x010000>;
+		reg-names  = "Capture", "Scatter-Gather", "AXI-DMA";
+	};
+
+	DMACapture_1: DMACapture_1 at 0x80070000 {
+		compatible = "generic-uio";
+		interrupt-parent = <0x04>;
+		interrupts = <0 90 1>;
+		reg = <0x08 0x08000000 0x00 0x8000000	/* 128 MB */
+		       0x08 0x10008000 0x00 0x0008000
+		       0x00 0x80070000 0x00 0x010000>;
+		reg-names  = "Capture", "Scatter-Gather", "AXI-DMA";
+	};
+};
diff --git a/board/digilent/genesys-zu/README.txt b/board/digilent/genesys-zu/README.txt
new file mode 100644
index 0000000000..50d6a6be8a
--- /dev/null
+++ b/board/digilent/genesys-zu/README.txt
@@ -0,0 +1,110 @@
+********************************
+Digilent Genesys ZU - ZynqMP SoC
+********************************
+
+This document describes the Buildroot support for the Genesys ZU board
+by Digilent, based on the Zynq UltraScale+ MPSoC (aka ZynqMP).
+
+How to build it
+===============
+
+Configure Buildroot:
+
+    $ make digilent_genesys_zu_defconfig
+
+Compile everything and build the rootfs image:
+
+    $ make
+
+Result of the build
+-------------------
+
+After building, you should get a tree like this:
+
+    output/images/
+    +-- bl31.bin
+    +-- boot.bin
+    +-- u-boot.itb
+    +-- uboot-env.bin
+    +-- GenesysZU.dtb
+    +-- Image
+    +-- image.ub
+    +-- rootfs.ext2
+    +-- rootfs.ext4 -> rootfs.ext2
+    +-- boot.vfat
+    `-- sdcard.img
+
+ * bl31.bin: Compiled xilinx' ARM Trusted Firmware, version xilinx-2020.1.
+ * boot.bin: U-boot SPL binary image. This is the file the zynqmp boots first.
+ * u-boot.itb: FIT Image containing both u-boot proper and ATF bl31.bin
+               SPL image will load these and will run BOTH.
+ * uboot-env.bin: U-boot environment
+ * GenesysZU.dtb: Device tree blob, compiled from source GenesysZU.dts
+ * Image: Kernel image
+ * image.ub: FIT Image containing kernel image, device tree blob and, optionally,
+             FPGA bitfile image
+ * rootfs.ext4: filesystem image
+ * boot.vfat: FAT partition to be written to SD.
+              Contains boot.bin, u-boot.itb, uboot-env.bin and image.ub
+ * sdcard.img: SD image with two partitions: boot.vfat and rootfs.ext4
+
+ZynqMP "community workflow" boot summary
+========================================
+
+No Xilinx utils are used to generate the resulting binaries, but several Xilinx
+source code modules are used indeed.
+
+The SoC will look for boot.bin image. In this case, this is U-boot SPL
+image. This will load u-boot proper and ARM Trusted Firmware binary from a
+FIT image, but also loads PMU firmware to the PMU processor, which is a
+Microblaze. PMU firmware is in charge of configuring internal peripherals as
+defined in the Vivado project, and for that it uses provided pm_cfg_obj.c
+and psu_init_gpl.c files. Both of them are generated by Xilinx' SDK, and the
+latter can be minimized using U-boot tools/zynqmp_psu_init_minimize.sh
+script.
+
+Finally, U-boot proper can then run linux or anything else, and also, if an
+FPGA BIT file is provided in the FIT image, it will also configure the PL
+section of the SoC. See image.its to check how to create a FIT image
+containing this file.
+
+An environment file for U-boot is provided in order to read the MAC address
+that is stored on flash by Digilent. Also, bootargs are modified to include
+uio_pdrv_genirq.of_id=generic-uio entry, which will be useful for the
+typical usage of accessing AXI Devices via UIO driver. A UIO device can be
+added to the DTS with the following format:
+
+        axi_device: axi_device at 80000000 {
+                compatible = "generic-uio";
+                reg = <0x00 0x80000000 0x00 0x10000>;
+                reg-names  = "axi_device";
+        };
+
+
+Ideally all firmware should be taken from a single Xilinx release, i.e,
+2019.1, 2019.2, 2020.1... etc. However, this configuration uses modules from
+different release versions. Kernel is Xilinx version 2019.2, while u-boot is
+mainstream 2021.04 and ATF is version 2020.1. The reason for this is that
+kernel version 2019.2 implements correctly the tested firmware, while
+mainstream u-boot is the only one that supports full "community workflow"
+mode. ATF version has been chosen to be 2020.1 because this version compiles
+using gcc-11 without any additional patches.
+
+This set of different versions is the most stable and easy to compile on
+buildroot that the author has found, but there may be some incompatibilities
+on subsystems that have not been tested.
+
+How to write the SD card
+========================
+
+WARNING! This will destroy all the card content. Use with care!
+
+The sdcard.img file is a complete bootable image ready to be written
+on the boot medium. To install it, simply copy the image to an SD
+card:
+
+    # dd if=output/images/sdcard.img of=/dev/sdX
+
+Where 'sdX' is the device node of the SD.
+
+Eject the SD card, insert it in the board, and power it up.
diff --git a/board/digilent/genesys-zu/genimage.cfg b/board/digilent/genesys-zu/genimage.cfg
new file mode 100644
index 0000000000..eeecfee37d
--- /dev/null
+++ b/board/digilent/genesys-zu/genimage.cfg
@@ -0,0 +1,28 @@
+image boot.vfat {
+	vfat {
+		files = {
+			"boot.bin",
+			"u-boot.itb",
+			"GenesysZU.dtb",
+			"uboot-env.bin",
+			"image.ub",
+		}
+	}
+	size = 32M
+}
+
+image sdcard.img {
+	hdimage {
+	}
+
+	partition boot {
+		partition-type = 0xC
+		bootable = "true"
+		image = "boot.vfat"
+	}
+
+	partition root {
+		partition-type = 0x83
+		image = "rootfs.ext4"
+	}
+}
diff --git a/board/digilent/genesys-zu/image.its b/board/digilent/genesys-zu/image.its
new file mode 100644
index 0000000000..ad1d73804d
--- /dev/null
+++ b/board/digilent/genesys-zu/image.its
@@ -0,0 +1,59 @@
+/dts-v1/;
+  
+/ {
+	description = "U-Boot fitImage";
+	#address-cells = <1>;
+  
+	images {
+		kernel {
+			description = "Linux Kernel";
+			data = /incbin/("Image");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "none";
+			load = <0x00080000>;
+			entry = <0x00080000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+/*	Enable this section to load a bitstream during boot
+		fpga {
+			description = "FPGA bitfile";
+			data = /incbin/("system.bit");
+			type = "fpga";
+			arch = "arm64";
+			compression = "none";
+			load = <0x4000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+*/
+		fdt {
+			description = "DTB";
+			data = /incbin/("GenesysZU.dtb");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+	configurations {
+		default = "conf";
+		conf {
+			description = "Boot Linux kernel with FDT blob";
+			kernel = "kernel";
+			fdt = "fdt";
+/*	Enable this section to load a bitstream during boot
+			fpga = "fpga";
+*/
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+	};
+};
diff --git a/board/digilent/genesys-zu/kernel_defconfig b/board/digilent/genesys-zu/kernel_defconfig
new file mode 100644
index 0000000000..5778417e7e
--- /dev/null
+++ b/board/digilent/genesys-zu/kernel_defconfig
@@ -0,0 +1,414 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_PCI=y
+CONFIG_PCIE_XILINX_NWL=y
+CONFIG_NR_CPUS=8
+CONFIG_XEN=y
+# CONFIG_DMI is not set
+CONFIG_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_EBT_T_FILTER=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_EBT_MARK_T=y
+CONFIG_BRIDGE=y
+CONFIG_NET_PKTGEN=y
+CONFIG_CAN=y
+CONFIG_CAN_XILINXCAN=y
+CONFIG_BT=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=y
+CONFIG_BT_LEDS=y
+CONFIG_BT_HCIBTUSB=y
+CONFIG_BT_HCIBTSDIO=y
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_INTEL=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIBCM203X=y
+CONFIG_BT_HCIBPA10X=y
+CONFIG_BT_HCIBFUSB=y
+CONFIG_BT_HCIVHCI=y
+CONFIG_BT_MRVL=y
+CONFIG_BT_MRVL_SDIO=y
+CONFIG_BT_ATH3K=y
+CONFIG_BT_WILINK=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_CERTIFICATION_ONUS=y
+CONFIG_CFG80211_REG_CELLULAR_HINTS=y
+CONFIG_CFG80211_REG_RELAX_NO_IR=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_MAC80211_DEBUG_MENU=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_NET_9P=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=1000
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_TESTS=m
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_OOPS=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ARASAN=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_CONFIGFS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_XEN_BLKDEV_BACKEND=m
+CONFIG_XILINX_SDFEC=y
+CONFIG_XILINX_JESD204B=y
+CONFIG_XILINX_JESD204B_PHY=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_TI_ST=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_XEN_SCSI_FRONTEND=m
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_CEVA=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_MACB=y
+CONFIG_XILINX_EMACLITE=y
+CONFIG_XILINX_AXI_EMAC=y
+CONFIG_AMD_PHY=y
+CONFIG_AT803X_PHY=y
+CONFIG_BCM7XXX_PHY=y
+CONFIG_BCM87XX_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_DP83867_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_STE10XP=y
+CONFIG_VITESSE_PHY=y
+CONFIG_XILINX_PHY=y
+CONFIG_XILINX_GMII2RGMII=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_SIERRA_NET=y
+CONFIG_WL18XX=y
+CONFIG_WLCORE_SPI=y
+CONFIG_WLCORE_SDIO=y
+CONFIG_XEN_NETDEV_BACKEND=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_INPUT_MISC=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_MAX310X=y
+CONFIG_SERIAL_UARTLITE=y
+CONFIG_SERIAL_UARTLITE_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX_PCA9541=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_CADENCE=y
+CONFIG_I2C_XILINX=y
+CONFIG_I2C_DEBUG_BUS=y
+CONFIG_SPI=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPI_ZYNQMP_GQSPI=y
+CONFIG_PINCTRL_MCP23S08=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_TPS65086=y
+CONFIG_POWER_RESET_LTC2952=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_PMBUS=y
+CONFIG_SENSORS_MAX20751=y
+CONFIG_SENSORS_INA2XX=y
+CONFIG_WATCHDOG=y
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_XEN_WDT=m
+CONFIG_MFD_TPS65086=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_TPS65086=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_XILINX=y
+CONFIG_VIDEO_XILINX_AXI4S_SWITCH=y
+CONFIG_VIDEO_XILINX_CFA=y
+CONFIG_VIDEO_XILINX_CRESAMPLE=y
+CONFIG_VIDEO_XILINX_DEMOSAIC=y
+CONFIG_VIDEO_XILINX_GAMMA=y
+CONFIG_VIDEO_XILINX_HLS=y
+CONFIG_VIDEO_XILINX_REMAPPER=y
+CONFIG_VIDEO_XILINX_RGB2YUV=y
+CONFIG_VIDEO_XILINX_SCALER=y
+CONFIG_VIDEO_XILINX_MULTISCALER=y
+CONFIG_VIDEO_XILINX_SDIRXSS=y
+CONFIG_VIDEO_XILINX_SWITCH=y
+CONFIG_VIDEO_XILINX_TPG=y
+CONFIG_VIDEO_XILINX_VPSS_CSC=y
+CONFIG_VIDEO_XILINX_VPSS_SCALER=y
+CONFIG_VIDEO_XILINX_CSI2RXSS=y
+CONFIG_VIDEO_XILINX_SCD=y
+CONFIG_VIDEO_XILINX_M2M=y
+# CONFIG_VGA_ARB is not set
+CONFIG_DRM=y
+CONFIG_DRM_XILINX=y
+CONFIG_DRM_XILINX_SDI=y
+CONFIG_DRM_XLNX=y
+CONFIG_DRM_XLNX_BRIDGE=y
+CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y
+CONFIG_DRM_ZYNQMP_DPSUB=y
+CONFIG_DRM_XLNX_DSI=y
+CONFIG_DRM_XLNX_MIXER=y
+CONFIG_DRM_XLNX_PL_DISP=y
+CONFIG_DRM_XLNX_SDI=y
+CONFIG_DRM_XLNX_BRIDGE_CSC=y
+CONFIG_DRM_XLNX_BRIDGE_SCALER=y
+CONFIG_FB_XILINX=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_XILINX_DP=y
+CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y
+CONFIG_SND_SOC_XILINX_SDI=y
+CONFIG_SND_SOC_XILINX_I2S=y
+CONFIG_SND_SOC_XILINX_SPDIF=y
+CONFIG_SND_SOC_XILINX_PL_SND_CARD=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEFAULT_PERSIST is not set
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_UAS=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_QUALCOMM=y
+CONFIG_USB_SERIAL_SIERRAWIRELESS=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_XILINX=y
+CONFIG_USB_CONFIGFS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_EEM=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_EDAC=y
+CONFIG_EDAC_SYNOPSYS=y
+CONFIG_EDAC_ZYNQMP_OCM=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_ZYNQMP=y
+CONFIG_DMADEVICES=y
+CONFIG_XILINX_DMA_ENGINES=y
+CONFIG_XILINX_DMA=y
+CONFIG_XILINX_ZYNQMP_DMA=y
+CONFIG_DMATEST=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_XILINX_APM=y
+CONFIG_STAGING=y
+CONFIG_ION=y
+CONFIG_ION_SYSTEM_HEAP=y
+CONFIG_ION_CARVEOUT_HEAP=y
+CONFIG_ION_CHUNK_HEAP=y
+CONFIG_ION_CMA_HEAP=y
+CONFIG_COMMON_CLK_XLNX_CLKWZRD=y
+CONFIG_XILINX_FCLK=y
+CONFIG_XLNX_CTRL_FRMBUF=y
+CONFIG_XLNX_CTRL_VPSS=y
+CONFIG_COMMON_CLK_SI570=y
+CONFIG_COMMON_CLK_SI5324=y
+# CONFIG_COMMON_CLK_XGENE is not set
+CONFIG_COMMON_CLK_ZYNQMP=y
+CONFIG_ARM_SMMU=y
+CONFIG_REMOTEPROC=m
+CONFIG_ZYNQMP_R5_REMOTEPROC=m
+CONFIG_RPMSG_CHAR=m
+CONFIG_XILINX_VCU=m
+CONFIG_IIO=y
+CONFIG_XILINX_XADC=y
+CONFIG_XILINX_AMS=y
+CONFIG_XILINX_INTC=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RAS=y
+CONFIG_ANDROID=y
+CONFIG_NVMEM_ZYNQMP=y
+CONFIG_FPGA=y
+CONFIG_XILINX_AFI_FPGA=y
+CONFIG_FPGA_BRIDGE=y
+CONFIG_XILINX_PR_DECOUPLER=y
+CONFIG_FPGA_REGION=y
+CONFIG_OF_FPGA_REGION=y
+CONFIG_FPGA_MGR_ZYNQMP_FPGA=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_BTRFS_FS=y
+CONFIG_QUOTA=y
+CONFIG_QFMT_V2=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_DEBUG=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_ECRYPT_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=y
+CONFIG_CRYPTO_DEV_XILINX_RSA=y
+CONFIG_CRYPTO_DEV_ZYNQMP_AES=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
diff --git a/board/digilent/genesys-zu/pm_cfg_obj.c b/board/digilent/genesys-zu/pm_cfg_obj.c
new file mode 100644
index 0000000000..a537a05493
--- /dev/null
+++ b/board/digilent/genesys-zu/pm_cfg_obj.c
@@ -0,0 +1,630 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+* THE SOFTWARE.
+*
+*
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "pm_defs.h"
+
+#define PM_CONFIG_MASTER_SECTION_ID	0x101U
+#define PM_CONFIG_SLAVE_SECTION_ID	0x102U
+#define PM_CONFIG_PREALLOC_SECTION_ID	0x103U
+#define PM_CONFIG_POWER_SECTION_ID	0x104U
+#define PM_CONFIG_RESET_SECTION_ID	0x105U
+#define PM_CONFIG_SHUTDOWN_SECTION_ID	0x106U
+#define PM_CONFIG_SET_CONFIG_SECTION_ID	0x107U
+#define PM_CONFIG_GPO_SECTION_ID	0x108U
+
+#define PM_SLAVE_FLAG_IS_SHAREABLE	0x1U
+#define PM_MASTER_USING_SLAVE_MASK	0x2U
+
+#define PM_CONFIG_GPO1_MIO_PIN_34_MAP	(1U << 10U)
+#define PM_CONFIG_GPO1_MIO_PIN_35_MAP	(1U << 11U)
+#define PM_CONFIG_GPO1_MIO_PIN_36_MAP	(1U << 12U)
+#define PM_CONFIG_GPO1_MIO_PIN_37_MAP	(1U << 13U)
+
+#define PM_CONFIG_GPO1_BIT_2_MASK	(1U << 2U)
+#define PM_CONFIG_GPO1_BIT_3_MASK	(1U << 3U)
+#define PM_CONFIG_GPO1_BIT_4_MASK	(1U << 4U)
+#define PM_CONFIG_GPO1_BIT_5_MASK	(1U << 5U)
+
+#define SUSPEND_TIMEOUT	0xFFFFFFFFU
+
+
+#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK    0x00000001
+#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK    0x00000100
+#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK    0x00000200
+
+
+
+#if defined (__ICCARM__)
+#pragma language=save
+#pragma language=extended
+#endif
+#if defined (__GNUC__)
+    const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
+#elif defined (__ICCARM__)
+#pragma location = ".sys_cfg_data"
+__root const u32 XPm_ConfigObject[] =
+#endif
+{
+	/**********************************************************************/
+	/* HEADER */
+	1,	/* Number of remaining words in the header */
+	8,	/* Number of sections included in config object */
+	/**********************************************************************/
+	/* MASTER SECTION */
+	PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
+	3U, /* No. of Masters*/
+
+	NODE_APU, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+	NODE_RPU_0, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
+
+	NODE_RPU_1, /* Master Node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
+	SUSPEND_TIMEOUT, /* Suspend timeout */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
+
+
+	/**********************************************************************/
+	/* SLAVE SECTION */
+
+
+	PM_CONFIG_SLAVE_SECTION_ID,	/* Section ID */
+	49,				/* Number of slaves */
+
+	NODE_OCM_BANK_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_OCM_BANK_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TCM_0_A,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_TCM_0_B,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_TCM_1_A,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TCM_1_B,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_L2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU_PP_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU_PP_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_USB_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_USB_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TTC_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_TTC_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_TTC_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_TTC_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_SATA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_ETH_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_ETH_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_2,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_ETH_3,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_UART_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_UART_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SPI_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SPI_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_I2C_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_I2C_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_SD_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_SD_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_DP,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GDMA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_ADMA,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_NAND,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_QSPI,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPIO,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_CAN_0,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_CAN_1,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_EXTERN,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_DDR,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_IPI_APU,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
+
+	NODE_IPI_RPU_0,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
+
+	NODE_IPI_RPU_1,
+	0U,
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_GPU,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_PCIE,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_PCAP,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_RTC,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+	NODE_VCU,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	0U, /* IPI Mask */
+
+	NODE_PL,
+	PM_SLAVE_FLAG_IS_SHAREABLE,
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
+
+
+	/**********************************************************************/
+	/* PREALLOC SECTION */
+
+	PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
+	3U, /* No. of Masters*/
+
+/* Prealloc for psu_cortexa53_0 */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
+	12,
+	NODE_IPI_APU,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_DDR,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_L2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_3,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_I2C_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_I2C_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_SD_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_QSPI,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_PL,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	/* Prealloc for psu_cortexr5_0 */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+	14,
+	NODE_IPI_RPU_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_0_A,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_0_B,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_DDR,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_L2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_2,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_OCM_BANK_3,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_I2C_0,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_I2C_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_SD_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_QSPI,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_PL,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	/* Prealloc for psu_cortexr5_1 */
+	PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	3,
+	NODE_IPI_RPU_1,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_1_A,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+	NODE_TCM_1_B,
+	PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
+	PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
+
+
+	
+	/**********************************************************************/
+	/* POWER SECTION */
+
+	PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
+	4U, /* Number of power nodes */
+
+	NODE_APU, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+	NODE_RPU, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* Force power down permissions */
+
+	NODE_FPD, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+	NODE_PLD, /* Power node ID */
+	PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
+
+
+	/**********************************************************************/
+	/* RESET SECTION */
+
+	PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
+	120U, /* Number of resets */
+
+	XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_SYSMON, 0,
+	XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
+	XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+	XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
+
+	/**********************************************************************/
+	/* SET CONFIG SECTION */
+	PM_CONFIG_SET_CONFIG_SECTION_ID,	/* Section ID */
+	0,					/* Permissions to set config */
+	/**********************************************************************/
+	/* SHUTDOWN SECTION */
+	PM_CONFIG_SHUTDOWN_SECTION_ID,		/* Section ID */
+	0,					/* Number of shutdown types */
+	/**********************************************************************/
+	/* GPO SECTION */
+	PM_CONFIG_GPO_SECTION_ID,		/* GPO Section ID */
+	0,					/* State of GPO pins */
+};
+#if defined (__ICCARM__)
+#pragma language=restore
+#endif
+
diff --git a/board/digilent/genesys-zu/post-image.sh b/board/digilent/genesys-zu/post-image.sh
new file mode 100755
index 0000000000..06d00553c7
--- /dev/null
+++ b/board/digilent/genesys-zu/post-image.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+set -x
+TMP_DIR=$(mktemp -d)
+cp -a board/digilent/genesys-zu/image.its "${TMP_DIR}"
+cp -a ${BINARIES_DIR}/Image ${BINARIES_DIR}/system.bit ${BINARIES_DIR}/GenesysZU.dtb "${TMP_DIR}"
+
+mkimage -f "${TMP_DIR}"/image.its ${BINARIES_DIR}/image.ub
+rm -rf "${TMP_DIR}"
+
+support/scripts/genimage.sh -c board/digilent/genesys-zu/genimage.cfg
diff --git a/board/digilent/genesys-zu/psu_init_gpl.c b/board/digilent/genesys-zu/psu_init_gpl.c
new file mode 100644
index 0000000000..7227917baa
--- /dev/null
+++ b/board/digilent/genesys-zu/psu_init_gpl.c
@@ -0,0 +1,985 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
+ */
+
+#include <asm/arch/psu_init_gpl.h>
+#include <xil_io.h>
+
+static unsigned long psu_pll_init_data(void)
+{
+	psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E578C62U);
+	psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013500U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000002U);
+	psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
+	psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00016400U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFF5E0040, 0x00000001U);
+	psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
+	psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00015000U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000001U);
+	psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00015D00U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000002U);
+	psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
+	psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C82U);
+	psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00016400U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
+	mask_poll(0xFD1A0044, 0x00000004U);
+	psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
+
+	return 1;
+}
+
+static unsigned long psu_clock_init_data(void)
+{
+	psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U);
+	psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
+	psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E0064, 0x023F3F07U, 0x02010600U);
+	psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x02031900U);
+	psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
+	psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
+	psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0078, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E007C, 0x013F3F07U, 0x01010402U);
+	psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U);
+	psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
+	psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
+	psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
+	psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
+	psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011E02U);
+	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
+	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01011003U);
+	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01010F03U);
+	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
+	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000300U);
+	psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
+	psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
+	psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000303U);
+	psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
+	psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
+	psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_init_data(void)
+{
+	psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x41040010U);
+	psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
+	psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
+	psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
+	psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
+	psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00407310U);
+	psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
+	psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
+	psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
+	psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00718079U);
+	psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
+	psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
+	psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0038051FU);
+	psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x000200E5U);
+	psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00020000U);
+	psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00001F05U);
+	psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05140301U);
+	psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00080200U);
+	psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U);
+	psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x000806C0U);
+	psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x04190000U);
+	psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
+	psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
+	psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0E0E1F10U);
+	psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00030316U);
+	psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0506060BU);
+	psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x0050400CU);
+	psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x06030307U);
+	psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x05050303U);
+	psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
+	psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000505U);
+	psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030B05U);
+	psu_mask_write(0xFD070124, 0x40070F3FU, 0x00020209U);
+	psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x0E06010EU);
+	psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
+	psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x81000040U);
+	psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020162C4U);
+	psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04888207U);
+	psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U);
+	psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
+	psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
+	psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
+	psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
+	psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
+	psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000605U);
+	psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U);
+	psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
+	psu_mask_write(0xFD070204, 0x001F1F1FU, 0x001F0A0AU);
+	psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x01010100U);
+	psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x01010101U);
+	psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x080F0808U);
+	psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F080808U);
+	psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
+	psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000801U);
+	psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x08080808U);
+	psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000008U);
+	psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
+	psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
+	psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
+	psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
+	psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
+	psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
+	psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
+	psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
+	psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
+	psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
+	psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
+	psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
+	psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
+	psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
+	psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
+	psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
+	psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
+	psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
+	psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
+	psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
+	psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
+	psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F0DEC0U);
+	psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
+	psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
+	psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x3A21D110U);
+	psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xB5A41059U);
+	psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x02120000U);
+	psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04121U);
+	psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E0U);
+	psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040CU);
+	psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x05200C07U);
+	psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0008U);
+	psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0255U);
+	psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82550800U);
+	psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00F22B06U);
+	psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x002C0C07U);
+	psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0CU);
+	psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
+	psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
+	psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000100U);
+	psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000414U);
+	psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000301U);
+	psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000200U);
+	psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x000006C0U);
+	psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000419U);
+	psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
+	psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
+	psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U);
+	psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
+	psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
+	psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
+	psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12341000U);
+	psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
+	psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
+	psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
+	psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
+	psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0CEU);
+	psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF9032019U);
+	psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
+	psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008A4A58U);
+	psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000079DDU);
+	psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
+	psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
+	psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x00087BDBU);
+	psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B004U);
+	psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
+	psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
+	psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0x00000000U);
+	psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x3F000008U);
+	psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B03CU);
+	psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
+	psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
+	psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
+	psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
+	psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00B000U);
+	psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09095555U);
+	psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
+	psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x02120000U);
+	psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x02120000U);
+	psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x02120000U);
+	psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
+	psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x02120000U);
+	psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
+	psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70800000U);
+	psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
+	psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x22120000U);
+	psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
+	psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
+	psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
+	psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_qos_init_data(void)
+{
+	psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_mio_init_data(void)
+{
+	psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180020, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180024, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180030, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180038, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180040, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180044, 0x000000FEU, 0x00000080U);
+	psu_mask_write(0xFF180048, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF18004C, 0x000000FEU, 0x000000C0U);
+	psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180058, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000040U);
+	psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF180068, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180070, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180074, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180078, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180080, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180084, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180088, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180090, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180094, 0x000000FEU, 0x00000002U);
+	psu_mask_write(0xFF180098, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF18009C, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U);
+	psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
+	psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180100, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180104, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180108, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180110, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180114, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180118, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180120, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180124, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180128, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000004U);
+	psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U);
+	psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00040000U);
+	psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00B0203FU);
+	psu_mask_write(0xFF18020C, 0x00003FFFU, 0x0000000BU);
+	psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180144, 0x02FFD3FFU, 0x02DFD3FFU);
+	psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x02FFD3FFU);
+	psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x03FBFF81U);
+	psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFC0U);
+	psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
+	psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x02FC0FEFU);
+	psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x0004103FU);
+	psu_mask_write(0xFF180160, 0x03FBEFC0U, 0x03FBE000U);
+	psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
+	psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00FBFFBFU);
+	psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x0304A04AU);
+	psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x03000000U);
+	psu_mask_write(0xFF18017C, 0x0304A04AU, 0x03040040U);
+	psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_pre_init_data(void)
+{
+	psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
+
+	return 1;
+}
+
+static unsigned long psu_peripherals_init_data(void)
+{
+	psu_mask_write(0xFD1A0100, 0x0001007EU, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000C00U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
+	psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
+	psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
+	psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
+	psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
+	psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000008U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF5E0238, 0x00000006U, 0x00000000U);
+	psu_mask_write(0xFF000034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF010034, 0x000000FFU, 0x00000006U);
+	psu_mask_write(0xFF010018, 0x0000FFFFU, 0x0000007CU);
+	psu_mask_write(0xFF010000, 0x000001FFU, 0x00000017U);
+	psu_mask_write(0xFF010004, 0x000003FFU, 0x00000020U);
+	psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
+	psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
+	psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
+	psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
+	psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01C9C380U);
+	psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
+	return 1;
+}
+
+static unsigned long psu_serdes_init_data(void)
+{
+	psu_mask_write(0xFD410000, 0x0000001FU, 0x00000011U);
+	psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU);
+	psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000EU);
+	psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000EU);
+	psu_mask_write(0xFD402860, 0x00000082U, 0x00000002U);
+	psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
+	psu_mask_write(0xFD402868, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD40286C, 0x00000084U, 0x00000004U);
+	psu_mask_write(0xFD406094, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40A368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40A36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD40E368, 0x000000FFU, 0x00000058U);
+	psu_mask_write(0xFD40E36C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD402368, 0x000000FFU, 0x00000018U);
+	psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
+	psu_mask_write(0xFD406368, 0x000000FFU, 0x00000022U);
+	psu_mask_write(0xFD40636C, 0x00000007U, 0x00000004U);
+	psu_mask_write(0xFD402370, 0x000000FFU, 0x000000D3U);
+	psu_mask_write(0xFD402374, 0x000000FFU, 0x000000DAU);
+	psu_mask_write(0xFD402378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U);
+	psu_mask_write(0xFD406370, 0x000000FFU, 0x000000EDU);
+	psu_mask_write(0xFD406374, 0x000000FFU, 0x00000055U);
+	psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD40637C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40A370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD40A374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD40A378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40A37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD40E370, 0x000000FFU, 0x0000007CU);
+	psu_mask_write(0xFD40E374, 0x000000FFU, 0x00000033U);
+	psu_mask_write(0xFD40E378, 0x000000FFU, 0x00000002U);
+	psu_mask_write(0xFD40E37C, 0x00000033U, 0x00000030U);
+	psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
+	psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
+	psu_mask_write(0xFD40506C, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4040F4, 0x00000003U, 0x00000003U);
+	psu_mask_write(0xFD4050CC, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4018F8, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD4018FC, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU);
+	psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U);
+	psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
+	psu_mask_write(0xFD401900, 0x000000FFU, 0x00000096U);
+	psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
+	psu_mask_write(0xFD4058F8, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD4058FC, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD405990, 0x000000FFU, 0x00000010U);
+	psu_mask_write(0xFD405924, 0x000000FFU, 0x000000FEU);
+	psu_mask_write(0xFD405928, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405900, 0x000000FFU, 0x00000064U);
+	psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
+	psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
+	psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
+	psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
+	psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
+	psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
+	psu_mask_write(0xFD410010, 0x00000077U, 0x00000032U);
+	psu_mask_write(0xFD410014, 0x00000077U, 0x00000044U);
+	psu_mask_write(0xFD408CB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD40CCB4, 0x00000037U, 0x00000037U);
+	psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD4081D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD40C1D8, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U);
+	psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU);
+	psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U);
+	psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U);
+	psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U);
+	psu_mask_write(0xFD408CC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD40CCC0, 0x0000001FU, 0x00000000U);
+	psu_mask_write(0xFD408048, 0x000000FFU, 0x00000000U);
+	psu_mask_write(0xFD40C048, 0x000000FFU, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_resetout_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
+	psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00000800U, 0x00000000U);
+	psu_mask_write(0xFF9E0080, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF9E007C, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFF5E023C, 0x00000280U, 0x00000000U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U);
+	psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00000000U);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000000U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x00000000U);
+	psu_mask_write(0xFE20C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE20C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE20C11C, 0x00000600U, 0x00000600U);
+	psu_mask_write(0xFE20C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C200, 0x00023FFFU, 0x00022457U);
+	psu_mask_write(0xFE30C630, 0x003FFF00U, 0x00000000U);
+	psu_mask_write(0xFE30C12C, 0x00004000U, 0x00004000U);
+	psu_mask_write(0xFE30C11C, 0x00000400U, 0x00000400U);
+	psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
+	mask_poll(0xFD4023E4, 0x00000010U);
+	mask_poll(0xFD4063E4, 0x00000010U);
+	mask_poll(0xFD40E3E4, 0x00000010U);
+	psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184D1BU);
+	psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081906U);
+	psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
+	psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
+
+	return 1;
+}
+
+static unsigned long psu_resetin_init_data(void)
+{
+	psu_mask_write(0xFF5E023C, 0x00000540U, 0x00000540U);
+	psu_mask_write(0xFF5E023C, 0x00000A80U, 0x00000A80U);
+	psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U);
+	psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD4A0238, 0x0000000FU, 0x0000000AU);
+	psu_mask_write(0xFD4A0200, 0x00000002U, 0x00000002U);
+	psu_mask_write(0xFD1A0100, 0x00010000U, 0x00010000U);
+
+	return 1;
+}
+
+static unsigned long psu_afi_config(void)
+{
+	psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
+	psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
+	psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U);
+	psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
+	psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
+
+	return 1;
+}
+
+static unsigned long psu_ddr_phybringup_data(void)
+{
+	unsigned int regval = 0;
+	unsigned int pll_retry = 10;
+	unsigned int pll_locked = 0;
+
+	while ((pll_retry > 0) && (!pll_locked)) {
+		Xil_Out32(0xFD080004, 0x00040010);
+		Xil_Out32(0xFD080004, 0x00040011);
+
+		while ((Xil_In32(0xFD080030) & 0x1) != 1)
+			;
+		pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
+		    >> 31;
+		pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
+		    >> 16;
+		pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
+		    >> 16;
+		pll_retry--;
+	}
+	Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
+	if (!pll_locked)
+		return 0;
+
+	Xil_Out32(0xFD080004U, 0x00040063U);
+
+	while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
+		;
+	prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
+		;
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
+		;
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	Xil_Out32(0xFD080004, 0x0004FE01);
+	regval = Xil_In32(0xFD080030);
+	while (regval != 0x80000FFF)
+		regval = Xil_In32(0xFD080030);
+	regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
+	if (regval != 0)
+		return 0;
+
+	Xil_Out32(0xFD080200U, 0x100091C7U);
+	int cur_R006_tREFPRD;
+
+	cur_R006_tREFPRD = (Xil_In32(0xFD080018U) & 0x0003FFFFU) >> 0x00000000U;
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U);
+
+	Xil_Out32(0xFD080004, 0x00060001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80004001) != 0x80004001)
+		regval = Xil_In32(0xFD080030);
+
+	prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U);
+	prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U);
+	prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U);
+
+	Xil_Out32(0xFD080200U, 0x800091C7U);
+	prog_reg(0xFD080018, 0x3FFFF, 0x0, cur_R006_tREFPRD);
+
+	Xil_Out32(0xFD080004, 0x0000C001);
+	regval = Xil_In32(0xFD080030);
+	while ((regval & 0x80000C01) != 0x80000C01)
+		regval = Xil_In32(0xFD080030);
+
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+	return 1;
+}
+
+static int serdes_enb_coarse_saturation(void)
+{
+	Xil_Out32(0xFD402094, 0x00000010);
+	Xil_Out32(0xFD406094, 0x00000010);
+	Xil_Out32(0xFD40A094, 0x00000010);
+	Xil_Out32(0xFD40E094, 0x00000010);
+	return 1;
+}
+
+static int serdes_fixcal_code(void)
+{
+	int maskstatus = 1;
+	unsigned int rdata = 0;
+	unsigned int match_pmos_code[23];
+	unsigned int match_nmos_code[23];
+	unsigned int match_ical_code[7];
+	unsigned int match_rcal_code[7];
+	unsigned int p_code = 0;
+	unsigned int n_code = 0;
+	unsigned int i_code = 0;
+	unsigned int r_code = 0;
+	unsigned int repeat_count = 0;
+	unsigned int L3_TM_CALIB_DIG20 = 0;
+	unsigned int L3_TM_CALIB_DIG19 = 0;
+	unsigned int L3_TM_CALIB_DIG18 = 0;
+	unsigned int L3_TM_CALIB_DIG16 = 0;
+	unsigned int L3_TM_CALIB_DIG15 = 0;
+	unsigned int L3_TM_CALIB_DIG14 = 0;
+	int i = 0;
+
+	rdata = Xil_In32(0xFD40289C);
+	rdata = rdata & ~0x03;
+	rdata = rdata | 0x1;
+	Xil_Out32(0xFD40289C, rdata);
+	int count = 0;
+	do {
+		if (count == 1100000)
+			break;
+		rdata = Xil_In32(0xFD402B1C);
+		count++;
+	} while ((rdata & 0x0000000E) != 0x0000000E);
+
+	for (i = 0; i < 23; i++) {
+		match_pmos_code[i] = 0;
+		match_nmos_code[i] = 0;
+	}
+	for (i = 0; i < 7; i++) {
+		match_ical_code[i] = 0;
+		match_rcal_code[i] = 0;
+	}
+
+	do {
+		Xil_Out32(0xFD410010, 0x00000000);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		Xil_Out32(0xFD410010, 0x00000001);
+		Xil_Out32(0xFD410014, 0x00000000);
+
+		maskstatus = mask_poll(0xFD40EF14, 0x2);
+		if (maskstatus == 0) {
+			xil_printf("#SERDES initialization timed out\n\r");
+			return maskstatus;
+		}
+
+		p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
+		n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
+		;
+		i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
+		r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
+		;
+
+		if (p_code >= 0x26 && p_code <= 0x3C)
+			match_pmos_code[p_code - 0x26] += 1;
+
+		if (n_code >= 0x26 && n_code <= 0x3C)
+			match_nmos_code[n_code - 0x26] += 1;
+
+		if (i_code >= 0xC && i_code <= 0x12)
+			match_ical_code[i_code - 0xC] += 1;
+
+		if (r_code >= 0x6 && r_code <= 0xC)
+			match_rcal_code[r_code - 0x6] += 1;
+
+	} while (repeat_count++ < 10);
+
+	for (i = 0; i < 23; i++) {
+		if (match_pmos_code[i] >= match_pmos_code[0]) {
+			match_pmos_code[0] = match_pmos_code[i];
+			p_code = 0x26 + i;
+		}
+		if (match_nmos_code[i] >= match_nmos_code[0]) {
+			match_nmos_code[0] = match_nmos_code[i];
+			n_code = 0x26 + i;
+		}
+	}
+
+	for (i = 0; i < 7; i++) {
+		if (match_ical_code[i] >= match_ical_code[0]) {
+			match_ical_code[0] = match_ical_code[i];
+			i_code = 0xC + i;
+		}
+		if (match_rcal_code[i] >= match_rcal_code[0]) {
+			match_rcal_code[0] = match_rcal_code[i];
+			r_code = 0x6 + i;
+		}
+	}
+
+	L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
+	L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
+
+	L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
+	L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6)
+	    | 0x20 | 0x4 | ((n_code >> 3) & 0x3);
+
+	L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
+	L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
+
+	L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
+	L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
+	L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7)
+	    | 0x40 | 0x8 | ((i_code >> 1) & 0x7);
+
+	L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
+	L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
+
+	Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
+	Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
+	Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
+	Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
+	Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
+	Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
+	return maskstatus;
+}
+
+static int init_serdes(void)
+{
+	int status = 1;
+
+	status &= psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+	status &= psu_serdes_init_data();
+	status &= psu_resetout_init_data();
+
+	return status;
+}
+
+static void init_peripheral(void)
+{
+	psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU);
+}
+
+int psu_init(void)
+{
+	int status = 1;
+
+	status &= psu_mio_init_data();
+	status &= psu_peripherals_pre_init_data();
+	status &= psu_pll_init_data();
+	status &= psu_clock_init_data();
+	status &= psu_ddr_init_data();
+	status &= psu_ddr_phybringup_data();
+	status &= psu_peripherals_init_data();
+	status &= init_serdes();
+	init_peripheral();
+
+	status &= psu_afi_config();
+	psu_ddr_qos_init_data();
+
+	if (status == 0)
+		return 1;
+	return 0;
+}
diff --git a/board/digilent/genesys-zu/psu_init_gpl.h b/board/digilent/genesys-zu/psu_init_gpl.h
new file mode 100644
index 0000000000..ce67e015d9
--- /dev/null
+++ b/board/digilent/genesys-zu/psu_init_gpl.h
@@ -0,0 +1,37545 @@
+/******************************************************************************
+*
+* Copyright (C) 2010-2019 <Xilinx Inc.>
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see <http://www.gnu.org/licenses/>
+* 
+* 
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file psu_init_gpl.h
+*
+* This file is automatically generated
+*
+*****************************************************************************/
+
+
+#undef CRL_APB_RPLL_CFG_OFFSET 
+#define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_IOPLL_CFG_OFFSET 
+#define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
+#undef CRF_APB_APLL_CFG_OFFSET 
+#define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
+#undef CRF_APB_DPLL_CFG_OFFSET 
+#define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
+#undef CRF_APB_VPLL_CFG_OFFSET 
+#define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
+
+/*
+* PLL loop filter resistor control
+*/
+#undef CRL_APB_RPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_RPLL_CFG_RES_SHIFT 
+#undef CRL_APB_RPLL_CFG_RES_MASK 
+#define CRL_APB_RPLL_CFG_RES_DEFVAL                            0x00000000
+#define CRL_APB_RPLL_CFG_RES_SHIFT                             0
+#define CRL_APB_RPLL_CFG_RES_MASK                              0x0000000FU
+
+/*
+* PLL charge pump control
+*/
+#undef CRL_APB_RPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_RPLL_CFG_CP_SHIFT 
+#undef CRL_APB_RPLL_CFG_CP_MASK 
+#define CRL_APB_RPLL_CFG_CP_DEFVAL                             0x00000000
+#define CRL_APB_RPLL_CFG_CP_SHIFT                              5
+#define CRL_APB_RPLL_CFG_CP_MASK                               0x000001E0U
+
+/*
+* PLL loop filter high frequency capacitor control
+*/
+#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_RPLL_CFG_LFHF_MASK 
+#define CRL_APB_RPLL_CFG_LFHF_DEFVAL                           0x00000000
+#define CRL_APB_RPLL_CFG_LFHF_SHIFT                            10
+#define CRL_APB_RPLL_CFG_LFHF_MASK                             0x00000C00U
+
+/*
+* Lock circuit counter setting
+*/
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                        13
+#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
+
+/*
+* Lock circuit configuration settings for lock windowsize
+*/
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                        25
+#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
+
+/*
+* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
+    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
+    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+*/
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
+#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                        20
+#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                         0x00700000U
+
+/*
+* The integer portion of the feedback divider to the PLL
+*/
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                         0x00012C09
+#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                          8
+#define CRL_APB_RPLL_CTRL_FBDIV_MASK                           0x00007F00U
+
+/*
+* This turns on the divide by 2 that is inside of the PLL. This does not c
+    * hange the VCO frequency, just the output frequency
+*/
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                          0x00012C09
+#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                           16
+#define CRL_APB_RPLL_CTRL_DIV2_MASK                            0x00010000U
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                         0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                          0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* RPLL is locked
+*/
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                    0x00000018
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                     1
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                      0x00000002U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                        0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                         3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Divisor value for this clock.
+*/
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL               0x00000400
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                8
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                 0x00003F00U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                   0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                    16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                   0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                    8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                     0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                      0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                     0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                      24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* PLL loop filter resistor control
+*/
+#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_RES_SHIFT 
+#undef CRL_APB_IOPLL_CFG_RES_MASK 
+#define CRL_APB_IOPLL_CFG_RES_DEFVAL                           0x00000000
+#define CRL_APB_IOPLL_CFG_RES_SHIFT                            0
+#define CRL_APB_IOPLL_CFG_RES_MASK                             0x0000000FU
+
+/*
+* PLL charge pump control
+*/
+#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_CP_SHIFT 
+#undef CRL_APB_IOPLL_CFG_CP_MASK 
+#define CRL_APB_IOPLL_CFG_CP_DEFVAL                            0x00000000
+#define CRL_APB_IOPLL_CFG_CP_SHIFT                             5
+#define CRL_APB_IOPLL_CFG_CP_MASK                              0x000001E0U
+
+/*
+* PLL loop filter high frequency capacitor control
+*/
+#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LFHF_MASK 
+#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                          0x00000000
+#define CRL_APB_IOPLL_CFG_LFHF_SHIFT                           10
+#define CRL_APB_IOPLL_CFG_LFHF_MASK                            0x00000C00U
+
+/*
+* Lock circuit counter setting
+*/
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                      0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                       13
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                        0x007FE000U
+
+/*
+* Lock circuit configuration settings for lock windowsize
+*/
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                      0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                       25
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                        0xFE000000U
+
+/*
+* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
+    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
+    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+*/
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                      0x00012C09
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                       20
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                        0x00700000U
+
+/*
+* The integer portion of the feedback divider to the PLL
+*/
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                        0x00012C09
+#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                         8
+#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                          0x00007F00U
+
+/*
+* This turns on the divide by 2 that is inside of the PLL. This does not c
+    * hange the VCO frequency, just the output frequency
+*/
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                         0x00012C09
+#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                          16
+#define CRL_APB_IOPLL_CTRL_DIV2_MASK                           0x00010000U
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                        0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                         0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                          0x00000001U
+
+/*
+* IOPLL is locked
+*/
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                   0x00000018
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                    0
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                     0x00000001U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                       0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                        3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                         0x00000008U
+
+/*
+* Divisor value for this clock.
+*/
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL              0x00000400
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT               8
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                0x00003F00U
+
+/*
+* PLL loop filter resistor control
+*/
+#undef CRF_APB_APLL_CFG_RES_DEFVAL 
+#undef CRF_APB_APLL_CFG_RES_SHIFT 
+#undef CRF_APB_APLL_CFG_RES_MASK 
+#define CRF_APB_APLL_CFG_RES_DEFVAL                            0x00000000
+#define CRF_APB_APLL_CFG_RES_SHIFT                             0
+#define CRF_APB_APLL_CFG_RES_MASK                              0x0000000FU
+
+/*
+* PLL charge pump control
+*/
+#undef CRF_APB_APLL_CFG_CP_DEFVAL 
+#undef CRF_APB_APLL_CFG_CP_SHIFT 
+#undef CRF_APB_APLL_CFG_CP_MASK 
+#define CRF_APB_APLL_CFG_CP_DEFVAL                             0x00000000
+#define CRF_APB_APLL_CFG_CP_SHIFT                              5
+#define CRF_APB_APLL_CFG_CP_MASK                               0x000001E0U
+
+/*
+* PLL loop filter high frequency capacitor control
+*/
+#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_APLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_APLL_CFG_LFHF_MASK 
+#define CRF_APB_APLL_CFG_LFHF_DEFVAL                           0x00000000
+#define CRF_APB_APLL_CFG_LFHF_SHIFT                            10
+#define CRF_APB_APLL_CFG_LFHF_MASK                             0x00000C00U
+
+/*
+* Lock circuit counter setting
+*/
+#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
+#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                        13
+#define CRF_APB_APLL_CFG_LOCK_CNT_MASK                         0x007FE000U
+
+/*
+* Lock circuit configuration settings for lock windowsize
+*/
+#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
+#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                        25
+#define CRF_APB_APLL_CFG_LOCK_DLY_MASK                         0xFE000000U
+
+/*
+* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
+    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
+    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+*/
+#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                       0x00012C09
+#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                        20
+#define CRF_APB_APLL_CTRL_PRE_SRC_MASK                         0x00700000U
+
+/*
+* The integer portion of the feedback divider to the PLL
+*/
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                         0x00012C09
+#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                          8
+#define CRF_APB_APLL_CTRL_FBDIV_MASK                           0x00007F00U
+
+/*
+* This turns on the divide by 2 that is inside of the PLL. This does not c
+    * hange the VCO frequency, just the output frequency
+*/
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                          0x00012C09
+#define CRF_APB_APLL_CTRL_DIV2_SHIFT                           16
+#define CRF_APB_APLL_CTRL_DIV2_MASK                            0x00010000U
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                         0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_APLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* APLL is locked
+*/
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                    0x00000038
+#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                     0
+#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                      0x00000001U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                        0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Divisor value for this clock.
+*/
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
+
+/*
+* PLL loop filter resistor control
+*/
+#undef CRF_APB_DPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_DPLL_CFG_RES_SHIFT 
+#undef CRF_APB_DPLL_CFG_RES_MASK 
+#define CRF_APB_DPLL_CFG_RES_DEFVAL                            0x00000000
+#define CRF_APB_DPLL_CFG_RES_SHIFT                             0
+#define CRF_APB_DPLL_CFG_RES_MASK                              0x0000000FU
+
+/*
+* PLL charge pump control
+*/
+#undef CRF_APB_DPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_DPLL_CFG_CP_SHIFT 
+#undef CRF_APB_DPLL_CFG_CP_MASK 
+#define CRF_APB_DPLL_CFG_CP_DEFVAL                             0x00000000
+#define CRF_APB_DPLL_CFG_CP_SHIFT                              5
+#define CRF_APB_DPLL_CFG_CP_MASK                               0x000001E0U
+
+/*
+* PLL loop filter high frequency capacitor control
+*/
+#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_DPLL_CFG_LFHF_MASK 
+#define CRF_APB_DPLL_CFG_LFHF_DEFVAL                           0x00000000
+#define CRF_APB_DPLL_CFG_LFHF_SHIFT                            10
+#define CRF_APB_DPLL_CFG_LFHF_MASK                             0x00000C00U
+
+/*
+* Lock circuit counter setting
+*/
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                        13
+#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
+
+/*
+* Lock circuit configuration settings for lock windowsize
+*/
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                        25
+#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
+
+/*
+* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
+    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
+    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+*/
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                       0x00002C09
+#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                        20
+#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                         0x00700000U
+
+/*
+* The integer portion of the feedback divider to the PLL
+*/
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                         0x00002C09
+#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                          8
+#define CRF_APB_DPLL_CTRL_FBDIV_MASK                           0x00007F00U
+
+/*
+* This turns on the divide by 2 that is inside of the PLL. This does not c
+    * hange the VCO frequency, just the output frequency
+*/
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                          0x00002C09
+#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                           16
+#define CRF_APB_DPLL_CTRL_DIV2_MASK                            0x00010000U
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                         0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* DPLL is locked
+*/
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                    0x00000038
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                     1
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                      0x00000002U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                        0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Divisor value for this clock.
+*/
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
+
+/*
+* PLL loop filter resistor control
+*/
+#undef CRF_APB_VPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_VPLL_CFG_RES_SHIFT 
+#undef CRF_APB_VPLL_CFG_RES_MASK 
+#define CRF_APB_VPLL_CFG_RES_DEFVAL                            0x00000000
+#define CRF_APB_VPLL_CFG_RES_SHIFT                             0
+#define CRF_APB_VPLL_CFG_RES_MASK                              0x0000000FU
+
+/*
+* PLL charge pump control
+*/
+#undef CRF_APB_VPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_VPLL_CFG_CP_SHIFT 
+#undef CRF_APB_VPLL_CFG_CP_MASK 
+#define CRF_APB_VPLL_CFG_CP_DEFVAL                             0x00000000
+#define CRF_APB_VPLL_CFG_CP_SHIFT                              5
+#define CRF_APB_VPLL_CFG_CP_MASK                               0x000001E0U
+
+/*
+* PLL loop filter high frequency capacitor control
+*/
+#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_VPLL_CFG_LFHF_MASK 
+#define CRF_APB_VPLL_CFG_LFHF_DEFVAL                           0x00000000
+#define CRF_APB_VPLL_CFG_LFHF_SHIFT                            10
+#define CRF_APB_VPLL_CFG_LFHF_MASK                             0x00000C00U
+
+/*
+* Lock circuit counter setting
+*/
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                       0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                        13
+#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                         0x007FE000U
+
+/*
+* Lock circuit configuration settings for lock windowsize
+*/
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                       0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                        25
+#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                         0xFE000000U
+
+/*
+* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
+    * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
+    * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+*/
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                       0x00012809
+#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                        20
+#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                         0x00700000U
+
+/*
+* The integer portion of the feedback divider to the PLL
+*/
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                         0x00012809
+#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                          8
+#define CRF_APB_VPLL_CTRL_FBDIV_MASK                           0x00007F00U
+
+/*
+* This turns on the divide by 2 that is inside of the PLL. This does not c
+    * hange the VCO frequency, just the output frequency
+*/
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                          0x00012809
+#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                           16
+#define CRF_APB_VPLL_CTRL_DIV2_MASK                            0x00010000U
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* Asserts Reset to the PLL. When asserting reset, the PLL must already be
+    * in BYPASS.
+*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                         0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                          0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                           0x00000001U
+
+/*
+* VPLL is locked
+*/
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                    0x00000038
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                     2
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                      0x00000004U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*
+* Bypasses the PLL clock. The usable clock will be determined from the POS
+    * T_SRC field. (This signal may only be toggled after 4 cycles of the old
+    * clock and 4 cycles of the new clock. This is not usually an issue, but d
+    * esigners must be aware.)
+*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                        0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                         3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                          0x00000008U
+
+/*
+* Divisor value for this clock.
+*/
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL               0x00000400
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                8
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                 0x00003F00U
+#undef CRL_APB_GEM0_REF_CTRL_OFFSET 
+#define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
+#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 
+#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
+#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET                                           0XFF5E0064
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
+#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET 
+#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
+#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
+#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
+#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
+#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
+#undef CRL_APB_SPI0_REF_CTRL_OFFSET 
+#define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
+#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
+#undef CRL_APB_PCAP_CTRL_OFFSET 
+#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
+#undef CRL_APB_PL0_REF_CTRL_OFFSET 
+#define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
+#undef CRF_APB_SATA_REF_CTRL_OFFSET 
+#define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
+#undef CRF_APB_ACPU_CTRL_OFFSET 
+#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
+#undef CRF_APB_DDR_CTRL_OFFSET 
+#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
+#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
+#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 
+#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
+#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 
+#define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
+#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 
+#define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
+
+/*
+* Clock active for the RX channel
+*/
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                 0x00002500
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                  26
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                   0x04000000U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                    0x00002500
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                     25
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                      0x02000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                  0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                   16
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                  0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                    0x00002500
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL               0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                8
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                 0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                 0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                  0
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                   0x00000007U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL               0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                16
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                 0x003F0000U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                 0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                  24
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                   0x01000000U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                 25
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                  0x02000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL              0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT               16
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL              0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT               8
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                 0
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                  0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL                0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT                 25
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK                  0x02000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL              0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT               16
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK                0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL              0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT               8
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK                0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL                0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT                 0
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK                  0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL               0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                25
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                 0x02000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL             0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT              16
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK               0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL             0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT              8
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK               0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL               0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                0
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                 0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                    0x01000800
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                     24
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                  0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                   16
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                  0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                    0x01000800
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                   0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                    24
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                 0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                  16
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                 0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                  8
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                   0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                    0
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
+    * [51] 1: MIO [76]
+*/
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL         0x00000000
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT          17
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK           0x00020000U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                   0x01001800
+#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                    24
+#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                  16
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                  8
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                    0
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                   0x01001800
+#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                    24
+#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                 0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                  16
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                   0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                 0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                  8
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                   0x01001800
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                    0
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                    0x01000500
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                     24
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                  0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                   16
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                    0x01000500
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                     24
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                  0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                   16
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                    0x01001800
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                     24
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                  0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                   16
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                    0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                  0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                    0x01001800
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Turing this off will shut down the OCM, some parts of the APM, and preve
+    * nt transactions going from the FPD to the LPD and could lead to system h
+    * ang
+*/
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                      0x03000600
+#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                       24
+#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                        0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                    0x03000600
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                     8
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                      0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                      0x03000600
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                       0
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                        0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                  0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                   24
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                    0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                 8
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                  0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                   0
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                        0x00001500
+#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                         24
+#define CRL_APB_PCAP_CTRL_CLKACT_MASK                          0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                      0x00001500
+#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                       8
+#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                        0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                        0x00001500
+#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                         0
+#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                          0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                  0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                   24
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                    0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                 8
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                  0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                  0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                   0
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                    0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                   0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                    24
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                 0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                  8
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                   0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                    0
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                     0x01002000
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                      24
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                   0x01002000
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                    8
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                     0x01002000
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                      0
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                    0x00002000
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                     24
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                  0x00002000
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                    0x00002000
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                     0x00052000
+#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                      24
+#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                   0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                    16
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                   0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                    8
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                     0x00052000
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                      0
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                   0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                    16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                     0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                   0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                    8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
+    * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    *  usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                     0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                      0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                     0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                      24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
+    *  of the old clock and 4 cycles of the new clock. This is not usually an
+    * issue, but designers must be aware.)
+*/
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                     0x00000000
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                      0
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* 6 bit divider
+*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL             0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT              8
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK               0x00003F00U
+
+/*
+* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
+    *  only be toggled after 4 cycles of the old clock and 4 cycles of the new
+    *  clock. This is not usually an issue, but designers must be aware.)
+*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL               0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                0
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                 0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL               0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                24
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                 0x01000000U
+
+/*
+* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog
+    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
+    *  is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                    0x01001600
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                    0x01001600
+#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                     24
+#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                  0x01001600
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL              0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT               16
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL              0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT               8
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                0x00003F00U
+
+/*
+* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
+    * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
+    * les of the new clock. This is not usually an issue, but designers must b
+    * e aware.)
+*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                 0
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                  0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                 24
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                  0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL              0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT               16
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL              0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT               8
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                0x00003F00U
+
+/*
+* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
+    * his signal may only be toggled after 4 cycles of the old clock and 4 cyc
+    * les of the new clock. This is not usually an issue, but designers must b
+    * e aware.)
+*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                 0
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                  0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                 24
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                  0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                 16
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                  0x003F0000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                 8
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                  0x00003F00U
+
+/*
+* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg
+    * led after 4 cycles of the old clock and 4 cycles of the new clock. This
+    * is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                  0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                   0
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                    0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                  0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                   24
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                    0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                      0x03000400
+#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                       8
+#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                        0x00003F00U
+
+/*
+* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft
+    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    * usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                        0x03000400
+#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                         0
+#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                          0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock. For the half spee
+    * d APU Clock
+*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                   0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                    25
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                     0x02000000U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock. For the full spee
+    * d ACPUX Clock. This will shut off the high speed clock to the entire APU
+*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                   0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                    24
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                   0x01002500
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                    8
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
+    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
+    *  is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                     0x01002500
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                      0
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                     0x01002500
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                      24
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                       0x01000500
+#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                        8
+#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                         0x00003F00U
+
+/*
+* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles
+    * of the old clock and 4 cycles of the new clock. This is not usually an i
+    * ssue, but designers must be aware.)
+*/
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                         0x01000500
+#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                          0
+#define CRF_APB_DDR_CTRL_SRCSEL_MASK                           0x00000007U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                   0x00001500
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                    8
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                     0x00003F00U
+
+/*
+* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog
+    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
+    *  is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                      0
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                       0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock, which will stop c
+    * lock for GPU (and both Pixel Processors).
+*/
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                      24
+#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                       0x01000000U
+
+/*
+* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
+    * k only to this Pixel Processor
+*/
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                 0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                  25
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                   0x02000000U
+
+/*
+* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc
+    * k only to this Pixel Processor
+*/
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                 0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                  26
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                   0x04000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                  0x01000500
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                   8
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                    0x00003F00U
+
+/*
+* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
+    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    * usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                    0x01000500
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                     0
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                      0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                    0x01000500
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                     24
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                      0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                 0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                  8
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
+    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    * usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                   0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                    0
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                   0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                    24
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                     0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                 8
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                  0x00003F00U
+
+/*
+* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft
+    * er 4 cycles of the old clock and 4 cycles of the new clock. This is not
+    * usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                  0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                   0
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                    0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                  0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                   24
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                    0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL               0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                8
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                 0x00003F00U
+
+/*
+* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog
+    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
+    *  is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                 0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                  0
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                   0x00000007U
+
+/*
+* Clock active signal. Switch to 0 to disable the clock
+*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                 0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                  24
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                   0x01000000U
+
+/*
+* 6 bit divider
+*/
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                 0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                  8
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                   0x00003F00U
+
+/*
+* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog
+    * gled after 4 cycles of the old clock and 4 cycles of the new clock. This
+    *  is not usually an issue, but designers must be aware.)
+*/
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                   0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                    0
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                     0x00000007U
+
+/*
+* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se
+    * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5
+    *  clock for the APB interface of TTC0
+*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL               0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                0
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                 0x00000003U
+
+/*
+* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se
+    * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5
+    *  clock for the APB interface of TTC1
+*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL               0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                2
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                 0x0000000CU
+
+/*
+* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se
+    * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5
+    *  clock for the APB interface of TTC2
+*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL               0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                4
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                 0x00000030U
+
+/*
+* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se
+    * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5
+    *  clock for the APB interface of TTC3
+*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL               0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                6
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                 0x000000C0U
+
+/*
+* System watchdog timer clock source selection: 0: Internal APB clock 1: E
+    * xternal (PL clock via EMIO or Pinout clock via MIO)
+*/
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U
+
+/*
+* System watchdog timer clock source selection: 0: internal clock APB cloc
+    * k 1: external clock from PL via EMIO, or from pinout via MIO
+*/
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                     0x00000000
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                      0
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                       0x00000001U
+
+/*
+* System watchdog timer clock source selection: 0: internal clock APB cloc
+    * k 1: external clock pss_ref_clk
+*/
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL              0x00000000
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT               0
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                0x00000001U
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDRC_MSTR_OFFSET 
+#define DDRC_MSTR_OFFSET                                                           0XFD070000
+#undef DDRC_MRCTRL0_OFFSET 
+#define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
+#undef DDRC_DERATEEN_OFFSET 
+#define DDRC_DERATEEN_OFFSET                                                       0XFD070020
+#undef DDRC_DERATEINT_OFFSET 
+#define DDRC_DERATEINT_OFFSET                                                      0XFD070024
+#undef DDRC_PWRCTL_OFFSET 
+#define DDRC_PWRCTL_OFFSET                                                         0XFD070030
+#undef DDRC_PWRTMG_OFFSET 
+#define DDRC_PWRTMG_OFFSET                                                         0XFD070034
+#undef DDRC_RFSHCTL0_OFFSET 
+#define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
+#undef DDRC_RFSHCTL1_OFFSET 
+#define DDRC_RFSHCTL1_OFFSET                                                       0XFD070054
+#undef DDRC_RFSHCTL3_OFFSET 
+#define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
+#undef DDRC_RFSHTMG_OFFSET 
+#define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
+#undef DDRC_ECCCFG0_OFFSET 
+#define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
+#undef DDRC_ECCCFG1_OFFSET 
+#define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
+#undef DDRC_CRCPARCTL1_OFFSET 
+#define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
+#undef DDRC_CRCPARCTL2_OFFSET 
+#define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
+#undef DDRC_INIT0_OFFSET 
+#define DDRC_INIT0_OFFSET                                                          0XFD0700D0
+#undef DDRC_INIT1_OFFSET 
+#define DDRC_INIT1_OFFSET                                                          0XFD0700D4
+#undef DDRC_INIT2_OFFSET 
+#define DDRC_INIT2_OFFSET                                                          0XFD0700D8
+#undef DDRC_INIT3_OFFSET 
+#define DDRC_INIT3_OFFSET                                                          0XFD0700DC
+#undef DDRC_INIT4_OFFSET 
+#define DDRC_INIT4_OFFSET                                                          0XFD0700E0
+#undef DDRC_INIT5_OFFSET 
+#define DDRC_INIT5_OFFSET                                                          0XFD0700E4
+#undef DDRC_INIT6_OFFSET 
+#define DDRC_INIT6_OFFSET                                                          0XFD0700E8
+#undef DDRC_INIT7_OFFSET 
+#define DDRC_INIT7_OFFSET                                                          0XFD0700EC
+#undef DDRC_DIMMCTL_OFFSET 
+#define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
+#undef DDRC_RANKCTL_OFFSET 
+#define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
+#undef DDRC_DRAMTMG0_OFFSET 
+#define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
+#undef DDRC_DRAMTMG1_OFFSET 
+#define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
+#undef DDRC_DRAMTMG2_OFFSET 
+#define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
+#undef DDRC_DRAMTMG3_OFFSET 
+#define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
+#undef DDRC_DRAMTMG4_OFFSET 
+#define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
+#undef DDRC_DRAMTMG5_OFFSET 
+#define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
+#undef DDRC_DRAMTMG6_OFFSET 
+#define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
+#undef DDRC_DRAMTMG7_OFFSET 
+#define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
+#undef DDRC_DRAMTMG8_OFFSET 
+#define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
+#undef DDRC_DRAMTMG9_OFFSET 
+#define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
+#undef DDRC_DRAMTMG11_OFFSET 
+#define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
+#undef DDRC_DRAMTMG12_OFFSET 
+#define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
+#undef DDRC_ZQCTL0_OFFSET 
+#define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
+#undef DDRC_ZQCTL1_OFFSET 
+#define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
+#undef DDRC_DFITMG0_OFFSET 
+#define DDRC_DFITMG0_OFFSET                                                        0XFD070190
+#undef DDRC_DFITMG1_OFFSET 
+#define DDRC_DFITMG1_OFFSET                                                        0XFD070194
+#undef DDRC_DFILPCFG0_OFFSET 
+#define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
+#undef DDRC_DFILPCFG1_OFFSET 
+#define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
+#undef DDRC_DFIUPD0_OFFSET 
+#define DDRC_DFIUPD0_OFFSET                                                        0XFD0701A0
+#undef DDRC_DFIUPD1_OFFSET 
+#define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
+#undef DDRC_DFIMISC_OFFSET 
+#define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
+#undef DDRC_DFITMG2_OFFSET 
+#define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
+#undef DDRC_DBICTL_OFFSET 
+#define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
+#undef DDRC_ADDRMAP0_OFFSET 
+#define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
+#undef DDRC_ADDRMAP1_OFFSET 
+#define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
+#undef DDRC_ADDRMAP2_OFFSET 
+#define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
+#undef DDRC_ADDRMAP3_OFFSET 
+#define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
+#undef DDRC_ADDRMAP4_OFFSET 
+#define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
+#undef DDRC_ADDRMAP5_OFFSET 
+#define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
+#undef DDRC_ADDRMAP6_OFFSET 
+#define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
+#undef DDRC_ADDRMAP7_OFFSET 
+#define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
+#undef DDRC_ADDRMAP8_OFFSET 
+#define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
+#undef DDRC_ADDRMAP9_OFFSET 
+#define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
+#undef DDRC_ADDRMAP10_OFFSET 
+#define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
+#undef DDRC_ADDRMAP11_OFFSET 
+#define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
+#undef DDRC_ODTCFG_OFFSET 
+#define DDRC_ODTCFG_OFFSET                                                         0XFD070240
+#undef DDRC_ODTMAP_OFFSET 
+#define DDRC_ODTMAP_OFFSET                                                         0XFD070244
+#undef DDRC_SCHED_OFFSET 
+#define DDRC_SCHED_OFFSET                                                          0XFD070250
+#undef DDRC_PERFLPR1_OFFSET 
+#define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
+#undef DDRC_PERFWR1_OFFSET 
+#define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
+#undef DDRC_DQMAP0_OFFSET 
+#define DDRC_DQMAP0_OFFSET                                                         0XFD070280
+#undef DDRC_DQMAP1_OFFSET 
+#define DDRC_DQMAP1_OFFSET                                                         0XFD070284
+#undef DDRC_DQMAP2_OFFSET 
+#define DDRC_DQMAP2_OFFSET                                                         0XFD070288
+#undef DDRC_DQMAP3_OFFSET 
+#define DDRC_DQMAP3_OFFSET                                                         0XFD07028C
+#undef DDRC_DQMAP4_OFFSET 
+#define DDRC_DQMAP4_OFFSET                                                         0XFD070290
+#undef DDRC_DQMAP5_OFFSET 
+#define DDRC_DQMAP5_OFFSET                                                         0XFD070294
+#undef DDRC_DBG0_OFFSET 
+#define DDRC_DBG0_OFFSET                                                           0XFD070300
+#undef DDRC_DBGCMD_OFFSET 
+#define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
+#undef DDRC_SWCTL_OFFSET 
+#define DDRC_SWCTL_OFFSET                                                          0XFD070320
+#undef DDRC_PCCFG_OFFSET 
+#define DDRC_PCCFG_OFFSET                                                          0XFD070400
+#undef DDRC_PCFGR_0_OFFSET 
+#define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
+#undef DDRC_PCFGW_0_OFFSET 
+#define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
+#undef DDRC_PCTRL_0_OFFSET 
+#define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
+#undef DDRC_PCFGQOS0_0_OFFSET 
+#define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
+#undef DDRC_PCFGQOS1_0_OFFSET 
+#define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
+#undef DDRC_PCFGR_1_OFFSET 
+#define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
+#undef DDRC_PCFGW_1_OFFSET 
+#define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
+#undef DDRC_PCTRL_1_OFFSET 
+#define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
+#undef DDRC_PCFGQOS0_1_OFFSET 
+#define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
+#undef DDRC_PCFGQOS1_1_OFFSET 
+#define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
+#undef DDRC_PCFGR_2_OFFSET 
+#define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
+#undef DDRC_PCFGW_2_OFFSET 
+#define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
+#undef DDRC_PCTRL_2_OFFSET 
+#define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
+#undef DDRC_PCFGQOS0_2_OFFSET 
+#define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
+#undef DDRC_PCFGQOS1_2_OFFSET 
+#define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
+#undef DDRC_PCFGR_3_OFFSET 
+#define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
+#undef DDRC_PCFGW_3_OFFSET 
+#define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
+#undef DDRC_PCTRL_3_OFFSET 
+#define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
+#undef DDRC_PCFGQOS0_3_OFFSET 
+#define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
+#undef DDRC_PCFGQOS1_3_OFFSET 
+#define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
+#undef DDRC_PCFGWQOS0_3_OFFSET 
+#define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
+#undef DDRC_PCFGWQOS1_3_OFFSET 
+#define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
+#undef DDRC_PCFGR_4_OFFSET 
+#define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
+#undef DDRC_PCFGW_4_OFFSET 
+#define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
+#undef DDRC_PCTRL_4_OFFSET 
+#define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
+#undef DDRC_PCFGQOS0_4_OFFSET 
+#define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
+#undef DDRC_PCFGQOS1_4_OFFSET 
+#define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
+#undef DDRC_PCFGWQOS0_4_OFFSET 
+#define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
+#undef DDRC_PCFGWQOS1_4_OFFSET 
+#define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
+#undef DDRC_PCFGR_5_OFFSET 
+#define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
+#undef DDRC_PCFGW_5_OFFSET 
+#define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
+#undef DDRC_PCTRL_5_OFFSET 
+#define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
+#undef DDRC_PCFGQOS0_5_OFFSET 
+#define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
+#undef DDRC_PCFGQOS1_5_OFFSET 
+#define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
+#undef DDRC_PCFGWQOS0_5_OFFSET 
+#define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
+#undef DDRC_PCFGWQOS1_5_OFFSET 
+#define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
+#undef DDRC_SARBASE0_OFFSET 
+#define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
+#undef DDRC_SARSIZE0_OFFSET 
+#define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
+#undef DDRC_SARBASE1_OFFSET 
+#define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
+#undef DDRC_SARSIZE1_OFFSET 
+#define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
+#undef DDRC_DFITMG0_SHADOW_OFFSET 
+#define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDR_PHY_PGCR0_OFFSET 
+#define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
+#undef DDR_PHY_PGCR2_OFFSET 
+#define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
+#undef DDR_PHY_PGCR3_OFFSET 
+#define DDR_PHY_PGCR3_OFFSET                                                       0XFD08001C
+#undef DDR_PHY_PGCR5_OFFSET 
+#define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
+#undef DDR_PHY_PTR0_OFFSET 
+#define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
+#undef DDR_PHY_PTR1_OFFSET 
+#define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
+#undef DDR_PHY_PLLCR0_OFFSET 
+#define DDR_PHY_PLLCR0_OFFSET                                                      0XFD080068
+#undef DDR_PHY_DSGCR_OFFSET 
+#define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
+#undef DDR_PHY_GPR0_OFFSET 
+#define DDR_PHY_GPR0_OFFSET                                                        0XFD0800C0
+#undef DDR_PHY_GPR1_OFFSET 
+#define DDR_PHY_GPR1_OFFSET                                                        0XFD0800C4
+#undef DDR_PHY_DCR_OFFSET 
+#define DDR_PHY_DCR_OFFSET                                                         0XFD080100
+#undef DDR_PHY_DTPR0_OFFSET 
+#define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
+#undef DDR_PHY_DTPR1_OFFSET 
+#define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
+#undef DDR_PHY_DTPR2_OFFSET 
+#define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
+#undef DDR_PHY_DTPR3_OFFSET 
+#define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
+#undef DDR_PHY_DTPR4_OFFSET 
+#define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
+#undef DDR_PHY_DTPR5_OFFSET 
+#define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
+#undef DDR_PHY_DTPR6_OFFSET 
+#define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
+#undef DDR_PHY_RDIMMGCR0_OFFSET 
+#define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
+#undef DDR_PHY_RDIMMGCR1_OFFSET 
+#define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
+#undef DDR_PHY_RDIMMCR0_OFFSET 
+#define DDR_PHY_RDIMMCR0_OFFSET                                                    0XFD080150
+#undef DDR_PHY_RDIMMCR1_OFFSET 
+#define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
+#undef DDR_PHY_MR0_OFFSET 
+#define DDR_PHY_MR0_OFFSET                                                         0XFD080180
+#undef DDR_PHY_MR1_OFFSET 
+#define DDR_PHY_MR1_OFFSET                                                         0XFD080184
+#undef DDR_PHY_MR2_OFFSET 
+#define DDR_PHY_MR2_OFFSET                                                         0XFD080188
+#undef DDR_PHY_MR3_OFFSET 
+#define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
+#undef DDR_PHY_MR4_OFFSET 
+#define DDR_PHY_MR4_OFFSET                                                         0XFD080190
+#undef DDR_PHY_MR5_OFFSET 
+#define DDR_PHY_MR5_OFFSET                                                         0XFD080194
+#undef DDR_PHY_MR6_OFFSET 
+#define DDR_PHY_MR6_OFFSET                                                         0XFD080198
+#undef DDR_PHY_MR11_OFFSET 
+#define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
+#undef DDR_PHY_MR12_OFFSET 
+#define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
+#undef DDR_PHY_MR13_OFFSET 
+#define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
+#undef DDR_PHY_MR14_OFFSET 
+#define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
+#undef DDR_PHY_MR22_OFFSET 
+#define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
+#undef DDR_PHY_DTCR0_OFFSET 
+#define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
+#undef DDR_PHY_DTCR1_OFFSET 
+#define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
+#undef DDR_PHY_CATR0_OFFSET 
+#define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
+#undef DDR_PHY_DQSDR0_OFFSET 
+#define DDR_PHY_DQSDR0_OFFSET                                                      0XFD080250
+#undef DDR_PHY_BISTLSR_OFFSET 
+#define DDR_PHY_BISTLSR_OFFSET                                                     0XFD080414
+#undef DDR_PHY_RIOCR5_OFFSET 
+#define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
+#undef DDR_PHY_ACIOCR0_OFFSET 
+#define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
+#undef DDR_PHY_ACIOCR2_OFFSET 
+#define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
+#undef DDR_PHY_ACIOCR3_OFFSET 
+#define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
+#undef DDR_PHY_ACIOCR4_OFFSET 
+#define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
+#undef DDR_PHY_IOVCR0_OFFSET 
+#define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
+#undef DDR_PHY_VTCR0_OFFSET 
+#define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
+#undef DDR_PHY_VTCR1_OFFSET 
+#define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
+#undef DDR_PHY_ACBDLR1_OFFSET 
+#define DDR_PHY_ACBDLR1_OFFSET                                                     0XFD080544
+#undef DDR_PHY_ACBDLR2_OFFSET 
+#define DDR_PHY_ACBDLR2_OFFSET                                                     0XFD080548
+#undef DDR_PHY_ACBDLR6_OFFSET 
+#define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
+#undef DDR_PHY_ACBDLR7_OFFSET 
+#define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
+#undef DDR_PHY_ACBDLR8_OFFSET 
+#define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
+#undef DDR_PHY_ACBDLR9_OFFSET 
+#define DDR_PHY_ACBDLR9_OFFSET                                                     0XFD080564
+#undef DDR_PHY_ZQCR_OFFSET 
+#define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
+#undef DDR_PHY_ZQ0PR0_OFFSET 
+#define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
+#undef DDR_PHY_ZQ0OR0_OFFSET 
+#define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
+#undef DDR_PHY_ZQ0OR1_OFFSET 
+#define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
+#undef DDR_PHY_ZQ1PR0_OFFSET 
+#define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
+#undef DDR_PHY_DX0GCR0_OFFSET 
+#define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
+#undef DDR_PHY_DX0GCR1_OFFSET 
+#define DDR_PHY_DX0GCR1_OFFSET                                                     0XFD080704
+#undef DDR_PHY_DX0GCR3_OFFSET 
+#define DDR_PHY_DX0GCR3_OFFSET                                                     0XFD08070C
+#undef DDR_PHY_DX0GCR4_OFFSET 
+#define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
+#undef DDR_PHY_DX0GCR5_OFFSET 
+#define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
+#undef DDR_PHY_DX0GCR6_OFFSET 
+#define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
+#undef DDR_PHY_DX1GCR0_OFFSET 
+#define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
+#undef DDR_PHY_DX1GCR1_OFFSET 
+#define DDR_PHY_DX1GCR1_OFFSET                                                     0XFD080804
+#undef DDR_PHY_DX1GCR3_OFFSET 
+#define DDR_PHY_DX1GCR3_OFFSET                                                     0XFD08080C
+#undef DDR_PHY_DX1GCR4_OFFSET 
+#define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
+#undef DDR_PHY_DX1GCR5_OFFSET 
+#define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
+#undef DDR_PHY_DX1GCR6_OFFSET 
+#define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
+#undef DDR_PHY_DX2GCR0_OFFSET 
+#define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
+#undef DDR_PHY_DX2GCR1_OFFSET 
+#define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
+#undef DDR_PHY_DX2GCR3_OFFSET 
+#define DDR_PHY_DX2GCR3_OFFSET                                                     0XFD08090C
+#undef DDR_PHY_DX2GCR4_OFFSET 
+#define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
+#undef DDR_PHY_DX2GCR5_OFFSET 
+#define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
+#undef DDR_PHY_DX2GCR6_OFFSET 
+#define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
+#undef DDR_PHY_DX3GCR0_OFFSET 
+#define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
+#undef DDR_PHY_DX3GCR1_OFFSET 
+#define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
+#undef DDR_PHY_DX3GCR3_OFFSET 
+#define DDR_PHY_DX3GCR3_OFFSET                                                     0XFD080A0C
+#undef DDR_PHY_DX3GCR4_OFFSET 
+#define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
+#undef DDR_PHY_DX3GCR5_OFFSET 
+#define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
+#undef DDR_PHY_DX3GCR6_OFFSET 
+#define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
+#undef DDR_PHY_DX4GCR0_OFFSET 
+#define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
+#undef DDR_PHY_DX4GCR1_OFFSET 
+#define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
+#undef DDR_PHY_DX4GCR2_OFFSET 
+#define DDR_PHY_DX4GCR2_OFFSET                                                     0XFD080B08
+#undef DDR_PHY_DX4GCR3_OFFSET 
+#define DDR_PHY_DX4GCR3_OFFSET                                                     0XFD080B0C
+#undef DDR_PHY_DX4GCR4_OFFSET 
+#define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
+#undef DDR_PHY_DX4GCR5_OFFSET 
+#define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
+#undef DDR_PHY_DX4GCR6_OFFSET 
+#define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
+#undef DDR_PHY_DX5GCR0_OFFSET 
+#define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
+#undef DDR_PHY_DX5GCR1_OFFSET 
+#define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
+#undef DDR_PHY_DX5GCR2_OFFSET 
+#define DDR_PHY_DX5GCR2_OFFSET                                                     0XFD080C08
+#undef DDR_PHY_DX5GCR3_OFFSET 
+#define DDR_PHY_DX5GCR3_OFFSET                                                     0XFD080C0C
+#undef DDR_PHY_DX5GCR4_OFFSET 
+#define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
+#undef DDR_PHY_DX5GCR5_OFFSET 
+#define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
+#undef DDR_PHY_DX5GCR6_OFFSET 
+#define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
+#undef DDR_PHY_DX6GCR0_OFFSET 
+#define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
+#undef DDR_PHY_DX6GCR1_OFFSET 
+#define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
+#undef DDR_PHY_DX6GCR2_OFFSET 
+#define DDR_PHY_DX6GCR2_OFFSET                                                     0XFD080D08
+#undef DDR_PHY_DX6GCR3_OFFSET 
+#define DDR_PHY_DX6GCR3_OFFSET                                                     0XFD080D0C
+#undef DDR_PHY_DX6GCR4_OFFSET 
+#define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
+#undef DDR_PHY_DX6GCR5_OFFSET 
+#define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
+#undef DDR_PHY_DX6GCR6_OFFSET 
+#define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
+#undef DDR_PHY_DX7GCR0_OFFSET 
+#define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
+#undef DDR_PHY_DX7GCR1_OFFSET 
+#define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
+#undef DDR_PHY_DX7GCR2_OFFSET 
+#define DDR_PHY_DX7GCR2_OFFSET                                                     0XFD080E08
+#undef DDR_PHY_DX7GCR3_OFFSET 
+#define DDR_PHY_DX7GCR3_OFFSET                                                     0XFD080E0C
+#undef DDR_PHY_DX7GCR4_OFFSET 
+#define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
+#undef DDR_PHY_DX7GCR5_OFFSET 
+#define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
+#undef DDR_PHY_DX7GCR6_OFFSET 
+#define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
+#undef DDR_PHY_DX8GCR0_OFFSET 
+#define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
+#undef DDR_PHY_DX8GCR1_OFFSET 
+#define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
+#undef DDR_PHY_DX8GCR2_OFFSET 
+#define DDR_PHY_DX8GCR2_OFFSET                                                     0XFD080F08
+#undef DDR_PHY_DX8GCR3_OFFSET 
+#define DDR_PHY_DX8GCR3_OFFSET                                                     0XFD080F0C
+#undef DDR_PHY_DX8GCR4_OFFSET 
+#define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
+#undef DDR_PHY_DX8GCR5_OFFSET 
+#define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
+#undef DDR_PHY_DX8GCR6_OFFSET 
+#define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
+#undef DDR_PHY_DX8SL0OSC_OFFSET 
+#define DDR_PHY_DX8SL0OSC_OFFSET                                                   0XFD081400
+#undef DDR_PHY_DX8SL0PLLCR0_OFFSET 
+#define DDR_PHY_DX8SL0PLLCR0_OFFSET                                                0XFD081404
+#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
+#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
+#undef DDR_PHY_DX8SL0IOCR_OFFSET 
+#define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
+#undef DDR_PHY_DX8SL1OSC_OFFSET 
+#define DDR_PHY_DX8SL1OSC_OFFSET                                                   0XFD081440
+#undef DDR_PHY_DX8SL1PLLCR0_OFFSET 
+#define DDR_PHY_DX8SL1PLLCR0_OFFSET                                                0XFD081444
+#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
+#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
+#undef DDR_PHY_DX8SL1IOCR_OFFSET 
+#define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
+#undef DDR_PHY_DX8SL2OSC_OFFSET 
+#define DDR_PHY_DX8SL2OSC_OFFSET                                                   0XFD081480
+#undef DDR_PHY_DX8SL2PLLCR0_OFFSET 
+#define DDR_PHY_DX8SL2PLLCR0_OFFSET                                                0XFD081484
+#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
+#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
+#undef DDR_PHY_DX8SL2IOCR_OFFSET 
+#define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
+#undef DDR_PHY_DX8SL3OSC_OFFSET 
+#define DDR_PHY_DX8SL3OSC_OFFSET                                                   0XFD0814C0
+#undef DDR_PHY_DX8SL3PLLCR0_OFFSET 
+#define DDR_PHY_DX8SL3PLLCR0_OFFSET                                                0XFD0814C4
+#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
+#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
+#undef DDR_PHY_DX8SL3IOCR_OFFSET 
+#define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
+#undef DDR_PHY_DX8SL4OSC_OFFSET 
+#define DDR_PHY_DX8SL4OSC_OFFSET                                                   0XFD081500
+#undef DDR_PHY_DX8SL4PLLCR0_OFFSET 
+#define DDR_PHY_DX8SL4PLLCR0_OFFSET                                                0XFD081504
+#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
+#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
+#undef DDR_PHY_DX8SL4IOCR_OFFSET 
+#define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
+#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 
+#define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
+
+/*
+* DDR block level reset inside of the DDR Sub System
+*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U
+
+/*
+* Indicates the configuration of the device used in the system. - 00 - x4
+    * device - 01 - x8 device - 10 - x16 device - 11 - x32 device
+*/
+#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 
+#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 
+#undef DDRC_MSTR_DEVICE_CONFIG_MASK 
+#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                         0x03040001
+#define DDRC_MSTR_DEVICE_CONFIG_SHIFT                          30
+#define DDRC_MSTR_DEVICE_CONFIG_MASK                           0xC0000000U
+
+/*
+* Choose which registers are used. - 0 - Original registers - 1 - Shadow r
+    * egisters
+*/
+#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 
+#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 
+#undef DDRC_MSTR_FREQUENCY_MODE_MASK 
+#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                        0x03040001
+#define DDRC_MSTR_FREQUENCY_MODE_SHIFT                         29
+#define DDRC_MSTR_FREQUENCY_MODE_MASK                          0x20000000U
+
+/*
+* Only present for multi-rank configurations. Each bit represents one rank
+    * . For two-rank configurations, only bits[25:24] are present. - 1 - popul
+    * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow
+    * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others -
+    * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran
+    * k - 0011 - Two ranks - 1111 - Four ranks
+*/
+#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 
+#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 
+#undef DDRC_MSTR_ACTIVE_RANKS_MASK 
+#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                          0x03040001
+#define DDRC_MSTR_ACTIVE_RANKS_SHIFT                           24
+#define DDRC_MSTR_ACTIVE_RANKS_MASK                            0x03000000U
+
+/*
+* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for
+    * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur
+    * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other
+    * values are reserved. This controls the burst size used to access the SDR
+    * AM. This must match the burst length mode register setting in the SDRAM.
+    *  (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100)
+    * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH
+    *  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
+*/
+#undef DDRC_MSTR_BURST_RDWR_DEFVAL 
+#undef DDRC_MSTR_BURST_RDWR_SHIFT 
+#undef DDRC_MSTR_BURST_RDWR_MASK 
+#define DDRC_MSTR_BURST_RDWR_DEFVAL                            0x03040001
+#define DDRC_MSTR_BURST_RDWR_SHIFT                             16
+#define DDRC_MSTR_BURST_RDWR_MASK                              0x000F0000U
+
+/*
+* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low
+    * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for
+    * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC
+    * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi
+    * s bit must be set to '0'.
+*/
+#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 
+#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 
+#undef DDRC_MSTR_DLL_OFF_MODE_MASK 
+#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                          0x03040001
+#define DDRC_MSTR_DLL_OFF_MODE_SHIFT                           15
+#define DDRC_MSTR_DLL_OFF_MODE_MASK                            0x00008000U
+
+/*
+* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full
+    *  DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter
+    * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is
+    * only supported when the SDRAM bus width is a multiple of 16, and quarter
+    *  bus width mode is only supported when the SDRAM bus width is a multiple
+    *  of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid
+    * th refers to DQ bus width (excluding any ECC width).
+*/
+#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 
+#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                        0x03040001
+#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                         12
+#define DDRC_MSTR_DATA_BUS_WIDTH_MASK                          0x00003000U
+
+/*
+* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D
+    * RAM in normal mode (1N). This register can be changed, only when the Con
+    * troller is in self-refresh mode. This signal must be set the same value
+    * as MR3 bit A3. Note: Geardown mode is not supported if the configuration
+    *  parameter MEMC_CMD_RTN2IDLE is set
+*/
+#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 
+#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 
+#undef DDRC_MSTR_GEARDOWN_MODE_MASK 
+#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                         0x03040001
+#define DDRC_MSTR_GEARDOWN_MODE_SHIFT                          11
+#define DDRC_MSTR_GEARDOWN_MODE_MASK                           0x00000800U
+
+/*
+* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin
+    * g, all command signals (except chip select) are held for 2 clocks on the
+    *  SDRAM bus. Chip select is asserted on the second cycle of the command N
+    * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti
+    * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i
+    * s set Note: 2T timing is not supported in DDR4 geardown mode.
+*/
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 
+#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                     0x03040001
+#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                      10
+#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                       0x00000400U
+
+/*
+* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci
+    * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full
+    * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer
+    * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is
+    *  disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl
+    * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported
+    * , and this bit must be set to '0'
+*/
+#undef DDRC_MSTR_BURSTCHOP_DEFVAL 
+#undef DDRC_MSTR_BURSTCHOP_SHIFT 
+#undef DDRC_MSTR_BURSTCHOP_MASK 
+#define DDRC_MSTR_BURSTCHOP_DEFVAL                             0x03040001
+#define DDRC_MSTR_BURSTCHOP_SHIFT                              9
+#define DDRC_MSTR_BURSTCHOP_MASK                               0x00000200U
+
+/*
+* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d
+    * evice in use Present only in designs configured to support LPDDR4.
+*/
+#undef DDRC_MSTR_LPDDR4_DEFVAL 
+#undef DDRC_MSTR_LPDDR4_SHIFT 
+#undef DDRC_MSTR_LPDDR4_MASK 
+#define DDRC_MSTR_LPDDR4_DEFVAL                                0x03040001
+#define DDRC_MSTR_LPDDR4_SHIFT                                 5
+#define DDRC_MSTR_LPDDR4_MASK                                  0x00000020U
+
+/*
+* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device
+    * in use Present only in designs configured to support DDR4.
+*/
+#undef DDRC_MSTR_DDR4_DEFVAL 
+#undef DDRC_MSTR_DDR4_SHIFT 
+#undef DDRC_MSTR_DDR4_MASK 
+#define DDRC_MSTR_DDR4_DEFVAL                                  0x03040001
+#define DDRC_MSTR_DDR4_SHIFT                                   4
+#define DDRC_MSTR_DDR4_MASK                                    0x00000010U
+
+/*
+* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d
+    * evice in use Present only in designs configured to support LPDDR3.
+*/
+#undef DDRC_MSTR_LPDDR3_DEFVAL 
+#undef DDRC_MSTR_LPDDR3_SHIFT 
+#undef DDRC_MSTR_LPDDR3_MASK 
+#define DDRC_MSTR_LPDDR3_DEFVAL                                0x03040001
+#define DDRC_MSTR_LPDDR3_SHIFT                                 3
+#define DDRC_MSTR_LPDDR3_MASK                                  0x00000008U
+
+/*
+* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d
+    * evice in use Present only in designs configured to support LPDDR2.
+*/
+#undef DDRC_MSTR_LPDDR2_DEFVAL 
+#undef DDRC_MSTR_LPDDR2_SHIFT 
+#undef DDRC_MSTR_LPDDR2_MASK 
+#define DDRC_MSTR_LPDDR2_DEFVAL                                0x03040001
+#define DDRC_MSTR_LPDDR2_SHIFT                                 2
+#define DDRC_MSTR_LPDDR2_MASK                                  0x00000004U
+
+/*
+* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de
+    * vice in use Only present in designs that support DDR3.
+*/
+#undef DDRC_MSTR_DDR3_DEFVAL 
+#undef DDRC_MSTR_DDR3_SHIFT 
+#undef DDRC_MSTR_DDR3_MASK 
+#define DDRC_MSTR_DDR3_DEFVAL                                  0x03040001
+#define DDRC_MSTR_DDR3_SHIFT                                   0
+#define DDRC_MSTR_DDR3_MASK                                    0x00000001U
+
+/*
+* Setting this register bit to 1 triggers a mode register read or write op
+    * eration. When the MR operation is complete, the uMCTL2 automatically cle
+    * ars this bit. The other register fields of this register must be written
+    *  in a separate APB transaction, before setting this mr_wr bit. It is rec
+    * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper
+    * ating modes.
+*/
+#undef DDRC_MRCTRL0_MR_WR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_WR_SHIFT 
+#undef DDRC_MRCTRL0_MR_WR_MASK 
+#define DDRC_MRCTRL0_MR_WR_DEFVAL                              0x00000030
+#define DDRC_MRCTRL0_MR_WR_SHIFT                               31
+#define DDRC_MRCTRL0_MR_WR_MASK                                0x80000000U
+
+/*
+* Address of the mode register that is to be written to. - 0000 - MR0 - 00
+    * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR
+    * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data
+    * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als
+    * o used for writing to control words of RDIMMs. In that case, it correspo
+    * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[
+    * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a
+    * s the bit[2:0] must be set to an appropriate value which is considered b
+    * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R
+    * DIMMs.
+*/
+#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 
+#undef DDRC_MRCTRL0_MR_ADDR_MASK 
+#define DDRC_MRCTRL0_MR_ADDR_DEFVAL                            0x00000030
+#define DDRC_MRCTRL0_MR_ADDR_SHIFT                             12
+#define DDRC_MRCTRL0_MR_ADDR_MASK                              0x0000F000U
+
+/*
+* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire
+    * d to access all ranks, so all bits should be set to 1. However, for mult
+    * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess
+    * ary to access ranks individually. Examples (assume uMCTL2 is configured
+    * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x
+    * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran
+    * ks 0, 1, 2 and 3
+*/
+#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 
+#undef DDRC_MRCTRL0_MR_RANK_SHIFT 
+#undef DDRC_MRCTRL0_MR_RANK_MASK 
+#define DDRC_MRCTRL0_MR_RANK_DEFVAL                            0x00000030
+#define DDRC_MRCTRL0_MR_RANK_SHIFT                             4
+#define DDRC_MRCTRL0_MR_RANK_MASK                              0x00000030U
+
+/*
+* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b
+    * efore automatic SDRAM initialization routine or not. For DDR4, this bit
+    * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init
+    * ialization. For LPDDR4, this bit can be used to program additional mode
+    * registers before automatic SDRAM initialization if necessary. Note: This
+    *  must be cleared to 0 after completing Software operation. Otherwise, SD
+    * RAM initialization routine will not re-start. - 0 - Software interventio
+    * n is not allowed - 1 - Software intervention is allowed
+*/
+#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 
+#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 
+#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 
+#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                        0x00000030
+#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                         3
+#define DDRC_MRCTRL0_SW_INIT_INT_MASK                          0x00000008U
+
+/*
+* Indicates whether the mode register operation is MRS in PDA mode or not
+    * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
+*/
+#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 
+#undef DDRC_MRCTRL0_PDA_EN_SHIFT 
+#undef DDRC_MRCTRL0_PDA_EN_MASK 
+#define DDRC_MRCTRL0_PDA_EN_DEFVAL                             0x00000030
+#define DDRC_MRCTRL0_PDA_EN_SHIFT                              2
+#define DDRC_MRCTRL0_PDA_EN_MASK                               0x00000004U
+
+/*
+* Indicates whether the mode register operation is MRS or WR/RD for MPR (o
+    * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
+*/
+#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 
+#undef DDRC_MRCTRL0_MPR_EN_SHIFT 
+#undef DDRC_MRCTRL0_MPR_EN_MASK 
+#define DDRC_MRCTRL0_MPR_EN_DEFVAL                             0x00000030
+#define DDRC_MRCTRL0_MPR_EN_SHIFT                              1
+#define DDRC_MRCTRL0_MPR_EN_MASK                               0x00000002U
+
+/*
+* Indicates whether the mode register operation is read or write. Only use
+    * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read
+*/
+#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 
+#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 
+#undef DDRC_MRCTRL0_MR_TYPE_MASK 
+#define DDRC_MRCTRL0_MR_TYPE_DEFVAL                            0x00000030
+#define DDRC_MRCTRL0_MR_TYPE_SHIFT                             0
+#define DDRC_MRCTRL0_MR_TYPE_MASK                              0x00000001U
+
+/*
+* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us
+    * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d
+    * esigns configured to support LPDDR4. The required number of cycles for d
+    * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p
+    * eriod, and rounding up the next integer.
+*/
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                   0x00000000
+#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                    8
+#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                     0x00000300U
+
+/*
+* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/
+    * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma
+    * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
+*/
+#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_BYTE_MASK 
+#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                       0x00000000
+#define DDRC_DERATEEN_DERATE_BYTE_SHIFT                        4
+#define DDRC_DERATEEN_DERATE_BYTE_MASK                         0x000000F0U
+
+/*
+* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl
+    * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all
+    *  LPDDR2 speed grades as derating value of +1.875 ns is less than a core_
+    * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8
+    * 75 ns is less than a core_ddrc_core_clk period or not.
+*/
+#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                      0x00000000
+#define DDRC_DERATEEN_DERATE_VALUE_SHIFT                       1
+#define DDRC_DERATEEN_DERATE_VALUE_MASK                        0x00000002U
+
+/*
+* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin
+    * g parameter derating is enabled using MR4 read value. Present only in de
+    * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set
+    * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
+*/
+#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 
+#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                     0x00000000
+#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                      0
+#define DDRC_DERATEEN_DERATE_ENABLE_MASK                       0x00000001U
+
+/*
+* Interval between two MR4 reads, used to derate the timing parameters. Pr
+    * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r
+    * egister must not be set to zero
+*/
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL                
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                 0
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                  0xFFFFFFFFU
+
+/*
+* Self refresh state is an intermediate state to enter to Self refresh pow
+    * er down state or exit Self refresh power down state for LPDDR4. This reg
+    * ister controls transition from the Self refresh state. - 1 - Prohibit tr
+    * ansition from Self refresh state - 0 - Allow transition from Self refres
+    * h state
+*/
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 
+#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                     0x00000000
+#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                      6
+#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                       0x00000040U
+
+/*
+* A value of 1 to this register causes system to move to Self Refresh stat
+    * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode.
+    * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa
+    * re Entry to Self Refresh - 0 - Software Exit from Self Refresh
+*/
+#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_SW_MASK 
+#define DDRC_PWRCTL_SELFREF_SW_DEFVAL                          0x00000000
+#define DDRC_PWRCTL_SELFREF_SW_SHIFT                           5
+#define DDRC_PWRCTL_SELFREF_SW_MASK                            0x00000020U
+
+/*
+* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode
+    *  when the transaction store is empty. This register must be reset to '0'
+    *  to bring uMCTL2 out of maximum power saving mode. Present only in desig
+    * ns configured to support DDR4. For non-DDR4, this register should not be
+    *  set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if
+    * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r
+    * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 
+#undef DDRC_PWRCTL_MPSM_EN_SHIFT 
+#undef DDRC_PWRCTL_MPSM_EN_MASK 
+#define DDRC_PWRCTL_MPSM_EN_DEFVAL                             0x00000000
+#define DDRC_PWRCTL_MPSM_EN_SHIFT                              4
+#define DDRC_PWRCTL_MPSM_EN_MASK                               0x00000010U
+
+/*
+* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req
+    * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted.
+    *  Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only
+    *  be asserted in Self Refresh. In DDR4, can be asserted in following: - i
+    * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca
+    * n be asserted in following: - in Self Refresh - in Power Down - in Deep
+    * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse
+    * rted in following: - in Self Refresh Power Down - in Power Down - during
+    *  Normal operation (Clock Stop)
+*/
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL             0x00000000
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT              3
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK               0x00000008U
+
+/*
+* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the
+    *  transaction store is empty. This register must be reset to '0' to bring
+    *  uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM
+    *  initialization on deep power-down exit. Present only in designs configu
+    * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD
+    * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                    0x00000000
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                     2
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                      0x00000004U
+
+/*
+* If true then the uMCTL2 goes into power-down after a programmable number
+    *  of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_
+    * x32). This register bit may be re-programmed during the course of normal
+    *  operation.
+*/
+#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                        0x00000000
+#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                         1
+#define DDRC_PWRCTL_POWERDOWN_EN_MASK                          0x00000002U
+
+/*
+* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program
+    * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG.
+    * selfref_to_x32)'. This register bit may be re-programmed during the cour
+    * se of normal operation.
+*/
+#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_EN_MASK 
+#define DDRC_PWRCTL_SELFREF_EN_DEFVAL                          0x00000000
+#define DDRC_PWRCTL_SELFREF_EN_SHIFT                           0
+#define DDRC_PWRCTL_SELFREF_EN_MASK                            0x00000001U
+
+/*
+* After this many clocks of NOP or deselect the uMCTL2 automatically puts
+    * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_
+    * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 
+#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                      0x00402010
+#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                       16
+#define DDRC_PWRTMG_SELFREF_TO_X32_MASK                        0x00FF0000U
+
+/*
+* Minimum deep power-down time. For mDDR, value from the JEDEC specificati
+    * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL
+    * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE
+    * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i
+    * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
+    * ONLY.
+*/
+#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 
+#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 
+#undef DDRC_PWRTMG_T_DPD_X4096_MASK 
+#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                         0x00402010
+#define DDRC_PWRTMG_T_DPD_X4096_SHIFT                          8
+#define DDRC_PWRTMG_T_DPD_X4096_MASK                           0x0000FF00U
+
+/*
+* After this many clocks of NOP or deselect the uMCTL2 automatically puts
+    * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_
+    * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                    0x00402010
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                     0
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                      0x0000001FU
+
+/*
+* Threshold value in number of clock cycles before the critical refresh or
+    *  page timer expires. A critical refresh is to be issued before this thre
+    * shold is reached. It is recommended that this not be changed from the de
+    * fault value, currently shown as 0x2. It must always be less than interna
+    * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u
+    * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i
+    * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n
+    * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo
+    * cks.
+*/
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                    0x00210000
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                     20
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                      0x00F00000U
+
+/*
+* If the refresh timer (tRFCnom, also known as tREFI) has expired at least
+    *  once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then
+    *  a speculative refresh may be performed. A speculative refresh is a refr
+    * esh performed at a time when refresh would be useful, but before it is a
+    * bsolutely required. When the SDRAM bus is idle for a period of time dete
+    * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired
+    *  at least once since the last refresh, then a speculative refresh is per
+    * formed. Speculative refreshes continues successively until there are no
+    * refreshes pending or until new reads or writes are issued to the uMCTL2.
+    *  FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                    0x00210000
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                     12
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                      0x0001F000U
+
+/*
+* The programmed value + 1 is the number of refresh timeouts that is allow
+    * ed to accumulate before traffic is blocked and the refreshes are forced
+    * to execute. Closing pages to perform a refresh is a one-time penalty tha
+    * t must be paid for each group of refreshes. Therefore, performing refres
+    * hes in a burst reduces the per-refresh penalty of these page closings. H
+    * igher numbers for RFSHCTL.refresh_burst slightly increases utilization;
+    * lower numbers decreases the worst-case latency associated with refreshes
+    * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh
+    *  For information on burst refresh feature refer to section 3.9 of DDR2 J
+    * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe
+    * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF
+    * I cycles using the burst refresh feature. In DDR4 mode, according to Fin
+    * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre
+    * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda
+    * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens
+    * ure that tRFCmax is not violated due to a PHY-initiated update occurring
+    *  shortly before a refresh burst was due. In this situation, the refresh
+    * burst will be delayed until the PHY-initiated update is complete.
+*/
+#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 
+#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                     0x00210000
+#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                      4
+#define DDRC_RFSHCTL0_REFRESH_BURST_MASK                       0x000001F0U
+
+/*
+* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
+    * traffic to flow to other banks. Per bank refresh is not supported by all
+    *  LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr
+    * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4
+*/
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                  0x00210000
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                   2
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                    0x00000004U
+
+/*
+* Refresh timer start for rank 1 (only present in multi-rank configuration
+    * s). This is useful in staggering the refreshes to multiple ranks to help
+    *  traffic to proceed. This is explained in Refresh Controls section of ar
+    * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 
+#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL    0x00000000
+#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT     16
+#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK      0x0FFF0000U
+
+/*
+* Refresh timer start for rank 0 (only present in multi-rank configuration
+    * s). This is useful in staggering the refreshes to multiple ranks to help
+    *  traffic to proceed. This is explained in Refresh Controls section of ar
+    * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 
+#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 
+#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL    0x00000000
+#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT     0
+#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK      0x00000FFFU
+
+/*
+* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix
+    * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11
+    * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No
+    * te: The on-the-fly modes is not supported in this version of the uMCTL2.
+    *  Note: This must be set up while the Controller is in reset or while the
+    *  Controller is in self-refresh mode. Changing this during normal operati
+    * on is not allowed. Making this a dynamic register will be supported in f
+    * uture version of the uMCTL2.
+*/
+#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 
+#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                      0x00000000
+#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                       4
+#define DDRC_RFSHCTL3_REFRESH_MODE_MASK                        0x00000070U
+
+/*
+* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
+    * the refresh register(s) have been updated. The value is automatically up
+    * dated when exiting reset, so it does not need to be toggled initially.
+*/
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL              0x00000000
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT               1
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                0x00000002U
+
+/*
+* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres
+    * h is disabled, the SoC core must generate refreshes using the registers
+    * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a
+    * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1
+    * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4
+    *  CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+    * isable auto-refresh is not supported, and this bit must be set to '0'. T
+    * his register field is changeable on the fly.
+*/
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                  0x00000000
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                   0
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                    0x00000001U
+
+/*
+* tREFI: Average time interval between refreshes per rank (Specification:
+    * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2,
+    *  LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre
+    * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE
+    * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
+    *  register should be set to tREFIpb For configurations with MEMC_FREQ_RAT
+    * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val
+    * ue is different depending on the refresh mode. The user should program t
+    * he appropriate value from the spec based on the value programmed in the
+    * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea
+    * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th
+    * an 0x1. Unit: Multiples of 32 clocks.
+*/
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                      0x0062008C
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                       16
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                        0x0FFF0000U
+
+/*
+* Used only when LPDDR3 memory type is connected. Should only be changed w
+    * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r
+    * equired by some LPDDR3 devices which comply with earlier versions of the
+    *  LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1
+    *  - tREFBW parameter used
+*/
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                   0x0062008C
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                    15
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                     0x00008000U
+
+/*
+* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F
+    * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t
+    * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro
+    * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using
+    * all-bank refreshes, the tRFCmin value in the above equations is equal to
+    *  tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq
+    * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+    * equations is different depending on the refresh mode (fixed 1X,2X,4X) an
+    * d the device density. The user should program the appropriate value from
+    *  the spec based on the 'refresh_mode' and the device density that is use
+    * d. Unit: Clocks.
+*/
+#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 
+#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                          0x0062008C
+#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                           0
+#define DDRC_RFSHTMG_T_RFC_MIN_MASK                            0x000003FFU
+
+/*
+* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U
+    * SE_RMW is defined
+*/
+#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 
+#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 
+#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 
+#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                          0x00000000
+#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                           4
+#define DDRC_ECCCFG0_DIS_SCRUB_MASK                            0x00000010U
+
+/*
+* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov
+    * er 1 beat - all other settings are reserved for future use
+*/
+#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 
+#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 
+#undef DDRC_ECCCFG0_ECC_MODE_MASK 
+#define DDRC_ECCCFG0_ECC_MODE_DEFVAL                           0x00000000
+#define DDRC_ECCCFG0_ECC_MODE_SHIFT                            0
+#define DDRC_ECCCFG0_ECC_MODE_MASK                             0x00000007U
+
+/*
+* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da
+    * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat
+    * a_poison_en=1
+*/
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                    0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                     1
+#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                      0x00000002U
+
+/*
+* Enable ECC data poisoning - introduces ECC errors on writes to address s
+    * pecified by the ECCPOISONADDR0/1 registers
+*/
+#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                     0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                      0
+#define DDRC_ECCCFG1_DATA_POISON_EN_MASK                       0x00000001U
+
+/*
+* The maximum number of DFI PHY clock cycles allowed from the assertion of
+    *  the dfi_rddata_en signal to the assertion of each of the corresponding
+    * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing
+    * parameter tphy_rdlat. Refer to PHY specification for correct value. This
+    *  value it only used for detecting read data timeout when DDR4 retry is e
+    * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value:
+    *  - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r
+    * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1
+    *  : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d
+    * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+    * rdlat < 'd114 Unit: DFI Clocks
+*/
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                 0x10000200
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                  24
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                   0x3F000000U
+
+/*
+* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa
+    * re has an option to read the mode registers in the DRAM before the hardw
+    * are begins the retry process - 1: Wait for software to read/write the mo
+    * de registers before hardware begins the retry. After software is done wi
+    * th its operations, it will clear the alert interrupt register bit - 0: H
+    * ardware can begin the retry right away after the dfi_alert_n pulse goes
+    * away. The value on this register is valid only when retry is enabled (PA
+    * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t
+    * he software doesn't clear the interrupt register after handling the pari
+    * ty/CRC error, then the hardware will not begin the retry process and the
+    *  system will hang. In the case of Parity/CRC error, there are two possib
+    * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten
+    * t parity' mode register bit is NOT set: the commands sent during retry a
+    * nd normal operation are executed without parity checking. The value in t
+    * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent
+    * parity' mode register bit is SET: Parity checking is done for commands s
+    * ent during retry and normal operation. If multiple errors occur before M
+    * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don'
+    * t care'.
+*/
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL               0x10000200
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                9
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                 0x00000200U
+
+/*
+* - 1: Enable command retry mechanism in case of C/A Parity or CRC error -
+    *  0: Disable command retry mechanism when C/A Parity or CRC features are
+    * enabled. Note that retry functionality is not supported if burst chop is
+    *  enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF
+    * SHCTL3.dis_auto_refresh = 1)
+*/
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL         0x10000200
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT          8
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK           0x00000100U
+
+/*
+* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no
+    * t includes DM signal Present only in designs configured to support DDR4.
+*/
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 
+#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                      0x10000200
+#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                       7
+#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                        0x00000080U
+
+/*
+* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio
+    * n of CRC The setting of this register should match the CRC mode register
+    *  setting in the DRAM.
+*/
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                      0x10000200
+#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                       4
+#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                        0x00000010U
+
+/*
+* C/A Parity enable register - 1: Enable generation of C/A parity and dete
+    * ction of C/A parity error - 0: Disable generation of C/A parity and disa
+    * ble detection of C/A parity error If RCD's parity error detection or SDR
+    * AM's parity detection is enabled, this register should be 1.
+*/
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                   0x10000200
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                    0
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                     0x00000001U
+
+/*
+* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
+    *  pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M
+    * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT
+    * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i
+    * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
+*/
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL              0x0030050C
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT               16
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                0x01FF0000U
+
+/*
+* Value from the DRAM spec indicating the maximum width of the dfi_alert_n
+    *  pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX
+    * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW
+    * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille
+    * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
+*/
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL              0x0030050C
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT               8
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                0x00001F00U
+
+/*
+* Indicates the maximum duration in number of DRAM clock cycles for which
+    * a command should be held in the Command Retry FIFO before it is popped o
+    * ut. Every location in the Command Retry FIFO has an associated down coun
+    * ting timer that will use this register as the start value. The down coun
+    * ting starts when a command is loaded into the FIFO. The timer counts dow
+    * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe
+    * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err
+    * or occurs before the counter reaches zero. The counter is reset to 0, af
+    * ter all the commands in the FIFO are retried. Recommended(minimum) value
+    * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK)
+    * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten
+    * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable
+    * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R
+    * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+    * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be
+    *  in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n
+    * ) should be considered. Note 3: Use the worst case(longer) value for PHY
+    *  Latencies/Board delay Note 4: The Recommended values are minimum value
+    * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max
+    *  value can be set to this register is defined below: - MEMC_BURST_LENGTH
+    *  == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2
+    *  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b
+    * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod
+    * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C
+    * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC=
+    * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16
+    *  Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full
+    * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod
+    * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC
+    * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF
+    * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma
+    * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal
+    * .
+*/
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL    0x0030050C
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT     0
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK      0x0000003FU
+
+/*
+* If lower bit is enabled the SDRAM initialization routine is skipped. The
+    *  upper bit decides what state the controller starts up in when reset is
+    * removed - 00 - SDRAM Intialization routine is run after power-up - 01 -
+    * SDRAM Intialization routine is skipped after power-up. Controller starts
+    *  up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p
+    * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ
+    * ation routine is run after power-up. Note: The only 2'b00 is supported f
+    * or LPDDR4 in this version of the uMCTL2.
+*/
+#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 
+#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                       0x0002004E
+#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                        30
+#define DDRC_INIT0_SKIP_DRAM_INIT_MASK                         0xC0000000U
+
+/*
+* Cycles to wait after driving CKE high to start the SDRAM initialization
+    * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req
+    * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD
+    * R3 typically requires this to be programmed for a delay of 200 us. LPDDR
+    * 4 typically requires this to be programmed for a delay of 2 us. For conf
+    * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi
+    * ded by 2, and round it up to next integer value.
+*/
+#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_POST_CKE_X1024_MASK 
+#define DDRC_INIT0_POST_CKE_X1024_DEFVAL                       0x0002004E
+#define DDRC_INIT0_POST_CKE_X1024_SHIFT                        16
+#define DDRC_INIT0_POST_CKE_X1024_MASK                         0x03FF0000U
+
+/*
+* Cycles to wait after reset before driving CKE high to start the SDRAM in
+    * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi
+    * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD
+    * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati
+    * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by
+    * 2, and round it up to next integer value.
+*/
+#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_PRE_CKE_X1024_MASK 
+#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                        0x0002004E
+#define DDRC_INIT0_PRE_CKE_X1024_SHIFT                         0
+#define DDRC_INIT0_PRE_CKE_X1024_MASK                          0x00000FFFU
+
+/*
+* Number of cycles to assert SDRAM reset signal during init sequence. This
+    *  is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo
+    * r use with a DDR PHY, this should be set to a minimum of 1
+*/
+#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 
+#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                      0x00000000
+#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                       16
+#define DDRC_INIT1_DRAM_RSTN_X1024_MASK                        0x01FF0000U
+
+/*
+* Cycles to wait after completing the SDRAM initialization sequence before
+    *  starting the dynamic scheduler. Unit: Counts of a global timer that pul
+    * ses every 32 clock cycles. There is no known specific requirement for th
+    * is; it may be set to zero.
+*/
+#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 
+#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 
+#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 
+#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                       0x00000000
+#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                        8
+#define DDRC_INIT1_FINAL_WAIT_X32_MASK                         0x00007F00U
+
+/*
+* Wait period before driving the OCD complete command to SDRAM. Unit: Coun
+    * ts of a global timer that pulses every 32 clock cycles. There is no know
+    * n specific requirement for this; it may be set to zero.
+*/
+#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 
+#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 
+#undef DDRC_INIT1_PRE_OCD_X32_MASK 
+#define DDRC_INIT1_PRE_OCD_X32_DEFVAL                          0x00000000
+#define DDRC_INIT1_PRE_OCD_X32_SHIFT                           0
+#define DDRC_INIT1_PRE_OCD_X32_MASK                            0x0000000FU
+
+/*
+* Idle time after the reset command, tINIT4. Present only in designs confi
+    * gured to support LPDDR2. Unit: 32 clock cycles.
+*/
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                 0x00000D05
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                  8
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                   0x0000FF00U
+
+/*
+* Time to wait after the first CKE high, tINIT2. Present only in designs c
+    * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t
+    * ypically requires 5 x tCK delay.
+*/
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                  0x00000D05
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                   0
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                    0x0000000FU
+
+/*
+* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he
+    * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value
+    * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP
+    * DDR3/LPDDR4 - Value to write to MR1 register
+*/
+#undef DDRC_INIT3_MR_DEFVAL 
+#undef DDRC_INIT3_MR_SHIFT 
+#undef DDRC_INIT3_MR_MASK 
+#define DDRC_INIT3_MR_DEFVAL                                   0x00000510
+#define DDRC_INIT3_MR_SHIFT                                    16
+#define DDRC_INIT3_MR_MASK                                     0xFFFF0000U
+
+/*
+* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti
+    * ng in this register is ignored. The uMCTL2 sets those bits appropriately
+    * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu
+    * ation mode training is enabled, this bit is set appropriately by the uMC
+    * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/
+    * LPDDR3/LPDDR4 - Value to write to MR2 register
+*/
+#undef DDRC_INIT3_EMR_DEFVAL 
+#undef DDRC_INIT3_EMR_SHIFT 
+#undef DDRC_INIT3_EMR_MASK 
+#define DDRC_INIT3_EMR_DEFVAL                                  0x00000510
+#define DDRC_INIT3_EMR_SHIFT                                   0
+#define DDRC_INIT3_EMR_MASK                                    0x0000FFFFU
+
+/*
+* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2
+    * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus
+    * ed
+*/
+#undef DDRC_INIT4_EMR2_DEFVAL 
+#undef DDRC_INIT4_EMR2_SHIFT 
+#undef DDRC_INIT4_EMR2_MASK 
+#define DDRC_INIT4_EMR2_DEFVAL                                 0x00000000
+#define DDRC_INIT4_EMR2_SHIFT                                  16
+#define DDRC_INIT4_EMR2_MASK                                   0xFFFF0000U
+
+/*
+* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3
+    * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis
+    * ter
+*/
+#undef DDRC_INIT4_EMR3_DEFVAL 
+#undef DDRC_INIT4_EMR3_SHIFT 
+#undef DDRC_INIT4_EMR3_MASK 
+#define DDRC_INIT4_EMR3_DEFVAL                                 0x00000000
+#define DDRC_INIT4_EMR3_SHIFT                                  0
+#define DDRC_INIT4_EMR3_MASK                                   0x0000FFFFU
+
+/*
+* ZQ initial calibration, tZQINIT. Present only in designs configured to s
+    * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica
+    * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir
+    * es 1 us.
+*/
+#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 
+#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                       0x00100004
+#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                        16
+#define DDRC_INIT5_DEV_ZQINIT_X32_MASK                         0x00FF0000U
+
+/*
+* Maximum duration of the auto initialization, tINIT5. Present only in des
+    * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir
+    * es 10 us.
+*/
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                  0x00100004
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                   0
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                    0x000003FFU
+
+/*
+* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs
+    * only.
+*/
+#undef DDRC_INIT6_MR4_DEFVAL 
+#undef DDRC_INIT6_MR4_SHIFT 
+#undef DDRC_INIT6_MR4_MASK 
+#define DDRC_INIT6_MR4_DEFVAL                                  0x00000000
+#define DDRC_INIT6_MR4_SHIFT                                   16
+#define DDRC_INIT6_MR4_MASK                                    0xFFFF0000U
+
+/*
+* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs
+    * only.
+*/
+#undef DDRC_INIT6_MR5_DEFVAL 
+#undef DDRC_INIT6_MR5_SHIFT 
+#undef DDRC_INIT6_MR5_MASK 
+#define DDRC_INIT6_MR5_DEFVAL                                  0x00000000
+#define DDRC_INIT6_MR5_SHIFT                                   0
+#define DDRC_INIT6_MR5_MASK                                    0x0000FFFFU
+
+/*
+* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs
+    * only.
+*/
+#undef DDRC_INIT7_MR6_DEFVAL 
+#undef DDRC_INIT7_MR6_SHIFT 
+#undef DDRC_INIT7_MR6_MASK 
+#define DDRC_INIT7_MR6_DEFVAL                                  
+#define DDRC_INIT7_MR6_SHIFT                                   16
+#define DDRC_INIT7_MR6_MASK                                    0xFFFF0000U
+
+/*
+* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
+    * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r
+    * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp
+    * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled.
+*/
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL              0x00000000
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT               5
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                0x00000020U
+
+/*
+* Enable for BG1 bit of MRS command. BG1 bit of the mode register address
+    * is specified as RFU (Reserved for Future Use) and must be programmed to
+    * 0 during MRS. In case where DRAMs which do not have BG1 are attached and
+    *  both the CA parity and the Output Inversion are enabled, this must be s
+    * et to 0, so that the calculation of CA parity will not include BG1 bit.
+    * Note: This has no effect on the address of any other memory accesses, or
+    *  of software-driven mode register accesses. If address mirroring is enab
+    * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En
+    * abled - 0 - Disabled
+*/
+#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 
+#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                         0x00000000
+#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                          4
+#define DDRC_DIMMCTL_MRS_BG1_EN_MASK                           0x00000010U
+
+/*
+* Enable for A17 bit of MRS command. A17 bit of the mode register address
+    * is specified as RFU (Reserved for Future Use) and must be programmed to
+    * 0 during MRS. In case where DRAMs which do not have A17 are attached and
+    *  the Output Inversion are enabled, this must be set to 0, so that the ca
+    * lculation of CA parity will not include A17 bit. Note: This has no effec
+    * t on the address of any other memory accesses, or of software-driven mod
+    * e register accesses. - 1 - Enabled - 0 - Disabled
+*/
+#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 
+#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                         0x00000000
+#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                          3
+#define DDRC_DIMMCTL_MRS_A17_EN_MASK                           0x00000008U
+
+/*
+* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM
+    * M implements the Output Inversion feature by default, which means that t
+    * he following address, bank address and bank group bits of B-side DRAMs a
+    * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en
+    * sures that, for mode register accesses generated by the uMCTL2 during th
+    * e automatic initialization routine and enabling of a particular DDR4 fea
+    * ture, separate A-side and B-side mode register accesses are generated. F
+    * or B-side mode register accesses, these bits are inverted within the uMC
+    * TL2 to compensate for this RDIMM inversion. Note: This has no effect on
+    * the address of any other memory accesses, or of software-driven mode reg
+    * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 -
+    *  Do not implement output inversion for B-side DRAMs.
+*/
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                 0x00000000
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                  2
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                   0x00000004U
+
+/*
+* Address Mirroring Enable (for multi-rank UDIMM implementations and multi
+    * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement
+    *  address mirroring for odd ranks, which means that the following address
+    * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7,
+    *  A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t
+    * his bit ensures that, for mode register accesses during the automatic in
+    * itialization routine, these bits are swapped within the uMCTL2 to compen
+    * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial
+    * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th
+    * e automatic MRS access to enable/disable of a particular DDR4 feature. N
+    * ote: This has no effect on the address of any other memory accesses, or
+    * of software-driven mode register accesses. This is not supported for mDD
+    * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1
+    *  output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+    * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran
+    * ks, implement address mirroring for MRS commands to during initializatio
+    * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp
+    * lements address mirroring) - 0 - Do not implement address mirroring
+*/
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                  0x00000000
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                   1
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                    0x00000002U
+
+/*
+* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM
+    * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3
+    * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of
+    *  software driven MR commands (via MRCTRL0/MRCTRL1), where software is re
+    * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se
+    * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma
+    * nds to even and odd ranks seperately - 0 - Do not stagger accesses
+*/
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                 0x00000000
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                  0
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                   0x00000001U
+
+/*
+* Only present for multi-rank configurations. Indicates the number of cloc
+    * ks of gap in data responses when performing consecutive writes to differ
+    * ent ranks. This is used to switch the delays in the PHY to match the ran
+    * k requirements. This value should consider both PHY requirement and ODT
+    * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v
+    * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by
+    * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas
+    * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc
+    * reased by 1. - ODT requirement: The value programmed in this register ta
+    * kes care of the ODT switch off timing requirement when switching ranks d
+    * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1
+    *  For configurations with MEMC_FREQ_RATIO=1, program this to the larger o
+    * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_
+    * RATIO=2, program this to the larger value divided by two and round it up
+    *  to the next integer.
+*/
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                   0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                    8
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                     0x00000F00U
+
+/*
+* Only present for multi-rank configurations. Indicates the number of cloc
+    * ks of gap in data responses when performing consecutive reads to differe
+    * nt ranks. This is used to switch the delays in the PHY to match the rank
+    *  requirements. This value should consider both PHY requirement and ODT r
+    * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va
+    * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only),
+    * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only
+    * ), should be increased by 1. - ODT requirement: The value programmed in
+    * this register takes care of the ODT switch off timing requirement when s
+    * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1,
+    * program this to the larger of PHY requirement or ODT requirement. For co
+    * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di
+    * vided by two and round it up to the next integer.
+*/
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                   0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                    4
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                     0x000000F0U
+
+/*
+* Only present for multi-rank configurations. Background: Reads to the sam
+    * e rank can be performed back-to-back. Reads to different ranks require a
+    * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is
+    *  to avoid possible data bus contention as well as to give PHY enough tim
+    * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus
+    *  access on a cycle-by-cycle basis; therefore after a read is scheduled,
+    * there are few clock cycles (determined by the value on RANKCTL.diff_rank
+    * _rd_gap register) in which only reads from the same rank are eligible to
+    *  be scheduled. This prevents reads from other ranks from having fair acc
+    * ess to the data bus. This parameter represents the maximum number of rea
+    * ds that can be scheduled consecutively to the same rank. After this numb
+    * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by
+    * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig
+    * her numbers increase bandwidth utilization, lower numbers increase fairn
+    * ess. This feature can be DISABLED by setting this register to 0. When se
+    * t to 0, the Controller will stay on the same rank as long as commands ar
+    * e available for it. Minimum programmable value is 0 (feature disabled) a
+    * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 
+#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 
+#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 
+#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                        0x0000066F
+#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                         0
+#define DDRC_RANKCTL_MAX_RANK_RD_MASK                          0x0000000FU
+
+/*
+* Minimum time between write and precharge to same bank. Unit: Clocks Spec
+    * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks
+    *  @400MHz and less for lower frequencies where: - WL = write latency - BL
+    *  = burst length. This must match the value programmed in the BL bit of t
+    * he mode register to the SDRAM. BST (burst terminate) is not supported at
+    *  present. - tWR = Write recovery time. This comes directly from the SDRA
+    * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p
+    * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the
+    *  above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT
+    * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u
+    * p to the next integer value.
+*/
+#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 
+#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 
+#undef DDRC_DRAMTMG0_WR2PRE_MASK 
+#define DDRC_DRAMTMG0_WR2PRE_DEFVAL                            0x0F101B0F
+#define DDRC_DRAMTMG0_WR2PRE_SHIFT                             24
+#define DDRC_DRAMTMG0_WR2PRE_MASK                              0x7F000000U
+
+/*
+* tFAW Valid only when 8 or more banks(or banks x bank groups) are present
+    * . In 8-bank design, at most 4 banks must be activated in a rolling windo
+    * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi
+    * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se
+    * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration.
+    *  Unit: Clocks
+*/
+#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 
+#undef DDRC_DRAMTMG0_T_FAW_SHIFT 
+#undef DDRC_DRAMTMG0_T_FAW_MASK 
+#define DDRC_DRAMTMG0_T_FAW_DEFVAL                             0x0F101B0F
+#define DDRC_DRAMTMG0_T_FAW_SHIFT                              16
+#define DDRC_DRAMTMG0_T_FAW_MASK                               0x003F0000U
+
+/*
+* tRAS(max): Maximum time between activate and precharge to same bank. Thi
+    * s is the maximum time that a page can be kept open Minimum value of this
+    *  register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO
+    * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of
+    * 1024 clocks.
+*/
+#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                         0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                          8
+#define DDRC_DRAMTMG0_T_RAS_MAX_MASK                           0x00007F00U
+
+/*
+* tRAS(min): Minimum time between activate and precharge to the same bank.
+    *  For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA
+    * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T
+    * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th
+    * e next integer value. Unit: Clocks
+*/
+#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                         0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                          0
+#define DDRC_DRAMTMG0_T_RAS_MIN_MASK                           0x0000003FU
+
+/*
+* tXP: Minimum time after power-down exit to any operation. For DDR3, this
+    *  should be programmed to tXPDLL if slow powerdown exit is selected in MR
+    * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf
+    * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it
+    * up to the next integer value. Units: Clocks
+*/
+#undef DDRC_DRAMTMG1_T_XP_DEFVAL 
+#undef DDRC_DRAMTMG1_T_XP_SHIFT 
+#undef DDRC_DRAMTMG1_T_XP_MASK 
+#define DDRC_DRAMTMG1_T_XP_DEFVAL                              0x00080414
+#define DDRC_DRAMTMG1_T_XP_SHIFT                               16
+#define DDRC_DRAMTMG1_T_XP_MASK                                0x001F0000U
+
+/*
+* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL
+    * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi
+    * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2
+    * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t
+    * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4)
+    *  - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_
+    * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi
+    * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo
+    * ve value by 2 and round it up to the next integer value. Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 
+#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 
+#undef DDRC_DRAMTMG1_RD2PRE_MASK 
+#define DDRC_DRAMTMG1_RD2PRE_DEFVAL                            0x00080414
+#define DDRC_DRAMTMG1_RD2PRE_SHIFT                             8
+#define DDRC_DRAMTMG1_RD2PRE_MASK                              0x00001F00U
+
+/*
+* tRC: Minimum time between activates to same bank. For configurations wit
+    * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege
+    * r value. Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG1_T_RC_DEFVAL 
+#undef DDRC_DRAMTMG1_T_RC_SHIFT 
+#undef DDRC_DRAMTMG1_T_RC_MASK 
+#define DDRC_DRAMTMG1_T_RC_DEFVAL                              0x00080414
+#define DDRC_DRAMTMG1_T_RC_SHIFT                               0
+#define DDRC_DRAMTMG1_T_RC_MASK                                0x0000007FU
+
+/*
+* Set to WL Time from write command to write data on SDRAM interface. This
+    *  must be set to WL. For mDDR, it should normally be set to 1. Note that,
+    *  depending on the PHY, if using RDIMM, it may be necessary to use a valu
+    * e of WL + 1 to compensate for the extra cycle of latency through the RDI
+    * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate
+    * d using the above equation by 2, and round it up to next integer. This r
+    * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING
+    *  is set), as the DFI read and write latencies defined in DFITMG0 and DFI
+    * TMG1 are sufficient for those protocols Unit: clocks
+*/
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 
+#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                     0x0305060D
+#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                      24
+#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                       0x3F000000U
+
+/*
+* Set to RL Time from read command to read data on SDRAM interface. This m
+    * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma
+    * t be necessary to use a value of RL + 1 to compensate for the extra cycl
+    * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2
+    * , divide the value calculated using the above equation by 2, and round i
+    * t up to next integer. This register field is not required for DDR2 and D
+    * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie
+    * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit
+    * : clocks
+*/
+#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 
+#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                      0x0305060D
+#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                       16
+#define DDRC_DRAMTMG2_READ_LATENCY_MASK                        0x003F0000U
+
+/*
+* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L
+    * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di
+    * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL
+    *  LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL
+    * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write
+    *  command. Include time for bus turnaround and all per-bank, per-rank, an
+    * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b
+    * urst length. This must match the value programmed in the BL bit of the m
+    * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL
+    * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE =
+    * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d
+    * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should
+    * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal
+    * culated using the above equation by 2, and round it up to next integer.
+*/
+#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 
+#undef DDRC_DRAMTMG2_RD2WR_SHIFT 
+#undef DDRC_DRAMTMG2_RD2WR_MASK 
+#define DDRC_DRAMTMG2_RD2WR_DEFVAL                             0x0305060D
+#define DDRC_DRAMTMG2_RD2WR_SHIFT                              8
+#define DDRC_DRAMTMG2_RD2WR_MASK                               0x00003F00U
+
+/*
+* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu
+    * m time from write command to read command for same bank group. In others
+    * , minimum time from write command to read command. Includes time for bus
+    *  turnaround, recovery times, and all per-bank, per-rank, and global cons
+    * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la
+    * tency - BL = burst length. This must match the value programmed in the B
+    * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea
+    * d command delay for same bank group. This comes directly from the SDRAM
+    * specification. - tWTR = internal write to read command delay. This comes
+    *  directly from the SDRAM specification. Add one extra cycle for LPDDR2/L
+    * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid
+    * e the value calculated using the above equation by 2, and round it up to
+    *  next integer.
+*/
+#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 
+#undef DDRC_DRAMTMG2_WR2RD_SHIFT 
+#undef DDRC_DRAMTMG2_WR2RD_MASK 
+#define DDRC_DRAMTMG2_WR2RD_DEFVAL                             0x0305060D
+#define DDRC_DRAMTMG2_WR2RD_SHIFT                              0
+#define DDRC_DRAMTMG2_WR2RD_MASK                               0x0000003FU
+
+/*
+* Time to wait after a mode register write or read (MRW or MRR). Present o
+    * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty
+    * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD
+    * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist
+    * er is used for the time from a MRW/MRR to all other commands. For LDPDR3
+    * , this register is used for the time from a MRW/MRR to a MRW/MRR.
+*/
+#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRW_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRW_MASK 
+#define DDRC_DRAMTMG3_T_MRW_DEFVAL                             0x0050400C
+#define DDRC_DRAMTMG3_T_MRW_SHIFT                              20
+#define DDRC_DRAMTMG3_T_MRW_MASK                               0x3FF00000U
+
+/*
+* tMRD: Cycles to wait after a mode register write or read. Depending on t
+    * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com
+    * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim
+    * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2,
+    *  program this to (tMRD/2) and round it up to the next integer value. If
+    * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
+*/
+#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRD_MASK 
+#define DDRC_DRAMTMG3_T_MRD_DEFVAL                             0x0050400C
+#define DDRC_DRAMTMG3_T_MRD_SHIFT                              12
+#define DDRC_DRAMTMG3_T_MRD_MASK                               0x0003F000U
+
+/*
+* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com
+    * mand and following non-load mode command. If C/A parity for DDR4 is used
+    * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or
+    *  tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if
+    * using RDIMM, depending on the PHY, it may be necessary to use a value of
+    *  tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a
+    * pplied to mode register writes by the RDIMM chip.
+*/
+#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MOD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MOD_MASK 
+#define DDRC_DRAMTMG3_T_MOD_DEFVAL                             0x0050400C
+#define DDRC_DRAMTMG3_T_MOD_SHIFT                              0
+#define DDRC_DRAMTMG3_T_MOD_MASK                               0x000003FFU
+
+/*
+* tRCD - tAL: Minimum time from activate to read or write command to same
+    * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD
+    * - tAL)/2) and round it up to the next integer value. Minimum value allow
+    * ed for this register is 1, which implies minimum (tRCD - tAL) value to b
+    * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RCD_MASK 
+#define DDRC_DRAMTMG4_T_RCD_DEFVAL                             0x05040405
+#define DDRC_DRAMTMG4_T_RCD_SHIFT                              24
+#define DDRC_DRAMTMG4_T_RCD_MASK                               0x1F000000U
+
+/*
+* DDR4: tCCD_L: This is the minimum time between two reads or two writes f
+    * or same bank group. Others: tCCD: This is the minimum time between two r
+    * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t
+    * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U
+    * nit: clocks.
+*/
+#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_CCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_CCD_MASK 
+#define DDRC_DRAMTMG4_T_CCD_DEFVAL                             0x05040405
+#define DDRC_DRAMTMG4_T_CCD_SHIFT                              16
+#define DDRC_DRAMTMG4_T_CCD_MASK                               0x000F0000U
+
+/*
+* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f
+    * or same bank group. Others: tRRD: Minimum time between activates from ba
+    * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi
+    * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni
+    * t: Clocks.
+*/
+#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RRD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RRD_MASK 
+#define DDRC_DRAMTMG4_T_RRD_DEFVAL                             0x05040405
+#define DDRC_DRAMTMG4_T_RRD_SHIFT                              8
+#define DDRC_DRAMTMG4_T_RRD_MASK                               0x00000F00U
+
+/*
+* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ
+    * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM
+    * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t
+    * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho
+    * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG4_T_RP_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RP_SHIFT 
+#undef DDRC_DRAMTMG4_T_RP_MASK 
+#define DDRC_DRAMTMG4_T_RP_DEFVAL                              0x05040405
+#define DDRC_DRAMTMG4_T_RP_SHIFT                               0
+#define DDRC_DRAMTMG4_T_RP_MASK                                0x0000001FU
+
+/*
+* This is the time before Self Refresh Exit that CK is maintained as a val
+    * id clock before issuing SRX. Specifies the clock stable time before SRX.
+    *  Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK
+    * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_
+    * FREQ_RATIO=2, program this to recommended value divided by two and round
+    *  it up to next integer.
+*/
+#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRX_MASK 
+#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                           0x05050403
+#define DDRC_DRAMTMG5_T_CKSRX_SHIFT                            24
+#define DDRC_DRAMTMG5_T_CKSRX_MASK                             0x0F000000U
+
+/*
+* This is the time after Self Refresh Down Entry that CK is maintained as
+    * a valid clock. Specifies the clock disable delay after SRE. Recommended
+    * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1
+    * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations
+    *  with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw
+    * o and round it up to next integer.
+*/
+#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRE_MASK 
+#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                           0x05050403
+#define DDRC_DRAMTMG5_T_CKSRE_SHIFT                            16
+#define DDRC_DRAMTMG5_T_CKSRE_MASK                             0x000F0000U
+
+/*
+* Minimum CKE low width for Self refresh or Self refresh power down entry
+    * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF
+    * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2:
+    * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ
+    * _RATIO=2, program this to recommended value divided by two and round it
+    * up to next integer.
+*/
+#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKESR_MASK 
+#define DDRC_DRAMTMG5_T_CKESR_DEFVAL                           0x05050403
+#define DDRC_DRAMTMG5_T_CKESR_SHIFT                            8
+#define DDRC_DRAMTMG5_T_CKESR_MASK                             0x00003F00U
+
+/*
+* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr
+    * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP
+    * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/
+    * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration
+    * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and
+    * round it up to the next integer value. Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKE_MASK 
+#define DDRC_DRAMTMG5_T_CKE_DEFVAL                             0x05050403
+#define DDRC_DRAMTMG5_T_CKE_SHIFT                              0
+#define DDRC_DRAMTMG5_T_CKE_MASK                               0x0000001FU
+
+/*
+* This is the time after Deep Power Down Entry that CK is maintained as a
+    * valid clock. Specifies the clock disable delay after DPDE. Recommended s
+    * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_
+    * FREQ_RATIO=2, program this to recommended value divided by two and round
+    *  it up to next integer. This is only present for designs supporting mDDR
+    *  or LPDDR2/LPDDR3 devices.
+*/
+#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                          0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                           24
+#define DDRC_DRAMTMG6_T_CKDPDE_MASK                            0x0F000000U
+
+/*
+* This is the time before Deep Power Down Exit that CK is maintained as a
+    * valid clock before issuing DPDX. Specifies the clock stable time before
+    * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config
+    * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid
+    * ed by two and round it up to next integer. This is only present for desi
+    * gns supporting mDDR or LPDDR2 devices.
+*/
+#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                          0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                           16
+#define DDRC_DRAMTMG6_T_CKDPDX_MASK                            0x000F0000U
+
+/*
+* This is the time before Clock Stop Exit that CK is maintained as a valid
+    *  clock before issuing Clock Stop Exit. Specifies the clock stable time b
+    * efore next command after Clock Stop Exit. Recommended settings: - mDDR:
+    * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio
+    * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by
+    * two and round it up to next integer. This is only present for designs su
+    * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKCSX_MASK 
+#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                           0x02020005
+#define DDRC_DRAMTMG6_T_CKCSX_SHIFT                            0
+#define DDRC_DRAMTMG6_T_CKCSX_MASK                             0x0000000FU
+
+/*
+* This is the time after Power Down Entry that CK is maintained as a valid
+    *  clock. Specifies the clock disable delay after PDE. Recommended setting
+    * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration
+    * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t
+    * wo and round it up to next integer. This is only present for designs sup
+    * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDE_MASK 
+#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                           0x00000202
+#define DDRC_DRAMTMG7_T_CKPDE_SHIFT                            8
+#define DDRC_DRAMTMG7_T_CKPDE_MASK                             0x00000F00U
+
+/*
+* This is the time before Power Down Exit that CK is maintained as a valid
+    *  clock before issuing PDX. Specifies the clock stable time before PDX. R
+    * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c
+    * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value
+    * divided by two and round it up to next integer. This is only present for
+    *  designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDX_MASK 
+#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                           0x00000202
+#define DDRC_DRAMTMG7_T_CKPDX_SHIFT                            0
+#define DDRC_DRAMTMG7_T_CKPDX_MASK                             0x0000000FU
+
+/*
+* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and
+    * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this
+    * to the above value divided by 2 and round up to next integer value. Unit
+    * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com
+    * mands. Note: Ensure this is less than or equal to t_xs_x32.
+*/
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                     0x03034405
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                      24
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                       0x7F000000U
+
+/*
+* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S
+    * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th
+    * is to the above value divided by 2 and round up to next integer value. U
+    * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to
+    * t_xs_x32.
+*/
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                    0x03034405
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                     16
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                      0x007F0000U
+
+/*
+* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config
+    * urations with MEMC_FREQ_RATIO=2, program this to the above value divided
+    *  by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
+    * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
+*/
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                      0x03034405
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                       8
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                        0x00007F00U
+
+/*
+* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi
+    * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide
+    * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
+    *  Note: Used only for DDR2, DDR3 and DDR4 SDRAMs.
+*/
+#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                          0x03034405
+#define DDRC_DRAMTMG8_T_XS_X32_SHIFT                           0
+#define DDRC_DRAMTMG8_T_XS_X32_MASK                            0x0000007FU
+
+/*
+* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o
+    * nly with MEMC_FREQ_RATIO=2
+*/
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                  0x0004040D
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                   30
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                    0x40000000U
+
+/*
+* tCCD_S: This is the minimum time between two reads or two writes for dif
+    * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m
+    * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2
+    * , program this to (tCCD_S/2) and round it up to the next integer value.
+    * Present only in designs configured to support DDR4. Unit: clocks.
+*/
+#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_CCD_S_MASK 
+#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                           0x0004040D
+#define DDRC_DRAMTMG9_T_CCD_S_SHIFT                            16
+#define DDRC_DRAMTMG9_T_CCD_S_MASK                             0x00070000U
+
+/*
+* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif
+    * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th
+    * is to (tRRD_S/2) and round it up to the next integer value. Present only
+    *  in designs configured to support DDR4. Unit: Clocks.
+*/
+#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_RRD_S_MASK 
+#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                           0x0004040D
+#define DDRC_DRAMTMG9_T_RRD_S_SHIFT                            8
+#define DDRC_DRAMTMG9_T_RRD_S_MASK                             0x00000F00U
+
+/*
+* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command
+    *  for different bank group. Includes time for bus turnaround, recovery ti
+    * mes, and all per-bank, per-rank, and global constraints. Present only in
+    *  designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr
+    * ite latency - PL = Parity latency - BL = burst length. This must match t
+    * he value programmed in the BL bit of the mode register to the SDRAM - tW
+    * TR_S = internal write to read command delay for different bank group. Th
+    * is comes directly from the SDRAM specification. For configurations with
+    * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation
+    * by 2, and round it up to next integer.
+*/
+#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 
+#undef DDRC_DRAMTMG9_WR2RD_S_MASK 
+#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                           0x0004040D
+#define DDRC_DRAMTMG9_WR2RD_S_SHIFT                            0
+#define DDRC_DRAMTMG9_WR2RD_S_MASK                             0x0000003FU
+
+/*
+* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL
+    * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2
+    * ) and round it up to the next integer value. Present only in designs con
+    * figured to support DDR4. Unit: Multiples of 32 clocks.
+*/
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                0x440C021C
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                 24
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                  0x7F000000U
+
+/*
+* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For
+    * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2
+    * )+1. Present only in designs configured to support DDR4. Unit: clocks.
+*/
+#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 
+#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                         0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                          16
+#define DDRC_DRAMTMG11_T_MPX_LH_MASK                           0x001F0000U
+
+/*
+* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_
+    * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int
+    * eger value. Present only in designs configured to support DDR4. Unit: Cl
+    * ocks.
+*/
+#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_S_MASK 
+#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                          0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_S_SHIFT                           8
+#define DDRC_DRAMTMG11_T_MPX_S_MASK                            0x00000300U
+
+/*
+* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i
+    * n designs configured to support DDR4. Unit: Clocks. For configurations w
+    * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat
+    * ion by 2, and round it up to next integer.
+*/
+#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 
+#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 
+#undef DDRC_DRAMTMG11_T_CKMPE_MASK 
+#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                          0x440C021C
+#define DDRC_DRAMTMG11_T_CKMPE_SHIFT                           0
+#define DDRC_DRAMTMG11_T_CKMPE_MASK                            0x0000001FU
+
+/*
+* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg
+    * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr
+    * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu
+    * e.
+*/
+#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 
+#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 
+#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                         0x00020610
+#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                          16
+#define DDRC_DRAMTMG12_T_CMDCKE_MASK                           0x00030000U
+
+/*
+* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat
+    * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u
+    * p to next integer value.
+*/
+#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 
+#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                        0x00020610
+#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                         8
+#define DDRC_DRAMTMG12_T_CKEHCMD_MASK                          0x00000F00U
+
+/*
+* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode.
+    * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2)
+    * and round it up to next integer value.
+*/
+#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 
+#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                        0x00020610
+#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                         0
+#define DDRC_DRAMTMG12_T_MRD_PDA_MASK                          0x0000001FU
+
+/*
+* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg
+    * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration
+    * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati
+    * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre
+    * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                         0x02000040
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                          31
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                           0x80000000U
+
+/*
+* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres
+    * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2
+    * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio
+    * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i
+    * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present
+    * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                        0x02000040
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                         30
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                          0x40000000U
+
+/*
+* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC
+    * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
+    * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co
+    * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share
+    * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR
+    * 3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                  0x02000040
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                   29
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                    0x20000000U
+
+/*
+* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit.
+    *  Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com
+    * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4
+    *  mode. This is only present for designs supporting DDR4 devices.
+*/
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                      0x02000040
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                       28
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                        0x10000000U
+
+/*
+* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe
+    * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St
+    * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO
+    * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int
+    * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th
+    * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t
+    * o the next integer value. Unit: Clock cycles. This is only present for d
+    * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                       0x02000040
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                        16
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                         0x07FF0000U
+
+/*
+* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of
+    *  NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command
+    * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t
+    * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy
+    * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP
+    * DDR3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                      0x02000040
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                       0
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                        0x000003FFU
+
+/*
+* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati
+    * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_
+    * RATIO=2, program this to tZQReset/2 and round it up to the next integer
+    * value. Unit: Clock cycles. This is only present for designs supporting L
+    * PDDR2/LPDDR3/LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                      0x02000100
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                       20
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                        0x3FF00000U
+
+/*
+* Average interval to wait between automatically issuing ZQCS (ZQ calibrat
+    * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR
+    * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles
+    * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3
+    * /LPDDR4 devices.
+*/
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL           0x02000100
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT            0
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK             0x000FFFFFU
+
+/*
+* Specifies the number of DFI clock cycles after an assertion or de-assert
+    * ion of the DFI control signals that the control signals at the PHY-DRAM
+    * interface reflect the assertion or de-assertion. If the DFI clock and th
+    * e memory clock are not phase-aligned, this timing parameter should be ro
+    * unded up to the next integer value. Note that if using RDIMM, it is nece
+    * ssary to increment this parameter by RDIMM's extra cycle of latency in t
+    * erms of DFI clock.
+*/
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                   0x07020002
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                    24
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                     0x1F000000U
+
+/*
+* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
+    * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
+    * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
+    *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
+    *  value.
+*/
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                 0x07020002
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                  23
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                   0x00800000U
+
+/*
+* Time from the assertion of a read command on the DFI interface to the as
+    * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
+    * ect value. This corresponds to the DFI parameter trddata_en. Note that,
+    * depending on the PHY, if using RDIMM, it may be necessary to use the val
+    * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
+    * the extra cycle of latency through the RDIMM. Unit: Clocks
+*/
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                    0x07020002
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                     16
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                      0x003F0000U
+
+/*
+* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
+    * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
+    *  in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
+    * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
+    *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
+    * n for correct value.
+*/
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                 0x07020002
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                  15
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                   0x00008000U
+
+/*
+* Specifies the number of clock cycles between when dfi_wrdata_en is asser
+    * ted to when the associated write data is driven on the dfi_wrdata signal
+    * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
+    *  specification for correct value. Note, max supported value is 8. Unit:
+    * Clocks
+*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                    0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                     8
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                      0x00003F00U
+
+/*
+* Write latency Number of clocks from the write command to write data enab
+    * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
+    * lat. Refer to PHY specification for correct value.Note that, depending o
+    * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
+    *  in the calculation of tphy_wrlat. This is to compensate for the extra c
+    * ycle of latency through the RDIMM.
+*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                     0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                      0
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                       0x0000003FU
+
+/*
+* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
+    *  asserted and when the associated command is driven. This field is used
+    * for CAL mode, should be set to '0' or the value which matches the CAL mo
+    * de register setting in the DRAM. If the PHY can add the latency for CAL
+    * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
+*/
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                      0x00000404
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                       28
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                        0xF0000000U
+
+/*
+* Specifies the number of DFI PHY clocks between when the dfi_cs signal is
+    *  asserted and when the associated dfi_parity_in signal is driven.
+*/
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                    0x00000404
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                     24
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                      0x03000000U
+
+/*
+* Specifies the number of DFI clocks between when the dfi_wrdata_en signal
+    *  is asserted and when the corresponding write data transfer is completed
+    *  on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d
+    * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set
+    *  to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI
+    *  2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va
+    * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_
+    * RATIO=2, divide PHY's value by 2 and round up to next integer. If using
+    * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks
+*/
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                 0x00000404
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                  16
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                   0x001F0000U
+
+/*
+* Specifies the number of DFI clock cycles from the assertion of the dfi_d
+    * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev
+    * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock
+    * and the memory clock are not phase aligned, this timing parameter should
+    *  be rounded up to the next integer value.
+*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL             0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT              8
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK               0x00000F00U
+
+/*
+* Specifies the number of DFI clock cycles from the de-assertion of the df
+    * i_dram_clk_disable signal on the DFI until the first valid rising edge o
+    * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the
+    *  DFI clock and the memory clock are not phase aligned, this timing param
+    * eter should be rounded up to the next integer value.
+*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL              0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT               0
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                0x0000000FU
+
+/*
+* Setting for DFI's tlp_resp time. Same value is used for both Power Down,
+    *  Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s
+    * pecification onwards, recommends using a fixed value of 7 always.
+*/
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                     0x07000000
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                      24
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                       0x0F000000U
+
+/*
+* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente
+    * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32
+    * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5
+    * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles -
+    * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553
+    * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T
+    * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices
+    * .
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                 20
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                  0x00F00000U
+
+/*
+* Enables DFI Low Power interface handshaking during Deep Power Down Entry
+    * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup
+    * porting mDDR or LPDDR2/LPDDR3 devices.
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                    0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                     16
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                      0x00010000U
+
+/*
+* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered
+    * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc
+    * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512
+    * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9
+    *  - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c
+    * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                 0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                  12
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                   0x0000F000U
+
+/*
+* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex
+    * it. - 0 - Disabled - 1 - Enabled
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                      8
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                       0x00000100U
+
+/*
+* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered.
+    * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle
+    * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy
+    * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 -
+    *  8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc
+    * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                 0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                  4
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                   0x000000F0U
+
+/*
+* Enables DFI Low Power interface handshaking during Power Down Entry/Exit
+    * . - 0 - Disabled - 1 - Enabled
+*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                      0
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                       0x00000001U
+
+/*
+* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is
+    *  entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1
+    * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x
+    * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl
+    * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC -
+    *  65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi
+    * ted This is only present for designs supporting DDR4 devices.
+*/
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL               0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                4
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                 0x000000F0U
+
+/*
+* Enables DFI Low Power interface handshaking during Maximum Power Saving
+    * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d
+    * esigns supporting DDR4 devices.
+*/
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                   0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                    0
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                     0x00000001U
+
+/*
+* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
+    * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc
+    * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically.
+*/
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL                   0x00400003
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT                    31
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK                     0x80000000U
+
+/*
+* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2
+    *  following a self-refresh exit. The core must issue the dfi_ctrlupd_req
+    * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct
+    * rlupd_req after exiting self-refresh.
+*/
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 
+#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL               0x00400003
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT                30
+#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK                 0x40000000U
+
+/*
+* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si
+    * gnal can assert. Lowest value to assign to this variable is 0x40. Unit:
+    * Clocks
+*/
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL                   0x00400003
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT                    16
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK                     0x03FF0000U
+
+/*
+* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si
+    * gnal must be asserted. The uMCTL2 expects the PHY to respond within this
+    *  time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup
+    * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this
+    * variable is 0x3. Unit: Clocks
+*/
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 
+#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL                   0x00400003
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT                    0
+#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK                     0x000003FFU
+
+/*
+* This is the minimum amount of time between uMCTL2 initiated DFI update r
+    * equests (which is executed whenever the uMCTL2 is idle). Set this number
+    *  higher to reduce the frequency of update requests, which can have a sma
+    * ll impact on the latency of the first read request when the uMCTL2 is id
+    * le. Unit: 1024 clocks
+*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL   0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT    16
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK     0x00FF0000U
+
+/*
+* This is the maximum amount of time between uMCTL2 initiated DFI update r
+    * equests. This timer resets with each update request; when the timer expi
+    * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd
+    * _ackx is received. PHY can use this idle time to recalibrate the delay l
+    * ines to the DLLs. The DFI controller update is also used to reset PHY FI
+    * FO pointers in case of data capture errors. Updates are required to main
+    * tain calibration over PVT, but frequent updates may impact performance.
+    * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must
+    *  be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl
+    * ocks
+*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL   0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT    0
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK     0x000000FFU
+
+/*
+* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal
+    * s are active low - 1: Signals are active high
+*/
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL               0x00000001
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                2
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                 0x00000004U
+
+/*
+* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality.
+    *  - 1 - PHY implements DBI functionality. Present only in designs configu
+    * red to support DDR4 and LPDDR4.
+*/
+#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 
+#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                       0x00000001
+#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                        1
+#define DDRC_DFIMISC_PHY_DBI_MODE_MASK                         0x00000002U
+
+/*
+* PHY initialization complete enable signal. When asserted the dfi_init_co
+    * mplete signal can be used to trigger SDRAM initialisation
+*/
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL               0x00000001
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                0
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                 0x00000001U
+
+/*
+* >Number of clocks between when a read command is sent on the DFI control
+    *  interface and when the associated dfi_rddata_cs signal is asserted. Thi
+    * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe
+    * cification for correct value.
+*/
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                   0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                    8
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                     0x00003F00U
+
+/*
+* Number of clocks between when a write command is sent on the DFI control
+    *  interface and when the associated dfi_wrdata_cs signal is asserted. Thi
+    * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe
+    * cification for correct value.
+*/
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                   0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                    0
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                     0x0000003FU
+
+/*
+* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D
+    * BI is enabled. This signal must be set the same value as DRAM's mode reg
+    * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b
+    * e set to 0. - LPDDR4: MR3[6]
+*/
+#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_RD_DBI_EN_MASK 
+#define DDRC_DBICTL_RD_DBI_EN_DEFVAL                           0x00000001
+#define DDRC_DBICTL_RD_DBI_EN_SHIFT                            2
+#define DDRC_DBICTL_RD_DBI_EN_MASK                             0x00000004U
+
+/*
+* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ
+    * e DBI is enabled. This signal must be set the same value as DRAM's mode
+    * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus
+    * t be set to 0. - LPDDR4: MR3[7]
+*/
+#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_WR_DBI_EN_MASK 
+#define DDRC_DBICTL_WR_DBI_EN_DEFVAL                           0x00000001
+#define DDRC_DBICTL_WR_DBI_EN_SHIFT                            1
+#define DDRC_DBICTL_WR_DBI_EN_MASK                             0x00000002U
+
+/*
+* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi
+    * s signal must be set the same logical value as DRAM's mode register. - D
+    * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th
+    * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13
+    * [5] which is opposite polarity from this signal
+*/
+#undef DDRC_DBICTL_DM_EN_DEFVAL 
+#undef DDRC_DBICTL_DM_EN_SHIFT 
+#undef DDRC_DBICTL_DM_EN_MASK 
+#define DDRC_DBICTL_DM_EN_DEFVAL                               0x00000001
+#define DDRC_DBICTL_DM_EN_SHIFT                                0
+#define DDRC_DBICTL_DM_EN_MASK                                 0x00000001U
+
+/*
+* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t
+    * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined
+    *  by adding the internal base to the value of this field. If set to 31, r
+    * ank address bit 0 is set to 0.
+*/
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL                   
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                    0
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                     0x0000001FU
+
+/*
+* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t
+    * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined
+    * by adding the internal base to the value of this field. If set to 31, ba
+    * nk address bit 2 is set to 0.
+*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                    16
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                     0x001F0000U
+
+/*
+* Selects the HIF address bits used as bank address bit 1. Valid Range: 0
+    * to 30 Internal Base: 3 The selected HIF address bit for each of the bank
+    *  address bits is determined by adding the internal base to the value of
+    * this field.
+*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                    8
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                     0x00001F00U
+
+/*
+* Selects the HIF address bits used as bank address bit 0. Valid Range: 0
+    * to 30 Internal Base: 2 The selected HIF address bit for each of the bank
+    *  address bits is determined by adding the internal base to the value of
+    * this field.
+*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                    0
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                     0x0000001FU
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base
+    * : 5 The selected HIF address bit is determined by adding the internal ba
+    * se to the value of this field. If set to 15, this column address bit is
+    * set to 0.
+*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                     24
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                      0x0F000000U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base:
+    *  4 The selected HIF address bit is determined by adding the internal bas
+    * e to the value of this field. If set to 15, this column address bit is s
+    * et to 0.
+*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                     16
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                      0x000F0000U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s
+    * elected HIF address bit is determined by adding the internal base to the
+    *  value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1
+    * 6, it is required to program this to 0, hence register does not exist in
+    *  this case.
+*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                     8
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                      0x00000F00U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s
+    * elected HIF address bit is determined by adding the internal base to the
+    *  value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8
+    *  or 16, it is required to program this to 0.
+*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                     0
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                      0x0000000FU
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode:
+    * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/
+    * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
+    * HIF address bit is determined by adding the internal base to the value o
+    * f this field. If set to 15, this column address bit is set to 0. Note: P
+    * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo
+    * r indicating auto-precharge, and hence no source address bit can be mapp
+    * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit
+    * for auto-precharge in the CA bus and hence column bit 10 is used.
+*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                     24
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                      0x0F000000U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0
+    *  to 7, and 15 Internal Base: 8 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi
+    * cation, column address bit 10 is reserved for indicating auto-precharge,
+    *  and hence no source address bit can be mapped to column address bit 10.
+    *  In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA
+    *  bus and hence column bit 10 is used.
+*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                     16
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                      0x000F0000U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base:
+    *  7 The selected HIF address bit is determined by adding the internal bas
+    * e to the value of this field. If set to 15, this column address bit is s
+    * et to 0.
+*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                     8
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                      0x00000F00U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu
+    * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit
+    * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base:
+    *  6 The selected HIF address bit is determined by adding the internal bas
+    * e to the value of this field. If set to 15, this column address bit is s
+    * et to 0.
+*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                     0
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                      0x0000000FU
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m
+    * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un
+    * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7,
+    *  and 15 Internal Base: 11 The selected HIF address bit is determined by
+    * adding the internal base to the value of this field. If set to 15, this
+    * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio
+    * n, column address bit 10 is reserved for indicating auto-precharge, and
+    * hence no source address bit can be mapped to column address bit 10. In L
+    * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus
+    * and hence column bit 10 is used.
+*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                    8
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                     0x00000F00U
+
+/*
+* - Full bus width mode: Selects the HIF address bit used as column addres
+    * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the
+    * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode)
+    * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied
+    *  to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
+    *  address bit is determined by adding the internal base to the value of t
+    * his field. If set to 15, this column address bit is set to 0. Note: Per
+    * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i
+    * ndicating auto-precharge, and hence no source address bit can be mapped
+    * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
+    *  auto-precharge in the CA bus and hence column bit 10 is used.
+*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                    0
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                     0x0000000FU
+
+/*
+* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 11 is set to 0.
+*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                    24
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                     0x0F000000U
+
+/*
+* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran
+    * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row
+    *  address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro
+    * w address bit 10) The selected HIF address bit for each of the row addre
+    * ss bits is determined by adding the internal base to the value of this f
+    * ield. When value 15 is used the values of row address bits 2 to 10 are d
+    * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
+*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                 0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                  16
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                   0x000F0000U
+
+/*
+* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t
+    * o 11 Internal Base: 7 The selected HIF address bit for each of the row a
+    * ddress bits is determined by adding the internal base to the value of th
+    * is field.
+*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                     8
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                      0x00000F00U
+
+/*
+* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t
+    * o 11 Internal Base: 6 The selected HIF address bit for each of the row a
+    * ddress bits is determined by adding the internal base to the value of th
+    * is field.
+*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                     0
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                      0x0000000FU
+
+/*
+* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1
+    *  - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]=
+    * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use.
+    *  All addresses are valid Present only in designs configured to support L
+    * PDDR3.
+*/
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                    31
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                     0x80000000U
+
+/*
+* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 15 is set to 0.
+*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                    24
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                     0x0F000000U
+
+/*
+* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 14 is set to 0.
+*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                    16
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                     0x000F0000U
+
+/*
+* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 13 is set to 0.
+*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                    8
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                     0x00000F00U
+
+/*
+* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 12 is set to 0.
+*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                    0
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                     0x0000000FU
+
+/*
+* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t
+    * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 17 is set to 0.
+*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                    8
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                     0x00000F00U
+
+/*
+* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t
+    * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine
+    * d by adding the internal base to the value of this field. If set to 15,
+    * row address bit 16 is set to 0.
+*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                    0
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                     0x0000000FU
+
+/*
+* Selects the HIF address bits used as bank group address bit 1. Valid Ran
+    * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea
+    * ch of the bank group address bits is determined by adding the internal b
+    * ase to the value of this field. If set to 31, bank group address bit 1 i
+    * s set to 0.
+*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                     0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                      8
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                       0x00001F00U
+
+/*
+* Selects the HIF address bits used as bank group address bit 0. Valid Ran
+    * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th
+    * e bank group address bits is determined by adding the internal base to t
+    * he value of this field.
+*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                     0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                      0
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                       0x0000001FU
+
+/*
+* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t
+    * o 11 Internal Base: 11 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                     24
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                      0x0F000000U
+
+/*
+* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t
+    * o 11 Internal Base: 10 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                     16
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                      0x000F0000U
+
+/*
+* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t
+    * o 11 Internal Base: 9 The selected HIF address bit for each of the row a
+    * ddress bits is determined by adding the internal base to the value of th
+    * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
+    * 10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                     8
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                      0x00000F00U
+
+/*
+* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t
+    * o 11 Internal Base: 8 The selected HIF address bit for each of the row a
+    * ddress bits is determined by adding the internal base to the value of th
+    * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_
+    * 10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                    0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                     0
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                      0x0000000FU
+
+/*
+* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t
+    * o 11 Internal Base: 15 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                    24
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                     0x0F000000U
+
+/*
+* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t
+    * o 11 Internal Base: 14 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                    16
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                     0x000F0000U
+
+/*
+* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t
+    * o 11 Internal Base: 13 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                    8
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                     0x00000F00U
+
+/*
+* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t
+    * o 11 Internal Base: 12 The selected HIF address bit for each of the row
+    * address bits is determined by adding the internal base to the value of t
+    * his field. This register field is used only when ADDRMAP5.addrmap_row_b2
+    * _10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                   0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                    0
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                     0x0000000FU
+
+/*
+* Selects the HIF address bits used as row address bit 10. Valid Range: 0
+    * to 11 Internal Base: 16 The selected HIF address bit for each of the row
+    *  address bits is determined by adding the internal base to the value of
+    * this field. This register field is used only when ADDRMAP5.addrmap_row_b
+    * 2_10 is set to value 15.
+*/
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL                  
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                   0
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                    0x0000000FU
+
+/*
+* Cycles to hold ODT for a write command. The minimum supported value is 2
+    * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800
+    * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D
+    * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR
+    * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (
+    * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
+*/
+#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                         0x04000400
+#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                          24
+#define DDRC_ODTCFG_WR_ODT_HOLD_MASK                           0x0F000000U
+
+/*
+* The delay, in clock cycles, from issuing a write command to setting ODT
+    * values associated with that command. ODT setting must remain constant fo
+    * r the entire time that DQS is driven by the uMCTL2. Recommended values:
+    * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL +
+    * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo
+    * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust
+    * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
+*/
+#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                        0x04000400
+#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                         16
+#define DDRC_ODTCFG_WR_ODT_DELAY_MASK                          0x001F0000U
+
+/*
+* Cycles to hold ODT for a read command. The minimum supported value is 2.
+    *  Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) -
+    *  BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8
+    * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p
+    * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) +
+    * RU(tODTon(max)/tCK)
+*/
+#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                         0x04000400
+#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                          8
+#define DDRC_ODTCFG_RD_ODT_HOLD_MASK                           0x00000F00U
+
+/*
+* The delay, in clock cycles, from issuing a read command to setting ODT v
+    * alues associated with that command. ODT setting must remain constant for
+    *  the entire time that DQS is driven by the uMCTL2. Recommended values: D
+    * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL
+    * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C
+    * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat
+    * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+    * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre
+    * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su
+    * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R
+    * U(tODTon(max)/tCK)
+*/
+#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                        0x04000400
+#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                         2
+#define DDRC_ODTCFG_RD_ODT_DELAY_MASK                          0x0000007CU
+
+/*
+* Indicates which remote ODTs must be turned on during a read from rank 1.
+    *  Each rank has a remote ODT (in the SDRAM) which can be turned on by set
+    * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
+    * s controlled by bit next to the LSB, etc. For each rank, set its bit to
+    * 1 to enable its ODT. Present only in configurations that have 2 or more
+    * ranks
+*/
+#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                        0x00002211
+#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                         12
+#define DDRC_ODTMAP_RANK1_RD_ODT_MASK                          0x00003000U
+
+/*
+* Indicates which remote ODTs must be turned on during a write to rank 1.
+    * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
+    * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
+    *  controlled by bit next to the LSB, etc. For each rank, set its bit to 1
+    *  to enable its ODT. Present only in configurations that have 2 or more r
+    * anks
+*/
+#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                        0x00002211
+#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                         8
+#define DDRC_ODTMAP_RANK1_WR_ODT_MASK                          0x00000300U
+
+/*
+* Indicates which remote ODTs must be turned on during a read from rank 0.
+    *  Each rank has a remote ODT (in the SDRAM) which can be turned on by set
+    * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i
+    * s controlled by bit next to the LSB, etc. For each rank, set its bit to
+    * 1 to enable its ODT.
+*/
+#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                        0x00002211
+#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                         4
+#define DDRC_ODTMAP_RANK0_RD_ODT_MASK                          0x00000030U
+
+/*
+* Indicates which remote ODTs must be turned on during a write to rank 0.
+    * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett
+    * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is
+    *  controlled by bit next to the LSB, etc. For each rank, set its bit to 1
+    *  to enable its ODT.
+*/
+#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                        0x00002211
+#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                         0
+#define DDRC_ODTMAP_RANK0_WR_ODT_MASK                          0x00000003U
+
+/*
+* When the preferred transaction store is empty for these many clock cycle
+    * s, switch to the alternate transaction store if it is non-empty. The rea
+    * d transaction store (both high and low priority) is the default preferre
+    * d transaction store and the write transaction store is the alternative s
+    * tore. When prefer write over read is set this is reversed. 0x0 is a lega
+    * l value for this register. When set to 0x0, the transaction store switch
+    * ing will happen immediately when the switching conditions become true. F
+    * OR PERFORMANCE ONLY
+*/
+#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 
+#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                        0x00002005
+#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                         24
+#define DDRC_SCHED_RDWR_IDLE_GAP_MASK                          0x7F000000U
+
+/*
+* UNUSED
+*/
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL               0x00002005
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                16
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                 0x00FF0000U
+
+/*
+* Number of entries in the low priority transaction store is this value +
+    * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent
+    * ries available for the high priority transaction store. Setting this to
+    * maximum value allocates all entries to low priority transaction store. S
+    * etting this to 0 allocates 1 entry to low priority transaction store and
+    *  the rest to high priority transaction store. Note: In ECC configuration
+    * s, the numbers of write and low priority read credits issued is one less
+    *  than in the non-ECC case. One entry each is reserved in the write and l
+    * ow-priority read CAMs for storing the RMW requests arising out of single
+    *  bit error correction RMW operation.
+*/
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 
+#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                      0x00002005
+#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                       8
+#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                        0x00003F00U
+
+/*
+* If true, bank is kept open only while there are page hit transactions av
+    * ailable in the CAM to that bank. The last read or write command in the C
+    * AM with a bank and page hit will be executed with auto-precharge if SCHE
+    * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos
+    * e_timer is set to 0, explicit precharge (and not auto-precharge) may be
+    * issued in some cases where there is a mode switch between Write and Read
+    *  or between LPR and HPR. The Read and Write commands that are executed a
+    * s part of the ECC scrub requests are also executed without auto-precharg
+    * e. If false, the bank remains open until there is a need to close it (to
+    *  open a different page, or for page timeout or refresh timeout) - also k
+    * nown as open page policy. The open page policy can be overridden by sett
+    * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
+    * The pageclose feature provids a midway between Open and Close page polic
+    * ies. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_SCHED_PAGECLOSE_DEFVAL 
+#undef DDRC_SCHED_PAGECLOSE_SHIFT 
+#undef DDRC_SCHED_PAGECLOSE_MASK 
+#define DDRC_SCHED_PAGECLOSE_DEFVAL                            0x00002005
+#define DDRC_SCHED_PAGECLOSE_SHIFT                             2
+#define DDRC_SCHED_PAGECLOSE_MASK                              0x00000004U
+
+/*
+* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
+*/
+#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 
+#undef DDRC_SCHED_PREFER_WRITE_SHIFT 
+#undef DDRC_SCHED_PREFER_WRITE_MASK 
+#define DDRC_SCHED_PREFER_WRITE_DEFVAL                         0x00002005
+#define DDRC_SCHED_PREFER_WRITE_SHIFT                          1
+#define DDRC_SCHED_PREFER_WRITE_MASK                           0x00000002U
+
+/*
+* Active low signal. When asserted ('0'), all incoming transactions are fo
+    * rced to low priority. This implies that all High Priority Read (HPR) and
+    *  Variable Priority Read commands (VPR) will be treated as Low Priority R
+    * ead (LPR) commands. On the write side, all Variable Priority Write (VPW)
+    *  commands will be treated as Normal Priority Write (NPW) commands. Forci
+    * ng the incoming transactions to low priority implicitly turns off Bypass
+    *  path for read commands. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 
+#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                      0x00002005
+#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                       0
+#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                        0x00000001U
+
+/*
+* Number of transactions that are serviced once the LPR queue goes critica
+    * l is the smaller of: - (a) This number - (b) Number of transactions avai
+    * lable. Unit: Transaction. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL               0x0F00007F
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                24
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                 0xFF000000U
+
+/*
+* Number of clocks that the LPR queue can be starved before it goes critic
+    * al. The minimum valid functional value for this register is 0x1. Program
+    * ming it to 0x0 will disable the starvation functionality; during normal
+    * operation, this function should not be disabled as it will cause excessi
+    * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                    0x0F00007F
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                     0
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                      0x0000FFFFU
+
+/*
+* Number of transactions that are serviced once the WR queue goes critical
+    *  is the smaller of: - (a) This number - (b) Number of transactions avail
+    * able. Unit: Transaction. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                  0x0F00007F
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                   24
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                    0xFF000000U
+
+/*
+* Number of clocks that the WR queue can be starved before it goes critica
+    * l. The minimum valid functional value for this register is 0x1. Programm
+    * ing it to 0x0 will disable the starvation functionality; during normal o
+    * peration, this function should not be disabled as it will cause excessiv
+    * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+*/
+#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 
+#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 
+#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                       0x0F00007F
+#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                        0
+#define DDRC_PERFWR1_W_MAX_STARVE_MASK                         0x0000FFFFU
+
+/*
+* DQ nibble map for DQ bits [12-15] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL                 0x00000000
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT                  24
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK                   0xFF000000U
+
+/*
+* DQ nibble map for DQ bits [8-11] Present only in designs configured to s
+    * upport DDR4.
+*/
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL                  0x00000000
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT                   16
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK                    0x00FF0000U
+
+/*
+* DQ nibble map for DQ bits [4-7] Present only in designs configured to su
+    * pport DDR4.
+*/
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL                   0x00000000
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT                    8
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK                     0x0000FF00U
+
+/*
+* DQ nibble map for DQ bits [0-3] Present only in designs configured to su
+    * pport DDR4.
+*/
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 
+#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL                   0x00000000
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT                    0
+#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK                     0x000000FFU
+
+/*
+* DQ nibble map for DQ bits [28-31] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL                 0x00000000
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT                  24
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK                   0xFF000000U
+
+/*
+* DQ nibble map for DQ bits [24-27] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL                 0x00000000
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT                  16
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK                   0x00FF0000U
+
+/*
+* DQ nibble map for DQ bits [20-23] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL                 0x00000000
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT                  8
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK                   0x0000FF00U
+
+/*
+* DQ nibble map for DQ bits [16-19] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 
+#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL                 0x00000000
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT                  0
+#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK                   0x000000FFU
+
+/*
+* DQ nibble map for DQ bits [44-47] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL                 0x00000000
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT                  24
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK                   0xFF000000U
+
+/*
+* DQ nibble map for DQ bits [40-43] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL                 0x00000000
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT                  16
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK                   0x00FF0000U
+
+/*
+* DQ nibble map for DQ bits [36-39] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL                 0x00000000
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT                  8
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK                   0x0000FF00U
+
+/*
+* DQ nibble map for DQ bits [32-35] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 
+#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL                 0x00000000
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT                  0
+#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK                   0x000000FFU
+
+/*
+* DQ nibble map for DQ bits [60-63] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL                 0x00000000
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT                  24
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK                   0xFF000000U
+
+/*
+* DQ nibble map for DQ bits [56-59] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL                 0x00000000
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT                  16
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK                   0x00FF0000U
+
+/*
+* DQ nibble map for DQ bits [52-55] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL                 0x00000000
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT                  8
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK                   0x0000FF00U
+
+/*
+* DQ nibble map for DQ bits [48-51] Present only in designs configured to
+    * support DDR4.
+*/
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 
+#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL                 0x00000000
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT                  0
+#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK                   0x000000FFU
+
+/*
+* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf
+    * igured to support DDR4.
+*/
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL                0x00000000
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT                 8
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK                  0x0000FF00U
+
+/*
+* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf
+    * igured to support DDR4.
+*/
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 
+#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL                0x00000000
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT                 0
+#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK                  0x000000FFU
+
+/*
+* All even ranks have the same DQ mapping controled by DQMAP0-4 register a
+    * s rank 0. This register provides DQ swap function for all odd ranks to s
+    * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b
+    * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba
+    * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs
+    *  configured to support DDR4.
+*/
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL                    
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                     0
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                      0x00000001U
+
+/*
+* When this is set to '0', auto-precharge is disabled for the flushed comm
+    * and in a collision case. Collision cases are write followed by read to s
+    * ame address, read followed by write to same address, or write followed b
+    * y write to same address with DBG0.dis_wc bit = 1 (where same address com
+    * parisons exclude the two address bits representing critical word). FOR D
+    * EBUG ONLY.
+*/
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                0x00000000
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                 4
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                  0x00000010U
+
+/*
+* When 1, disable write combine. FOR DEBUG ONLY
+*/
+#undef DDRC_DBG0_DIS_WC_DEFVAL 
+#undef DDRC_DBG0_DIS_WC_SHIFT 
+#undef DDRC_DBG0_DIS_WC_MASK 
+#define DDRC_DBG0_DIS_WC_DEFVAL                                0x00000000
+#define DDRC_DBG0_DIS_WC_SHIFT                                 0
+#define DDRC_DBG0_DIS_WC_MASK                                  0x00000001U
+
+/*
+* Setting this register bit to 1 allows refresh and ZQCS commands to be tr
+    * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD.
+    * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore
+    * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and
+    *  ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor
+    * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no
+    *  function, and are ignored by the uMCTL2 logic. This register is static,
+    *  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is
+    * asserted (0).
+*/
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                        0x00000000
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                         31
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                          0x80000000U
+
+/*
+* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct
+    * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit
+    *  is automatically cleared. This operation must only be performed when DF
+    * IUPD0.dis_auto_ctrlupd=1.
+*/
+#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 
+#undef DDRC_DBGCMD_CTRLUPD_SHIFT 
+#undef DDRC_DBGCMD_CTRLUPD_MASK 
+#define DDRC_DBGCMD_CTRLUPD_DEFVAL                             0x00000000
+#define DDRC_DBGCMD_CTRLUPD_SHIFT                              5
+#define DDRC_DBGCMD_CTRLUPD_MASK                               0x00000020U
+
+/*
+* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (
+    * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi
+    * s request is stored in the uMCTL2, the bit is automatically cleared. Thi
+    * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom
+    * mended NOT to set this register bit if in Init operating mode. This regi
+    * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown
+    * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo
+    * de.
+*/
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                      0x00000000
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                       4
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                        0x00000010U
+
+/*
+* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
+    * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be
+    *  set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s
+    * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
+    * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
+    * t or Deep power-down operating modes or Maximum Power Saving Mode.
+*/
+#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                       0x00000000
+#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                        1
+#define DDRC_DBGCMD_RANK1_REFRESH_MASK                         0x00000002U
+
+/*
+* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres
+    * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be
+    *  set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s
+    * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_
+    * auto_refresh=1. It is recommended NOT to set this register bit if in Ini
+    * t or Deep power-down operating modes or Maximum Power Saving Mode.
+*/
+#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                       0x00000000
+#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                        0
+#define DDRC_DBGCMD_RANK0_REFRESH_MASK                         0x00000001U
+
+/*
+* Enable quasi-dynamic register programming outside reset. Program registe
+    * r to 0 to enable quasi-dynamic programming. Set back register to 1 once
+    * programming is done.
+*/
+#undef DDRC_SWCTL_SW_DONE_DEFVAL 
+#undef DDRC_SWCTL_SW_DONE_SHIFT 
+#undef DDRC_SWCTL_SW_DONE_MASK 
+#define DDRC_SWCTL_SW_DONE_DEFVAL                              
+#define DDRC_SWCTL_SW_DONE_SHIFT                               0
+#define DDRC_SWCTL_SW_DONE_MASK                                0x00000001U
+
+/*
+* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand
+    * s every AXI burst into multiple HIF commands, using the memory burst len
+    * gth as a unit. If set to 1, then XPI will use half of the memory burst l
+    * ength as a unit. This applies to both reads and writes. When MSTR.data_b
+    * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i
+    * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d
+    * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd
+    * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali
+    * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT
+    * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an
+    * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST
+    * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs
+    * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR
+    * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared
+    * -AC is enabled
+*/
+#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 
+#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 
+#undef DDRC_PCCFG_BL_EXP_MODE_MASK 
+#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                          0x00000000
+#define DDRC_PCCFG_BL_EXP_MODE_SHIFT                           8
+#define DDRC_PCCFG_BL_EXP_MODE_MASK                            0x00000100U
+
+/*
+* Page match four limit. If set to 1, limits the number of consecutive sam
+    * e page DDRC transactions that can be granted by the Port Arbiter to four
+    *  when Page Match feature is enabled. If set to 0, there is no limit impo
+    * sed on number of consecutive same page DDRC transactions.
+*/
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                      0x00000000
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                       4
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                        0x00000010U
+
+/*
+* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l
+    * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw
+    * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_
+    * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a
+    * t DDRC are driven to 1b'0.
+*/
+#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 
+#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                       0x00000000
+#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                        0
+#define DDRC_PCCFG_GO2CRITICAL_EN_MASK                         0x00000001U
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_0_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_0_PORT_EN_MASK 
+#define DDRC_PCTRL_0_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_0_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_0_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_1_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_1_PORT_EN_MASK 
+#define DDRC_PCTRL_1_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_1_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_1_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region2. For dual address q
+    * ueue configurations, region2 maps to the red address queue. Valid values
+    *  are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
+    *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
+    * ased to LPR traffic.
+*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                 24
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                  0x03000000U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level2 indicating the end of region1 mapping; start of region
+    * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
+    * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
+    *  that for PA, arqos values are used directly as port priorities, where t
+    * he higher the value corresponds to higher port priority. All of the map_
+    * level* registers must be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                  8
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                   0x00000F00U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_2_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_2_PORT_EN_MASK 
+#define DDRC_PCTRL_2_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_2_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_2_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region2. For dual address q
+    * ueue configurations, region2 maps to the red address queue. Valid values
+    *  are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN
+    *  = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali
+    * ased to LPR traffic.
+*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                 24
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                  0x03000000U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level2 indicating the end of region1 mapping; start of region
+    * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi
+    * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note
+    *  that for PA, arqos values are used directly as port priorities, where t
+    * he higher the value corresponds to higher port priority. All of the map_
+    * level* registers must be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                 0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                  8
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                   0x00000F00U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                 0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_3_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_3_PORT_EN_MASK 
+#define DDRC_PCTRL_3_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_3_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_3_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
+    *  traffic.
+*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                20
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                 0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
+    * traffic.
+*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                16
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                 0x00030000U
+
+/*
+* Separation level indicating the end of region0 mapping; start of region0
+    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
+    * . Note that for PA, awqos values are used directly as port priorities, w
+    * here the higher the value corresponds to higher port priority.
+*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                  0
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for write transactions.
+*/
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL               
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                0
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_4_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_4_PORT_EN_MASK 
+#define DDRC_PCTRL_4_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_4_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_4_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
+    *  traffic.
+*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                20
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                 0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
+    * traffic.
+*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                16
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                 0x00030000U
+
+/*
+* Separation level indicating the end of region0 mapping; start of region0
+    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
+    * . Note that for PA, awqos values are used directly as port priorities, w
+    * here the higher the value corresponds to higher port priority.
+*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                  0
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for write transactions.
+*/
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL               
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                0
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL               0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena
+    * bled and arurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD
+    * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar
+    * urgent signal can be asserted anytime and as long as required which is i
+    * ndependent of address handshaking (it is not associated with any particu
+    * lar command).
+*/
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                  0x00000000
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the read channel of the port.
+*/
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                   0x00000000
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of read aging counters. These counters
+    *  will be parallel loaded after reset, or after each grant to the corresp
+    * onding port. The aging counters down-count every clock cycle where the p
+    * ort is requesting but not granted. The higher significant 5-bits of the
+    * read aging counter sets the priority of the read channel of a given port
+    * . Port's priority will increase as the higher significant 5-bits of the
+    * counter starts to decrease. When the aging counter becomes 0, the corres
+    * ponding port channel will have the highest priority level (timeout condi
+    * tion - Priority0). For multi-port configurations, the aging counters can
+    * not be used to set port priorities when external dynamic priority inputs
+    *  (arqos) are enabled (timeout is still applicable). For single port conf
+    * igurations, the aging counters are only used when they timeout (become 0
+    * ) to force read-write direction switching. In this case, external dynami
+    * c priority input, arqos (for reads only) can still be used to set the DD
+    * RC read priority (2 priority levels: low priority read - LPR, high prior
+    * ity read - HPR) on a command by command basis. Note: The two LSBs of thi
+    * s register field are tied internally to 2'b00.
+*/
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                   0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* If set to 1, enables the Page Match feature. If enabled, once a requesti
+    * ng port is granted, the port is continued to be granted if the following
+    *  immediate commands are to the same memory page (same bank and same row)
+    * . See also related PCCFG.pagematch_limit register.
+*/
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL               0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                14
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                 0x00004000U
+
+/*
+* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena
+    * bled and awurgent is asserted by the master, that port becomes the highe
+    * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl
+    * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as
+    * serted anytime and as long as required which is independent of address h
+    * andshaking (it is not associated with any particular command).
+*/
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                  0x00004000
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                   13
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                    0x00002000U
+
+/*
+* If set to 1, enables aging function for the write channel of the port.
+*/
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                   0x00004000
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                    12
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                     0x00001000U
+
+/*
+* Determines the initial load value of write aging counters. These counter
+    * s will be parallel loaded after reset, or after each grant to the corres
+    * ponding port. The aging counters down-count every clock cycle where the
+    * port is requesting but not granted. The higher significant 5-bits of the
+    *  write aging counter sets the initial priority of the write channel of a
+    *  given port. Port's priority will increase as the higher significant 5-b
+    * its of the counter starts to decrease. When the aging counter becomes 0,
+    *  the corresponding port channel will have the highest priority level. Fo
+    * r multi-port configurations, the aging counters cannot be used to set po
+    * rt priorities when external dynamic priority inputs (awqos) are enabled
+    * (timeout is still applicable). For single port configurations, the aging
+    *  counters are only used when they timeout (become 0) to force read-write
+    *  direction switching. Note: The two LSBs of this register field are tied
+    *  internally to 2'b00.
+*/
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                   0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                    0
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                     0x000003FFU
+
+/*
+* Enables port n.
+*/
+#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_5_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_5_PORT_EN_MASK 
+#define DDRC_PCTRL_5_PORT_EN_DEFVAL                            
+#define DDRC_PCTRL_5_PORT_EN_SHIFT                             0
+#define DDRC_PCTRL_5_PORT_EN_MASK                              0x00000001U
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1
+    *  maps to the blue address queue. In this case, valid values are 0: LPR a
+    * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra
+    * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                 20
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                  0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0
+    *  maps to the blue address queue. In this case, valid values are: 0: LPR
+    * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
+    * traffic.
+*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                 16
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                  0x00030000U
+
+/*
+* Separation level1 indicating the end of region0 mapping; start of region
+    * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14
+    *  (for single RAQ) which corresponds to arqos. Note that for PA, arqos va
+    * lues are used directly as port priorities, where the higher the value co
+    * rresponds to higher port priority. All of the map_level* registers must
+    * be set to distinct values.
+*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                 0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                  0
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for transactions mapped to the red address q
+    * ueue.
+*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                16
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                 0x07FF0000U
+
+/*
+* Specifies the timeout value for transactions mapped to the blue address
+    * queue.
+*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL               0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                0
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                 0x000007FFU
+
+/*
+* This bitfield indicates the traffic class of region 1. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW
+    *  traffic.
+*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                20
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                 0x00300000U
+
+/*
+* This bitfield indicates the traffic class of region 0. Valid values are:
+    *  0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr
+    * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW
+    * traffic.
+*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL               0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                16
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                 0x00030000U
+
+/*
+* Separation level indicating the end of region0 mapping; start of region0
+    *  is 0. Possible values for level1 are 0 to 14 which corresponds to awqos
+    * . Note that for PA, awqos values are used directly as port priorities, w
+    * here the higher the value corresponds to higher port priority.
+*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                 0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                  0
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                   0x0000000FU
+
+/*
+* Specifies the timeout value for write transactions.
+*/
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL               
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                0
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                 0x000007FFU
+
+/*
+* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
+    * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
+    * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+*/
+#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE0_BASE_ADDR_MASK 
+#define DDRC_SARBASE0_BASE_ADDR_DEFVAL                         
+#define DDRC_SARBASE0_BASE_ADDR_SHIFT                          0
+#define DDRC_SARBASE0_BASE_ADDR_MASK                           0x000001FFU
+
+/*
+* Number of blocks for address region n. This register determines the tota
+    * l size of the region in multiples of minimum block size as specified by
+    * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
+    * as number of blocks = nblocks + 1. For example, if register is programme
+    * d to 0, region will have 1 block.
+*/
+#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE0_NBLOCKS_MASK 
+#define DDRC_SARSIZE0_NBLOCKS_DEFVAL                           
+#define DDRC_SARSIZE0_NBLOCKS_SHIFT                            0
+#define DDRC_SARSIZE0_NBLOCKS_MASK                             0x000000FFU
+
+/*
+* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x
+    * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl
+    * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+*/
+#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE1_BASE_ADDR_MASK 
+#define DDRC_SARBASE1_BASE_ADDR_DEFVAL                         
+#define DDRC_SARBASE1_BASE_ADDR_SHIFT                          0
+#define DDRC_SARBASE1_BASE_ADDR_MASK                           0x000001FFU
+
+/*
+* Number of blocks for address region n. This register determines the tota
+    * l size of the region in multiples of minimum block size as specified by
+    * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded
+    * as number of blocks = nblocks + 1. For example, if register is programme
+    * d to 0, region will have 1 block.
+*/
+#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE1_NBLOCKS_MASK 
+#define DDRC_SARSIZE1_NBLOCKS_DEFVAL                           
+#define DDRC_SARSIZE1_NBLOCKS_SHIFT                            0
+#define DDRC_SARSIZE1_NBLOCKS_MASK                             0x000000FFU
+
+/*
+* Specifies the number of DFI clock cycles after an assertion or de-assert
+    * ion of the DFI control signals that the control signals at the PHY-DRAM
+    * interface reflect the assertion or de-assertion. If the DFI clock and th
+    * e memory clock are not phase-aligned, this timing parameter should be ro
+    * unded up to the next integer value. Note that if using RDIMM, it is nece
+    * ssary to increment this parameter by RDIMM's extra cycle of latency in t
+    * erms of DFI clock.
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL            0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT             24
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK              0x1F000000U
+
+/*
+* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u
+    * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en
+    * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles
+    *  - 1 in terms of SDR clock cycles Refer to PHY specification for correct
+    *  value.
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL          0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT           23
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK            0x00800000U
+
+/*
+* Time from the assertion of a read command on the DFI interface to the as
+    * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr
+    * ect value. This corresponds to the DFI parameter trddata_en. Note that,
+    * depending on the PHY, if using RDIMM, it may be necessary to use the val
+    * ue (CL + 1) in the calculation of trddata_en. This is to compensate for
+    * the extra cycle of latency through the RDIMM. Unit: Clocks
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL             0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT              16
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK               0x003F0000U
+
+/*
+* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us
+    * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is
+    *  in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df
+    * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR
+    *  clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio
+    * n for correct value.
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL          0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT           15
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK            0x00008000U
+
+/*
+* Specifies the number of clock cycles between when dfi_wrdata_en is asser
+    * ted to when the associated write data is driven on the dfi_wrdata signal
+    * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY
+    *  specification for correct value. Note, max supported value is 8. Unit:
+    * Clocks
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL             0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT              8
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK               0x00003F00U
+
+/*
+* Write latency Number of clocks from the write command to write data enab
+    * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr
+    * lat. Refer to PHY specification for correct value.Note that, depending o
+    * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1)
+    *  in the calculation of tphy_wrlat. This is to compensate for the extra c
+    * ycle of latency through the RDIMM.
+*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL              0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT               0
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                0x0000003FU
+
+/*
+* DDR block level reset inside of the DDR Sub System
+*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                    0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                     3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                      0x00000008U
+
+/*
+* APM block level reset inside of the DDR Sub System
+*/
+#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL                    0x0000000F
+#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT                     2
+#define CRF_APB_RST_DDR_SS_APM_RESET_MASK                      0x00000004U
+
+/*
+* Address Copy
+*/
+#undef DDR_PHY_PGCR0_ADCP_DEFVAL 
+#undef DDR_PHY_PGCR0_ADCP_SHIFT 
+#undef DDR_PHY_PGCR0_ADCP_MASK 
+#define DDR_PHY_PGCR0_ADCP_DEFVAL                              0x07001E00
+#define DDR_PHY_PGCR0_ADCP_SHIFT                               31
+#define DDR_PHY_PGCR0_ADCP_MASK                                0x80000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 
+#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                    0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                     27
+#define DDR_PHY_PGCR0_RESERVED_30_27_MASK                      0x78000000U
+
+/*
+* PHY FIFO Reset
+*/
+#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 
+#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 
+#undef DDR_PHY_PGCR0_PHYFRST_MASK 
+#define DDR_PHY_PGCR0_PHYFRST_DEFVAL                           0x07001E00
+#define DDR_PHY_PGCR0_PHYFRST_SHIFT                            26
+#define DDR_PHY_PGCR0_PHYFRST_MASK                             0x04000000U
+
+/*
+* Oscillator Mode Address/Command Delay Line Select
+*/
+#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 
+#undef DDR_PHY_PGCR0_OSCACDL_MASK 
+#define DDR_PHY_PGCR0_OSCACDL_DEFVAL                           0x07001E00
+#define DDR_PHY_PGCR0_OSCACDL_SHIFT                            24
+#define DDR_PHY_PGCR0_OSCACDL_MASK                             0x03000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 
+#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                    0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                     19
+#define DDR_PHY_PGCR0_RESERVED_23_19_MASK                      0x00F80000U
+
+/*
+* Digital Test Output Select
+*/
+#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 
+#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 
+#undef DDR_PHY_PGCR0_DTOSEL_MASK 
+#define DDR_PHY_PGCR0_DTOSEL_DEFVAL                            0x07001E00
+#define DDR_PHY_PGCR0_DTOSEL_SHIFT                             14
+#define DDR_PHY_PGCR0_DTOSEL_MASK                              0x0007C000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_13_MASK 
+#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                       0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_13_SHIFT                        13
+#define DDR_PHY_PGCR0_RESERVED_13_MASK                         0x00002000U
+
+/*
+* Oscillator Mode Division
+*/
+#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 
+#undef DDR_PHY_PGCR0_OSCDIV_MASK 
+#define DDR_PHY_PGCR0_OSCDIV_DEFVAL                            0x07001E00
+#define DDR_PHY_PGCR0_OSCDIV_SHIFT                             9
+#define DDR_PHY_PGCR0_OSCDIV_MASK                              0x00001E00U
+
+/*
+* Oscillator Enable
+*/
+#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCEN_SHIFT 
+#undef DDR_PHY_PGCR0_OSCEN_MASK 
+#define DDR_PHY_PGCR0_OSCEN_DEFVAL                             0x07001E00
+#define DDR_PHY_PGCR0_OSCEN_SHIFT                              8
+#define DDR_PHY_PGCR0_OSCEN_MASK                               0x00000100U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 
+#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                      0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                       0
+#define DDR_PHY_PGCR0_RESERVED_7_0_MASK                        0x000000FFU
+
+/*
+* Clear Training Status Registers
+*/
+#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 
+#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 
+#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                          0x00F12480
+#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                           31
+#define DDR_PHY_PGCR2_CLRTSTAT_MASK                            0x80000000U
+
+/*
+* Clear Impedance Calibration
+*/
+#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 
+#undef DDR_PHY_PGCR2_CLRZCAL_MASK 
+#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                           0x00F12480
+#define DDR_PHY_PGCR2_CLRZCAL_SHIFT                            30
+#define DDR_PHY_PGCR2_CLRZCAL_MASK                             0x40000000U
+
+/*
+* Clear Parity Error
+*/
+#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 
+#undef DDR_PHY_PGCR2_CLRPERR_MASK 
+#define DDR_PHY_PGCR2_CLRPERR_DEFVAL                           0x00F12480
+#define DDR_PHY_PGCR2_CLRPERR_SHIFT                            29
+#define DDR_PHY_PGCR2_CLRPERR_MASK                             0x20000000U
+
+/*
+* Initialization Complete Pin Configuration
+*/
+#undef DDR_PHY_PGCR2_ICPC_DEFVAL 
+#undef DDR_PHY_PGCR2_ICPC_SHIFT 
+#undef DDR_PHY_PGCR2_ICPC_MASK 
+#define DDR_PHY_PGCR2_ICPC_DEFVAL                              0x00F12480
+#define DDR_PHY_PGCR2_ICPC_SHIFT                               28
+#define DDR_PHY_PGCR2_ICPC_MASK                                0x10000000U
+
+/*
+* Data Training PUB Mode Exit Timer
+*/
+#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 
+#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 
+#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 
+#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                          0x00F12480
+#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                           20
+#define DDR_PHY_PGCR2_DTPMXTMR_MASK                            0x0FF00000U
+
+/*
+* Initialization Bypass
+*/
+#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 
+#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                        0x00F12480
+#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                         19
+#define DDR_PHY_PGCR2_INITFSMBYP_MASK                          0x00080000U
+
+/*
+* PLL FSM Bypass
+*/
+#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 
+#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                         0x00F12480
+#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                          18
+#define DDR_PHY_PGCR2_PLLFSMBYP_MASK                           0x00040000U
+
+/*
+* Refresh Period
+*/
+#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 
+#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 
+#undef DDR_PHY_PGCR2_TREFPRD_MASK 
+#define DDR_PHY_PGCR2_TREFPRD_DEFVAL                           0x00F12480
+#define DDR_PHY_PGCR2_TREFPRD_SHIFT                            0
+#define DDR_PHY_PGCR2_TREFPRD_MASK                             0x0003FFFFU
+
+/*
+* CKN Enable
+*/
+#undef DDR_PHY_PGCR3_CKNEN_DEFVAL 
+#undef DDR_PHY_PGCR3_CKNEN_SHIFT 
+#undef DDR_PHY_PGCR3_CKNEN_MASK 
+#define DDR_PHY_PGCR3_CKNEN_DEFVAL                             0x55AA0080
+#define DDR_PHY_PGCR3_CKNEN_SHIFT                              24
+#define DDR_PHY_PGCR3_CKNEN_MASK                               0xFF000000U
+
+/*
+* CK Enable
+*/
+#undef DDR_PHY_PGCR3_CKEN_DEFVAL 
+#undef DDR_PHY_PGCR3_CKEN_SHIFT 
+#undef DDR_PHY_PGCR3_CKEN_MASK 
+#define DDR_PHY_PGCR3_CKEN_DEFVAL                              0x55AA0080
+#define DDR_PHY_PGCR3_CKEN_SHIFT                               16
+#define DDR_PHY_PGCR3_CKEN_MASK                                0x00FF0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL 
+#undef DDR_PHY_PGCR3_RESERVED_15_SHIFT 
+#undef DDR_PHY_PGCR3_RESERVED_15_MASK 
+#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL                       0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_15_SHIFT                        15
+#define DDR_PHY_PGCR3_RESERVED_15_MASK                         0x00008000U
+
+/*
+* Enable Clock Gating for AC [0] ctl_rd_clk
+*/
+#undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 
+#undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 
+#undef DDR_PHY_PGCR3_GATEACRDCLK_MASK 
+#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL                       0x55AA0080
+#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT                        13
+#define DDR_PHY_PGCR3_GATEACRDCLK_MASK                         0x00006000U
+
+/*
+* Enable Clock Gating for AC [0] ddr_clk
+*/
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 
+#undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK 
+#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL                      0x55AA0080
+#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT                       11
+#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK                        0x00001800U
+
+/*
+* Enable Clock Gating for AC [0] ctl_clk
+*/
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 
+#undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK 
+#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL                      0x55AA0080
+#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT                       9
+#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK                        0x00000600U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL 
+#undef DDR_PHY_PGCR3_RESERVED_8_SHIFT 
+#undef DDR_PHY_PGCR3_RESERVED_8_MASK 
+#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL                        0x55AA0080
+#define DDR_PHY_PGCR3_RESERVED_8_SHIFT                         8
+#define DDR_PHY_PGCR3_RESERVED_8_MASK                          0x00000100U
+
+/*
+* Controls DDL Bypass Modes
+*/
+#undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 
+#undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 
+#undef DDR_PHY_PGCR3_DDLBYPMODE_MASK 
+#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL                        0x55AA0080
+#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT                         6
+#define DDR_PHY_PGCR3_DDLBYPMODE_MASK                          0x000000C0U
+
+/*
+* IO Loop-Back Select
+*/
+#undef DDR_PHY_PGCR3_IOLB_DEFVAL 
+#undef DDR_PHY_PGCR3_IOLB_SHIFT 
+#undef DDR_PHY_PGCR3_IOLB_MASK 
+#define DDR_PHY_PGCR3_IOLB_DEFVAL                              0x55AA0080
+#define DDR_PHY_PGCR3_IOLB_SHIFT                               5
+#define DDR_PHY_PGCR3_IOLB_MASK                                0x00000020U
+
+/*
+* AC Receive FIFO Read Mode
+*/
+#undef DDR_PHY_PGCR3_RDMODE_DEFVAL 
+#undef DDR_PHY_PGCR3_RDMODE_SHIFT 
+#undef DDR_PHY_PGCR3_RDMODE_MASK 
+#define DDR_PHY_PGCR3_RDMODE_DEFVAL                            0x55AA0080
+#define DDR_PHY_PGCR3_RDMODE_SHIFT                             3
+#define DDR_PHY_PGCR3_RDMODE_MASK                              0x00000018U
+
+/*
+* Read FIFO Reset Disable
+*/
+#undef DDR_PHY_PGCR3_DISRST_DEFVAL 
+#undef DDR_PHY_PGCR3_DISRST_SHIFT 
+#undef DDR_PHY_PGCR3_DISRST_MASK 
+#define DDR_PHY_PGCR3_DISRST_DEFVAL                            0x55AA0080
+#define DDR_PHY_PGCR3_DISRST_SHIFT                             2
+#define DDR_PHY_PGCR3_DISRST_MASK                              0x00000004U
+
+/*
+* Clock Level when Clock Gating
+*/
+#undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 
+#undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT 
+#undef DDR_PHY_PGCR3_CLKLEVEL_MASK 
+#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL                          0x55AA0080
+#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT                           0
+#define DDR_PHY_PGCR3_CLKLEVEL_MASK                            0x00000003U
+
+/*
+* Frequency B Ratio Term
+*/
+#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQBT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQBT_MASK 
+#define DDR_PHY_PGCR5_FRQBT_DEFVAL                             0x01010000
+#define DDR_PHY_PGCR5_FRQBT_SHIFT                              24
+#define DDR_PHY_PGCR5_FRQBT_MASK                               0xFF000000U
+
+/*
+* Frequency A Ratio Term
+*/
+#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQAT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQAT_MASK 
+#define DDR_PHY_PGCR5_FRQAT_DEFVAL                             0x01010000
+#define DDR_PHY_PGCR5_FRQAT_SHIFT                              16
+#define DDR_PHY_PGCR5_FRQAT_MASK                               0x00FF0000U
+
+/*
+* DFI Disconnect Time Period
+*/
+#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 
+#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                       0x01010000
+#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                        8
+#define DDR_PHY_PGCR5_DISCNPERIOD_MASK                         0x0000FF00U
+
+/*
+* Receiver bias core side control
+*/
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 
+#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                       0x01010000
+#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                        4
+#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                         0x000000F0U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 
+#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 
+#undef DDR_PHY_PGCR5_RESERVED_3_MASK 
+#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                        0x01010000
+#define DDR_PHY_PGCR5_RESERVED_3_SHIFT                         3
+#define DDR_PHY_PGCR5_RESERVED_3_MASK                          0x00000008U
+
+/*
+* Internal VREF generator REFSEL ragne select
+*/
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 
+#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                    0x01010000
+#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                     2
+#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                      0x00000004U
+
+/*
+* DDL Page Read Write select
+*/
+#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGACT_MASK 
+#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                          0x01010000
+#define DDR_PHY_PGCR5_DDLPGACT_SHIFT                           1
+#define DDR_PHY_PGCR5_DDLPGACT_MASK                            0x00000002U
+
+/*
+* DDL Page Read Write select
+*/
+#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGRW_MASK 
+#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                           0x01010000
+#define DDR_PHY_PGCR5_DDLPGRW_SHIFT                            0
+#define DDR_PHY_PGCR5_DDLPGRW_MASK                             0x00000001U
+
+/*
+* PLL Power-Down Time
+*/
+#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLPD_SHIFT 
+#undef DDR_PHY_PTR0_TPLLPD_MASK 
+#define DDR_PHY_PTR0_TPLLPD_DEFVAL                             0x42C21590
+#define DDR_PHY_PTR0_TPLLPD_SHIFT                              21
+#define DDR_PHY_PTR0_TPLLPD_MASK                               0xFFE00000U
+
+/*
+* PLL Gear Shift Time
+*/
+#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLGS_SHIFT 
+#undef DDR_PHY_PTR0_TPLLGS_MASK 
+#define DDR_PHY_PTR0_TPLLGS_DEFVAL                             0x42C21590
+#define DDR_PHY_PTR0_TPLLGS_SHIFT                              6
+#define DDR_PHY_PTR0_TPLLGS_MASK                               0x001FFFC0U
+
+/*
+* PHY Reset Time
+*/
+#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 
+#undef DDR_PHY_PTR0_TPHYRST_SHIFT 
+#undef DDR_PHY_PTR0_TPHYRST_MASK 
+#define DDR_PHY_PTR0_TPHYRST_DEFVAL                            0x42C21590
+#define DDR_PHY_PTR0_TPHYRST_SHIFT                             0
+#define DDR_PHY_PTR0_TPHYRST_MASK                              0x0000003FU
+
+/*
+* PLL Lock Time
+*/
+#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 
+#undef DDR_PHY_PTR1_TPLLLOCK_MASK 
+#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                           0xD05612C0
+#define DDR_PHY_PTR1_TPLLLOCK_SHIFT                            16
+#define DDR_PHY_PTR1_TPLLLOCK_MASK                             0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 
+#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                     0xD05612C0
+#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                      13
+#define DDR_PHY_PTR1_RESERVED_15_13_MASK                       0x0000E000U
+
+/*
+* PLL Reset Time
+*/
+#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLRST_SHIFT 
+#undef DDR_PHY_PTR1_TPLLRST_MASK 
+#define DDR_PHY_PTR1_TPLLRST_DEFVAL                            0xD05612C0
+#define DDR_PHY_PTR1_TPLLRST_SHIFT                             0
+#define DDR_PHY_PTR1_TPLLRST_MASK                              0x00001FFFU
+
+/*
+* PLL Bypass
+*/
+#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL 
+#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT 
+#undef DDR_PHY_PLLCR0_PLLBYP_MASK 
+#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_PLLBYP_SHIFT                            31
+#define DDR_PHY_PLLCR0_PLLBYP_MASK                             0x80000000U
+
+/*
+* PLL Reset
+*/
+#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL 
+#undef DDR_PHY_PLLCR0_PLLRST_SHIFT 
+#undef DDR_PHY_PLLCR0_PLLRST_MASK 
+#define DDR_PHY_PLLCR0_PLLRST_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_PLLRST_SHIFT                            30
+#define DDR_PHY_PLLCR0_PLLRST_MASK                             0x40000000U
+
+/*
+* PLL Power Down
+*/
+#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL 
+#undef DDR_PHY_PLLCR0_PLLPD_SHIFT 
+#undef DDR_PHY_PLLCR0_PLLPD_MASK 
+#define DDR_PHY_PLLCR0_PLLPD_DEFVAL                            0x001C0000
+#define DDR_PHY_PLLCR0_PLLPD_SHIFT                             29
+#define DDR_PHY_PLLCR0_PLLPD_MASK                              0x20000000U
+
+/*
+* Reference Stop Mode
+*/
+#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL 
+#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT 
+#undef DDR_PHY_PLLCR0_RSTOPM_MASK 
+#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_RSTOPM_SHIFT                            28
+#define DDR_PHY_PLLCR0_RSTOPM_MASK                             0x10000000U
+
+/*
+* PLL Frequency Select
+*/
+#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL 
+#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT 
+#undef DDR_PHY_PLLCR0_FRQSEL_MASK 
+#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_FRQSEL_SHIFT                            24
+#define DDR_PHY_PLLCR0_FRQSEL_MASK                             0x0F000000U
+
+/*
+* Relock Mode
+*/
+#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL 
+#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT 
+#undef DDR_PHY_PLLCR0_RLOCKM_MASK 
+#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_RLOCKM_SHIFT                            23
+#define DDR_PHY_PLLCR0_RLOCKM_MASK                             0x00800000U
+
+/*
+* Charge Pump Proportional Current Control
+*/
+#undef DDR_PHY_PLLCR0_CPPC_DEFVAL 
+#undef DDR_PHY_PLLCR0_CPPC_SHIFT 
+#undef DDR_PHY_PLLCR0_CPPC_MASK 
+#define DDR_PHY_PLLCR0_CPPC_DEFVAL                             0x001C0000
+#define DDR_PHY_PLLCR0_CPPC_SHIFT                              17
+#define DDR_PHY_PLLCR0_CPPC_MASK                               0x007E0000U
+
+/*
+* Charge Pump Integrating Current Control
+*/
+#undef DDR_PHY_PLLCR0_CPIC_DEFVAL 
+#undef DDR_PHY_PLLCR0_CPIC_SHIFT 
+#undef DDR_PHY_PLLCR0_CPIC_MASK 
+#define DDR_PHY_PLLCR0_CPIC_DEFVAL                             0x001C0000
+#define DDR_PHY_PLLCR0_CPIC_SHIFT                              13
+#define DDR_PHY_PLLCR0_CPIC_MASK                               0x0001E000U
+
+/*
+* Gear Shift
+*/
+#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL 
+#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT 
+#undef DDR_PHY_PLLCR0_GSHIFT_MASK 
+#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL                           0x001C0000
+#define DDR_PHY_PLLCR0_GSHIFT_SHIFT                            12
+#define DDR_PHY_PLLCR0_GSHIFT_MASK                             0x00001000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 
+#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK 
+#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL                    0x001C0000
+#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT                     9
+#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK                      0x00000E00U
+
+/*
+* Analog Test Enable
+*/
+#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL 
+#undef DDR_PHY_PLLCR0_ATOEN_SHIFT 
+#undef DDR_PHY_PLLCR0_ATOEN_MASK 
+#define DDR_PHY_PLLCR0_ATOEN_DEFVAL                            0x001C0000
+#define DDR_PHY_PLLCR0_ATOEN_SHIFT                             8
+#define DDR_PHY_PLLCR0_ATOEN_MASK                              0x00000100U
+
+/*
+* Analog Test Control
+*/
+#undef DDR_PHY_PLLCR0_ATC_DEFVAL 
+#undef DDR_PHY_PLLCR0_ATC_SHIFT 
+#undef DDR_PHY_PLLCR0_ATC_MASK 
+#define DDR_PHY_PLLCR0_ATC_DEFVAL                              0x001C0000
+#define DDR_PHY_PLLCR0_ATC_SHIFT                               4
+#define DDR_PHY_PLLCR0_ATC_MASK                                0x000000F0U
+
+/*
+* Digital Test Control
+*/
+#undef DDR_PHY_PLLCR0_DTC_DEFVAL 
+#undef DDR_PHY_PLLCR0_DTC_SHIFT 
+#undef DDR_PHY_PLLCR0_DTC_MASK 
+#define DDR_PHY_PLLCR0_DTC_DEFVAL                              0x001C0000
+#define DDR_PHY_PLLCR0_DTC_SHIFT                               0
+#define DDR_PHY_PLLCR0_DTC_MASK                                0x0000000FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 
+#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                    0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                     28
+#define DDR_PHY_DSGCR_RESERVED_31_28_MASK                      0xF0000000U
+
+/*
+* When RDBI enabled, this bit is used to select RDBI CL calculation, if it
+    *  is 1b1, calculation will use RDBICL, otherwise use default calculation.
+*/
+#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 
+#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                         0x02A04101
+#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                          27
+#define DDR_PHY_DSGCR_RDBICLSEL_MASK                           0x08000000U
+
+/*
+* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v
+    * alue.
+*/
+#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICL_MASK 
+#define DDR_PHY_DSGCR_RDBICL_DEFVAL                            0x02A04101
+#define DDR_PHY_DSGCR_RDBICL_SHIFT                             24
+#define DDR_PHY_DSGCR_RDBICL_MASK                              0x07000000U
+
+/*
+* PHY Impedance Update Enable
+*/
+#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_PHYZUEN_MASK 
+#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                           0x02A04101
+#define DDR_PHY_DSGCR_PHYZUEN_SHIFT                            23
+#define DDR_PHY_DSGCR_PHYZUEN_MASK                             0x00800000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_22_MASK 
+#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                       0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_22_SHIFT                        22
+#define DDR_PHY_DSGCR_RESERVED_22_MASK                         0x00400000U
+
+/*
+* SDRAM Reset Output Enable
+*/
+#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 
+#undef DDR_PHY_DSGCR_RSTOE_SHIFT 
+#undef DDR_PHY_DSGCR_RSTOE_MASK 
+#define DDR_PHY_DSGCR_RSTOE_DEFVAL                             0x02A04101
+#define DDR_PHY_DSGCR_RSTOE_SHIFT                              21
+#define DDR_PHY_DSGCR_RSTOE_MASK                               0x00200000U
+
+/*
+* Single Data Rate Mode
+*/
+#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 
+#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 
+#undef DDR_PHY_DSGCR_SDRMODE_MASK 
+#define DDR_PHY_DSGCR_SDRMODE_DEFVAL                           0x02A04101
+#define DDR_PHY_DSGCR_SDRMODE_SHIFT                            19
+#define DDR_PHY_DSGCR_SDRMODE_MASK                             0x00180000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_18_MASK 
+#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                       0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_18_SHIFT                        18
+#define DDR_PHY_DSGCR_RESERVED_18_MASK                         0x00040000U
+
+/*
+* ATO Analog Test Enable
+*/
+#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 
+#undef DDR_PHY_DSGCR_ATOAE_SHIFT 
+#undef DDR_PHY_DSGCR_ATOAE_MASK 
+#define DDR_PHY_DSGCR_ATOAE_DEFVAL                             0x02A04101
+#define DDR_PHY_DSGCR_ATOAE_SHIFT                              17
+#define DDR_PHY_DSGCR_ATOAE_MASK                               0x00020000U
+
+/*
+* DTO Output Enable
+*/
+#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOOE_SHIFT 
+#undef DDR_PHY_DSGCR_DTOOE_MASK 
+#define DDR_PHY_DSGCR_DTOOE_DEFVAL                             0x02A04101
+#define DDR_PHY_DSGCR_DTOOE_SHIFT                              16
+#define DDR_PHY_DSGCR_DTOOE_MASK                               0x00010000U
+
+/*
+* DTO I/O Mode
+*/
+#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 
+#undef DDR_PHY_DSGCR_DTOIOM_MASK 
+#define DDR_PHY_DSGCR_DTOIOM_DEFVAL                            0x02A04101
+#define DDR_PHY_DSGCR_DTOIOM_SHIFT                             15
+#define DDR_PHY_DSGCR_DTOIOM_MASK                              0x00008000U
+
+/*
+* DTO Power Down Receiver
+*/
+#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 
+#undef DDR_PHY_DSGCR_DTOPDR_MASK 
+#define DDR_PHY_DSGCR_DTOPDR_DEFVAL                            0x02A04101
+#define DDR_PHY_DSGCR_DTOPDR_SHIFT                             14
+#define DDR_PHY_DSGCR_DTOPDR_MASK                              0x00004000U
+
+/*
+* Reserved. Return zeroes on reads
+*/
+#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_13_MASK 
+#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                       0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_13_SHIFT                        13
+#define DDR_PHY_DSGCR_RESERVED_13_MASK                         0x00002000U
+
+/*
+* DTO On-Die Termination
+*/
+#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOODT_SHIFT 
+#undef DDR_PHY_DSGCR_DTOODT_MASK 
+#define DDR_PHY_DSGCR_DTOODT_DEFVAL                            0x02A04101
+#define DDR_PHY_DSGCR_DTOODT_SHIFT                             12
+#define DDR_PHY_DSGCR_DTOODT_MASK                              0x00001000U
+
+/*
+* PHY Update Acknowledge Delay
+*/
+#undef DDR_PHY_DSGCR_PUAD_DEFVAL 
+#undef DDR_PHY_DSGCR_PUAD_SHIFT 
+#undef DDR_PHY_DSGCR_PUAD_MASK 
+#define DDR_PHY_DSGCR_PUAD_DEFVAL                              0x02A04101
+#define DDR_PHY_DSGCR_PUAD_SHIFT                               6
+#define DDR_PHY_DSGCR_PUAD_MASK                                0x00000FC0U
+
+/*
+* Controller Update Acknowledge Enable
+*/
+#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CUAEN_SHIFT 
+#undef DDR_PHY_DSGCR_CUAEN_MASK 
+#define DDR_PHY_DSGCR_CUAEN_DEFVAL                             0x02A04101
+#define DDR_PHY_DSGCR_CUAEN_SHIFT                              5
+#define DDR_PHY_DSGCR_CUAEN_MASK                               0x00000020U
+
+/*
+* Reserved. Return zeroes on reads
+*/
+#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 
+#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                      0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                       3
+#define DDR_PHY_DSGCR_RESERVED_4_3_MASK                        0x00000018U
+
+/*
+* Controller Impedance Update Enable
+*/
+#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_CTLZUEN_MASK 
+#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                           0x02A04101
+#define DDR_PHY_DSGCR_CTLZUEN_SHIFT                            2
+#define DDR_PHY_DSGCR_CTLZUEN_MASK                             0x00000004U
+
+/*
+* Reserved. Return zeroes on reads
+*/
+#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_1_MASK 
+#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                        0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_1_SHIFT                         1
+#define DDR_PHY_DSGCR_RESERVED_1_MASK                          0x00000002U
+
+/*
+* PHY Update Request Enable
+*/
+#undef DDR_PHY_DSGCR_PUREN_DEFVAL 
+#undef DDR_PHY_DSGCR_PUREN_SHIFT 
+#undef DDR_PHY_DSGCR_PUREN_MASK 
+#define DDR_PHY_DSGCR_PUREN_DEFVAL                             0x02A04101
+#define DDR_PHY_DSGCR_PUREN_SHIFT                              0
+#define DDR_PHY_DSGCR_PUREN_MASK                               0x00000001U
+
+/*
+* General Purpose Register 0
+*/
+#undef DDR_PHY_GPR0_GPR0_DEFVAL 
+#undef DDR_PHY_GPR0_GPR0_SHIFT 
+#undef DDR_PHY_GPR0_GPR0_MASK 
+#define DDR_PHY_GPR0_GPR0_DEFVAL                               
+#define DDR_PHY_GPR0_GPR0_SHIFT                                0
+#define DDR_PHY_GPR0_GPR0_MASK                                 0xFFFFFFFFU
+
+/*
+* General Purpose Register 1
+*/
+#undef DDR_PHY_GPR1_GPR1_DEFVAL 
+#undef DDR_PHY_GPR1_GPR1_SHIFT 
+#undef DDR_PHY_GPR1_GPR1_MASK 
+#define DDR_PHY_GPR1_GPR1_DEFVAL                               
+#define DDR_PHY_GPR1_GPR1_SHIFT                                0
+#define DDR_PHY_GPR1_GPR1_MASK                                 0xFFFFFFFFU
+
+/*
+* DDR4 Gear Down Timing.
+*/
+#undef DDR_PHY_DCR_GEARDN_DEFVAL 
+#undef DDR_PHY_DCR_GEARDN_SHIFT 
+#undef DDR_PHY_DCR_GEARDN_MASK 
+#define DDR_PHY_DCR_GEARDN_DEFVAL                              0x0000040D
+#define DDR_PHY_DCR_GEARDN_SHIFT                               31
+#define DDR_PHY_DCR_GEARDN_MASK                                0x80000000U
+
+/*
+* Un-used Bank Group
+*/
+#undef DDR_PHY_DCR_UBG_DEFVAL 
+#undef DDR_PHY_DCR_UBG_SHIFT 
+#undef DDR_PHY_DCR_UBG_MASK 
+#define DDR_PHY_DCR_UBG_DEFVAL                                 0x0000040D
+#define DDR_PHY_DCR_UBG_SHIFT                                  30
+#define DDR_PHY_DCR_UBG_MASK                                   0x40000000U
+
+/*
+* Un-buffered DIMM Address Mirroring
+*/
+#undef DDR_PHY_DCR_UDIMM_DEFVAL 
+#undef DDR_PHY_DCR_UDIMM_SHIFT 
+#undef DDR_PHY_DCR_UDIMM_MASK 
+#define DDR_PHY_DCR_UDIMM_DEFVAL                               0x0000040D
+#define DDR_PHY_DCR_UDIMM_SHIFT                                29
+#define DDR_PHY_DCR_UDIMM_MASK                                 0x20000000U
+
+/*
+* DDR 2T Timing
+*/
+#undef DDR_PHY_DCR_DDR2T_DEFVAL 
+#undef DDR_PHY_DCR_DDR2T_SHIFT 
+#undef DDR_PHY_DCR_DDR2T_MASK 
+#define DDR_PHY_DCR_DDR2T_DEFVAL                               0x0000040D
+#define DDR_PHY_DCR_DDR2T_SHIFT                                28
+#define DDR_PHY_DCR_DDR2T_MASK                                 0x10000000U
+
+/*
+* No Simultaneous Rank Access
+*/
+#undef DDR_PHY_DCR_NOSRA_DEFVAL 
+#undef DDR_PHY_DCR_NOSRA_SHIFT 
+#undef DDR_PHY_DCR_NOSRA_MASK 
+#define DDR_PHY_DCR_NOSRA_DEFVAL                               0x0000040D
+#define DDR_PHY_DCR_NOSRA_SHIFT                                27
+#define DDR_PHY_DCR_NOSRA_MASK                                 0x08000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 
+#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 
+#undef DDR_PHY_DCR_RESERVED_26_18_MASK 
+#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                      0x0000040D
+#define DDR_PHY_DCR_RESERVED_26_18_SHIFT                       18
+#define DDR_PHY_DCR_RESERVED_26_18_MASK                        0x07FC0000U
+
+/*
+* Byte Mask
+*/
+#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 
+#undef DDR_PHY_DCR_BYTEMASK_SHIFT 
+#undef DDR_PHY_DCR_BYTEMASK_MASK 
+#define DDR_PHY_DCR_BYTEMASK_DEFVAL                            0x0000040D
+#define DDR_PHY_DCR_BYTEMASK_SHIFT                             10
+#define DDR_PHY_DCR_BYTEMASK_MASK                              0x0003FC00U
+
+/*
+* DDR Type
+*/
+#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 
+#undef DDR_PHY_DCR_DDRTYPE_SHIFT 
+#undef DDR_PHY_DCR_DDRTYPE_MASK 
+#define DDR_PHY_DCR_DDRTYPE_DEFVAL                             0x0000040D
+#define DDR_PHY_DCR_DDRTYPE_SHIFT                              8
+#define DDR_PHY_DCR_DDRTYPE_MASK                               0x00000300U
+
+/*
+* Multi-Purpose Register (MPR) DQ (DDR3 Only)
+*/
+#undef DDR_PHY_DCR_MPRDQ_DEFVAL 
+#undef DDR_PHY_DCR_MPRDQ_SHIFT 
+#undef DDR_PHY_DCR_MPRDQ_MASK 
+#define DDR_PHY_DCR_MPRDQ_DEFVAL                               0x0000040D
+#define DDR_PHY_DCR_MPRDQ_SHIFT                                7
+#define DDR_PHY_DCR_MPRDQ_MASK                                 0x00000080U
+
+/*
+* Primary DQ (DDR3 Only)
+*/
+#undef DDR_PHY_DCR_PDQ_DEFVAL 
+#undef DDR_PHY_DCR_PDQ_SHIFT 
+#undef DDR_PHY_DCR_PDQ_MASK 
+#define DDR_PHY_DCR_PDQ_DEFVAL                                 0x0000040D
+#define DDR_PHY_DCR_PDQ_SHIFT                                  4
+#define DDR_PHY_DCR_PDQ_MASK                                   0x00000070U
+
+/*
+* DDR 8-Bank
+*/
+#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 
+#undef DDR_PHY_DCR_DDR8BNK_SHIFT 
+#undef DDR_PHY_DCR_DDR8BNK_MASK 
+#define DDR_PHY_DCR_DDR8BNK_DEFVAL                             0x0000040D
+#define DDR_PHY_DCR_DDR8BNK_SHIFT                              3
+#define DDR_PHY_DCR_DDR8BNK_MASK                               0x00000008U
+
+/*
+* DDR Mode
+*/
+#undef DDR_PHY_DCR_DDRMD_DEFVAL 
+#undef DDR_PHY_DCR_DDRMD_SHIFT 
+#undef DDR_PHY_DCR_DDRMD_MASK 
+#define DDR_PHY_DCR_DDRMD_DEFVAL                               0x0000040D
+#define DDR_PHY_DCR_DDRMD_SHIFT                                0
+#define DDR_PHY_DCR_DDRMD_MASK                                 0x00000007U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                    0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                     29
+#define DDR_PHY_DTPR0_RESERVED_31_29_MASK                      0xE0000000U
+
+/*
+* Activate to activate command delay (different banks)
+*/
+#undef DDR_PHY_DTPR0_TRRD_DEFVAL 
+#undef DDR_PHY_DTPR0_TRRD_SHIFT 
+#undef DDR_PHY_DTPR0_TRRD_MASK 
+#define DDR_PHY_DTPR0_TRRD_DEFVAL                              0x105A2D08
+#define DDR_PHY_DTPR0_TRRD_SHIFT                               24
+#define DDR_PHY_DTPR0_TRRD_MASK                                0x1F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_23_MASK 
+#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                       0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_23_SHIFT                        23
+#define DDR_PHY_DTPR0_RESERVED_23_MASK                         0x00800000U
+
+/*
+* Activate to precharge command delay
+*/
+#undef DDR_PHY_DTPR0_TRAS_DEFVAL 
+#undef DDR_PHY_DTPR0_TRAS_SHIFT 
+#undef DDR_PHY_DTPR0_TRAS_MASK 
+#define DDR_PHY_DTPR0_TRAS_DEFVAL                              0x105A2D08
+#define DDR_PHY_DTPR0_TRAS_SHIFT                               16
+#define DDR_PHY_DTPR0_TRAS_MASK                                0x007F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_15_MASK 
+#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                       0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_15_SHIFT                        15
+#define DDR_PHY_DTPR0_RESERVED_15_MASK                         0x00008000U
+
+/*
+* Precharge command period
+*/
+#undef DDR_PHY_DTPR0_TRP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRP_SHIFT 
+#undef DDR_PHY_DTPR0_TRP_MASK 
+#define DDR_PHY_DTPR0_TRP_DEFVAL                               0x105A2D08
+#define DDR_PHY_DTPR0_TRP_SHIFT                                8
+#define DDR_PHY_DTPR0_TRP_MASK                                 0x00007F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                      0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                       5
+#define DDR_PHY_DTPR0_RESERVED_7_5_MASK                        0x000000E0U
+
+/*
+* Internal read to precharge command delay
+*/
+#undef DDR_PHY_DTPR0_TRTP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRTP_SHIFT 
+#undef DDR_PHY_DTPR0_TRTP_MASK 
+#define DDR_PHY_DTPR0_TRTP_DEFVAL                              0x105A2D08
+#define DDR_PHY_DTPR0_TRTP_SHIFT                               0
+#define DDR_PHY_DTPR0_TRTP_MASK                                0x0000001FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_31_MASK 
+#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                       0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_31_SHIFT                        31
+#define DDR_PHY_DTPR1_RESERVED_31_MASK                         0x80000000U
+
+/*
+* Minimum delay from when write leveling mode is programmed to the first D
+    * QS/DQS# rising edge.
+*/
+#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TWLMRD_MASK 
+#define DDR_PHY_DTPR1_TWLMRD_DEFVAL                            0x5656041E
+#define DDR_PHY_DTPR1_TWLMRD_SHIFT                             24
+#define DDR_PHY_DTPR1_TWLMRD_MASK                              0x7F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_23_MASK 
+#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                       0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_23_SHIFT                        23
+#define DDR_PHY_DTPR1_RESERVED_23_MASK                         0x00800000U
+
+/*
+* 4-bank activate period
+*/
+#undef DDR_PHY_DTPR1_TFAW_DEFVAL 
+#undef DDR_PHY_DTPR1_TFAW_SHIFT 
+#undef DDR_PHY_DTPR1_TFAW_MASK 
+#define DDR_PHY_DTPR1_TFAW_DEFVAL                              0x5656041E
+#define DDR_PHY_DTPR1_TFAW_SHIFT                               16
+#define DDR_PHY_DTPR1_TFAW_MASK                                0x007F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 
+#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                    0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                     11
+#define DDR_PHY_DTPR1_RESERVED_15_11_MASK                      0x0000F800U
+
+/*
+* Load mode update delay (DDR4 and DDR3 only)
+*/
+#undef DDR_PHY_DTPR1_TMOD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMOD_SHIFT 
+#undef DDR_PHY_DTPR1_TMOD_MASK 
+#define DDR_PHY_DTPR1_TMOD_DEFVAL                              0x5656041E
+#define DDR_PHY_DTPR1_TMOD_SHIFT                               8
+#define DDR_PHY_DTPR1_TMOD_MASK                                0x00000700U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                      0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                       5
+#define DDR_PHY_DTPR1_RESERVED_7_5_MASK                        0x000000E0U
+
+/*
+* Load mode cycle time
+*/
+#undef DDR_PHY_DTPR1_TMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TMRD_MASK 
+#define DDR_PHY_DTPR1_TMRD_DEFVAL                              0x5656041E
+#define DDR_PHY_DTPR1_TMRD_SHIFT                               0
+#define DDR_PHY_DTPR1_TMRD_MASK                                0x0000001FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                    0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                     29
+#define DDR_PHY_DTPR2_RESERVED_31_29_MASK                      0xE0000000U
+
+/*
+* Read to Write command delay. Valid values are
+*/
+#undef DDR_PHY_DTPR2_TRTW_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTW_SHIFT 
+#undef DDR_PHY_DTPR2_TRTW_MASK 
+#define DDR_PHY_DTPR2_TRTW_DEFVAL                              0x000B01D0
+#define DDR_PHY_DTPR2_TRTW_SHIFT                               28
+#define DDR_PHY_DTPR2_TRTW_MASK                                0x10000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 
+#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                    0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                     25
+#define DDR_PHY_DTPR2_RESERVED_27_25_MASK                      0x0E000000U
+
+/*
+* Read to ODT delay (DDR3 only)
+*/
+#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTODT_SHIFT 
+#undef DDR_PHY_DTPR2_TRTODT_MASK 
+#define DDR_PHY_DTPR2_TRTODT_DEFVAL                            0x000B01D0
+#define DDR_PHY_DTPR2_TRTODT_SHIFT                             24
+#define DDR_PHY_DTPR2_TRTODT_MASK                              0x01000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 
+#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                    0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                     20
+#define DDR_PHY_DTPR2_RESERVED_23_20_MASK                      0x00F00000U
+
+/*
+* CKE minimum pulse width
+*/
+#undef DDR_PHY_DTPR2_TCKE_DEFVAL 
+#undef DDR_PHY_DTPR2_TCKE_SHIFT 
+#undef DDR_PHY_DTPR2_TCKE_MASK 
+#define DDR_PHY_DTPR2_TCKE_DEFVAL                              0x000B01D0
+#define DDR_PHY_DTPR2_TCKE_SHIFT                               16
+#define DDR_PHY_DTPR2_TCKE_MASK                                0x000F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 
+#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                    0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                     10
+#define DDR_PHY_DTPR2_RESERVED_15_10_MASK                      0x0000FC00U
+
+/*
+* Self refresh exit delay
+*/
+#undef DDR_PHY_DTPR2_TXS_DEFVAL 
+#undef DDR_PHY_DTPR2_TXS_SHIFT 
+#undef DDR_PHY_DTPR2_TXS_MASK 
+#define DDR_PHY_DTPR2_TXS_DEFVAL                               0x000B01D0
+#define DDR_PHY_DTPR2_TXS_SHIFT                                0
+#define DDR_PHY_DTPR2_TXS_MASK                                 0x000003FFU
+
+/*
+* ODT turn-off delay extension
+*/
+#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 
+#undef DDR_PHY_DTPR3_TOFDX_SHIFT 
+#undef DDR_PHY_DTPR3_TOFDX_MASK 
+#define DDR_PHY_DTPR3_TOFDX_DEFVAL                             0x02000804
+#define DDR_PHY_DTPR3_TOFDX_SHIFT                              29
+#define DDR_PHY_DTPR3_TOFDX_MASK                               0xE0000000U
+
+/*
+* Read to read and write to write command delay
+*/
+#undef DDR_PHY_DTPR3_TCCD_DEFVAL 
+#undef DDR_PHY_DTPR3_TCCD_SHIFT 
+#undef DDR_PHY_DTPR3_TCCD_MASK 
+#define DDR_PHY_DTPR3_TCCD_DEFVAL                              0x02000804
+#define DDR_PHY_DTPR3_TCCD_SHIFT                               26
+#define DDR_PHY_DTPR3_TCCD_MASK                                0x1C000000U
+
+/*
+* DLL locking time
+*/
+#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDLLK_SHIFT 
+#undef DDR_PHY_DTPR3_TDLLK_MASK 
+#define DDR_PHY_DTPR3_TDLLK_DEFVAL                             0x02000804
+#define DDR_PHY_DTPR3_TDLLK_SHIFT                              16
+#define DDR_PHY_DTPR3_TDLLK_MASK                               0x03FF0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 
+#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                    0x02000804
+#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                     12
+#define DDR_PHY_DTPR3_RESERVED_15_12_MASK                      0x0000F000U
+
+/*
+* Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
+*/
+#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 
+#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                         0x02000804
+#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                          8
+#define DDR_PHY_DTPR3_TDQSCKMAX_MASK                           0x00000F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 
+#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                      0x02000804
+#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                       3
+#define DDR_PHY_DTPR3_RESERVED_7_3_MASK                        0x000000F8U
+
+/*
+* DQS output access time from CK/CK# (LPDDR2/3 only)
+*/
+#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCK_MASK 
+#define DDR_PHY_DTPR3_TDQSCK_DEFVAL                            0x02000804
+#define DDR_PHY_DTPR3_TDQSCK_SHIFT                             0
+#define DDR_PHY_DTPR3_TDQSCK_MASK                              0x00000007U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 
+#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                    0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                     30
+#define DDR_PHY_DTPR4_RESERVED_31_30_MASK                      0xC0000000U
+
+/*
+* ODT turn-on/turn-off delays (DDR2 only)
+*/
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 
+#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                       0x01C02B10
+#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                        28
+#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                         0x30000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 
+#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                    0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                     26
+#define DDR_PHY_DTPR4_RESERVED_27_26_MASK                      0x0C000000U
+
+/*
+* Refresh-to-Refresh
+*/
+#undef DDR_PHY_DTPR4_TRFC_DEFVAL 
+#undef DDR_PHY_DTPR4_TRFC_SHIFT 
+#undef DDR_PHY_DTPR4_TRFC_MASK 
+#define DDR_PHY_DTPR4_TRFC_DEFVAL                              0x01C02B10
+#define DDR_PHY_DTPR4_TRFC_SHIFT                               16
+#define DDR_PHY_DTPR4_TRFC_MASK                                0x03FF0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 
+#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                    0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                     14
+#define DDR_PHY_DTPR4_RESERVED_15_14_MASK                      0x0000C000U
+
+/*
+* Write leveling output delay
+*/
+#undef DDR_PHY_DTPR4_TWLO_DEFVAL 
+#undef DDR_PHY_DTPR4_TWLO_SHIFT 
+#undef DDR_PHY_DTPR4_TWLO_MASK 
+#define DDR_PHY_DTPR4_TWLO_DEFVAL                              0x01C02B10
+#define DDR_PHY_DTPR4_TWLO_SHIFT                               8
+#define DDR_PHY_DTPR4_TWLO_MASK                                0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                      0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                       5
+#define DDR_PHY_DTPR4_RESERVED_7_5_MASK                        0x000000E0U
+
+/*
+* Power down exit delay
+*/
+#undef DDR_PHY_DTPR4_TXP_DEFVAL 
+#undef DDR_PHY_DTPR4_TXP_SHIFT 
+#undef DDR_PHY_DTPR4_TXP_MASK 
+#define DDR_PHY_DTPR4_TXP_DEFVAL                               0x01C02B10
+#define DDR_PHY_DTPR4_TXP_SHIFT                                0
+#define DDR_PHY_DTPR4_TXP_MASK                                 0x0000001FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 
+#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                    0x00872716
+#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                     24
+#define DDR_PHY_DTPR5_RESERVED_31_24_MASK                      0xFF000000U
+
+/*
+* Activate to activate command delay (same bank)
+*/
+#undef DDR_PHY_DTPR5_TRC_DEFVAL 
+#undef DDR_PHY_DTPR5_TRC_SHIFT 
+#undef DDR_PHY_DTPR5_TRC_MASK 
+#define DDR_PHY_DTPR5_TRC_DEFVAL                               0x00872716
+#define DDR_PHY_DTPR5_TRC_SHIFT                                16
+#define DDR_PHY_DTPR5_TRC_MASK                                 0x00FF0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_15_MASK 
+#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                       0x00872716
+#define DDR_PHY_DTPR5_RESERVED_15_SHIFT                        15
+#define DDR_PHY_DTPR5_RESERVED_15_MASK                         0x00008000U
+
+/*
+* Activate to read or write delay
+*/
+#undef DDR_PHY_DTPR5_TRCD_DEFVAL 
+#undef DDR_PHY_DTPR5_TRCD_SHIFT 
+#undef DDR_PHY_DTPR5_TRCD_MASK 
+#define DDR_PHY_DTPR5_TRCD_DEFVAL                              0x00872716
+#define DDR_PHY_DTPR5_TRCD_SHIFT                               8
+#define DDR_PHY_DTPR5_TRCD_MASK                                0x00007F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                      0x00872716
+#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                       5
+#define DDR_PHY_DTPR5_RESERVED_7_5_MASK                        0x000000E0U
+
+/*
+* Internal write to read command delay
+*/
+#undef DDR_PHY_DTPR5_TWTR_DEFVAL 
+#undef DDR_PHY_DTPR5_TWTR_SHIFT 
+#undef DDR_PHY_DTPR5_TWTR_MASK 
+#define DDR_PHY_DTPR5_TWTR_DEFVAL                              0x00872716
+#define DDR_PHY_DTPR5_TWTR_SHIFT                               0
+#define DDR_PHY_DTPR5_TWTR_MASK                                0x0000001FU
+
+/*
+* PUB Write Latency Enable
+*/
+#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWLEN_MASK 
+#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                           0x00000505
+#define DDR_PHY_DTPR6_PUBWLEN_SHIFT                            31
+#define DDR_PHY_DTPR6_PUBWLEN_MASK                             0x80000000U
+
+/*
+* PUB Read Latency Enable
+*/
+#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRLEN_MASK 
+#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                           0x00000505
+#define DDR_PHY_DTPR6_PUBRLEN_SHIFT                            30
+#define DDR_PHY_DTPR6_PUBRLEN_MASK                             0x40000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 
+#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                    0x00000505
+#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                     14
+#define DDR_PHY_DTPR6_RESERVED_29_14_MASK                      0x3FFFC000U
+
+/*
+* Write Latency
+*/
+#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWL_MASK 
+#define DDR_PHY_DTPR6_PUBWL_DEFVAL                             0x00000505
+#define DDR_PHY_DTPR6_PUBWL_SHIFT                              8
+#define DDR_PHY_DTPR6_PUBWL_MASK                               0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                      0x00000505
+#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                       6
+#define DDR_PHY_DTPR6_RESERVED_7_6_MASK                        0x000000C0U
+
+/*
+* Read Latency
+*/
+#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRL_MASK 
+#define DDR_PHY_DTPR6_PUBRL_DEFVAL                             0x00000505
+#define DDR_PHY_DTPR6_PUBRL_SHIFT                              0
+#define DDR_PHY_DTPR6_PUBRL_MASK                               0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                   0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                    31
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                     0x80000000U
+
+/*
+* RDMIMM Quad CS Enable
+*/
+#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 
+#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                         0x08400020
+#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                          30
+#define DDR_PHY_RDIMMGCR0_QCSEN_MASK                           0x40000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                 28
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                  0x30000000U
+
+/*
+* RDIMM Outputs I/O Mode
+*/
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                      0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                       27
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                        0x08000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                 24
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                  0x07000000U
+
+/*
+* ERROUT# Output Enable
+*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                      0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                       23
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                        0x00800000U
+
+/*
+* ERROUT# I/O Mode
+*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                     0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                      22
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                       0x00400000U
+
+/*
+* ERROUT# Power Down Receiver
+*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                     0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                      21
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                       0x00200000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                   0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                    20
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                     0x00100000U
+
+/*
+* ERROUT# On-Die Termination
+*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                     0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                      19
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                       0x00080000U
+
+/*
+* Load Reduced DIMM
+*/
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                        0x08400020
+#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                         18
+#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                          0x00040000U
+
+/*
+* PAR_IN I/O Mode
+*/
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                      0x08400020
+#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                       17
+#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                        0x00020000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                 0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                  8
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                   0x0001FF00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                 0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                  6
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                   0x000000C0U
+
+/*
+* Rank Mirror Enable.
+*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                      0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                       4
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                        0x00000030U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                    0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                     3
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                      0x00000008U
+
+/*
+* Stop on Parity Error
+*/
+#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 
+#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                        0x08400020
+#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                         2
+#define DDR_PHY_RDIMMGCR0_SOPERR_MASK                          0x00000004U
+
+/*
+* Parity Error No Registering
+*/
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                      0x08400020
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                       1
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                        0x00000002U
+
+/*
+* Registered DIMM
+*/
+#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                         0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                          0
+#define DDR_PHY_RDIMMGCR0_RDIMM_MASK                           0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                 29
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                  0xE0000000U
+
+/*
+* Address [17] B-side Inversion Disable
+*/
+#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 
+#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                        0x00000C80
+#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                         28
+#define DDR_PHY_RDIMMGCR1_A17BID_MASK                          0x10000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                   0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                    27
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                     0x08000000U
+
+/*
+* Command word to command word programming delay
+*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                     0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                      24
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                       0x07000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                   0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                    23
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                     0x00800000U
+
+/*
+* Command word to command word programming delay
+*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                      0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                       20
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                        0x00700000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                   0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                    19
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                     0x00080000U
+
+/*
+* Command word to command word programming delay
+*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                        0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                         16
+#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                          0x00070000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                 14
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                  0x0000C000U
+
+/*
+* Stabilization time
+*/
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                        0
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                         0x00003FFFU
+
+/*
+* DDR4/DDR3 Control Word 7
+*/
+#undef DDR_PHY_RDIMMCR0_RC7_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC7_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC7_MASK 
+#define DDR_PHY_RDIMMCR0_RC7_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC7_SHIFT                             28
+#define DDR_PHY_RDIMMCR0_RC7_MASK                              0xF0000000U
+
+/*
+* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
+*/
+#undef DDR_PHY_RDIMMCR0_RC6_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC6_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC6_MASK 
+#define DDR_PHY_RDIMMCR0_RC6_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC6_SHIFT                             24
+#define DDR_PHY_RDIMMCR0_RC6_MASK                              0x0F000000U
+
+/*
+* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC5_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC5_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC5_MASK 
+#define DDR_PHY_RDIMMCR0_RC5_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC5_SHIFT                             20
+#define DDR_PHY_RDIMMCR0_RC5_MASK                              0x00F00000U
+
+/*
+* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control
+    * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont
+    * rol Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC4_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC4_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC4_MASK 
+#define DDR_PHY_RDIMMCR0_RC4_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC4_SHIFT                             16
+#define DDR_PHY_RDIMMCR0_RC4_MASK                              0x000F0000U
+
+/*
+* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo
+    * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri
+    * cs Control Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC3_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC3_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC3_MASK 
+#define DDR_PHY_RDIMMCR0_RC3_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC3_SHIFT                             12
+#define DDR_PHY_RDIMMCR0_RC3_MASK                              0x0000F000U
+
+/*
+* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2
+    * (Timing Control Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC2_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC2_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC2_MASK 
+#define DDR_PHY_RDIMMCR0_RC2_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC2_SHIFT                             8
+#define DDR_PHY_RDIMMCR0_RC2_MASK                              0x00000F00U
+
+/*
+* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC1_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC1_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC1_MASK 
+#define DDR_PHY_RDIMMCR0_RC1_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC1_SHIFT                             4
+#define DDR_PHY_RDIMMCR0_RC1_MASK                              0x000000F0U
+
+/*
+* DDR4/DDR3 Control Word 0 (Global Features Control Word)
+*/
+#undef DDR_PHY_RDIMMCR0_RC0_DEFVAL 
+#undef DDR_PHY_RDIMMCR0_RC0_SHIFT 
+#undef DDR_PHY_RDIMMCR0_RC0_MASK 
+#define DDR_PHY_RDIMMCR0_RC0_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR0_RC0_SHIFT                             0
+#define DDR_PHY_RDIMMCR0_RC0_MASK                              0x0000000FU
+
+/*
+* Control Word 15
+*/
+#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC15_MASK 
+#define DDR_PHY_RDIMMCR1_RC15_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC15_SHIFT                            28
+#define DDR_PHY_RDIMMCR1_RC15_MASK                             0xF0000000U
+
+/*
+* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
+*/
+#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC14_MASK 
+#define DDR_PHY_RDIMMCR1_RC14_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC14_SHIFT                            24
+#define DDR_PHY_RDIMMCR1_RC14_MASK                             0x0F000000U
+
+/*
+* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
+*/
+#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC13_MASK 
+#define DDR_PHY_RDIMMCR1_RC13_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC13_SHIFT                            20
+#define DDR_PHY_RDIMMCR1_RC13_MASK                             0x00F00000U
+
+/*
+* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
+*/
+#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC12_MASK 
+#define DDR_PHY_RDIMMCR1_RC12_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC12_SHIFT                            16
+#define DDR_PHY_RDIMMCR1_RC12_MASK                             0x000F0000U
+
+/*
+* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo
+    * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word)
+*/
+#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC11_MASK 
+#define DDR_PHY_RDIMMCR1_RC11_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC11_SHIFT                            12
+#define DDR_PHY_RDIMMCR1_RC11_MASK                             0x0000F000U
+
+/*
+* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
+*/
+#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC10_MASK 
+#define DDR_PHY_RDIMMCR1_RC10_DEFVAL                           0x00000000
+#define DDR_PHY_RDIMMCR1_RC10_SHIFT                            8
+#define DDR_PHY_RDIMMCR1_RC10_MASK                             0x00000F00U
+
+/*
+* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
+*/
+#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC9_MASK 
+#define DDR_PHY_RDIMMCR1_RC9_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR1_RC9_SHIFT                             4
+#define DDR_PHY_RDIMMCR1_RC9_MASK                              0x000000F0U
+
+/*
+* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con
+    * trol Word 8 (Additional Input Bus Termination Setting Control Word)
+*/
+#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC8_MASK 
+#define DDR_PHY_RDIMMCR1_RC8_DEFVAL                            0x00000000
+#define DDR_PHY_RDIMMCR1_RC8_SHIFT                             0
+#define DDR_PHY_RDIMMCR1_RC8_MASK                              0x0000000FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR0_RESERVED_31_8_MASK 
+#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                       0x00000052
+#define DDR_PHY_MR0_RESERVED_31_8_SHIFT                        8
+#define DDR_PHY_MR0_RESERVED_31_8_MASK                         0xFFFFFF00U
+
+/*
+* CA Terminating Rank
+*/
+#undef DDR_PHY_MR0_CATR_DEFVAL 
+#undef DDR_PHY_MR0_CATR_SHIFT 
+#undef DDR_PHY_MR0_CATR_MASK 
+#define DDR_PHY_MR0_CATR_DEFVAL                                0x00000052
+#define DDR_PHY_MR0_CATR_SHIFT                                 7
+#define DDR_PHY_MR0_CATR_MASK                                  0x00000080U
+
+/*
+* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
+    * be programmed to 0x0.
+*/
+#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 
+#undef DDR_PHY_MR0_RSVD_6_5_MASK 
+#define DDR_PHY_MR0_RSVD_6_5_DEFVAL                            0x00000052
+#define DDR_PHY_MR0_RSVD_6_5_SHIFT                             5
+#define DDR_PHY_MR0_RSVD_6_5_MASK                              0x00000060U
+
+/*
+* Built-in Self-Test for RZQ
+*/
+#undef DDR_PHY_MR0_RZQI_DEFVAL 
+#undef DDR_PHY_MR0_RZQI_SHIFT 
+#undef DDR_PHY_MR0_RZQI_MASK 
+#define DDR_PHY_MR0_RZQI_DEFVAL                                0x00000052
+#define DDR_PHY_MR0_RZQI_SHIFT                                 3
+#define DDR_PHY_MR0_RZQI_MASK                                  0x00000018U
+
+/*
+* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to
+    * be programmed to 0x0.
+*/
+#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 
+#undef DDR_PHY_MR0_RSVD_2_0_MASK 
+#define DDR_PHY_MR0_RSVD_2_0_DEFVAL                            0x00000052
+#define DDR_PHY_MR0_RSVD_2_0_SHIFT                             0
+#define DDR_PHY_MR0_RSVD_2_0_MASK                              0x00000007U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR1_RESERVED_31_8_MASK 
+#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                       0x00000004
+#define DDR_PHY_MR1_RESERVED_31_8_SHIFT                        8
+#define DDR_PHY_MR1_RESERVED_31_8_MASK                         0xFFFFFF00U
+
+/*
+* Read Postamble Length
+*/
+#undef DDR_PHY_MR1_RDPST_DEFVAL 
+#undef DDR_PHY_MR1_RDPST_SHIFT 
+#undef DDR_PHY_MR1_RDPST_MASK 
+#define DDR_PHY_MR1_RDPST_DEFVAL                               0x00000004
+#define DDR_PHY_MR1_RDPST_SHIFT                                7
+#define DDR_PHY_MR1_RDPST_MASK                                 0x00000080U
+
+/*
+* Write-recovery for auto-precharge command
+*/
+#undef DDR_PHY_MR1_NWR_DEFVAL 
+#undef DDR_PHY_MR1_NWR_SHIFT 
+#undef DDR_PHY_MR1_NWR_MASK 
+#define DDR_PHY_MR1_NWR_DEFVAL                                 0x00000004
+#define DDR_PHY_MR1_NWR_SHIFT                                  4
+#define DDR_PHY_MR1_NWR_MASK                                   0x00000070U
+
+/*
+* Read Preamble Length
+*/
+#undef DDR_PHY_MR1_RDPRE_DEFVAL 
+#undef DDR_PHY_MR1_RDPRE_SHIFT 
+#undef DDR_PHY_MR1_RDPRE_MASK 
+#define DDR_PHY_MR1_RDPRE_DEFVAL                               0x00000004
+#define DDR_PHY_MR1_RDPRE_SHIFT                                3
+#define DDR_PHY_MR1_RDPRE_MASK                                 0x00000008U
+
+/*
+* Write Preamble Length
+*/
+#undef DDR_PHY_MR1_WRPRE_DEFVAL 
+#undef DDR_PHY_MR1_WRPRE_SHIFT 
+#undef DDR_PHY_MR1_WRPRE_MASK 
+#define DDR_PHY_MR1_WRPRE_DEFVAL                               0x00000004
+#define DDR_PHY_MR1_WRPRE_SHIFT                                2
+#define DDR_PHY_MR1_WRPRE_MASK                                 0x00000004U
+
+/*
+* Burst Length
+*/
+#undef DDR_PHY_MR1_BL_DEFVAL 
+#undef DDR_PHY_MR1_BL_SHIFT 
+#undef DDR_PHY_MR1_BL_MASK 
+#define DDR_PHY_MR1_BL_DEFVAL                                  0x00000004
+#define DDR_PHY_MR1_BL_SHIFT                                   0
+#define DDR_PHY_MR1_BL_MASK                                    0x00000003U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR2_RESERVED_31_8_MASK 
+#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                       0x00000000
+#define DDR_PHY_MR2_RESERVED_31_8_SHIFT                        8
+#define DDR_PHY_MR2_RESERVED_31_8_MASK                         0xFFFFFF00U
+
+/*
+* Write Leveling
+*/
+#undef DDR_PHY_MR2_WRL_DEFVAL 
+#undef DDR_PHY_MR2_WRL_SHIFT 
+#undef DDR_PHY_MR2_WRL_MASK 
+#define DDR_PHY_MR2_WRL_DEFVAL                                 0x00000000
+#define DDR_PHY_MR2_WRL_SHIFT                                  7
+#define DDR_PHY_MR2_WRL_MASK                                   0x00000080U
+
+/*
+* Write Latency Set
+*/
+#undef DDR_PHY_MR2_WLS_DEFVAL 
+#undef DDR_PHY_MR2_WLS_SHIFT 
+#undef DDR_PHY_MR2_WLS_MASK 
+#define DDR_PHY_MR2_WLS_DEFVAL                                 0x00000000
+#define DDR_PHY_MR2_WLS_SHIFT                                  6
+#define DDR_PHY_MR2_WLS_MASK                                   0x00000040U
+
+/*
+* Write Latency
+*/
+#undef DDR_PHY_MR2_WL_DEFVAL 
+#undef DDR_PHY_MR2_WL_SHIFT 
+#undef DDR_PHY_MR2_WL_MASK 
+#define DDR_PHY_MR2_WL_DEFVAL                                  0x00000000
+#define DDR_PHY_MR2_WL_SHIFT                                   3
+#define DDR_PHY_MR2_WL_MASK                                    0x00000038U
+
+/*
+* Read Latency
+*/
+#undef DDR_PHY_MR2_RL_DEFVAL 
+#undef DDR_PHY_MR2_RL_SHIFT 
+#undef DDR_PHY_MR2_RL_MASK 
+#define DDR_PHY_MR2_RL_DEFVAL                                  0x00000000
+#define DDR_PHY_MR2_RL_SHIFT                                   0
+#define DDR_PHY_MR2_RL_MASK                                    0x00000007U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR3_RESERVED_31_8_MASK 
+#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                       0x00000031
+#define DDR_PHY_MR3_RESERVED_31_8_SHIFT                        8
+#define DDR_PHY_MR3_RESERVED_31_8_MASK                         0xFFFFFF00U
+
+/*
+* DBI-Write Enable
+*/
+#undef DDR_PHY_MR3_DBIWR_DEFVAL 
+#undef DDR_PHY_MR3_DBIWR_SHIFT 
+#undef DDR_PHY_MR3_DBIWR_MASK 
+#define DDR_PHY_MR3_DBIWR_DEFVAL                               0x00000031
+#define DDR_PHY_MR3_DBIWR_SHIFT                                7
+#define DDR_PHY_MR3_DBIWR_MASK                                 0x00000080U
+
+/*
+* DBI-Read Enable
+*/
+#undef DDR_PHY_MR3_DBIRD_DEFVAL 
+#undef DDR_PHY_MR3_DBIRD_SHIFT 
+#undef DDR_PHY_MR3_DBIRD_MASK 
+#define DDR_PHY_MR3_DBIRD_DEFVAL                               0x00000031
+#define DDR_PHY_MR3_DBIRD_SHIFT                                6
+#define DDR_PHY_MR3_DBIRD_MASK                                 0x00000040U
+
+/*
+* Pull-down Drive Strength
+*/
+#undef DDR_PHY_MR3_PDDS_DEFVAL 
+#undef DDR_PHY_MR3_PDDS_SHIFT 
+#undef DDR_PHY_MR3_PDDS_MASK 
+#define DDR_PHY_MR3_PDDS_DEFVAL                                0x00000031
+#define DDR_PHY_MR3_PDDS_SHIFT                                 3
+#define DDR_PHY_MR3_PDDS_MASK                                  0x00000038U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR3_RSVD_DEFVAL 
+#undef DDR_PHY_MR3_RSVD_SHIFT 
+#undef DDR_PHY_MR3_RSVD_MASK 
+#define DDR_PHY_MR3_RSVD_DEFVAL                                0x00000031
+#define DDR_PHY_MR3_RSVD_SHIFT                                 2
+#define DDR_PHY_MR3_RSVD_MASK                                  0x00000004U
+
+/*
+* Write Postamble Length
+*/
+#undef DDR_PHY_MR3_WRPST_DEFVAL 
+#undef DDR_PHY_MR3_WRPST_SHIFT 
+#undef DDR_PHY_MR3_WRPST_MASK 
+#define DDR_PHY_MR3_WRPST_DEFVAL                               0x00000031
+#define DDR_PHY_MR3_WRPST_SHIFT                                1
+#define DDR_PHY_MR3_WRPST_MASK                                 0x00000002U
+
+/*
+* Pull-up Calibration Point
+*/
+#undef DDR_PHY_MR3_PUCAL_DEFVAL 
+#undef DDR_PHY_MR3_PUCAL_SHIFT 
+#undef DDR_PHY_MR3_PUCAL_MASK 
+#define DDR_PHY_MR3_PUCAL_DEFVAL                               0x00000031
+#define DDR_PHY_MR3_PUCAL_SHIFT                                0
+#define DDR_PHY_MR3_PUCAL_MASK                                 0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR4_RESERVED_31_16_MASK 
+#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                      0x00000000
+#define DDR_PHY_MR4_RESERVED_31_16_SHIFT                       16
+#define DDR_PHY_MR4_RESERVED_31_16_MASK                        0xFFFF0000U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR4_RSVD_15_13_MASK 
+#define DDR_PHY_MR4_RSVD_15_13_DEFVAL                          0x00000000
+#define DDR_PHY_MR4_RSVD_15_13_SHIFT                           13
+#define DDR_PHY_MR4_RSVD_15_13_MASK                            0x0000E000U
+
+/*
+* Write Preamble
+*/
+#undef DDR_PHY_MR4_WRP_DEFVAL 
+#undef DDR_PHY_MR4_WRP_SHIFT 
+#undef DDR_PHY_MR4_WRP_MASK 
+#define DDR_PHY_MR4_WRP_DEFVAL                                 0x00000000
+#define DDR_PHY_MR4_WRP_SHIFT                                  12
+#define DDR_PHY_MR4_WRP_MASK                                   0x00001000U
+
+/*
+* Read Preamble
+*/
+#undef DDR_PHY_MR4_RDP_DEFVAL 
+#undef DDR_PHY_MR4_RDP_SHIFT 
+#undef DDR_PHY_MR4_RDP_MASK 
+#define DDR_PHY_MR4_RDP_DEFVAL                                 0x00000000
+#define DDR_PHY_MR4_RDP_SHIFT                                  11
+#define DDR_PHY_MR4_RDP_MASK                                   0x00000800U
+
+/*
+* Read Preamble Training Mode
+*/
+#undef DDR_PHY_MR4_RPTM_DEFVAL 
+#undef DDR_PHY_MR4_RPTM_SHIFT 
+#undef DDR_PHY_MR4_RPTM_MASK 
+#define DDR_PHY_MR4_RPTM_DEFVAL                                0x00000000
+#define DDR_PHY_MR4_RPTM_SHIFT                                 10
+#define DDR_PHY_MR4_RPTM_MASK                                  0x00000400U
+
+/*
+* Self Refresh Abort
+*/
+#undef DDR_PHY_MR4_SRA_DEFVAL 
+#undef DDR_PHY_MR4_SRA_SHIFT 
+#undef DDR_PHY_MR4_SRA_MASK 
+#define DDR_PHY_MR4_SRA_DEFVAL                                 0x00000000
+#define DDR_PHY_MR4_SRA_SHIFT                                  9
+#define DDR_PHY_MR4_SRA_MASK                                   0x00000200U
+
+/*
+* CS to Command Latency Mode
+*/
+#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 
+#undef DDR_PHY_MR4_CS2CMDL_SHIFT 
+#undef DDR_PHY_MR4_CS2CMDL_MASK 
+#define DDR_PHY_MR4_CS2CMDL_DEFVAL                             0x00000000
+#define DDR_PHY_MR4_CS2CMDL_SHIFT                              6
+#define DDR_PHY_MR4_CS2CMDL_MASK                               0x000001C0U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR4_RSVD1_DEFVAL 
+#undef DDR_PHY_MR4_RSVD1_SHIFT 
+#undef DDR_PHY_MR4_RSVD1_MASK 
+#define DDR_PHY_MR4_RSVD1_DEFVAL                               0x00000000
+#define DDR_PHY_MR4_RSVD1_SHIFT                                5
+#define DDR_PHY_MR4_RSVD1_MASK                                 0x00000020U
+
+/*
+* Internal VREF Monitor
+*/
+#undef DDR_PHY_MR4_IVM_DEFVAL 
+#undef DDR_PHY_MR4_IVM_SHIFT 
+#undef DDR_PHY_MR4_IVM_MASK 
+#define DDR_PHY_MR4_IVM_DEFVAL                                 0x00000000
+#define DDR_PHY_MR4_IVM_SHIFT                                  4
+#define DDR_PHY_MR4_IVM_MASK                                   0x00000010U
+
+/*
+* Temperature Controlled Refresh Mode
+*/
+#undef DDR_PHY_MR4_TCRM_DEFVAL 
+#undef DDR_PHY_MR4_TCRM_SHIFT 
+#undef DDR_PHY_MR4_TCRM_MASK 
+#define DDR_PHY_MR4_TCRM_DEFVAL                                0x00000000
+#define DDR_PHY_MR4_TCRM_SHIFT                                 3
+#define DDR_PHY_MR4_TCRM_MASK                                  0x00000008U
+
+/*
+* Temperature Controlled Refresh Range
+*/
+#undef DDR_PHY_MR4_TCRR_DEFVAL 
+#undef DDR_PHY_MR4_TCRR_SHIFT 
+#undef DDR_PHY_MR4_TCRR_MASK 
+#define DDR_PHY_MR4_TCRR_DEFVAL                                0x00000000
+#define DDR_PHY_MR4_TCRR_SHIFT                                 2
+#define DDR_PHY_MR4_TCRR_MASK                                  0x00000004U
+
+/*
+* Maximum Power Down Mode
+*/
+#undef DDR_PHY_MR4_MPDM_DEFVAL 
+#undef DDR_PHY_MR4_MPDM_SHIFT 
+#undef DDR_PHY_MR4_MPDM_MASK 
+#define DDR_PHY_MR4_MPDM_DEFVAL                                0x00000000
+#define DDR_PHY_MR4_MPDM_SHIFT                                 1
+#define DDR_PHY_MR4_MPDM_MASK                                  0x00000002U
+
+/*
+* This is a JEDEC reserved bit and is recommended by JEDEC to be programme
+    * d to 0x0.
+*/
+#undef DDR_PHY_MR4_RSVD_0_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_0_SHIFT 
+#undef DDR_PHY_MR4_RSVD_0_MASK 
+#define DDR_PHY_MR4_RSVD_0_DEFVAL                              0x00000000
+#define DDR_PHY_MR4_RSVD_0_SHIFT                               0
+#define DDR_PHY_MR4_RSVD_0_MASK                                0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR5_RESERVED_31_16_MASK 
+#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                      0x00000000
+#define DDR_PHY_MR5_RESERVED_31_16_SHIFT                       16
+#define DDR_PHY_MR5_RESERVED_31_16_MASK                        0xFFFF0000U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR5_RSVD_DEFVAL 
+#undef DDR_PHY_MR5_RSVD_SHIFT 
+#undef DDR_PHY_MR5_RSVD_MASK 
+#define DDR_PHY_MR5_RSVD_DEFVAL                                0x00000000
+#define DDR_PHY_MR5_RSVD_SHIFT                                 13
+#define DDR_PHY_MR5_RSVD_MASK                                  0x0000E000U
+
+/*
+* Read DBI
+*/
+#undef DDR_PHY_MR5_RDBI_DEFVAL 
+#undef DDR_PHY_MR5_RDBI_SHIFT 
+#undef DDR_PHY_MR5_RDBI_MASK 
+#define DDR_PHY_MR5_RDBI_DEFVAL                                0x00000000
+#define DDR_PHY_MR5_RDBI_SHIFT                                 12
+#define DDR_PHY_MR5_RDBI_MASK                                  0x00001000U
+
+/*
+* Write DBI
+*/
+#undef DDR_PHY_MR5_WDBI_DEFVAL 
+#undef DDR_PHY_MR5_WDBI_SHIFT 
+#undef DDR_PHY_MR5_WDBI_MASK 
+#define DDR_PHY_MR5_WDBI_DEFVAL                                0x00000000
+#define DDR_PHY_MR5_WDBI_SHIFT                                 11
+#define DDR_PHY_MR5_WDBI_MASK                                  0x00000800U
+
+/*
+* Data Mask
+*/
+#undef DDR_PHY_MR5_DM_DEFVAL 
+#undef DDR_PHY_MR5_DM_SHIFT 
+#undef DDR_PHY_MR5_DM_MASK 
+#define DDR_PHY_MR5_DM_DEFVAL                                  0x00000000
+#define DDR_PHY_MR5_DM_SHIFT                                   10
+#define DDR_PHY_MR5_DM_MASK                                    0x00000400U
+
+/*
+* CA Parity Persistent Error
+*/
+#undef DDR_PHY_MR5_CAPPE_DEFVAL 
+#undef DDR_PHY_MR5_CAPPE_SHIFT 
+#undef DDR_PHY_MR5_CAPPE_MASK 
+#define DDR_PHY_MR5_CAPPE_DEFVAL                               0x00000000
+#define DDR_PHY_MR5_CAPPE_SHIFT                                9
+#define DDR_PHY_MR5_CAPPE_MASK                                 0x00000200U
+
+/*
+* RTT_PARK
+*/
+#undef DDR_PHY_MR5_RTTPARK_DEFVAL 
+#undef DDR_PHY_MR5_RTTPARK_SHIFT 
+#undef DDR_PHY_MR5_RTTPARK_MASK 
+#define DDR_PHY_MR5_RTTPARK_DEFVAL                             0x00000000
+#define DDR_PHY_MR5_RTTPARK_SHIFT                              6
+#define DDR_PHY_MR5_RTTPARK_MASK                               0x000001C0U
+
+/*
+* ODT Input Buffer during Power Down mode
+*/
+#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 
+#undef DDR_PHY_MR5_ODTIBPD_SHIFT 
+#undef DDR_PHY_MR5_ODTIBPD_MASK 
+#define DDR_PHY_MR5_ODTIBPD_DEFVAL                             0x00000000
+#define DDR_PHY_MR5_ODTIBPD_SHIFT                              5
+#define DDR_PHY_MR5_ODTIBPD_MASK                               0x00000020U
+
+/*
+* C/A Parity Error Status
+*/
+#undef DDR_PHY_MR5_CAPES_DEFVAL 
+#undef DDR_PHY_MR5_CAPES_SHIFT 
+#undef DDR_PHY_MR5_CAPES_MASK 
+#define DDR_PHY_MR5_CAPES_DEFVAL                               0x00000000
+#define DDR_PHY_MR5_CAPES_SHIFT                                4
+#define DDR_PHY_MR5_CAPES_MASK                                 0x00000010U
+
+/*
+* CRC Error Clear
+*/
+#undef DDR_PHY_MR5_CRCEC_DEFVAL 
+#undef DDR_PHY_MR5_CRCEC_SHIFT 
+#undef DDR_PHY_MR5_CRCEC_MASK 
+#define DDR_PHY_MR5_CRCEC_DEFVAL                               0x00000000
+#define DDR_PHY_MR5_CRCEC_SHIFT                                3
+#define DDR_PHY_MR5_CRCEC_MASK                                 0x00000008U
+
+/*
+* C/A Parity Latency Mode
+*/
+#undef DDR_PHY_MR5_CAPM_DEFVAL 
+#undef DDR_PHY_MR5_CAPM_SHIFT 
+#undef DDR_PHY_MR5_CAPM_MASK 
+#define DDR_PHY_MR5_CAPM_DEFVAL                                0x00000000
+#define DDR_PHY_MR5_CAPM_SHIFT                                 0
+#define DDR_PHY_MR5_CAPM_MASK                                  0x00000007U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR6_RESERVED_31_16_MASK 
+#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                      0x00000000
+#define DDR_PHY_MR6_RESERVED_31_16_SHIFT                       16
+#define DDR_PHY_MR6_RESERVED_31_16_MASK                        0xFFFF0000U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR6_RSVD_15_13_MASK 
+#define DDR_PHY_MR6_RSVD_15_13_DEFVAL                          0x00000000
+#define DDR_PHY_MR6_RSVD_15_13_SHIFT                           13
+#define DDR_PHY_MR6_RSVD_15_13_MASK                            0x0000E000U
+
+/*
+* CAS_n to CAS_n command delay for same bank group (tCCD_L)
+*/
+#undef DDR_PHY_MR6_TCCDL_DEFVAL 
+#undef DDR_PHY_MR6_TCCDL_SHIFT 
+#undef DDR_PHY_MR6_TCCDL_MASK 
+#define DDR_PHY_MR6_TCCDL_DEFVAL                               0x00000000
+#define DDR_PHY_MR6_TCCDL_SHIFT                                10
+#define DDR_PHY_MR6_TCCDL_MASK                                 0x00001C00U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 
+#undef DDR_PHY_MR6_RSVD_9_8_MASK 
+#define DDR_PHY_MR6_RSVD_9_8_DEFVAL                            0x00000000
+#define DDR_PHY_MR6_RSVD_9_8_SHIFT                             8
+#define DDR_PHY_MR6_RSVD_9_8_MASK                              0x00000300U
+
+/*
+* VrefDQ Training Enable
+*/
+#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 
+#undef DDR_PHY_MR6_VDDQTEN_SHIFT 
+#undef DDR_PHY_MR6_VDDQTEN_MASK 
+#define DDR_PHY_MR6_VDDQTEN_DEFVAL                             0x00000000
+#define DDR_PHY_MR6_VDDQTEN_SHIFT                              7
+#define DDR_PHY_MR6_VDDQTEN_MASK                               0x00000080U
+
+/*
+* VrefDQ Training Range
+*/
+#undef DDR_PHY_MR6_VDQTRG_DEFVAL 
+#undef DDR_PHY_MR6_VDQTRG_SHIFT 
+#undef DDR_PHY_MR6_VDQTRG_MASK 
+#define DDR_PHY_MR6_VDQTRG_DEFVAL                              0x00000000
+#define DDR_PHY_MR6_VDQTRG_SHIFT                               6
+#define DDR_PHY_MR6_VDQTRG_MASK                                0x00000040U
+
+/*
+* VrefDQ Training Values
+*/
+#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 
+#undef DDR_PHY_MR6_VDQTVAL_SHIFT 
+#undef DDR_PHY_MR6_VDQTVAL_MASK 
+#define DDR_PHY_MR6_VDQTVAL_DEFVAL                             0x00000000
+#define DDR_PHY_MR6_VDQTVAL_SHIFT                              0
+#define DDR_PHY_MR6_VDQTVAL_MASK                               0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR11_RESERVED_31_8_MASK 
+#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                      0x00000000
+#define DDR_PHY_MR11_RESERVED_31_8_SHIFT                       8
+#define DDR_PHY_MR11_RESERVED_31_8_MASK                        0xFFFFFF00U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR11_RSVD_DEFVAL 
+#undef DDR_PHY_MR11_RSVD_SHIFT 
+#undef DDR_PHY_MR11_RSVD_MASK 
+#define DDR_PHY_MR11_RSVD_DEFVAL                               0x00000000
+#define DDR_PHY_MR11_RSVD_SHIFT                                3
+#define DDR_PHY_MR11_RSVD_MASK                                 0x000000F8U
+
+/*
+* Power Down Control
+*/
+#undef DDR_PHY_MR11_PDCTL_DEFVAL 
+#undef DDR_PHY_MR11_PDCTL_SHIFT 
+#undef DDR_PHY_MR11_PDCTL_MASK 
+#define DDR_PHY_MR11_PDCTL_DEFVAL                              0x00000000
+#define DDR_PHY_MR11_PDCTL_SHIFT                               2
+#define DDR_PHY_MR11_PDCTL_MASK                                0x00000004U
+
+/*
+* DQ Bus Receiver On-Die-Termination
+*/
+#undef DDR_PHY_MR11_DQODT_DEFVAL 
+#undef DDR_PHY_MR11_DQODT_SHIFT 
+#undef DDR_PHY_MR11_DQODT_MASK 
+#define DDR_PHY_MR11_DQODT_DEFVAL                              0x00000000
+#define DDR_PHY_MR11_DQODT_SHIFT                               0
+#define DDR_PHY_MR11_DQODT_MASK                                0x00000003U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR12_RESERVED_31_8_MASK 
+#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                      0x0000004D
+#define DDR_PHY_MR12_RESERVED_31_8_SHIFT                       8
+#define DDR_PHY_MR12_RESERVED_31_8_MASK                        0xFFFFFF00U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR12_RSVD_DEFVAL 
+#undef DDR_PHY_MR12_RSVD_SHIFT 
+#undef DDR_PHY_MR12_RSVD_MASK 
+#define DDR_PHY_MR12_RSVD_DEFVAL                               0x0000004D
+#define DDR_PHY_MR12_RSVD_SHIFT                                7
+#define DDR_PHY_MR12_RSVD_MASK                                 0x00000080U
+
+/*
+* VREF_CA Range Select.
+*/
+#undef DDR_PHY_MR12_VR_CA_DEFVAL 
+#undef DDR_PHY_MR12_VR_CA_SHIFT 
+#undef DDR_PHY_MR12_VR_CA_MASK 
+#define DDR_PHY_MR12_VR_CA_DEFVAL                              0x0000004D
+#define DDR_PHY_MR12_VR_CA_SHIFT                               6
+#define DDR_PHY_MR12_VR_CA_MASK                                0x00000040U
+
+/*
+* Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
+*/
+#undef DDR_PHY_MR12_VREF_CA_DEFVAL 
+#undef DDR_PHY_MR12_VREF_CA_SHIFT 
+#undef DDR_PHY_MR12_VREF_CA_MASK 
+#define DDR_PHY_MR12_VREF_CA_DEFVAL                            0x0000004D
+#define DDR_PHY_MR12_VREF_CA_SHIFT                             0
+#define DDR_PHY_MR12_VREF_CA_MASK                              0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR13_RESERVED_31_8_MASK 
+#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                      0x00000000
+#define DDR_PHY_MR13_RESERVED_31_8_SHIFT                       8
+#define DDR_PHY_MR13_RESERVED_31_8_MASK                        0xFFFFFF00U
+
+/*
+* Frequency Set Point Operation Mode
+*/
+#undef DDR_PHY_MR13_FSPOP_DEFVAL 
+#undef DDR_PHY_MR13_FSPOP_SHIFT 
+#undef DDR_PHY_MR13_FSPOP_MASK 
+#define DDR_PHY_MR13_FSPOP_DEFVAL                              0x00000000
+#define DDR_PHY_MR13_FSPOP_SHIFT                               7
+#define DDR_PHY_MR13_FSPOP_MASK                                0x00000080U
+
+/*
+* Frequency Set Point Write Enable
+*/
+#undef DDR_PHY_MR13_FSPWR_DEFVAL 
+#undef DDR_PHY_MR13_FSPWR_SHIFT 
+#undef DDR_PHY_MR13_FSPWR_MASK 
+#define DDR_PHY_MR13_FSPWR_DEFVAL                              0x00000000
+#define DDR_PHY_MR13_FSPWR_SHIFT                               6
+#define DDR_PHY_MR13_FSPWR_MASK                                0x00000040U
+
+/*
+* Data Mask Enable
+*/
+#undef DDR_PHY_MR13_DMD_DEFVAL 
+#undef DDR_PHY_MR13_DMD_SHIFT 
+#undef DDR_PHY_MR13_DMD_MASK 
+#define DDR_PHY_MR13_DMD_DEFVAL                                0x00000000
+#define DDR_PHY_MR13_DMD_SHIFT                                 5
+#define DDR_PHY_MR13_DMD_MASK                                  0x00000020U
+
+/*
+* Refresh Rate Option
+*/
+#undef DDR_PHY_MR13_RRO_DEFVAL 
+#undef DDR_PHY_MR13_RRO_SHIFT 
+#undef DDR_PHY_MR13_RRO_MASK 
+#define DDR_PHY_MR13_RRO_DEFVAL                                0x00000000
+#define DDR_PHY_MR13_RRO_SHIFT                                 4
+#define DDR_PHY_MR13_RRO_MASK                                  0x00000010U
+
+/*
+* VREF Current Generator
+*/
+#undef DDR_PHY_MR13_VRCG_DEFVAL 
+#undef DDR_PHY_MR13_VRCG_SHIFT 
+#undef DDR_PHY_MR13_VRCG_MASK 
+#define DDR_PHY_MR13_VRCG_DEFVAL                               0x00000000
+#define DDR_PHY_MR13_VRCG_SHIFT                                3
+#define DDR_PHY_MR13_VRCG_MASK                                 0x00000008U
+
+/*
+* VREF Output
+*/
+#undef DDR_PHY_MR13_VRO_DEFVAL 
+#undef DDR_PHY_MR13_VRO_SHIFT 
+#undef DDR_PHY_MR13_VRO_MASK 
+#define DDR_PHY_MR13_VRO_DEFVAL                                0x00000000
+#define DDR_PHY_MR13_VRO_SHIFT                                 2
+#define DDR_PHY_MR13_VRO_MASK                                  0x00000004U
+
+/*
+* Read Preamble Training Mode
+*/
+#undef DDR_PHY_MR13_RPT_DEFVAL 
+#undef DDR_PHY_MR13_RPT_SHIFT 
+#undef DDR_PHY_MR13_RPT_MASK 
+#define DDR_PHY_MR13_RPT_DEFVAL                                0x00000000
+#define DDR_PHY_MR13_RPT_SHIFT                                 1
+#define DDR_PHY_MR13_RPT_MASK                                  0x00000002U
+
+/*
+* Command Bus Training
+*/
+#undef DDR_PHY_MR13_CBT_DEFVAL 
+#undef DDR_PHY_MR13_CBT_SHIFT 
+#undef DDR_PHY_MR13_CBT_MASK 
+#define DDR_PHY_MR13_CBT_DEFVAL                                0x00000000
+#define DDR_PHY_MR13_CBT_SHIFT                                 0
+#define DDR_PHY_MR13_CBT_MASK                                  0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR14_RESERVED_31_8_MASK 
+#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                      0x0000004D
+#define DDR_PHY_MR14_RESERVED_31_8_SHIFT                       8
+#define DDR_PHY_MR14_RESERVED_31_8_MASK                        0xFFFFFF00U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR14_RSVD_DEFVAL 
+#undef DDR_PHY_MR14_RSVD_SHIFT 
+#undef DDR_PHY_MR14_RSVD_MASK 
+#define DDR_PHY_MR14_RSVD_DEFVAL                               0x0000004D
+#define DDR_PHY_MR14_RSVD_SHIFT                                7
+#define DDR_PHY_MR14_RSVD_MASK                                 0x00000080U
+
+/*
+* VREFDQ Range Selects.
+*/
+#undef DDR_PHY_MR14_VR_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VR_DQ_SHIFT 
+#undef DDR_PHY_MR14_VR_DQ_MASK 
+#define DDR_PHY_MR14_VR_DQ_DEFVAL                              0x0000004D
+#define DDR_PHY_MR14_VR_DQ_SHIFT                               6
+#define DDR_PHY_MR14_VR_DQ_MASK                                0x00000040U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VREF_DQ_SHIFT 
+#undef DDR_PHY_MR14_VREF_DQ_MASK 
+#define DDR_PHY_MR14_VREF_DQ_DEFVAL                            0x0000004D
+#define DDR_PHY_MR14_VREF_DQ_SHIFT                             0
+#define DDR_PHY_MR14_VREF_DQ_MASK                              0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR22_RESERVED_31_8_MASK 
+#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                      0x00000000
+#define DDR_PHY_MR22_RESERVED_31_8_SHIFT                       8
+#define DDR_PHY_MR22_RESERVED_31_8_MASK                        0xFFFFFF00U
+
+/*
+* These are JEDEC reserved bits and are recommended by JEDEC to be program
+    * med to 0x0.
+*/
+#undef DDR_PHY_MR22_RSVD_DEFVAL 
+#undef DDR_PHY_MR22_RSVD_SHIFT 
+#undef DDR_PHY_MR22_RSVD_MASK 
+#define DDR_PHY_MR22_RSVD_DEFVAL                               0x00000000
+#define DDR_PHY_MR22_RSVD_SHIFT                                6
+#define DDR_PHY_MR22_RSVD_MASK                                 0x000000C0U
+
+/*
+* CA ODT termination disable.
+*/
+#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 
+#undef DDR_PHY_MR22_ODTD_CA_SHIFT 
+#undef DDR_PHY_MR22_ODTD_CA_MASK 
+#define DDR_PHY_MR22_ODTD_CA_DEFVAL                            0x00000000
+#define DDR_PHY_MR22_ODTD_CA_SHIFT                             5
+#define DDR_PHY_MR22_ODTD_CA_MASK                              0x00000020U
+
+/*
+* ODT CS override.
+*/
+#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CS_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CS_MASK 
+#define DDR_PHY_MR22_ODTE_CS_DEFVAL                            0x00000000
+#define DDR_PHY_MR22_ODTE_CS_SHIFT                             4
+#define DDR_PHY_MR22_ODTE_CS_MASK                              0x00000010U
+
+/*
+* ODT CK override.
+*/
+#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CK_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CK_MASK 
+#define DDR_PHY_MR22_ODTE_CK_DEFVAL                            0x00000000
+#define DDR_PHY_MR22_ODTE_CK_SHIFT                             3
+#define DDR_PHY_MR22_ODTE_CK_MASK                              0x00000008U
+
+/*
+* Controller ODT value for VOH calibration.
+*/
+#undef DDR_PHY_MR22_CODT_DEFVAL 
+#undef DDR_PHY_MR22_CODT_SHIFT 
+#undef DDR_PHY_MR22_CODT_MASK 
+#define DDR_PHY_MR22_CODT_DEFVAL                               0x00000000
+#define DDR_PHY_MR22_CODT_SHIFT                                0
+#define DDR_PHY_MR22_CODT_MASK                                 0x00000007U
+
+/*
+* Refresh During Training
+*/
+#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHDT_MASK 
+#define DDR_PHY_DTCR0_RFSHDT_DEFVAL                            0x800091C7
+#define DDR_PHY_DTCR0_RFSHDT_SHIFT                             28
+#define DDR_PHY_DTCR0_RFSHDT_MASK                              0xF0000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 
+#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                    0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                     26
+#define DDR_PHY_DTCR0_RESERVED_27_26_MASK                      0x0C000000U
+
+/*
+* Data Training Debug Rank Select
+*/
+#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDRS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDRS_MASK 
+#define DDR_PHY_DTCR0_DTDRS_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTDRS_SHIFT                              24
+#define DDR_PHY_DTCR0_DTDRS_MASK                               0x03000000U
+
+/*
+* Data Training with Early/Extended Gate
+*/
+#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXG_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXG_MASK 
+#define DDR_PHY_DTCR0_DTEXG_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTEXG_SHIFT                              23
+#define DDR_PHY_DTCR0_DTEXG_MASK                               0x00800000U
+
+/*
+* Data Training Extended Write DQS
+*/
+#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXD_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXD_MASK 
+#define DDR_PHY_DTCR0_DTEXD_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTEXD_SHIFT                              22
+#define DDR_PHY_DTCR0_DTEXD_MASK                               0x00400000U
+
+/*
+* Data Training Debug Step
+*/
+#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 
+#undef DDR_PHY_DTCR0_DTDSTP_MASK 
+#define DDR_PHY_DTCR0_DTDSTP_DEFVAL                            0x800091C7
+#define DDR_PHY_DTCR0_DTDSTP_SHIFT                             21
+#define DDR_PHY_DTCR0_DTDSTP_MASK                              0x00200000U
+
+/*
+* Data Training Debug Enable
+*/
+#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDEN_SHIFT 
+#undef DDR_PHY_DTCR0_DTDEN_MASK 
+#define DDR_PHY_DTCR0_DTDEN_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTDEN_SHIFT                              20
+#define DDR_PHY_DTCR0_DTDEN_MASK                               0x00100000U
+
+/*
+* Data Training Debug Byte Select
+*/
+#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDBS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDBS_MASK 
+#define DDR_PHY_DTCR0_DTDBS_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTDBS_SHIFT                              16
+#define DDR_PHY_DTCR0_DTDBS_MASK                               0x000F0000U
+
+/*
+* Data Training read DBI deskewing configuration
+*/
+#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 
+#undef DDR_PHY_DTCR0_DTRDBITR_MASK 
+#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                          0x800091C7
+#define DDR_PHY_DTCR0_DTRDBITR_SHIFT                           14
+#define DDR_PHY_DTCR0_DTRDBITR_MASK                            0x0000C000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_13_MASK 
+#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                       0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_13_SHIFT                        13
+#define DDR_PHY_DTCR0_RESERVED_13_MASK                         0x00002000U
+
+/*
+* Data Training Write Bit Deskew Data Mask
+*/
+#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 
+#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 
+#undef DDR_PHY_DTCR0_DTWBDDM_MASK 
+#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                           0x800091C7
+#define DDR_PHY_DTCR0_DTWBDDM_SHIFT                            12
+#define DDR_PHY_DTCR0_DTWBDDM_MASK                             0x00001000U
+
+/*
+* Refreshes Issued During Entry to Training
+*/
+#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHEN_MASK 
+#define DDR_PHY_DTCR0_RFSHEN_DEFVAL                            0x800091C7
+#define DDR_PHY_DTCR0_RFSHEN_SHIFT                             8
+#define DDR_PHY_DTCR0_RFSHEN_MASK                              0x00000F00U
+
+/*
+* Data Training Compare Data
+*/
+#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 
+#undef DDR_PHY_DTCR0_DTCMPD_MASK 
+#define DDR_PHY_DTCR0_DTCMPD_DEFVAL                            0x800091C7
+#define DDR_PHY_DTCR0_DTCMPD_SHIFT                             7
+#define DDR_PHY_DTCR0_DTCMPD_MASK                              0x00000080U
+
+/*
+* Data Training Using MPR
+*/
+#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTMPR_SHIFT 
+#undef DDR_PHY_DTCR0_DTMPR_MASK 
+#define DDR_PHY_DTCR0_DTMPR_DEFVAL                             0x800091C7
+#define DDR_PHY_DTCR0_DTMPR_SHIFT                              6
+#define DDR_PHY_DTCR0_DTMPR_MASK                               0x00000040U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 
+#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                      0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                       4
+#define DDR_PHY_DTCR0_RESERVED_5_4_MASK                        0x00000030U
+
+/*
+* Data Training Repeat Number
+*/
+#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 
+#undef DDR_PHY_DTCR0_DTRPTN_MASK 
+#define DDR_PHY_DTCR0_DTRPTN_DEFVAL                            0x800091C7
+#define DDR_PHY_DTCR0_DTRPTN_SHIFT                             0
+#define DDR_PHY_DTCR0_DTRPTN_MASK                              0x0000000FU
+
+/*
+* Rank Enable.
+*/
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 
+#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                       0x00030237
+#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                        18
+#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                         0xFFFC0000U
+
+/*
+* Rank Enable.
+*/
+#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_MASK 
+#define DDR_PHY_DTCR1_RANKEN_DEFVAL                            0x00030237
+#define DDR_PHY_DTCR1_RANKEN_SHIFT                             16
+#define DDR_PHY_DTCR1_RANKEN_MASK                              0x00030000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                    0x00030237
+#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                     14
+#define DDR_PHY_DTCR1_RESERVED_15_14_MASK                      0x0000C000U
+
+/*
+* Data Training Rank
+*/
+#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 
+#undef DDR_PHY_DTCR1_DTRANK_SHIFT 
+#undef DDR_PHY_DTCR1_DTRANK_MASK 
+#define DDR_PHY_DTCR1_DTRANK_DEFVAL                            0x00030237
+#define DDR_PHY_DTCR1_DTRANK_SHIFT                             12
+#define DDR_PHY_DTCR1_DTRANK_MASK                              0x00003000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_11_MASK 
+#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                       0x00030237
+#define DDR_PHY_DTCR1_RESERVED_11_SHIFT                        11
+#define DDR_PHY_DTCR1_RESERVED_11_MASK                         0x00000800U
+
+/*
+* Read Leveling Gate Sampling Difference
+*/
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 
+#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                        0x00030237
+#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                         8
+#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                          0x00000700U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_7_MASK 
+#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                        0x00030237
+#define DDR_PHY_DTCR1_RESERVED_7_SHIFT                         7
+#define DDR_PHY_DTCR1_RESERVED_7_MASK                          0x00000080U
+
+/*
+* Read Leveling Gate Shift
+*/
+#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGS_MASK 
+#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                           0x00030237
+#define DDR_PHY_DTCR1_RDLVLGS_SHIFT                            4
+#define DDR_PHY_DTCR1_RDLVLGS_MASK                             0x00000070U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_3_MASK 
+#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                        0x00030237
+#define DDR_PHY_DTCR1_RESERVED_3_SHIFT                         3
+#define DDR_PHY_DTCR1_RESERVED_3_MASK                          0x00000008U
+
+/*
+* Read Preamble Training enable
+*/
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                       0x00030237
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                        2
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                         0x00000004U
+
+/*
+* Read Leveling Enable
+*/
+#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLEN_MASK 
+#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                           0x00030237
+#define DDR_PHY_DTCR1_RDLVLEN_SHIFT                            1
+#define DDR_PHY_DTCR1_RDLVLEN_MASK                             0x00000002U
+
+/*
+* Basic Gate Training Enable
+*/
+#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 
+#undef DDR_PHY_DTCR1_BSTEN_SHIFT 
+#undef DDR_PHY_DTCR1_BSTEN_MASK 
+#define DDR_PHY_DTCR1_BSTEN_DEFVAL                             0x00030237
+#define DDR_PHY_DTCR1_BSTEN_SHIFT                              0
+#define DDR_PHY_DTCR1_BSTEN_MASK                               0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 
+#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                    0x00141054
+#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                     21
+#define DDR_PHY_CATR0_RESERVED_31_21_MASK                      0xFFE00000U
+
+/*
+* Minimum time (in terms of number of dram clocks) between two consectuve
+    * CA calibration command
+*/
+#undef DDR_PHY_CATR0_CACD_DEFVAL 
+#undef DDR_PHY_CATR0_CACD_SHIFT 
+#undef DDR_PHY_CATR0_CACD_MASK 
+#define DDR_PHY_CATR0_CACD_DEFVAL                              0x00141054
+#define DDR_PHY_CATR0_CACD_SHIFT                               16
+#define DDR_PHY_CATR0_CACD_MASK                                0x001F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 
+#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                    0x00141054
+#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                     13
+#define DDR_PHY_CATR0_RESERVED_15_13_MASK                      0x0000E000U
+
+/*
+* Minimum time (in terms of number of dram clocks) PUB should wait before
+    * sampling the CA response after Calibration command has been sent to the
+    * memory
+*/
+#undef DDR_PHY_CATR0_CAADR_DEFVAL 
+#undef DDR_PHY_CATR0_CAADR_SHIFT 
+#undef DDR_PHY_CATR0_CAADR_MASK 
+#define DDR_PHY_CATR0_CAADR_DEFVAL                             0x00141054
+#define DDR_PHY_CATR0_CAADR_SHIFT                              8
+#define DDR_PHY_CATR0_CAADR_MASK                               0x00001F00U
+
+/*
+* CA_1 Response Byte Lane 1
+*/
+#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE1_MASK 
+#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                          0x00141054
+#define DDR_PHY_CATR0_CA1BYTE1_SHIFT                           4
+#define DDR_PHY_CATR0_CA1BYTE1_MASK                            0x000000F0U
+
+/*
+* CA_1 Response Byte Lane 0
+*/
+#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE0_MASK 
+#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                          0x00141054
+#define DDR_PHY_CATR0_CA1BYTE0_SHIFT                           0
+#define DDR_PHY_CATR0_CA1BYTE0_MASK                            0x0000000FU
+
+/*
+* Number of delay taps by which the DQS gate LCDL will be updated when DQS
+    *  drift is detected
+*/
+#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTDLY_MASK 
+#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL                           0x00088000
+#define DDR_PHY_DQSDR0_DFTDLY_SHIFT                            28
+#define DDR_PHY_DQSDR0_DFTDLY_MASK                             0xF0000000U
+
+/*
+* Drift Impedance Update
+*/
+#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTZQUP_MASK 
+#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL                          0x00088000
+#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT                           27
+#define DDR_PHY_DQSDR0_DFTZQUP_MASK                            0x08000000U
+
+/*
+* Drift DDL Update
+*/
+#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK 
+#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL                         0x00088000
+#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT                          26
+#define DDR_PHY_DQSDR0_DFTDDLUP_MASK                           0x04000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 
+#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK 
+#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL                   0x00088000
+#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT                    22
+#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK                     0x03C00000U
+
+/*
+* Drift Read Spacing
+*/
+#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK 
+#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL                         0x00088000
+#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT                          20
+#define DDR_PHY_DQSDR0_DFTRDSPC_MASK                           0x00300000U
+
+/*
+* Drift Back-to-Back Reads
+*/
+#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK 
+#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL                         0x00088000
+#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT                          16
+#define DDR_PHY_DQSDR0_DFTB2BRD_MASK                           0x000F0000U
+
+/*
+* Drift Idle Reads
+*/
+#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK 
+#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL                         0x00088000
+#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT                          12
+#define DDR_PHY_DQSDR0_DFTIDLRD_MASK                           0x0000F000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 
+#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK 
+#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL                    0x00088000
+#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT                     8
+#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK                      0x00000F00U
+
+/*
+* Gate Pulse Enable
+*/
+#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK 
+#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL                        0x00088000
+#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT                         4
+#define DDR_PHY_DQSDR0_DFTGPULSE_MASK                          0x000000F0U
+
+/*
+* DQS Drift Update Mode
+*/
+#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK 
+#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL                        0x00088000
+#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT                         2
+#define DDR_PHY_DQSDR0_DFTUPMODE_MASK                          0x0000000CU
+
+/*
+* DQS Drift Detection Mode
+*/
+#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK 
+#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL                        0x00088000
+#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT                         1
+#define DDR_PHY_DQSDR0_DFTDTMODE_MASK                          0x00000002U
+
+/*
+* DQS Drift Detection Enable
+*/
+#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 
+#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT 
+#undef DDR_PHY_DQSDR0_DFTDTEN_MASK 
+#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL                          0x00088000
+#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT                           0
+#define DDR_PHY_DQSDR0_DFTDTEN_MASK                            0x00000001U
+
+/*
+* LFSR seed for pseudo-random BIST patterns
+*/
+#undef DDR_PHY_BISTLSR_SEED_DEFVAL 
+#undef DDR_PHY_BISTLSR_SEED_SHIFT 
+#undef DDR_PHY_BISTLSR_SEED_MASK 
+#define DDR_PHY_BISTLSR_SEED_DEFVAL                            
+#define DDR_PHY_BISTLSR_SEED_SHIFT                             0
+#define DDR_PHY_BISTLSR_SEED_MASK                              0xFFFFFFFFU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 
+#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                   0x00000005
+#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                    16
+#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                     0xFFFF0000U
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                   0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                    4
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                     0x0000FFF0U
+
+/*
+* SDRAM On-die Termination Output Enable (OE) Mode Selection.
+*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                        0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                         0
+#define DDR_PHY_RIOCR5_ODTOEMODE_MASK                          0x0000000FU
+
+/*
+* Address/Command Slew Rate (D3F I/O Only)
+*/
+#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACSR_MASK 
+#define DDR_PHY_ACIOCR0_ACSR_DEFVAL                            0x30000000
+#define DDR_PHY_ACIOCR0_ACSR_SHIFT                             30
+#define DDR_PHY_ACIOCR0_ACSR_MASK                              0xC0000000U
+
+/*
+* SDRAM Reset I/O Mode
+*/
+#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 
+#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                          0x30000000
+#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                           29
+#define DDR_PHY_ACIOCR0_RSTIOM_MASK                            0x20000000U
+
+/*
+* SDRAM Reset Power Down Receiver
+*/
+#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 
+#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                          0x30000000
+#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                           28
+#define DDR_PHY_ACIOCR0_RSTPDR_MASK                            0x10000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                     0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                      27
+#define DDR_PHY_ACIOCR0_RESERVED_27_MASK                       0x08000000U
+
+/*
+* SDRAM Reset On-Die Termination
+*/
+#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTODT_MASK 
+#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                          0x30000000
+#define DDR_PHY_ACIOCR0_RSTODT_SHIFT                           26
+#define DDR_PHY_ACIOCR0_RSTODT_MASK                            0x04000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                  0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                   10
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                    0x03FFFC00U
+
+/*
+* CK Duty Cycle Correction
+*/
+#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 
+#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 
+#undef DDR_PHY_ACIOCR0_CKDCC_MASK 
+#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                           0x30000000
+#define DDR_PHY_ACIOCR0_CKDCC_SHIFT                            6
+#define DDR_PHY_ACIOCR0_CKDCC_MASK                             0x000003C0U
+
+/*
+* AC Power Down Receiver Mode
+*/
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                       0x30000000
+#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                        4
+#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                         0x00000030U
+
+/*
+* AC On-die Termination Mode
+*/
+#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                       0x30000000
+#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                        2
+#define DDR_PHY_ACIOCR0_ACODTMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                      0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                       1
+#define DDR_PHY_ACIOCR0_RESERVED_1_MASK                        0x00000002U
+
+/*
+* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
+*/
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                    0x30000000
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                     0
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                      0x00000001U
+
+/*
+* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL
+    * slice
+*/
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                   0x00000000
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                    31
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                     0x80000000U
+
+/*
+* Clock gating for Output Enable D slices [0]
+*/
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                    0x00000000
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                     30
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                      0x40000000U
+
+/*
+* Clock gating for Power Down Receiver D slices [0]
+*/
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                   0x00000000
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                    29
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                     0x20000000U
+
+/*
+* Clock gating for Termination Enable D slices [0]
+*/
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                    0x00000000
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                     28
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                      0x10000000U
+
+/*
+* Clock gating for CK# D slices [1:0]
+*/
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                     0x00000000
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                      26
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                       0x0C000000U
+
+/*
+* Clock gating for CK D slices [1:0]
+*/
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                      0x00000000
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                       24
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                        0x03000000U
+
+/*
+* Clock gating for AC D slices [23:0]
+*/
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                      0x00000000
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                       0
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                        0x00FFFFFFU
+
+/*
+* SDRAM Parity Output Enable (OE) Mode Selection
+*/
+#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 
+#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                       0x00000005
+#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                        30
+#define DDR_PHY_ACIOCR3_PAROEMODE_MASK                         0xC0000000U
+
+/*
+* SDRAM Bank Group Output Enable (OE) Mode Selection
+*/
+#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                        0x00000005
+#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                         26
+#define DDR_PHY_ACIOCR3_BGOEMODE_MASK                          0x3C000000U
+
+/*
+* SDRAM Bank Address Output Enable (OE) Mode Selection
+*/
+#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                        0x00000005
+#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                         22
+#define DDR_PHY_ACIOCR3_BAOEMODE_MASK                          0x03C00000U
+
+/*
+* SDRAM A[17] Output Enable (OE) Mode Selection
+*/
+#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                       0x00000005
+#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                        20
+#define DDR_PHY_ACIOCR3_A17OEMODE_MASK                         0x00300000U
+
+/*
+* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
+*/
+#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                       0x00000005
+#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                        18
+#define DDR_PHY_ACIOCR3_A16OEMODE_MASK                         0x000C0000U
+
+/*
+* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
+*/
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                       0x00000005
+#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                        16
+#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                         0x00030000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                   0x00000005
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                    8
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                     0x0000FF00U
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                   0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                    4
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                     0x000000F0U
+
+/*
+* SDRAM CK Output Enable (OE) Mode Selection.
+*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                        0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                         0
+#define DDR_PHY_ACIOCR3_CKOEMODE_MASK                          0x0000000FU
+
+/*
+* Clock gating for AC LB slices and loopback read valid slices
+*/
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 
+#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                       0x00000000
+#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                        31
+#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                         0x80000000U
+
+/*
+* Clock gating for Output Enable D slices [1]
+*/
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                    0x00000000
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                     30
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                      0x40000000U
+
+/*
+* Clock gating for Power Down Receiver D slices [1]
+*/
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                   0x00000000
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                    29
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                     0x20000000U
+
+/*
+* Clock gating for Termination Enable D slices [1]
+*/
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                    0x00000000
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                     28
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                      0x10000000U
+
+/*
+* Clock gating for CK# D slices [3:2]
+*/
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                     0x00000000
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                      26
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                       0x0C000000U
+
+/*
+* Clock gating for CK D slices [3:2]
+*/
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                      0x00000000
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                       24
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                        0x03000000U
+
+/*
+* Clock gating for AC D slices [47:24]
+*/
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                      0x00000000
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                       0
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                        0x00FFFFFFU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 
+#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                   0x0F000000
+#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                    29
+#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                     0xE0000000U
+
+/*
+* Address/command lane VREF Pad Enable
+*/
+#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                         0x0F000000
+#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                          28
+#define DDR_PHY_IOVCR0_ACREFPEN_MASK                           0x10000000U
+
+/*
+* Address/command lane Internal VREF Enable
+*/
+#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                         0x0F000000
+#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                          26
+#define DDR_PHY_IOVCR0_ACREFEEN_MASK                           0x0C000000U
+
+/*
+* Address/command lane Single-End VREF Enable
+*/
+#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                         0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                          25
+#define DDR_PHY_IOVCR0_ACREFSEN_MASK                           0x02000000U
+
+/*
+* Address/command lane Internal VREF Enable
+*/
+#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                         0x0F000000
+#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                          24
+#define DDR_PHY_IOVCR0_ACREFIEN_MASK                           0x01000000U
+
+/*
+* External VREF generato REFSEL range select
+*/
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                   0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                    23
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                     0x00800000U
+
+/*
+* Address/command lane External VREF Select
+*/
+#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                        0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                         16
+#define DDR_PHY_IOVCR0_ACREFESEL_MASK                          0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                   0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                    15
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                     0x00008000U
+
+/*
+* Address/command lane Single-End VREF Select
+*/
+#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                        0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                         8
+#define DDR_PHY_IOVCR0_ACREFSSEL_MASK                          0x00007F00U
+
+/*
+* Internal VREF generator REFSEL ragne select
+*/
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                  0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                   7
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                    0x00000080U
+
+/*
+* REFSEL Control for internal AC IOs
+*/
+#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                       0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                        0
+#define DDR_PHY_IOVCR0_ACVREFISEL_MASK                         0x0000007FU
+
+/*
+* Number of ctl_clk required to meet (> 150ns) timing requirements during
+    * DRAM DQ VREF training
+*/
+#undef DDR_PHY_VTCR0_TVREF_DEFVAL 
+#undef DDR_PHY_VTCR0_TVREF_SHIFT 
+#undef DDR_PHY_VTCR0_TVREF_MASK 
+#define DDR_PHY_VTCR0_TVREF_DEFVAL                             0x70032019
+#define DDR_PHY_VTCR0_TVREF_SHIFT                              29
+#define DDR_PHY_VTCR0_TVREF_MASK                               0xE0000000U
+
+/*
+* DRM DQ VREF training Enable
+*/
+#undef DDR_PHY_VTCR0_DVEN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVEN_SHIFT 
+#undef DDR_PHY_VTCR0_DVEN_MASK 
+#define DDR_PHY_VTCR0_DVEN_DEFVAL                              0x70032019
+#define DDR_PHY_VTCR0_DVEN_SHIFT                               28
+#define DDR_PHY_VTCR0_DVEN_MASK                                0x10000000U
+
+/*
+* Per Device Addressability Enable
+*/
+#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 
+#undef DDR_PHY_VTCR0_PDAEN_SHIFT 
+#undef DDR_PHY_VTCR0_PDAEN_MASK 
+#define DDR_PHY_VTCR0_PDAEN_DEFVAL                             0x70032019
+#define DDR_PHY_VTCR0_PDAEN_SHIFT                              27
+#define DDR_PHY_VTCR0_PDAEN_MASK                               0x08000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 
+#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 
+#undef DDR_PHY_VTCR0_RESERVED_26_MASK 
+#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                       0x70032019
+#define DDR_PHY_VTCR0_RESERVED_26_SHIFT                        26
+#define DDR_PHY_VTCR0_RESERVED_26_MASK                         0x04000000U
+
+/*
+* VREF Word Count
+*/
+#undef DDR_PHY_VTCR0_VWCR_DEFVAL 
+#undef DDR_PHY_VTCR0_VWCR_SHIFT 
+#undef DDR_PHY_VTCR0_VWCR_MASK 
+#define DDR_PHY_VTCR0_VWCR_DEFVAL                              0x70032019
+#define DDR_PHY_VTCR0_VWCR_SHIFT                               22
+#define DDR_PHY_VTCR0_VWCR_MASK                                0x03C00000U
+
+/*
+* DRAM DQ VREF step size used during DRAM VREF training
+*/
+#undef DDR_PHY_VTCR0_DVSS_DEFVAL 
+#undef DDR_PHY_VTCR0_DVSS_SHIFT 
+#undef DDR_PHY_VTCR0_DVSS_MASK 
+#define DDR_PHY_VTCR0_DVSS_DEFVAL                              0x70032019
+#define DDR_PHY_VTCR0_DVSS_SHIFT                               18
+#define DDR_PHY_VTCR0_DVSS_MASK                                0x003C0000U
+
+/*
+* Maximum VREF limit value used during DRAM VREF training
+*/
+#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMAX_SHIFT 
+#undef DDR_PHY_VTCR0_DVMAX_MASK 
+#define DDR_PHY_VTCR0_DVMAX_DEFVAL                             0x70032019
+#define DDR_PHY_VTCR0_DVMAX_SHIFT                              12
+#define DDR_PHY_VTCR0_DVMAX_MASK                               0x0003F000U
+
+/*
+* Minimum VREF limit value used during DRAM VREF training
+*/
+#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMIN_SHIFT 
+#undef DDR_PHY_VTCR0_DVMIN_MASK 
+#define DDR_PHY_VTCR0_DVMIN_DEFVAL                             0x70032019
+#define DDR_PHY_VTCR0_DVMIN_SHIFT                              6
+#define DDR_PHY_VTCR0_DVMIN_MASK                               0x00000FC0U
+
+/*
+* Initial DRAM DQ VREF value used during DRAM VREF training
+*/
+#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 
+#undef DDR_PHY_VTCR0_DVINIT_SHIFT 
+#undef DDR_PHY_VTCR0_DVINIT_MASK 
+#define DDR_PHY_VTCR0_DVINIT_DEFVAL                            0x70032019
+#define DDR_PHY_VTCR0_DVINIT_SHIFT                             0
+#define DDR_PHY_VTCR0_DVINIT_MASK                              0x0000003FU
+
+/*
+* Host VREF step size used during VREF training. The register value of N i
+    * ndicates step size of (N+1)
+*/
+#undef DDR_PHY_VTCR1_HVSS_DEFVAL 
+#undef DDR_PHY_VTCR1_HVSS_SHIFT 
+#undef DDR_PHY_VTCR1_HVSS_MASK 
+#define DDR_PHY_VTCR1_HVSS_DEFVAL                              0x07F00072
+#define DDR_PHY_VTCR1_HVSS_SHIFT                               28
+#define DDR_PHY_VTCR1_HVSS_MASK                                0xF0000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_27_MASK 
+#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                       0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_27_SHIFT                        27
+#define DDR_PHY_VTCR1_RESERVED_27_MASK                         0x08000000U
+
+/*
+* Maximum VREF limit value used during DRAM VREF training.
+*/
+#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMAX_SHIFT 
+#undef DDR_PHY_VTCR1_HVMAX_MASK 
+#define DDR_PHY_VTCR1_HVMAX_DEFVAL                             0x07F00072
+#define DDR_PHY_VTCR1_HVMAX_SHIFT                              20
+#define DDR_PHY_VTCR1_HVMAX_MASK                               0x07F00000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_19_MASK 
+#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                       0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_19_SHIFT                        19
+#define DDR_PHY_VTCR1_RESERVED_19_MASK                         0x00080000U
+
+/*
+* Minimum VREF limit value used during DRAM VREF training.
+*/
+#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMIN_SHIFT 
+#undef DDR_PHY_VTCR1_HVMIN_MASK 
+#define DDR_PHY_VTCR1_HVMIN_DEFVAL                             0x07F00072
+#define DDR_PHY_VTCR1_HVMIN_SHIFT                              12
+#define DDR_PHY_VTCR1_HVMIN_MASK                               0x0007F000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_11_MASK 
+#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                       0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_11_SHIFT                        11
+#define DDR_PHY_VTCR1_RESERVED_11_MASK                         0x00000800U
+
+/*
+* Static Host Vref Rank Value
+*/
+#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 
+#undef DDR_PHY_VTCR1_SHRNK_SHIFT 
+#undef DDR_PHY_VTCR1_SHRNK_MASK 
+#define DDR_PHY_VTCR1_SHRNK_DEFVAL                             0x07F00072
+#define DDR_PHY_VTCR1_SHRNK_SHIFT                              9
+#define DDR_PHY_VTCR1_SHRNK_MASK                               0x00000600U
+
+/*
+* Static Host Vref Rank Enable
+*/
+#undef DDR_PHY_VTCR1_SHREN_DEFVAL 
+#undef DDR_PHY_VTCR1_SHREN_SHIFT 
+#undef DDR_PHY_VTCR1_SHREN_MASK 
+#define DDR_PHY_VTCR1_SHREN_DEFVAL                             0x07F00072
+#define DDR_PHY_VTCR1_SHREN_SHIFT                              8
+#define DDR_PHY_VTCR1_SHREN_MASK                               0x00000100U
+
+/*
+* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir
+    * ements during Host IO VREF training
+*/
+#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 
+#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 
+#undef DDR_PHY_VTCR1_TVREFIO_MASK 
+#define DDR_PHY_VTCR1_TVREFIO_DEFVAL                           0x07F00072
+#define DDR_PHY_VTCR1_TVREFIO_SHIFT                            5
+#define DDR_PHY_VTCR1_TVREFIO_MASK                             0x000000E0U
+
+/*
+* Eye LCDL Offset value for VREF training
+*/
+#undef DDR_PHY_VTCR1_EOFF_DEFVAL 
+#undef DDR_PHY_VTCR1_EOFF_SHIFT 
+#undef DDR_PHY_VTCR1_EOFF_MASK 
+#define DDR_PHY_VTCR1_EOFF_DEFVAL                              0x07F00072
+#define DDR_PHY_VTCR1_EOFF_SHIFT                               3
+#define DDR_PHY_VTCR1_EOFF_MASK                                0x00000018U
+
+/*
+* Number of LCDL Eye points for which VREF training is repeated
+*/
+#undef DDR_PHY_VTCR1_ENUM_DEFVAL 
+#undef DDR_PHY_VTCR1_ENUM_SHIFT 
+#undef DDR_PHY_VTCR1_ENUM_MASK 
+#define DDR_PHY_VTCR1_ENUM_DEFVAL                              0x07F00072
+#define DDR_PHY_VTCR1_ENUM_SHIFT                               2
+#define DDR_PHY_VTCR1_ENUM_MASK                                0x00000004U
+
+/*
+* HOST (IO) internal VREF training Enable
+*/
+#undef DDR_PHY_VTCR1_HVEN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVEN_SHIFT 
+#undef DDR_PHY_VTCR1_HVEN_MASK 
+#define DDR_PHY_VTCR1_HVEN_DEFVAL                              0x07F00072
+#define DDR_PHY_VTCR1_HVEN_SHIFT                               1
+#define DDR_PHY_VTCR1_HVEN_MASK                                0x00000002U
+
+/*
+* Host IO Type Control
+*/
+#undef DDR_PHY_VTCR1_HVIO_DEFVAL 
+#undef DDR_PHY_VTCR1_HVIO_SHIFT 
+#undef DDR_PHY_VTCR1_HVIO_MASK 
+#define DDR_PHY_VTCR1_HVIO_DEFVAL                              0x07F00072
+#define DDR_PHY_VTCR1_HVIO_SHIFT                               0
+#define DDR_PHY_VTCR1_HVIO_MASK                                0x00000001U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on Parity.
+*/
+#undef DDR_PHY_ACBDLR1_PARBD_DEFVAL 
+#undef DDR_PHY_ACBDLR1_PARBD_SHIFT 
+#undef DDR_PHY_ACBDLR1_PARBD_MASK 
+#define DDR_PHY_ACBDLR1_PARBD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR1_PARBD_SHIFT                            24
+#define DDR_PHY_ACBDLR1_PARBD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn
+    * ected to WE.
+*/
+#undef DDR_PHY_ACBDLR1_A16BD_DEFVAL 
+#undef DDR_PHY_ACBDLR1_A16BD_SHIFT 
+#undef DDR_PHY_ACBDLR1_A16BD_MASK 
+#define DDR_PHY_ACBDLR1_A16BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR1_A16BD_SHIFT                            16
+#define DDR_PHY_ACBDLR1_A16BD_MASK                             0x003F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi
+    * s pin is connected to CAS.
+*/
+#undef DDR_PHY_ACBDLR1_A17BD_DEFVAL 
+#undef DDR_PHY_ACBDLR1_A17BD_SHIFT 
+#undef DDR_PHY_ACBDLR1_A17BD_MASK 
+#define DDR_PHY_ACBDLR1_A17BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR1_A17BD_SHIFT                            8
+#define DDR_PHY_ACBDLR1_A17BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on ACTN.
+*/
+#undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL 
+#undef DDR_PHY_ACBDLR1_ACTBD_SHIFT 
+#undef DDR_PHY_ACBDLR1_ACTBD_MASK 
+#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR1_ACTBD_SHIFT                            0
+#define DDR_PHY_ACBDLR1_ACTBD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on BG[1].
+*/
+#undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL 
+#undef DDR_PHY_ACBDLR2_BG1BD_SHIFT 
+#undef DDR_PHY_ACBDLR2_BG1BD_MASK 
+#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR2_BG1BD_SHIFT                            24
+#define DDR_PHY_ACBDLR2_BG1BD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on BG[0].
+*/
+#undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL 
+#undef DDR_PHY_ACBDLR2_BG0BD_SHIFT 
+#undef DDR_PHY_ACBDLR2_BG0BD_MASK 
+#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR2_BG0BD_SHIFT                            16
+#define DDR_PHY_ACBDLR2_BG0BD_MASK                             0x003F0000U
+
+/*
+* Reser.ved Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on BA[1].
+*/
+#undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL 
+#undef DDR_PHY_ACBDLR2_BA1BD_SHIFT 
+#undef DDR_PHY_ACBDLR2_BA1BD_MASK 
+#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR2_BA1BD_SHIFT                            8
+#define DDR_PHY_ACBDLR2_BA1BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on BA[0].
+*/
+#undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL 
+#undef DDR_PHY_ACBDLR2_BA0BD_SHIFT 
+#undef DDR_PHY_ACBDLR2_BA0BD_MASK 
+#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR2_BA0BD_SHIFT                            0
+#define DDR_PHY_ACBDLR2_BA0BD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on Address A[3].
+*/
+#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A03BD_MASK 
+#define DDR_PHY_ACBDLR6_A03BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR6_A03BD_SHIFT                            24
+#define DDR_PHY_ACBDLR6_A03BD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on Address A[2].
+*/
+#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A02BD_MASK 
+#define DDR_PHY_ACBDLR6_A02BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR6_A02BD_SHIFT                            16
+#define DDR_PHY_ACBDLR6_A02BD_MASK                             0x003F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on Address A[1].
+*/
+#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A01BD_MASK 
+#define DDR_PHY_ACBDLR6_A01BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR6_A01BD_SHIFT                            8
+#define DDR_PHY_ACBDLR6_A01BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on Address A[0].
+*/
+#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A00BD_MASK 
+#define DDR_PHY_ACBDLR6_A00BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR6_A00BD_SHIFT                            0
+#define DDR_PHY_ACBDLR6_A00BD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on Address A[7].
+*/
+#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A07BD_MASK 
+#define DDR_PHY_ACBDLR7_A07BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR7_A07BD_SHIFT                            24
+#define DDR_PHY_ACBDLR7_A07BD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on Address A[6].
+*/
+#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A06BD_MASK 
+#define DDR_PHY_ACBDLR7_A06BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR7_A06BD_SHIFT                            16
+#define DDR_PHY_ACBDLR7_A06BD_MASK                             0x003F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on Address A[5].
+*/
+#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A05BD_MASK 
+#define DDR_PHY_ACBDLR7_A05BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR7_A05BD_SHIFT                            8
+#define DDR_PHY_ACBDLR7_A05BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on Address A[4].
+*/
+#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A04BD_MASK 
+#define DDR_PHY_ACBDLR7_A04BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR7_A04BD_SHIFT                            0
+#define DDR_PHY_ACBDLR7_A04BD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on Address A[11].
+*/
+#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A11BD_MASK 
+#define DDR_PHY_ACBDLR8_A11BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR8_A11BD_SHIFT                            24
+#define DDR_PHY_ACBDLR8_A11BD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on Address A[10].
+*/
+#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A10BD_MASK 
+#define DDR_PHY_ACBDLR8_A10BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR8_A10BD_SHIFT                            16
+#define DDR_PHY_ACBDLR8_A10BD_MASK                             0x003F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on Address A[9].
+*/
+#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A09BD_MASK 
+#define DDR_PHY_ACBDLR8_A09BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR8_A09BD_SHIFT                            8
+#define DDR_PHY_ACBDLR8_A09BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on Address A[8].
+*/
+#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A08BD_MASK 
+#define DDR_PHY_ACBDLR8_A08BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR8_A08BD_SHIFT                            0
+#define DDR_PHY_ACBDLR8_A08BD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Delay select for the BDL on Address A[15].
+*/
+#undef DDR_PHY_ACBDLR9_A15BD_DEFVAL 
+#undef DDR_PHY_ACBDLR9_A15BD_SHIFT 
+#undef DDR_PHY_ACBDLR9_A15BD_MASK 
+#define DDR_PHY_ACBDLR9_A15BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR9_A15BD_SHIFT                            24
+#define DDR_PHY_ACBDLR9_A15BD_MASK                             0x3F000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Delay select for the BDL on Address A[14].
+*/
+#undef DDR_PHY_ACBDLR9_A14BD_DEFVAL 
+#undef DDR_PHY_ACBDLR9_A14BD_SHIFT 
+#undef DDR_PHY_ACBDLR9_A14BD_MASK 
+#define DDR_PHY_ACBDLR9_A14BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR9_A14BD_SHIFT                            16
+#define DDR_PHY_ACBDLR9_A14BD_MASK                             0x003F0000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL                  0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* Delay select for the BDL on Address A[13].
+*/
+#undef DDR_PHY_ACBDLR9_A13BD_DEFVAL 
+#undef DDR_PHY_ACBDLR9_A13BD_SHIFT 
+#undef DDR_PHY_ACBDLR9_A13BD_MASK 
+#define DDR_PHY_ACBDLR9_A13BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR9_A13BD_SHIFT                            8
+#define DDR_PHY_ACBDLR9_A13BD_MASK                             0x00003F00U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL                    0x00000000
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* Delay select for the BDL on Address A[12].
+*/
+#undef DDR_PHY_ACBDLR9_A12BD_DEFVAL 
+#undef DDR_PHY_ACBDLR9_A12BD_SHIFT 
+#undef DDR_PHY_ACBDLR9_A12BD_MASK 
+#define DDR_PHY_ACBDLR9_A12BD_DEFVAL                           0x00000000
+#define DDR_PHY_ACBDLR9_A12BD_SHIFT                            0
+#define DDR_PHY_ACBDLR9_A12BD_MASK                             0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                     0x008A2858
+#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                      26
+#define DDR_PHY_ZQCR_RESERVED_31_26_MASK                       0xFC000000U
+
+/*
+* ZQ VREF Range
+*/
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                     0x008A2858
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                      25
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                       0x02000000U
+
+/*
+* Programmable Wait for Frequency B
+*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                        0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                         19
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                          0x01F80000U
+
+/*
+* Programmable Wait for Frequency A
+*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                        0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                         13
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                          0x0007E000U
+
+/*
+* ZQ VREF Pad Enable
+*/
+#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                           0x008A2858
+#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                            12
+#define DDR_PHY_ZQCR_ZQREFPEN_MASK                             0x00001000U
+
+/*
+* ZQ Internal VREF Enable
+*/
+#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                           0x008A2858
+#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                            11
+#define DDR_PHY_ZQCR_ZQREFIEN_MASK                             0x00000800U
+
+/*
+* Choice of termination mode
+*/
+#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 
+#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 
+#undef DDR_PHY_ZQCR_ODT_MODE_MASK 
+#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                           0x008A2858
+#define DDR_PHY_ZQCR_ODT_MODE_SHIFT                            9
+#define DDR_PHY_ZQCR_ODT_MODE_MASK                             0x00000600U
+
+/*
+* Force ZCAL VT update
+*/
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL               0x008A2858
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                8
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                 0x00000100U
+
+/*
+* IO VT Drift Limit
+*/
+#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 
+#undef DDR_PHY_ZQCR_IODLMT_SHIFT 
+#undef DDR_PHY_ZQCR_IODLMT_MASK 
+#define DDR_PHY_ZQCR_IODLMT_DEFVAL                             0x008A2858
+#define DDR_PHY_ZQCR_IODLMT_SHIFT                              5
+#define DDR_PHY_ZQCR_IODLMT_MASK                               0x000000E0U
+
+/*
+* Averaging algorithm enable, if set, enables averaging algorithm
+*/
+#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGEN_SHIFT 
+#undef DDR_PHY_ZQCR_AVGEN_MASK 
+#define DDR_PHY_ZQCR_AVGEN_DEFVAL                              0x008A2858
+#define DDR_PHY_ZQCR_AVGEN_SHIFT                               4
+#define DDR_PHY_ZQCR_AVGEN_MASK                                0x00000010U
+
+/*
+* Maximum number of averaging rounds to be used by averaging algorithm
+*/
+#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 
+#undef DDR_PHY_ZQCR_AVGMAX_MASK 
+#define DDR_PHY_ZQCR_AVGMAX_DEFVAL                             0x008A2858
+#define DDR_PHY_ZQCR_AVGMAX_SHIFT                              2
+#define DDR_PHY_ZQCR_AVGMAX_MASK                               0x0000000CU
+
+/*
+* ZQ Calibration Type
+*/
+#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 
+#undef DDR_PHY_ZQCR_ZCALT_SHIFT 
+#undef DDR_PHY_ZQCR_ZCALT_MASK 
+#define DDR_PHY_ZQCR_ZCALT_DEFVAL                              0x008A2858
+#define DDR_PHY_ZQCR_ZCALT_SHIFT                               1
+#define DDR_PHY_ZQCR_ZCALT_MASK                                0x00000002U
+
+/*
+* ZQ Power Down
+*/
+#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQPD_SHIFT 
+#undef DDR_PHY_ZQCR_ZQPD_MASK 
+#define DDR_PHY_ZQCR_ZQPD_DEFVAL                               0x008A2858
+#define DDR_PHY_ZQCR_ZQPD_SHIFT                                0
+#define DDR_PHY_ZQCR_ZQPD_MASK                                 0x00000001U
+
+/*
+* Pull-down drive strength ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                       31
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                        0x80000000U
+
+/*
+* Pull-up drive strength ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                       30
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                        0x40000000U
+
+/*
+* Pull-down termination ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                       29
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                        0x20000000U
+
+/*
+* Pull-up termination ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                       28
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                        0x10000000U
+
+/*
+* Calibration segment bypass
+*/
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                          0x000077BB
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                           27
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                            0x08000000U
+
+/*
+* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
+    *  is driven by the PUB
+*/
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                         0x000077BB
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                          25
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                           0x06000000U
+
+/*
+* Termination adjustment
+*/
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                       0x000077BB
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                        22
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                         0x01C00000U
+
+/*
+* Pulldown drive strength adjustment
+*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                     19
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                      0x00380000U
+
+/*
+* Pullup drive strength adjustment
+*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                     16
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                      0x00070000U
+
+/*
+* DRAM Impedance Divide Ratio
+*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                    12
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U
+
+/*
+* HOST Impedance Divide Ratio
+*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                    8
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U
+
+/*
+* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
+    * ve strength calibration)
+*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U
+
+/*
+* Impedance Divide Ratio (pullup drive calibration during asymmetric drive
+    *  strength calibration)
+*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                   0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                    26
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                     0xFC000000U
+
+/*
+* Override value for the pull-up output impedance
+*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                 16
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                  0x03FF0000U
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                   0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                    10
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                     0x0000FC00U
+
+/*
+* Override value for the pull-down output impedance
+*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                 0
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                  0x000003FFU
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                   0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                    26
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                     0xFC000000U
+
+/*
+* Override value for the pull-up termination
+*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                 16
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                  0x03FF0000U
+
+/*
+* Reserved. Return zeros on reads.
+*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                   0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                    10
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                     0x0000FC00U
+
+/*
+* Override value for the pull-down termination
+*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                 0
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                  0x000003FFU
+
+/*
+* Pull-down drive strength ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                       31
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                        0x80000000U
+
+/*
+* Pull-up drive strength ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                       30
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                        0x40000000U
+
+/*
+* Pull-down termination ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                       29
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                        0x20000000U
+
+/*
+* Pull-up termination ZCTRL over-ride enable
+*/
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                      0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                       28
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                        0x10000000U
+
+/*
+* Calibration segment bypass
+*/
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                          0x000077BB
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                           27
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                            0x08000000U
+
+/*
+* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell
+    *  is driven by the PUB
+*/
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                         0x000077BB
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                          25
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                           0x06000000U
+
+/*
+* Termination adjustment
+*/
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                       0x000077BB
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                        22
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                         0x01C00000U
+
+/*
+* Pulldown drive strength adjustment
+*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                    0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                     19
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                      0x00380000U
+
+/*
+* Pullup drive strength adjustment
+*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                    0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                     16
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                      0x00070000U
+
+/*
+* DRAM Impedance Divide Ratio
+*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                   0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                    12
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                     0x0000F000U
+
+/*
+* HOST Impedance Divide Ratio
+*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                   0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                    8
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                     0x00000F00U
+
+/*
+* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri
+    * ve strength calibration)
+*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                 4
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                  0x000000F0U
+
+/*
+* Impedance Divide Ratio (pullup drive calibration during asymmetric drive
+    *  strength calibration)
+*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                 0
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                  0x0000000FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX0GCR0_CALBYP_MASK 
+#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX0GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX0GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX0GCR0_MDLEN_MASK 
+#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX0GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX0GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX0GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX0GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX0GCR0_RDDLY_MASK 
+#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX0GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX0GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX0GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOH_MASK 
+#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX0GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX0GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX0GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX0GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX0GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX0GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX0GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX0GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX0GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX0GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX0GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX0GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX0GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX0GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX0GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX0GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX0GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX0GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX0GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX0GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX0GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX0GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX0GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX0GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX0GCR1_QSSEL_MASK 
+#define DDR_PHY_DX0GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX0GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX0GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX0GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX0GCR1_OEEN_MASK 
+#define DDR_PHY_DX0GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX0GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX0GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX0GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX0GCR1_PDREN_MASK 
+#define DDR_PHY_DX0GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX0GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX0GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX0GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX0GCR1_TEEN_MASK 
+#define DDR_PHY_DX0GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX0GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX0GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX0GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX0GCR1_DSEN_MASK 
+#define DDR_PHY_DX0GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX0GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX0GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX0GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX0GCR1_DMEN_MASK 
+#define DDR_PHY_DX0GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX0GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX0GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX0GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX0GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX0GCR1_DQEN_MASK 
+#define DDR_PHY_DX0GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX0GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX0GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX0GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX0GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX0GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX0GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_RDBVT_MASK 
+#define DDR_PHY_DX0GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX0GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_WDBVT_MASK 
+#define DDR_PHY_DX0GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX0GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_RGLVT_MASK 
+#define DDR_PHY_DX0GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX0GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_RDLVT_MASK 
+#define DDR_PHY_DX0GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX0GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_WDLVT_MASK 
+#define DDR_PHY_DX0GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX0GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX0GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX0GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX0GCR3_WLLVT_MASK 
+#define DDR_PHY_DX0GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX0GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX0GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX0GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX0GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX0GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX0GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX0GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX0GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX0GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX0GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX0GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX0GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX0GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX0GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX0GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX0GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX0GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX0GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX0GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX0GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX0GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX0GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX0GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX0GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX0GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX0GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX0GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX0GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX0GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX0GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX0GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX0GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX0GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX0GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX0GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX0GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX0GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX0GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX0GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX0GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX0GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX0GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX0GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX0GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX0GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX0GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX1GCR0_CALBYP_MASK 
+#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX1GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX1GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX1GCR0_MDLEN_MASK 
+#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX1GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX1GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX1GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX1GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX1GCR0_RDDLY_MASK 
+#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX1GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX1GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX1GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOH_MASK 
+#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX1GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX1GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX1GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX1GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX1GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX1GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX1GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX1GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX1GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX1GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX1GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX1GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX1GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX1GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX1GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX1GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX1GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX1GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX1GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX1GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX1GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX1GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX1GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX1GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX1GCR1_QSSEL_MASK 
+#define DDR_PHY_DX1GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX1GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX1GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX1GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX1GCR1_OEEN_MASK 
+#define DDR_PHY_DX1GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX1GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX1GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX1GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX1GCR1_PDREN_MASK 
+#define DDR_PHY_DX1GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX1GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX1GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX1GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX1GCR1_TEEN_MASK 
+#define DDR_PHY_DX1GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX1GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX1GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX1GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX1GCR1_DSEN_MASK 
+#define DDR_PHY_DX1GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX1GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX1GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX1GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX1GCR1_DMEN_MASK 
+#define DDR_PHY_DX1GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX1GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX1GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX1GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX1GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX1GCR1_DQEN_MASK 
+#define DDR_PHY_DX1GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX1GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX1GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX1GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX1GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX1GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX1GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_RDBVT_MASK 
+#define DDR_PHY_DX1GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX1GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_WDBVT_MASK 
+#define DDR_PHY_DX1GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX1GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_RGLVT_MASK 
+#define DDR_PHY_DX1GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX1GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_RDLVT_MASK 
+#define DDR_PHY_DX1GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX1GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_WDLVT_MASK 
+#define DDR_PHY_DX1GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX1GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX1GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX1GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX1GCR3_WLLVT_MASK 
+#define DDR_PHY_DX1GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX1GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX1GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX1GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX1GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX1GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX1GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX1GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX1GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX1GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX1GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX1GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX1GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX1GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX1GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX1GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX1GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX1GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX1GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX1GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX1GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX1GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX1GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX1GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX1GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX1GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX1GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX1GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX1GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX1GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX1GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX1GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX1GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX1GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX1GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX1GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX1GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX1GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX1GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX1GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX1GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX1GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX1GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX1GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX1GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX1GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX1GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX2GCR0_CALBYP_MASK 
+#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX2GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX2GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX2GCR0_MDLEN_MASK 
+#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX2GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX2GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX2GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX2GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX2GCR0_RDDLY_MASK 
+#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX2GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX2GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX2GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOH_MASK 
+#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX2GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX2GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX2GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX2GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX2GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX2GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX2GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX2GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX2GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX2GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX2GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_OEEN_MASK 
+#define DDR_PHY_DX2GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX2GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX2GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX2GCR1_PDREN_MASK 
+#define DDR_PHY_DX2GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX2GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX2GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_TEEN_MASK 
+#define DDR_PHY_DX2GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX2GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX2GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DSEN_MASK 
+#define DDR_PHY_DX2GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX2GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX2GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DMEN_MASK 
+#define DDR_PHY_DX2GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX2GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX2GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DQEN_MASK 
+#define DDR_PHY_DX2GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX2GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX2GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX2GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX2GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX2GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX2GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_RDBVT_MASK 
+#define DDR_PHY_DX2GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX2GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_WDBVT_MASK 
+#define DDR_PHY_DX2GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX2GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_RGLVT_MASK 
+#define DDR_PHY_DX2GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX2GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_RDLVT_MASK 
+#define DDR_PHY_DX2GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX2GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_WDLVT_MASK 
+#define DDR_PHY_DX2GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX2GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX2GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX2GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX2GCR3_WLLVT_MASK 
+#define DDR_PHY_DX2GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX2GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX2GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX2GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX2GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX2GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX2GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX2GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX2GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX2GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX2GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX2GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX2GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX2GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX2GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX2GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX2GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX2GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX2GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX2GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX2GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX2GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX2GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX2GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX2GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX2GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX2GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX2GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX2GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX2GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX2GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX2GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX2GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX2GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX2GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX2GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX2GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX2GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX2GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX2GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX2GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX2GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX2GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX2GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX2GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX2GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX3GCR0_CALBYP_MASK 
+#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX3GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX3GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX3GCR0_MDLEN_MASK 
+#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX3GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX3GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX3GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX3GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX3GCR0_RDDLY_MASK 
+#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX3GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX3GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX3GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOH_MASK 
+#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX3GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX3GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX3GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX3GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX3GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX3GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX3GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX3GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX3GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX3GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX3GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_OEEN_MASK 
+#define DDR_PHY_DX3GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX3GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX3GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX3GCR1_PDREN_MASK 
+#define DDR_PHY_DX3GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX3GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX3GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_TEEN_MASK 
+#define DDR_PHY_DX3GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX3GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX3GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DSEN_MASK 
+#define DDR_PHY_DX3GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX3GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX3GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DMEN_MASK 
+#define DDR_PHY_DX3GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX3GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX3GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DQEN_MASK 
+#define DDR_PHY_DX3GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX3GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX3GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX3GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX3GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX3GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX3GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_RDBVT_MASK 
+#define DDR_PHY_DX3GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX3GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_WDBVT_MASK 
+#define DDR_PHY_DX3GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX3GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_RGLVT_MASK 
+#define DDR_PHY_DX3GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX3GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_RDLVT_MASK 
+#define DDR_PHY_DX3GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX3GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_WDLVT_MASK 
+#define DDR_PHY_DX3GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX3GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX3GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX3GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX3GCR3_WLLVT_MASK 
+#define DDR_PHY_DX3GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX3GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX3GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX3GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX3GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX3GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX3GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX3GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX3GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX3GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX3GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX3GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX3GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX3GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX3GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX3GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX3GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX3GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX3GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX3GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX3GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX3GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX3GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX3GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX3GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX3GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX3GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX3GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX3GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX3GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX3GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX3GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX3GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX3GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX3GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX3GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX3GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX3GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX3GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX3GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX3GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX3GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX3GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX3GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX3GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX3GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX4GCR0_CALBYP_MASK 
+#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX4GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX4GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX4GCR0_MDLEN_MASK 
+#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX4GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX4GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX4GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX4GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX4GCR0_RDDLY_MASK 
+#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX4GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX4GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX4GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOH_MASK 
+#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX4GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX4GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX4GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX4GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX4GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX4GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX4GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX4GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX4GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX4GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX4GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_OEEN_MASK 
+#define DDR_PHY_DX4GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX4GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX4GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX4GCR1_PDREN_MASK 
+#define DDR_PHY_DX4GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX4GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX4GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_TEEN_MASK 
+#define DDR_PHY_DX4GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX4GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX4GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DSEN_MASK 
+#define DDR_PHY_DX4GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX4GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX4GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DMEN_MASK 
+#define DDR_PHY_DX4GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX4GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX4GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DQEN_MASK 
+#define DDR_PHY_DX4GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX4GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX4GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Enables the OE mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR2_DXOEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR2_DXOEMODE_MASK 
+#define DDR_PHY_DX4GCR2_DXOEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX4GCR2_DXOEMODE_SHIFT                         16
+#define DDR_PHY_DX4GCR2_DXOEMODE_MASK                          0xFFFF0000U
+
+/*
+* Enables the TE (ODT) mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR2_DXTEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR2_DXTEMODE_MASK 
+#define DDR_PHY_DX4GCR2_DXTEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX4GCR2_DXTEMODE_SHIFT                         0
+#define DDR_PHY_DX4GCR2_DXTEMODE_MASK                          0x0000FFFFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX4GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX4GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX4GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX4GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_RDBVT_MASK 
+#define DDR_PHY_DX4GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX4GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_WDBVT_MASK 
+#define DDR_PHY_DX4GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX4GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_RGLVT_MASK 
+#define DDR_PHY_DX4GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX4GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_RDLVT_MASK 
+#define DDR_PHY_DX4GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX4GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_WDLVT_MASK 
+#define DDR_PHY_DX4GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX4GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX4GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX4GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX4GCR3_WLLVT_MASK 
+#define DDR_PHY_DX4GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX4GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX4GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX4GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX4GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX4GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX4GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX4GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX4GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX4GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX4GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX4GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX4GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX4GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX4GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX4GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX4GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX4GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX4GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX4GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX4GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX4GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX4GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX4GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX4GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX4GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX4GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX4GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX4GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX4GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX4GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX4GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX4GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX4GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX4GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX4GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX4GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX4GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX4GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX4GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX4GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX4GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX4GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX4GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX4GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX4GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX5GCR0_CALBYP_MASK 
+#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX5GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX5GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX5GCR0_MDLEN_MASK 
+#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX5GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX5GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX5GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX5GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX5GCR0_RDDLY_MASK 
+#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX5GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX5GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX5GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOH_MASK 
+#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX5GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX5GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX5GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX5GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX5GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX5GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX5GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX5GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX5GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX5GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX5GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_OEEN_MASK 
+#define DDR_PHY_DX5GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX5GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX5GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX5GCR1_PDREN_MASK 
+#define DDR_PHY_DX5GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX5GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX5GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_TEEN_MASK 
+#define DDR_PHY_DX5GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX5GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX5GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DSEN_MASK 
+#define DDR_PHY_DX5GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX5GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX5GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DMEN_MASK 
+#define DDR_PHY_DX5GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX5GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX5GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DQEN_MASK 
+#define DDR_PHY_DX5GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX5GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX5GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Enables the OE mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR2_DXOEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR2_DXOEMODE_MASK 
+#define DDR_PHY_DX5GCR2_DXOEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX5GCR2_DXOEMODE_SHIFT                         16
+#define DDR_PHY_DX5GCR2_DXOEMODE_MASK                          0xFFFF0000U
+
+/*
+* Enables the TE (ODT) mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR2_DXTEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR2_DXTEMODE_MASK 
+#define DDR_PHY_DX5GCR2_DXTEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX5GCR2_DXTEMODE_SHIFT                         0
+#define DDR_PHY_DX5GCR2_DXTEMODE_MASK                          0x0000FFFFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX5GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX5GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX5GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX5GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_RDBVT_MASK 
+#define DDR_PHY_DX5GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX5GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_WDBVT_MASK 
+#define DDR_PHY_DX5GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX5GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_RGLVT_MASK 
+#define DDR_PHY_DX5GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX5GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_RDLVT_MASK 
+#define DDR_PHY_DX5GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX5GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_WDLVT_MASK 
+#define DDR_PHY_DX5GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX5GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX5GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX5GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX5GCR3_WLLVT_MASK 
+#define DDR_PHY_DX5GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX5GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX5GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX5GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX5GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX5GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX5GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX5GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX5GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX5GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX5GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX5GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX5GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX5GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX5GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX5GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX5GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX5GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX5GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX5GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX5GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX5GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX5GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX5GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX5GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX5GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX5GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX5GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX5GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX5GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX5GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX5GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX5GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX5GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX5GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX5GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX5GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX5GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX5GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX5GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX5GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX5GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX5GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX5GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX5GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX5GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX6GCR0_CALBYP_MASK 
+#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX6GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX6GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX6GCR0_MDLEN_MASK 
+#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX6GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX6GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX6GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX6GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX6GCR0_RDDLY_MASK 
+#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX6GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX6GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX6GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOH_MASK 
+#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX6GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX6GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX6GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX6GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX6GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX6GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX6GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX6GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX6GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX6GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX6GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_OEEN_MASK 
+#define DDR_PHY_DX6GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX6GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX6GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX6GCR1_PDREN_MASK 
+#define DDR_PHY_DX6GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX6GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX6GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_TEEN_MASK 
+#define DDR_PHY_DX6GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX6GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX6GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DSEN_MASK 
+#define DDR_PHY_DX6GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX6GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX6GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DMEN_MASK 
+#define DDR_PHY_DX6GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX6GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX6GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DQEN_MASK 
+#define DDR_PHY_DX6GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX6GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX6GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Enables the OE mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR2_DXOEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR2_DXOEMODE_MASK 
+#define DDR_PHY_DX6GCR2_DXOEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX6GCR2_DXOEMODE_SHIFT                         16
+#define DDR_PHY_DX6GCR2_DXOEMODE_MASK                          0xFFFF0000U
+
+/*
+* Enables the TE (ODT) mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR2_DXTEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR2_DXTEMODE_MASK 
+#define DDR_PHY_DX6GCR2_DXTEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX6GCR2_DXTEMODE_SHIFT                         0
+#define DDR_PHY_DX6GCR2_DXTEMODE_MASK                          0x0000FFFFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX6GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX6GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX6GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX6GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_RDBVT_MASK 
+#define DDR_PHY_DX6GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX6GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_WDBVT_MASK 
+#define DDR_PHY_DX6GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX6GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_RGLVT_MASK 
+#define DDR_PHY_DX6GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX6GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_RDLVT_MASK 
+#define DDR_PHY_DX6GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX6GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_WDLVT_MASK 
+#define DDR_PHY_DX6GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX6GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX6GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX6GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX6GCR3_WLLVT_MASK 
+#define DDR_PHY_DX6GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX6GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX6GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX6GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX6GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX6GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX6GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX6GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX6GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX6GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX6GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX6GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX6GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX6GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX6GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX6GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX6GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX6GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX6GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX6GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX6GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX6GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX6GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX6GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX6GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX6GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX6GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX6GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX6GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX6GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX6GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX6GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX6GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX6GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX6GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX6GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX6GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX6GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX6GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX6GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX6GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX6GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX6GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX6GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX6GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX6GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX7GCR0_CALBYP_MASK 
+#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX7GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX7GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX7GCR0_MDLEN_MASK 
+#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX7GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX7GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX7GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX7GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX7GCR0_RDDLY_MASK 
+#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX7GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX7GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX7GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOH_MASK 
+#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX7GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX7GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX7GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX7GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX7GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX7GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX7GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX7GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX7GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX7GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX7GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_OEEN_MASK 
+#define DDR_PHY_DX7GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX7GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX7GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX7GCR1_PDREN_MASK 
+#define DDR_PHY_DX7GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX7GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX7GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_TEEN_MASK 
+#define DDR_PHY_DX7GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX7GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX7GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DSEN_MASK 
+#define DDR_PHY_DX7GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX7GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX7GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DMEN_MASK 
+#define DDR_PHY_DX7GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX7GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX7GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DQEN_MASK 
+#define DDR_PHY_DX7GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX7GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX7GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Enables the OE mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR2_DXOEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR2_DXOEMODE_MASK 
+#define DDR_PHY_DX7GCR2_DXOEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX7GCR2_DXOEMODE_SHIFT                         16
+#define DDR_PHY_DX7GCR2_DXOEMODE_MASK                          0xFFFF0000U
+
+/*
+* Enables the TE (ODT) mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR2_DXTEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR2_DXTEMODE_MASK 
+#define DDR_PHY_DX7GCR2_DXTEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX7GCR2_DXTEMODE_SHIFT                         0
+#define DDR_PHY_DX7GCR2_DXTEMODE_MASK                          0x0000FFFFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX7GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX7GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX7GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX7GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_RDBVT_MASK 
+#define DDR_PHY_DX7GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX7GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_WDBVT_MASK 
+#define DDR_PHY_DX7GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX7GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_RGLVT_MASK 
+#define DDR_PHY_DX7GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX7GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_RDLVT_MASK 
+#define DDR_PHY_DX7GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX7GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_WDLVT_MASK 
+#define DDR_PHY_DX7GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX7GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX7GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX7GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX7GCR3_WLLVT_MASK 
+#define DDR_PHY_DX7GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX7GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX7GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX7GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX7GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX7GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX7GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX7GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX7GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX7GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX7GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX7GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX7GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX7GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX7GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX7GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX7GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX7GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX7GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX7GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX7GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX7GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX7GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX7GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX7GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX7GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX7GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX7GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX7GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX7GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX7GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX7GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX7GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX7GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX7GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX7GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX7GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX7GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX7GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX7GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX7GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX7GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX7GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX7GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX7GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX7GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Calibration Bypass
+*/
+#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX8GCR0_CALBYP_MASK 
+#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                          0x40200204
+#define DDR_PHY_DX8GCR0_CALBYP_SHIFT                           31
+#define DDR_PHY_DX8GCR0_CALBYP_MASK                            0x80000000U
+
+/*
+* Master Delay Line Enable
+*/
+#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX8GCR0_MDLEN_MASK 
+#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                           0x40200204
+#define DDR_PHY_DX8GCR0_MDLEN_SHIFT                            30
+#define DDR_PHY_DX8GCR0_MDLEN_MASK                             0x40000000U
+
+/*
+* Configurable ODT(TE) Phase Shift
+*/
+#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                         28
+#define DDR_PHY_DX8GCR0_CODTSHFT_MASK                          0x30000000U
+
+/*
+* DQS Duty Cycle Correction
+*/
+#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                          0x40200204
+#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                           24
+#define DDR_PHY_DX8GCR0_DQSDCC_MASK                            0x0F000000U
+
+/*
+* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd
+    *  input for the respective bypte lane of the PHY
+*/
+#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX8GCR0_RDDLY_MASK 
+#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                           0x40200204
+#define DDR_PHY_DX8GCR0_RDDLY_SHIFT                            20
+#define DDR_PHY_DX8GCR0_RDDLY_MASK                             0x00F00000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                  0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                   14
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                    0x000FC000U
+
+/*
+* DQSNSE Power Down Receiver
+*/
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                       0x40200204
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                        13
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                         0x00002000U
+
+/*
+* DQSSE Power Down Receiver
+*/
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                        0x40200204
+#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                         12
+#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                          0x00001000U
+
+/*
+* RTT On Additive Latency
+*/
+#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                          0x40200204
+#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                           11
+#define DDR_PHY_DX8GCR0_RTTOAL_MASK                            0x00000800U
+
+/*
+* RTT Output Hold
+*/
+#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOH_MASK 
+#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                           0x40200204
+#define DDR_PHY_DX8GCR0_RTTOH_SHIFT                            9
+#define DDR_PHY_DX8GCR0_RTTOH_MASK                             0x00000600U
+
+/*
+* Configurable PDR Phase Shift
+*/
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                        0x40200204
+#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                         7
+#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                          0x00000180U
+
+/*
+* DQSR Power Down
+*/
+#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                          0x40200204
+#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                           6
+#define DDR_PHY_DX8GCR0_DQSRPD_MASK                            0x00000040U
+
+/*
+* DQSG Power Down Receiver
+*/
+#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                         0x40200204
+#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                          5
+#define DDR_PHY_DX8GCR0_DQSGPDR_MASK                           0x00000020U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                      0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                       4
+#define DDR_PHY_DX8GCR0_RESERVED_4_MASK                        0x00000010U
+
+/*
+* DQSG On-Die Termination
+*/
+#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                         0x40200204
+#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                          3
+#define DDR_PHY_DX8GCR0_DQSGODT_MASK                           0x00000008U
+
+/*
+* DQSG Output Enable
+*/
+#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                          0x40200204
+#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                           2
+#define DDR_PHY_DX8GCR0_DQSGOE_MASK                            0x00000004U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                    0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Enables the PDR mode for DQ[7:0]
+*/
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                       0x00007FFF
+#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                        16
+#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                         0xFFFF0000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                     0x00007FFF
+#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX8GCR1_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Select the delayed or non-delayed read data strobe #
+*/
+#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                          0x00007FFF
+#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                           14
+#define DDR_PHY_DX8GCR1_QSNSEL_MASK                            0x00004000U
+
+/*
+* Select the delayed or non-delayed read data strobe
+*/
+#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX8GCR1_QSSEL_SHIFT                            13
+#define DDR_PHY_DX8GCR1_QSSEL_MASK                             0x00002000U
+
+/*
+* Enables Read Data Strobe in a byte lane
+*/
+#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_OEEN_MASK 
+#define DDR_PHY_DX8GCR1_OEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX8GCR1_OEEN_SHIFT                             12
+#define DDR_PHY_DX8GCR1_OEEN_MASK                              0x00001000U
+
+/*
+* Enables PDR in a byte lane
+*/
+#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX8GCR1_PDREN_MASK 
+#define DDR_PHY_DX8GCR1_PDREN_DEFVAL                           0x00007FFF
+#define DDR_PHY_DX8GCR1_PDREN_SHIFT                            11
+#define DDR_PHY_DX8GCR1_PDREN_MASK                             0x00000800U
+
+/*
+* Enables ODT/TE in a byte lane
+*/
+#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_TEEN_MASK 
+#define DDR_PHY_DX8GCR1_TEEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX8GCR1_TEEN_SHIFT                             10
+#define DDR_PHY_DX8GCR1_TEEN_MASK                              0x00000400U
+
+/*
+* Enables Write Data strobe in a byte lane
+*/
+#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DSEN_MASK 
+#define DDR_PHY_DX8GCR1_DSEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX8GCR1_DSEN_SHIFT                             9
+#define DDR_PHY_DX8GCR1_DSEN_MASK                              0x00000200U
+
+/*
+* Enables DM pin in a byte lane
+*/
+#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DMEN_MASK 
+#define DDR_PHY_DX8GCR1_DMEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX8GCR1_DMEN_SHIFT                             8
+#define DDR_PHY_DX8GCR1_DMEN_MASK                              0x00000100U
+
+/*
+* Enables DQ corresponding to each bit in a byte
+*/
+#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DQEN_MASK 
+#define DDR_PHY_DX8GCR1_DQEN_DEFVAL                            0x00007FFF
+#define DDR_PHY_DX8GCR1_DQEN_SHIFT                             0
+#define DDR_PHY_DX8GCR1_DQEN_MASK                              0x000000FFU
+
+/*
+* Enables the OE mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR2_DXOEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR2_DXOEMODE_MASK 
+#define DDR_PHY_DX8GCR2_DXOEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX8GCR2_DXOEMODE_SHIFT                         16
+#define DDR_PHY_DX8GCR2_DXOEMODE_MASK                          0xFFFF0000U
+
+/*
+* Enables the TE (ODT) mode values for DQ[7:0]
+*/
+#undef DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR2_DXTEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR2_DXTEMODE_MASK 
+#define DDR_PHY_DX8GCR2_DXTEMODE_DEFVAL                        0x00000000
+#define DDR_PHY_DX8GCR2_DXTEMODE_SHIFT                         0
+#define DDR_PHY_DX8GCR2_DXTEMODE_MASK                          0x0000FFFFU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX8GCR3_RESERVED_31_30_MASK 
+#define DDR_PHY_DX8GCR3_RESERVED_31_30_DEFVAL                  0x3F000008
+#define DDR_PHY_DX8GCR3_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX8GCR3_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* Read Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_RDBVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RDBVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_RDBVT_MASK 
+#define DDR_PHY_DX8GCR3_RDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_RDBVT_SHIFT                            29
+#define DDR_PHY_DX8GCR3_RDBVT_MASK                             0x20000000U
+
+/*
+* Write Data BDL VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_WDBVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_WDBVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_WDBVT_MASK 
+#define DDR_PHY_DX8GCR3_WDBVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_WDBVT_SHIFT                            28
+#define DDR_PHY_DX8GCR3_WDBVT_MASK                             0x10000000U
+
+/*
+* Read DQS Gating LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_RGLVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RGLVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_RGLVT_MASK 
+#define DDR_PHY_DX8GCR3_RGLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_RGLVT_SHIFT                            27
+#define DDR_PHY_DX8GCR3_RGLVT_MASK                             0x08000000U
+
+/*
+* Read DQS LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_RDLVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RDLVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_RDLVT_MASK 
+#define DDR_PHY_DX8GCR3_RDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_RDLVT_SHIFT                            26
+#define DDR_PHY_DX8GCR3_RDLVT_MASK                             0x04000000U
+
+/*
+* Write DQ LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_WDLVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_WDLVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_WDLVT_MASK 
+#define DDR_PHY_DX8GCR3_WDLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_WDLVT_SHIFT                            25
+#define DDR_PHY_DX8GCR3_WDLVT_MASK                             0x02000000U
+
+/*
+* Write Leveling LCDL Delay VT Compensation
+*/
+#undef DDR_PHY_DX8GCR3_WLLVT_DEFVAL 
+#undef DDR_PHY_DX8GCR3_WLLVT_SHIFT 
+#undef DDR_PHY_DX8GCR3_WLLVT_MASK 
+#define DDR_PHY_DX8GCR3_WLLVT_DEFVAL                           0x3F000008
+#define DDR_PHY_DX8GCR3_WLLVT_SHIFT                            24
+#define DDR_PHY_DX8GCR3_WLLVT_MASK                             0x01000000U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8GCR3_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8GCR3_RESERVED_23_22_DEFVAL                  0x3F000008
+#define DDR_PHY_DX8GCR3_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX8GCR3_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* Enables the OE mode for DQs
+*/
+#undef DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSNOEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSNOEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX8GCR3_DSNOEMODE_SHIFT                        20
+#define DDR_PHY_DX8GCR3_DSNOEMODE_MASK                         0x00300000U
+
+/*
+* Enables the TE mode for DQS
+*/
+#undef DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSNTEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSNTEMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX8GCR3_DSNTEMODE_SHIFT                        18
+#define DDR_PHY_DX8GCR3_DSNTEMODE_MASK                         0x000C0000U
+
+/*
+* Enables the PDR mode for DQS
+*/
+#undef DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSNPDRMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSNPDRMODE_DEFVAL                      0x3F000008
+#define DDR_PHY_DX8GCR3_DSNPDRMODE_SHIFT                       16
+#define DDR_PHY_DX8GCR3_DSNPDRMODE_MASK                        0x00030000U
+
+/*
+* Enables the OE mode values for DM.
+*/
+#undef DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DMOEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DMOEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DMOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX8GCR3_DMOEMODE_SHIFT                         14
+#define DDR_PHY_DX8GCR3_DMOEMODE_MASK                          0x0000C000U
+
+/*
+* Enables the TE mode values for DM.
+*/
+#undef DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DMTEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DMTEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DMTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX8GCR3_DMTEMODE_SHIFT                         12
+#define DDR_PHY_DX8GCR3_DMTEMODE_MASK                          0x00003000U
+
+/*
+* Enables the PDR mode values for DM.
+*/
+#undef DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DMPDRMODE_MASK 
+#define DDR_PHY_DX8GCR3_DMPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX8GCR3_DMPDRMODE_SHIFT                        10
+#define DDR_PHY_DX8GCR3_DMPDRMODE_MASK                         0x00000C00U
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT 
+#undef DDR_PHY_DX8GCR3_RESERVED_9_8_MASK 
+#define DDR_PHY_DX8GCR3_RESERVED_9_8_DEFVAL                    0x3F000008
+#define DDR_PHY_DX8GCR3_RESERVED_9_8_SHIFT                     8
+#define DDR_PHY_DX8GCR3_RESERVED_9_8_MASK                      0x00000300U
+
+/*
+* Enables the OE mode values for DQS.
+*/
+#undef DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSOEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSOEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSOEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX8GCR3_DSOEMODE_SHIFT                         6
+#define DDR_PHY_DX8GCR3_DSOEMODE_MASK                          0x000000C0U
+
+/*
+* Enables the TE mode values for DQS.
+*/
+#undef DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSTEMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSTEMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSTEMODE_DEFVAL                        0x3F000008
+#define DDR_PHY_DX8GCR3_DSTEMODE_SHIFT                         4
+#define DDR_PHY_DX8GCR3_DSTEMODE_MASK                          0x00000030U
+
+/*
+* Enables the PDR mode values for DQS.
+*/
+#undef DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR3_DSPDRMODE_MASK 
+#define DDR_PHY_DX8GCR3_DSPDRMODE_DEFVAL                       0x3F000008
+#define DDR_PHY_DX8GCR3_DSPDRMODE_SHIFT                        2
+#define DDR_PHY_DX8GCR3_DSPDRMODE_MASK                         0x0000000CU
+
+/*
+* Reserved. Returns zeroes on reads.
+*/
+#undef DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX8GCR3_RESERVED_1_0_MASK 
+#define DDR_PHY_DX8GCR3_RESERVED_1_0_DEFVAL                    0x3F000008
+#define DDR_PHY_DX8GCR3_RESERVED_1_0_SHIFT                     0
+#define DDR_PHY_DX8GCR3_RESERVED_1_0_MASK                      0x00000003U
+
+/*
+* Byte lane VREF IOM (Used only by D4MU IOs)
+*/
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                   29
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                    0xE0000000U
+
+/*
+* Byte Lane VREF Pad Enable
+*/
+#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                         28
+#define DDR_PHY_DX8GCR4_DXREFPEN_MASK                          0x10000000U
+
+/*
+* Byte Lane Internal VREF Enable
+*/
+#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                         26
+#define DDR_PHY_DX8GCR4_DXREFEEN_MASK                          0x0C000000U
+
+/*
+* Byte Lane Single-End VREF Enable
+*/
+#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                         25
+#define DDR_PHY_DX8GCR4_DXREFSEN_MASK                          0x02000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                     0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                      24
+#define DDR_PHY_DX8GCR4_RESERVED_24_MASK                       0x01000000U
+
+/*
+* External VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                   23
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                    0x00800000U
+
+/*
+* Byte Lane External VREF Select
+*/
+#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                        16
+#define DDR_PHY_DX8GCR4_DXREFESEL_MASK                         0x007F0000U
+
+/*
+* Single ended VREF generator REFSEL range select
+*/
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                  0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                   15
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                    0x00008000U
+
+/*
+* Byte Lane Single-End VREF Select
+*/
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                        8
+#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                         0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                    0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                        0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                         2
+#define DDR_PHY_DX8GCR4_DXREFIEN_MASK                          0x0000003CU
+
+/*
+* VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+*/
+#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                       0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                        0
+#define DDR_PHY_DX8GCR4_DXREFIMON_MASK                         0x00000003U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                      31
+#define DDR_PHY_DX8GCR5_RESERVED_31_MASK                       0x80000000U
+
+/*
+* Byte Lane internal VREF Select for Rank 3
+*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                      24
+#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                       0x7F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                      23
+#define DDR_PHY_DX8GCR5_RESERVED_23_MASK                       0x00800000U
+
+/*
+* Byte Lane internal VREF Select for Rank 2
+*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                      16
+#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                       0x007F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                      15
+#define DDR_PHY_DX8GCR5_RESERVED_15_MASK                       0x00008000U
+
+/*
+* Byte Lane internal VREF Select for Rank 1
+*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                      8
+#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                       0x00007F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                      0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                       7
+#define DDR_PHY_DX8GCR5_RESERVED_7_MASK                        0x00000080U
+
+/*
+* Byte Lane internal VREF Select for Rank 0
+*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                     0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                      0
+#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                       0x0000007FU
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                  0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                   30
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                    0xC0000000U
+
+/*
+* DRAM DQ VREF Select for Rank3
+*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                      0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                       24
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                        0x3F000000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                  0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                   22
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                    0x00C00000U
+
+/*
+* DRAM DQ VREF Select for Rank2
+*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                      0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                       16
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                        0x003F0000U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                  0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                   14
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                    0x0000C000U
+
+/*
+* DRAM DQ VREF Select for Rank1
+*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                      0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                       8
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                        0x00003F00U
+
+/*
+* Reserved. Returns zeros on reads.
+*/
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                    0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                     6
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                      0x000000C0U
+
+/*
+* DRAM DQ VREF Select for Rank0
+*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                      0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                       0
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                        0x0000003FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL                0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT                 30
+#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK                  0xC0000000U
+
+/*
+* Enable Clock Gating for DX ddr_clk
+*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL                   0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT                    28
+#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK                     0x30000000U
+
+/*
+* Enable Clock Gating for DX ctl_rd_clk
+*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL                  0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT                   26
+#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK                    0x0C000000U
+
+/*
+* Enable Clock Gating for DX ctl_clk
+*/
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL                  0x00019FFE
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT                   24
+#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK                    0x03000000U
+
+/*
+* Selects the level to which clocks will be stalled when clock gating is e
+    * nabled.
+*/
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL                      0x00019FFE
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT                       22
+#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK                        0x00C00000U
+
+/*
+* Loopback Mode
+*/
+#undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_LBMODE_MASK 
+#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL                        0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT                         21
+#define DDR_PHY_DX8SL0OSC_LBMODE_MASK                          0x00200000U
+
+/*
+* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
+*/
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL                       0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT                        20
+#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK                         0x00100000U
+
+/*
+* Loopback DQS Gating
+*/
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK 
+#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL                        0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT                         18
+#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK                          0x000C0000U
+
+/*
+* Loopback DQS Shift
+*/
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK 
+#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL                        0x00019FFE
+#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT                         17
+#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK                          0x00020000U
+
+/*
+* PHY High-Speed Reset
+*/
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK 
+#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL                       0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT                        16
+#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK                         0x00010000U
+
+/*
+* PHY FIFO Reset
+*/
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK 
+#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL                       0x00019FFE
+#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT                        15
+#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK                         0x00008000U
+
+/*
+* Delay Line Test Start
+*/
+#undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_DLTST_MASK 
+#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL                         0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT                          14
+#define DDR_PHY_DX8SL0OSC_DLTST_MASK                           0x00004000U
+
+/*
+* Delay Line Test Mode
+*/
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK 
+#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL                       0x00019FFE
+#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT                        13
+#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK                         0x00002000U
+
+/*
+* Reserved. Caution, do not write to this register field.
+*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL                0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT                 11
+#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK                  0x00001800U
+
+/*
+* Oscillator Mode Write-Data Delay Line Select
+*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL                       0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT                        9
+#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK                         0x00000600U
+
+/*
+* Reserved. Caution, do not write to this register field.
+*/
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL                  0x00019FFE
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT                   7
+#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK                    0x00000180U
+
+/*
+* Oscillator Mode Write-Leveling Delay Line Select
+*/
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK 
+#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL                        0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT                         5
+#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK                          0x00000060U
+
+/*
+* Oscillator Mode Division
+*/
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK 
+#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL                        0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT                         1
+#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK                          0x0000001EU
+
+/*
+* Oscillator Enable
+*/
+#undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 
+#undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 
+#undef DDR_PHY_DX8SL0OSC_OSCEN_MASK 
+#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL                         0x00019FFE
+#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT                          0
+#define DDR_PHY_DX8SL0OSC_OSCEN_MASK                           0x00000001U
+
+/*
+* PLL Bypass
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT                      31
+#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK                       0x80000000U
+
+/*
+* PLL Reset
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT                      30
+#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK                       0x40000000U
+
+/*
+* PLL Power Down
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL                      0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT                       29
+#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK                        0x20000000U
+
+/*
+* Reference Stop Mode
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT                      28
+#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK                       0x10000000U
+
+/*
+* PLL Frequency Select
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT                      24
+#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK                       0x0F000000U
+
+/*
+* Relock Mode
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT                      23
+#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK                       0x00800000U
+
+/*
+* Charge Pump Proportional Current Control
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL                       0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT                        17
+#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK                         0x007E0000U
+
+/*
+* Charge Pump Integrating Current Control
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL                       0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT                        13
+#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK                         0x0001E000U
+
+/*
+* Gear Shift
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL                     0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT                      12
+#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK                       0x00001000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL              0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT               9
+#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK                0x00000E00U
+
+/*
+* Analog Test Enable (ATOEN)
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL                      0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT                       8
+#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK                        0x00000100U
+
+/*
+* Analog Test Control
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL                        0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT                         4
+#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK                          0x000000F0U
+
+/*
+* Digital Test Control
+*/
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 
+#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK 
+#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL                        0x001C0000
+#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT                         0
+#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK                          0x0000000FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL             0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT              25
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK               0xFE000000U
+
+/*
+* Read Path Rise-to-Rise Mode
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                    0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                     24
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                      0x01000000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL             0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT              22
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK               0x00C00000U
+
+/*
+* Write Path Rise-to-Rise Mode
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                    0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                     21
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                      0x00200000U
+
+/*
+* DQS Gate Extension
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                      0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                       19
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                        0x00180000U
+
+/*
+* Low Power PLL Power Down
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                    0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                     18
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                      0x00040000U
+
+/*
+* Low Power I/O Power Down
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                     0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                      17
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                       0x00020000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL             0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT              15
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK               0x00018000U
+
+/*
+* QS Counter Enable
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                    0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                     14
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                      0x00004000U
+
+/*
+* Unused DQ I/O Mode
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                     0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                      13
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                       0x00002000U
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL             0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT              10
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK               0x00001C00U
+
+/*
+* Data Slew Rate
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                       0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                        8
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                         0x00000300U
+
+/*
+* DQS_N Resistor
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                    0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                     4
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                      0x000000F0U
+
+/*
+* DQS Resistor
+*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                     0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                      0
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                       0x0000000FU
+
+/*
+* Reserved. Return zeroes on reads.
+*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL             0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT              24
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK               0xFF000000U
+
+/*
+* Configurable Read Data Enable
+*/
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                      0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                       23
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                        0x00800000U
+
+/*
+* OX Extension during Post-amble
+*/
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                     0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                      20
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK