[Buildroot] [PATCH 1/1] package/guile: fix build on riscv32

Fabrice Fontaine fontaine.fabrice at gmail.com
Sat Aug 7 15:08:08 UTC 2021


Yann,

Le sam. 7 août 2021 à 10:53, Yann E. MORIN <yann.morin.1998 at free.fr> a écrit :
>
> Fabrice, All,
>
> On 2021-08-06 20:44 +0200, Fabrice Fontaine spake thusly:
> > Fix the following build failure on riscv32:
> >
> > system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > unknown CPU word size "riscv32"
> >
> > Fixes:
> >  - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> >
> > Signed-off-by: Fabrice Fontaine <fontaine.fabrice at gmail.com>
> > ---
> >  ...stem-base-target.scm-support-riscv32.patch | 33 +++++++++++++++++++
> >  1 file changed, 33 insertions(+)
> >  create mode 100644 package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> >
> > diff --git a/package/guile/0004-module-system-base-target.scm-support-riscv32.patch b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > new file mode 100644
> > index 0000000000..cadd040f12
> > --- /dev/null
> > +++ b/package/guile/0004-module-system-base-target.scm-support-riscv32.patch
> > @@ -0,0 +1,33 @@
> > +From 995a5e1da735b75733f059615c593c330b534d80 Mon Sep 17 00:00:00 2001
> > +From: Fabrice Fontaine <fontaine.fabrice at gmail.com>
> > +Date: Fri, 6 Aug 2021 19:49:37 +0200
> > +Subject: [PATCH] module/system/base/target.scm: support riscv32
> > +
> > +Fix the following build failure on riscv32:
> > +
> > +system/base/target.scm:132:16: In procedure triplet-pointer-size:
> > +unknown CPU word size "riscv32"
> > +
> > +Fixes:
> > + - http://autobuild.buildroot.org/results/6705630c1484239ec8b73d57ebc2e2570fbfc8f8
> > +
> > +Signed-off-by: Fabrice Fontaine <fontaine.fabrice at gmail.com>
> > +---
> > + module/system/base/target.scm | 1 +
> > + 1 file changed, 1 insertion(+)
> > +
> > +diff --git a/module/system/base/target.scm b/module/system/base/target.scm
> > +index 2088cd866..5544e234f 100644
> > +--- a/module/system/base/target.scm
> > ++++ b/module/system/base/target.scm
> > +@@ -121,6 +121,7 @@
> > +           ((member cpu '("sparc" "powerpc" "mips" "mipsel" "nios2" "m68k" "sh3" "sh4")) 4)
> > +           ((member cpu '("s390x" "alpha")) 8)
> > +           ((string-match "^arm.*" cpu) 4)
> > ++          ((string-match "^riscv.*" cpu) 8)
>
> Are you sure that a 32-bit CPU will have 8-byte wide words? I would
> have naturrally expected them to be just 4-byte wide...
As I'm not an expert in riscv, I searched on wikipedia and here is an
extract of https://en.wikipedia.org/wiki/RISC-V:
"Memory is addressed as 8-bit bytes, with words being in little-endian order"
It would be great if a riscv expert could confirm or not this information.
>
> If htis is indeed the case, then please explain that in the patch commit
> log...
>
> Regards,
> Yann E. MORIN.
>
> > +           (else (error "unknown CPU word size" cpu)))))
> > +
> > + (define (triplet-cpu t)
> > +--
> > +2.30.2
> > +
> > --
> > 2.30.2
> >
> > _______________________________________________
> > buildroot mailing list
> > buildroot at busybox.net
> > http://lists.busybox.net/mailman/listinfo/buildroot
>
> --
> .-----------------.--------------------.------------------.--------------------.
> |  Yann E. MORIN  | Real-Time Embedded | /"\ ASCII RIBBON | Erics' conspiracy: |
> | +33 662 376 056 | Software  Designer | \ / CAMPAIGN     |  ___               |
> | +33 561 099 427 `------------.-------:  X  AGAINST      |  \e/  There is no  |
> | http://ymorin.is-a-geek.org/ | _/*\_ | / \ HTML MAIL    |   v   conspiracy.  |
> '------------------------------^-------^------------------^--------------------'
Best Regards,

Fabrice


More information about the buildroot mailing list