[Buildroot] [PATCH 38/55] Remove the few remaining unused Atmel-specific bits

Sun Dec 5 20:53:09 UTC 2010

Signed-off-by: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
---
 .../linux-2.6.27-at91.patch.gz                     |  Bin 93020 -> 0 bytes
 .../linux-2.6.28-at91.patch.bz2                    |  Bin 67725 -> 0 bytes
 .../linux-2.6.28-exp.patch.bz2                     |  Bin 56841 -> 0 bytes
 .../linux-2.6.28.7-100-avr32.patch                 |16813 ------------
 ...28.7-201-avr32-atmel_mpopfb-disable-debug.patch |   23 -
 ...mpopfb-add-signal-to-disable-line-caching.patch |   43 -
 ....28.7-203-avr32-fix-arch-header-byteorder.patch |   35 -
 ...4-avr32-ap700x-fix-det_pin-for-nand-flash.patch |   33 -
 .../linux-2.6.27.6-100-avr32-atmel.1.patch         |26786 --------------------
 ...00-avr32-remove.note.gnu.build-id-section.patch |   27 -
 ...27.6-201-avr32-atmel_mpopfb-disable-debug.patch |   23 -
 ...mpopfb-add-signal-to-disable-line-caching.patch |   59 -
 ....27.6-203-avr32-fix-arch-header-byteorder.patch |   35 -
 ...4-avr32-ap700x-fix-det_pin-for-nand-flash.patch |   31 -
 target/device/Atmel/misc-patches/README            |    2 -
 .../misc-patches/u-boot-1.3.0-200MHz-ngw100.patch  |   20 -
 .../u-boot-1.3.0-64MB-sdram-ngw100.patch           |   11 -
 target/device/Atmel/root/device_table.txt          |  162 -
 target/device/Atmel/root/skel.patch                |   71 -
 target/device/Atmel/root/skel.tar.gz               |  Bin 629 -> 0 bytes
 target/device/Atmel/root/target_skeleton/etc/TZ    |    1 -
 target/device/Atmel/root/target_skeleton/etc/fstab |    9 -
 target/device/Atmel/root/target_skeleton/etc/group |   16 -
 .../device/Atmel/root/target_skeleton/etc/hostname |    1 -
 target/device/Atmel/root/target_skeleton/etc/hosts |    1 -
 .../root/target_skeleton/etc/init.d/S20urandom     |   54 -
 .../root/target_skeleton/etc/init.d/S40network     |   35 -
 .../Atmel/root/target_skeleton/etc/init.d/rcS      |   27 -
 .../device/Atmel/root/target_skeleton/etc/inittab  |   45 -
 .../device/Atmel/root/target_skeleton/etc/inputrc  |   44 -
 target/device/Atmel/root/target_skeleton/etc/issue |    3 -
 .../Atmel/root/target_skeleton/etc/ld.so.conf      |    1 -
 .../root/target_skeleton/etc/network/interfaces    |    4 -
 .../device/Atmel/root/target_skeleton/etc/passwd   |   15 -
 .../device/Atmel/root/target_skeleton/etc/profile  |   48 -
 .../Atmel/root/target_skeleton/etc/protocols       |   31 -
 .../Atmel/root/target_skeleton/etc/random-seed     |  Bin 512 -> 0 bytes
 .../Atmel/root/target_skeleton/etc/securetty       |   12 -
 .../device/Atmel/root/target_skeleton/etc/services |  302 -
 .../device/Atmel/root/target_skeleton/etc/shadow   |   12 -
 .../Atmel/root/target_skeleton/root/.bash_logout   |    7 -
 .../Atmel/root/target_skeleton/root/.bash_profile  |   15 -
 .../device/Atmel/root/target_skeleton/root/.bashrc |   48 -
 .../usr/share/udhcpc/default.script                |   39 -
 target/device/Atmel/root/uClibc.config             |  167 -
 45 files changed, 0 insertions(+), 45111 deletions(-)
 delete mode 100644 target/device/Atmel/arch-arm/kernel-patches-2.6.27/linux-2.6.27-at91.patch.gz
 delete mode 100644 target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-at91.patch.bz2
 delete mode 100644 target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-exp.patch.bz2
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-100-avr32.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-201-avr32-atmel_mpopfb-disable-debug.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-203-avr32-fix-arch-header-byteorder.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-200-avr32-remove.note.gnu.build-id-section.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-201-avr32-atmel_mpopfb-disable-debug.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-203-avr32-fix-arch-header-byteorder.patch
 delete mode 100644 target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
 delete mode 100644 target/device/Atmel/misc-patches/README
 delete mode 100644 target/device/Atmel/misc-patches/u-boot-1.3.0-200MHz-ngw100.patch
 delete mode 100644 target/device/Atmel/misc-patches/u-boot-1.3.0-64MB-sdram-ngw100.patch
 delete mode 100644 target/device/Atmel/root/device_table.txt
 delete mode 100644 target/device/Atmel/root/skel.patch
 delete mode 100644 target/device/Atmel/root/skel.tar.gz
 delete mode 100644 target/device/Atmel/root/target_skeleton/bin/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/boot/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/config/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/dev/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/TZ
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/fstab
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/group
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/hostname
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/hosts
 delete mode 100755 target/device/Atmel/root/target_skeleton/etc/init.d/S20urandom
 delete mode 100755 target/device/Atmel/root/target_skeleton/etc/init.d/S40network
 delete mode 100755 target/device/Atmel/root/target_skeleton/etc/init.d/rcS
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/inittab
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/inputrc
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/issue
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/ld.so.conf
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/ld.so.conf.d/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/network/interfaces
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/passwd
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/profile
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/protocols
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/random-seed
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/securetty
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/services
 delete mode 100644 target/device/Atmel/root/target_skeleton/etc/shadow
 delete mode 100644 target/device/Atmel/root/target_skeleton/home/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/lib/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/mnt/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/opt/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/proc/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/root/.bash_history
 delete mode 100644 target/device/Atmel/root/target_skeleton/root/.bash_logout
 delete mode 100644 target/device/Atmel/root/target_skeleton/root/.bash_profile
 delete mode 100644 target/device/Atmel/root/target_skeleton/root/.bashrc
 delete mode 100644 target/device/Atmel/root/target_skeleton/root/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/sbin/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/sys/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/tmp/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/bin/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/include/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/lib/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/man/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/sbin/.empty
 delete mode 100755 target/device/Atmel/root/target_skeleton/usr/share/udhcpc/default.script
 delete mode 100644 target/device/Atmel/root/target_skeleton/usr/src/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/cache/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/lib/pcmcia/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/lock/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/log/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/pcmcia/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/run/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/spool/.empty
 delete mode 100644 target/device/Atmel/root/target_skeleton/var/tmp/.empty
 delete mode 100644 target/device/Atmel/root/uClibc.config

diff --git a/target/device/Atmel/arch-arm/kernel-patches-2.6.27/linux-2.6.27-at91.patch.gz b/target/device/Atmel/arch-arm/kernel-patches-2.6.27/linux-2.6.27-at91.patch.gz
deleted file mode 100644
index 8acde845bb725afa574b4e0317bffd5d281a38b6..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 93020
zcmV)RK(oIeiwFp>EdEFW12Qf)E;2VQVRSh$E^uLVV`u=ZTwRmmHnYBd^DA8Qo~m=P
zAp_=ntEMWlEQ1!y_F6I at xpA=!yGtztQ@|wIe}7sw2Fplhk~*o)Fr$9lYDukDcdO0w
z=Id9h at pcHT#@`m6a%;QUz5U&=f9w5b_kY_THs2nXht+rZ@$$IZ at 4jxn9UqscVe7bj
z86LLlAL;Y at Yu<i+^1V;|(r7gPeSiP4o6SL^)oj>J%Wi&b4nMX#zcq{htPf3~|MKC(
zhkq_t&bc{kGzXU5`q*uKZ1!(B|Ngtx=nQ+m_N))`qi_BG`!CjiEgS|O9i<{n at R;M6
zkRXjnz``UD*5+vK_9yGOJ{geN?=c;X-;15mpp5*W!6Ctjp9+p#jGulQm?hY0bzo?B
zdri2L;*dolr-JC=G>8(BGRkq8{`@cWY<2w7Yxm!$VO8vVb*uW^tyZ<{f2vh_p3P39
zHLzO!kDdO<?m(+gy+Icg=|ldJ>64sSYGVs+zk&Rx?=MH$*tkx%jZ@^0LWc^SB9zF=
z+86B+_6&=70U!mCi#crn+O<JW`0Utc#g|f!mxt%SmWQ?FydACM+w1H8a5 at j7#CH_Y
zu*_5)O^CyoaI;hqilZ<VsbAeDDjQCjAlOV7DC8-bGIK{<Bu>rqG+4;ppv<}|C`Kve
zmFdeTgKdth^>(}5t at kida^~>&&1-qauARBO)f?FQZa4{e7;}kfxBK at o{f>UP1%{9)
z4p}`0RA$gs8C`|ViQRfhU}A>d_V69u3|sncM8tdDW~*7>Pb~1D+q*MlhUUG2Dskfm
zB)D&PyN2$dn{?i?n_ao;W_5CjlZ;ZS-1jhY-`&GF3BTLbm_|3s2V>(Ay=WSY;<9Ji
zez!S+k=cFIE24Z(KT8pXY2<>$diu<;icvTtamte@@)wGrXZm=?!ay-wSxY*lZvAp0
zx8DI%Tf6SaWv!;&dJm}k9#HR|ND?%B2dDOZnTB?!d9ORs at ATgVYS(Wf#GRJOF}PsF
zJh~&bv|@IvULLRC8Z^7!ebB)6M)y$NcE8K(hvsoSR&`d30bi$nY$Lzh8gO<OWH;}D
zs2KGBADpKCKX97*|I%qvp8HR0*l#wPE%;|O?T=0Ho0|W^Y3gg7reVYGNT;dUhJRY8
zsrf7X)%taqdm<nHD_0S{o%S!w(`L2YZhu<e*1Pp#d0IbPFUucmE9d{wdfxB;_hhY~
zH`&7bQZ(zw`mkGXtv}a?<7U76Xl2vTYaCX##DIyk*z%{<vaMG0W4ree#w*3ldOfct
ziW%6f;xE47nS}$71@=kAQo<4+37Q$U0yH84iD~W_X_^IPMAMA at 5KqXI1cH~Sj3x4~
zi)sa7N<-Pb&OIzxjZy5<_;Z;L7YI*8j4&zWFA-(WE{Qah{0ZRY`Dny7fTF9E&r<O7
zNZ at LQ27nYi5vM%tc*Y64AmGdiq!h|nQH;mX0qi3`9NB5oHn>eyoa!UoOwNo*S5vnF
z$fr(>1c4LRM~f07>*2cYVN!nlk1&8I7%DYQ2^P`-IEa&{=HFl8KdI#xx=Xxb>M0jb
z50Bf;m&cd=^V at cPeEgpzK#ag_`UD<-{4Lk-hhILNH^V4X|E(O{+iO`>$vlE_Fwh|6
zmxOWRZ~~zooV1)pl~qqCBo0U!O#>=Y5=>#tQaT2aM%ykwgZwFpxzzZFM!v}(N^4OD
zq$m-gZYlT-Me3%S(g@$S$WJWF(#b$|p0dvgNr<8=4tJ%BVZvd3Fcx}E5r|J<CkVqy
zf)dvdcTMtN%JVcSM1o$GS(V<Lm+~?7#8azNVvk30m_%HwoRX5t1FXD%JVfIvspO}Y
zNjjzpm;TtzgZR#4FzFtg at DMu?44c7K*F_<vQ(Kiu?i(FXsnI+FTf!B50=p?NEQVZv
z6D=E=i5OA0N-LDapMdbwOvhulqVzFhFg6}0F(ywB4;LDS7&Zc%P5&UN7s7<XFY1(>
zRrDeNVGeO!!<taH)w_8-`#`>LB!Kr%a_e{|PoR-6m^z(BBZM5jer_%ZGKT>}@XfUo
zH4a7OCuMbyVj76D0FFW?zL&*9r6!qHLISLh@)TIK)Jv3+dWj(Ovat=obkHDlN%;UH
zQK-%j9R<ku%Bv_3)>vuDj#H(Dj~OW+=u?)1K-?sNkViQ)edH+f%l*WVAmDyzpn!Ss
zs855Dp3G1TCRo1+Xi7l!vgcJ}H^~lD^FwF4a!kwSn20Oo8ih$3oL}Jg3%w-L#DT7i
zNDA>9g_Er^Ni^`vjt*ERCfBsmPnKfI=3l!vrDkv at H^KFsWTBh*6*hUB+=}3t_#x76
zvok0OB*6T5PB*Mf=$_9pZUjh9JjR#vuCncl<pN}R58OC9zGIN#Vz9#86Vs!7?$tl;
za8>)xjsy)YzWTnFUdQ2Bb|h$+9S-1ZhUIg*Xh!OS6wNL{E-1P|$O47E&$>ARj|e5c
zsPZnF>v<QbD(@SB98g{FXCa>+mOBVGHm}Rm{_wMO6!>5-!BLEH=9HhOk^elN)-RU$
z`MN&0l)XlT2)3KeW{v9#mX(aa?+oJ_P)xwDqGVPBk!lFBh);Aw%!Lud)~$<;{fPIw
zwIXJaR%>1d3GG3*hE5!gTCKWHNHlEE>$>p5P&hGlN2CT65K+ft+_#%`bjoU}VbrRZ
z5fE+r9-v(dm`C=VJ^*n?rRGtmmW2<~P{&}x2fbn4at3 at jukC@&aSb($!C-dlo{xfg
z2V(I$#2nRan5eG*Oc(1WfVZ*Tsa01FvG1gAipPD_sns<XO=*B>-83;2)y*+y{du#A
zbk^P3L&N^{wAt at +<9=?B_J6Gp*2{9Y{I-5s?@nbJI=!s7mb4OQtJc`>8uBhfXV?H0
zvthj&Nf1YX>b(!usx at 6XrhRL{3S#Wv=>?-`cn309ld%^efRsiIgU^s%zFns5Di=)o
z^6;!V2pCcaKqgwBMWQfwAfm4DKQj(*7c--J>*eX~u(tSmyIx%(*P&&i$03|Cj3Ebn
zmMquAjl;|w>2&<ZQ>&D-$S4HG{vvgqk(!k%(GregVOs18to1&a{XSUxeX!2^U|rpw
ziVpkL`gq(Qu8Ul_22ql>?Q-}74M^^fo~X38?LWI!paVWLnRdme3L(lUK}bCmS4bGt
zg``tDt at 6iVv`D9&nNw*OzLPc6Dn4p;HBCk8 at n+~}b*m~_%u+E<m>~?3Txl+{OSx1+
zGtT{IxLHgE5#u;aMq at KL#{wvD;ipq6w75V+2wdVEtTn2oi*RN55vE0~UUy^^DMZE%
zRzJcR#jdXFNuJ79X8#gd;Yk_>ghSk3TFD at kd$<$?(vkEddA`4SeGVD|eCoSO27nM2
zDY at T@fgniHtq}e^X8~?4HY_guDd-5o!IT6y3w^ms at d<`-lCUsd$cRhHReHXxhGAei
zg9NEL7=?dMH$?6cia9Z$)P5>Gr!qy6=1)dyp5Ve$CL1Zf*Ygy90FRn^kimDJf+ur9
z0$0t-MLrd2B(j7q=sJJuG>1JUEtjXYc-re2Doctawj9~$sdWujVZ-2ZT4zeZAc;`k
zSgSECarFm^Pe*~wNy`W}DjAd;|D=$_0WTl6D3}u%>r?aZriSEju23+`!o#PBm-Wk2
zufyb}&~d+AKb=lLdGpuy09?s(ntD#7bL!iWCnIyU+N6-$+wPYqd8hum-|SA-`sHoA
zltWOxC~Lc39$|F5^%Y^gyg}2KHL#P%^!m9xXfGmZFoU1UoL*YfxxovRG!JnBpL)R5
zi*&<Cju7&{E>~;o%VxJc{ItIA4=>A;vJf(@!-P!jshRe?Szdw|vJN?*S}|twKNTIg
z+CgUY1bM<E*aGq{fKw+=jh!D3)~CPrhaa#$<$*v%sKw~CFG64dReO~;rL5|T7a84v
z&ebbA08fZE4Nij!Z%{*)_+TPn4NYnA6uDCbn^2xxNu?^|!xiOGM_z)B%L$tZqNu3a
zAvC4#7)J&^k}UUGbi*i(Q5 at Y2l}6N{oH=zA8>98ekoMw>01l3DLW${aK(a>T8Y1CQ
z4V6anT&e-gJ?YLQfzd!@sJnoSjXbra at eBCPy{!@be#Q<Vbv*qztf9IT8S>HsN3aCJ
z=%Reuy3_)M6Ni>B!HRrZ0eE^?y?xoN9x5F$x6A3sr1#UFQLScSJOSSTGh+k}AdmXO
zR1X3Q?P44mi5v?9QBY%EK`?_stVvl-eH5gFrrk1TE^%O5VBg2KX#}RUgFwDv#^$ym
z-Q%Ok;M5cNGzm9 at acS(8VjOO-AXOV}oz}-wVa$~$qlo~YRnK{hSd3h1(0hywkI~pQ
zq>~)O5RsS0^J<#uEbDA at fMfnxIn}T?l51^<duLSM`SZ-jGu;;9n&&AYq=p=O6KaZ1
z<eUz*o`Spna|3RId)WM0+!B=Q5H_nbNy$zWM`M1qHYR=qK^4RS<EMwmBX}H--}k52
z?c2A9a(znRA|Lcg4LLFf9*x-y#pD{3TpgfUb_ZnAvb=QCjp_6bf=px6VIymP#tRt1
zlyXyw9zKGs=0ls<5tS<_;pW{Mz>*tA<w#35LbM>LtTf^`%wpnZp0R{*Bh%bP&OtXU
zkjFKTtB|;_fs`Cdi{%w87TP^q;;`Hu&z`Tp{8_nS$^;rKIStw5_!C$Oe$!gLF!O{-
zkBt;+CdHm>=E%9{V)LYgVWgdp7_mnPR35$U^7!3a$#U at L(iSRDgGVdl{Y1d(SL>xD
zVI<!^DcTh=fQdY*vr2_9FzSE|G9465z|^>6oVF_bD`dN#+_{mW0vMR5ttv?G-Ox%A
zSY-}qbx2vGt(`C0F?X8L2emx~0*v)sX!=9U<-*kvz{nv at b0VmJyQdK|i&v at Yuk2HY
z6ZP$+LMhqu^;O0_XHAqrU#^<V)#~P~$_){VV32YRA{va0dKHZqoGCS3rB*rYSO)Tg
zyw+2T at k#Kcr^vO>mj21UF-Yw0-KoS;7NNeG9QjC8XS=xCU2nfOR{Py)x!J9sEkIk(
z`FU90%nCQ|*REVNt|i0&we-vs+ENbPQN20-XoUHNjqco551_E-TKWoT-33H`V$_QO
z1-D0^Y?OD^)LZ1a+q$R0$HXaTSkHweoFt$GZmk58u7BR8d;(`}<;{wl=d*Y2D$0E&
zWFn4d`W~(b9(uw&nH6vlnra;`VEKbnb_XSu+Y93w81y8O+C$x;R>Mkm$NfQ8TYuT^
zS3j)H%ktY=qfip8Pig0Gc-0i-srjXI(FzV{(*Ce8s4M03&m}6ikH?EhgnqT);|3Qv
zZXJKvjY{dxr8O at YdusKx#H>hg&>GsB9_OZf33g>_6G9v8PF-XCmWHr*QX<A$m8D$1
zFEpjqO3Pfeq8T&BuJWx?>{C;ym%U1s4%>L%t7E~r!C4{!_Cub46VIh5jcdx+sH-|S
z at VC}DV@?Zmti6+o5p^|1ZCBS0n{HtwMP|cms1PxMJ3TQjlVQVYl?{05*6iAxCkeBv
zXG0W|Ft#u#dKkDh<%d{iAPh_PIYB-svNos at NuUTjHE1Lp<DgWf{41l>g2wuT6vb2G
z`|@GKcoEEt+$<)*XHFP3ll{3c6EVfeMP~XG&MeM}8NeCrLL=3QAz-Z)o?>~Zn(49@
zOpu8g;L$m8&1B}%Fm<Q^*J@<YM`>W>{fOe<QYBJBSgnpl^TD7$?3tzn4^8D`E*ly>
z5$Z4yXO<G^F8xF5&V5)sdLK?0GstC>{9%X`oKDA>PLY<rWgJ!s(5y=zS+F_Ptud1c
z!zivx^vsH!qA5=_^Jf&|j+-mHa`Mh_mPe7P0J`QD0Dj}4=_ViOvb5Wrmy%SO5)m={
zVod0AH_+C&?q1(cx>KV3?FQ;;lYQTT=gFI0nT<206C_HC2J2`_h-{a;XKS-Ntq)(9
zEA`6${H+QhIIvX*NF}8aN6B1&nWW&(-{>%ZYBlZ79nj*b-y7U?`6*mf2cyu*R4*!-
zR&!a(<kv+aIfDsVIAOKyK{p?D0Fa)`LWnwykoW7N7IFP at j9O_7mz$TjujylGNnNXq
z7knR6VtRxax$%>Wr at t=`%N6L+S(6o2QVM{k@=b<px0MSuX644~IVMUJd2M^+CtPx*
z)5*F1K^Y11WuTI$ZuLbge0|s~xB5f=%wb at 6wI(pw?;08HnDdacsoTM4Hq{ud+^m at r
zg&et9H at 34=EEY)UYf~~*<+YbmtEO9dSv(x1kyw<IoIV*LyfC+(V-368Q|@@c!5PEU
z`+5frmNo`zs4iPDHRc!M_ONF-&tf#IO`;1dzr=wVzdXZK0Ao0%XNH5z^bG?a)Nd3p
zooND(-B4?&_<pxp9WB1uZdUu9<t$e}Ugg($D0;>nrR1QLA$GLMwzutR^Yv|)Rb<wC
zyPgaFQP-Gj@#HHP6dURr$3niFb3-pn at v?s2EEUsnOI_^`hA?Uh at mH8uPll`aHg#^k
z21D1oZsab~PTlCReElvLL@&<>$+9Zbg=!{km<Va6&t8MUNj8MK4#Jb{+h|fByG6;K
zA>RgC^0PJubt#X0w5Vf)^HL at 2xnP&yr<ul{>b$9P7+5wt7yW+QJy)!+tb{aZ6x9#A
z^!lY!4`2-I<BD14bSg&9<@tLxC2^rqcUzKSi<jz4P;uCN`=-N+n2ttjrDM50uY)uZ
z#{|W~A(i4q1yYnb=u=eki)7BBukz(G*=P+DTX7DGqO%RC$1y9&KdLW$3p at 4Hq`|o@
zoy)|BA+9eV`m`sI+h?w7OU|>}TSm#>%SPBY_L#vq!AVTT!ieffC)LxYhCVsUtI<4V
zPFAK{c>$Ti0qpTAj|<>a4ekCo<~2`;*yFZAb~gwG^%lw-$A*^d-DYJ>pOes(PLeO!
z*NBvpJLUl=@@-u0{UvrA^7>LHBBl0~m9G?Yg~ML2X=I<co`Jg?@<$Je$3Wb0zr6Y`
zs+!F>JZ6~S=@nmMaCt8<bcw8>ed at IPS^y2 at Wi%(^>0xu+4+h;~qg5_e3dHR!7v+q{
z_1p8_`l=sB_U5c2SJra#y$0Ef_2pNYSyUN))^blj$H|DuGJiQ(W1#|k7)PUili63(
z%KsmGZ{MFrj-?I%?fDei%yakJ4LDTsVsKC9-l71TF>g&lob>Ge_+co=Y%q8LC-Kbm
z{n;NKNmV7OBvoPKbkgnKo!BlNy}unD9bK1GH;uZcA at JNBM(kd?@LIzVxn>Ac#0!@L
zI%&D44?a;B4enAh3?P?QwNbMvP1HyL03hfMmu?jTNe}PV&cG<5T*w6pxS}02Jo5gS
z-Tuca^NYL<(a-H)dZxSwuss?DM%rf-tZc+XF?N at wkm=)NF>DNqQc?l9P)W|J>AdZY
z26DZEp-&JV#1pV-LGQHiVNE|+`-Z4Lci$DYV-ByYBuqR+y!YPf7gB9nfiEOL1mGlw
zjSk=Y-FQCm>1{#hJcGlE+OWF1GQA-L%4kATDd<HWzu=9!gT8d?CZC8MqM$p6_Fb$(
zjL$r8d at -n%5{10}MMnpS)~RXR+imGWx^7<|t5<gni=uV|nXI>Saz=zVWwIN5;Phqm
z!=*c8D9g8f+Y|o^wmfm8<HCcza$Ka(5TmN|fhRh6N>NIJj#SB1N_l-Ym6Dwzn at Xva
zN-9l}E4qiOl9ZK7Dpl#rg;Y|-R8py0qFhcTRZSsPEu=}STFR$ND@}V<i)qSLIWe>s
zR$O7|>m1aCge*H%*|C^mNI0G=-AE})W5wn{5Mn1+rI0L=qCrZ at BIRU}lVp)<vWS(U
zN>++GS%yko^jekiAR&CD4<8MinlV&wcMOj>Zzj`^F~4>Su{4fpU7-U7dAfb+47zG?
zE+)_!dBYf7RC553auAnY4{=xRXDxCd8E9T0jJj}lge5w)UfVM{QEOGD1~_PYv{35%
z1&AI&(Mjog=dFPTG-e2|L&38Ol#Y=AD#tKs7)}-Eyn(+PFyQFhcY^>eQ?K?noV8H|
zkdgGY<(|_@@gn#n9Y8S+9}gSe(CpS8z$%(#jCoNJ^03rt;~!d#tG5jzrFAqRNkFTn
zDK2ihMx&opq87YP>bKyHa1)xsScMDPVfy~S|HCJ?TF+}Jx&#2OOsT)^m_o^U(UmC!
zVpVE+=EhN8&C!Y7?|~nzcp9ZI0_d7jkKyt~qsbkOhrPiNJhPw`^)_*a9tu!zdO>DS
z=|W?-bXPH+18&8hzB2+FnDDVN81x37YJC7~Q$TGvYv_|~t5%j4R;XQ9eQ`OxU(dG>
z>es0kjrUqGVv~h42qovWvFr4mTC0t9cHQ)&PK>JZwdYrBc(=P=-EZehUwXJZgoiT&
zX($Je{G0fI1y5 at 5HX%O-SIc%A?+l{uz#Y48Yp4&_dG|xi)({Ur^=aKLh<^L{i$=3(
zw`xROdFcSg517Dhyj}9Bt?;?tkU#ecAS(}?hc$_w`1qfGivi(!3<UNuD9<;mTb}?N
zrvrLch^NJRRz%$g+_Ng#7~->?Hz7V-0HO0tkk8g}Apm^-+x-#&aff|sS5AvI06w4W
z8SptajdVKQzR;atV48muBxZLt^YMV((w$=Af5PKVfhn*fF0%%KISKt)gl2xF{7!C!
zM0NO5jcUMQGMf;2wRp{(&qjpUtkEs at 0o`mu5{|<<M^$1d&f1rs0^G6A8&?B*yc^tb
zw9hF3hc%7<EXc!VXyNAv4o-s+976+^V0{DV-V`XmdqAtz!vF``+G;YJTrKcoK~@%(
z8yg38`z>SG2H-v9DbNDm^$MEjb3 at ziid-9mpLLYOR)(-uMomPQbvzTctTOHWBiGLS
z$qegh{;L;!+CL^f?NiZblM!x{uw_%h(<VUNCgIa2!q5Hz;A3Opu&Gd7)fldNOx4Fh
zx9X${DWoJ6R}Siw;msOxR`D6Y(Y<$-DqX+OzKY|;8YVH<t7*CV0)etw02jCM)-e{P
zQPTtM5|N8U0jFuo!aX0=w4k)-U;qIi!`}dxHt~t-6QEi13TW2iP>szR`_AxJi<iT1
z5|~wnWfe_nza<*$ju5LsH7PLaVc+ezE$6k12OgF@(xI{Lf}+aZV~{%;&3#{Q+^XX-
zdj5;@;KQ&`qu~l at s3z?1KP&+1bE1}hYjC80B+Sv at 5L%R*T6nP=><xDG>9C^Wi(d`q
z*Vh3ZRX~o)(4c!j8ja(Os_;h%z^E2|F~Ax%!HPZ-bQEe&D))j(`V}!rWz12*7TTaV
zp~3g>0fH0?T~5~_WuwFsuuOxe6aZuDl8cG^HC^-%`3r|5>CJ`$_%y^*8Sa=;3?-FG
z5RBCHDZN0dJ_%BlHRjJN4^5V{*Z3fCJ(;i3Kkof|UkRT2TfnZSMpu=wOyAt95Ki^@
znUM%_o)}*?`jCVs)O9<i;Ne9}9SkmK_-L#t91GPKl1F;wbcm;5t?me*D#NGBj}df;
zr_r0$B~~c$Sj(aN<@|c?&(M9S`28jKS9T3g|6a_OAK67g0%B_L49UM;Va;*qPj8m1
z#p=TYYnlx@><sHi5`<<7a8(J_5a3m{Scbm=&gvfzL^T~us*K60 at 6!k~^#%KM|JbL`
zhfFF$5!T?{`miwuL`LuV5lmlTK)((QC^7Wbv7*#$vtwhRZ~*Wmo%@P{J`G4TF3O-p
zzYbJrI>1iW4!xysZi=*so&CvrvRL>Ev>YQGXApaF{{eJJ{LAD)6T91YTnV>D at Co2i
zM$%$>#^iQ~?TiViuQT=m>q*U&icm5uiHP*Z;wiwMPXxQ<AS<P35MFCMJR3e1;gU$O
z*X`Q!vVx-R!<~-~XLw!8qV43)&oX#{Bhhz+wxlPq)t?XOXPtjB3-5Va-}NBjfjI^5
zEFs)g_sr_n=eq~%sQ&SXV_Ze_zxN;gtJRnAk^<cV9?spuN9|EpM#F*zC5E{%4m32n
zOA)t*22fKxf6mUdPcevu=i<Yp<Gt^?+TJ6|rwYT2#P7F~pjF3BH&LWT{!Nnd950nj
zyH)cX{cv2YKIf>DrgGb+Wf|&NVJIeSLj!fkfX)E;_3&=JnjO(~G+2(wcmK;BmICAR
zWO1Y}gA5$Y<0$3C>5mR!%9Cu`Z#$AnrK8*(n)l!mjo^yQw3IYQp8Rwp at VmlCTx1oh
zMReGluYEwNJW^fOwd|fM2g%H!M`hFi;yxDTRt;nu*`G$r%5osJ>aCC<+p1zVwl{G4
z#a(3O5!O(xe7<uv-yTU-OvYG++gnOZ3X<Xiz8j#bqGVViDwQ%^AuwEh^p|KrbnrNy
z7!O;D4wtKC?q+hkp3LT}Slx-OD0YPr8b$^~)%FvpOIHAxwe_R?rjzw-6U~gfwV$ix
z?PJT5=7l#L=q?Tb)asYIW$Sd^^B!JymC7H)vaG?SU=0dB>X(em$x;RfeHH*#@7(Dd
zSeTv<oHbYs0Gf4ke?^gG<TdxJz_$LbFj-~9QZGS(z_ywNcExX1qPOxc<m?k(ye?{@
zJ{Jagqwa-Hi4TR^7s)d3hRHJB#^q3V=!i-*>|HvSx`&dX7`*a%ex%xG!J*|*XeG?j
z9{el48lvCvCfE1u7(i+dP(i;RDBJHIxc0k1rwta4ey1hh7HZIH!_9Czy_u~(AaLvw
z#zcVI%H<t=!kvhxYj4Egp at a#UtSE3nqXvZKTobADr;vZJk9f7*)nwz(RK?~MioUDN
zgoCSP7`>VeRu9%&AL=e0cZcx}RJ(phZM{*U`|>WF_$(-KjnI!8WOTp-R&D7ve|?Yt
zB6l0G5#I_?oyCXMdcM7hp%LO3PW!B<eW)A=^xbBXfTJsSxUOo6;7KCj{i at BP2eZ%9
zhcg4+m|)QA#k}FDW=O<!jDcA5a*_c6p~}RJtgNcnzzfL08`nKc>jKTo=pcCl8OkwZ
zmcgA at DJ3O@>sKumswq;^^;00!ao&|HCnbGTQXGL8{;@&^MplwcZR90pC0n3_4XfYM
z^pXx`8%#JI$J6<hOz<e!{O1N)xzG5Ng|6=9BZ_5IJUXl8e2XV4J}4 at SWkBjCK>*~e
z8=zV!>nFf%^U%YpMKHiF)<%k7+Q+bo&6wN?fZO5i&WHIHYZY(jGk=9@>(yj7oe+18
z;Er4ZpnhA^pLgpH9&wL=;7*3f)}d^FW0=>$sKsMV*?Q;dK?see*utPm!&mO-E`K5t
zf_mq!xMK>T4IHZU`SfbBNLu59xQ;`46~4_h1+cS8D3K)Keb?!<T!6vs=`61x*BhSc
zn&^DB*+N%u*Q><>cdt?xgEU%R-?GZ at pv^QjCv6tAshB?m)Cm4nz2yKlmd-g?CEe+?
zdd4i<t>F+KDX4fXbFW>otXQ$RCSY2qi`UYPdO0F}?{@S>CNHSfi*&a)Y at 8xekYR5C
z_&5F%-WhL*!8=Qg!~aR|Cgz)u!I1q=elfbmvv0E4tiVfr>H9N(_7l#+7ZN at 97kA{U
z{T4_9=1c0)9eAMg%|Ro?n~8omIpzpra8>Nok_DUieC+l*DN^jaDWvf4&M;ZbtJeql
zYC1U`G$k+hw^66>o%d4Y?6jSc&X10lyKn{_gBU*1k39LQ2RCSWyN_bD8Wu$eA}=ZW
z>(zEOT`lxuUTd_0K!Xj1%$HVwsC$(M;g^naR5)(Kbqu**)P|<fM`%boS_TRbNi^Sp
z(EEm?zhDJ{cYRYSondP{Xmom}azrw=p}LLtULSl*lM?Iq+YM4Pz0BFr?P-VA?c{@e
zaUk}3-L2?+QAl{p9rWam=Q0Q`mYmt-ZmS%0E<TPM8p64huiwRvZ=5;a$gmd<hIl_H
z8ESz42Uc?}KV2kanj2kR0}xY_LKB5BX3 at giF%I2I$`-$d5EGGbml1sqKzIyG5VKCT
z2Cn|SpeWcMXo1Fg!NEnr(mBg<a<xYLqSZ|lyF70V8|Mw<dQT<mt+N&Y(=^(R1WFWU
zT<hDG?h=U?drxrN$DK-|XrqHio=!_)GR<MVHTGIPUB@*?T|EOaCl`15RY|q_&d<q0
z$>}ueXXzR>5F8I%iLz&S_e(JXTK&sJnP6$`8+TnnHd(IiCD-AiS8KK5fkmQZ#~qGG
zcEL^-?0F|Ac0QF{rI;+&b>4PTRJY%@3;9B#*m=MBE>XyHn#l`=*J=y~PH>Z)D4t?K
zx$kR@!QUMBB2n at kUiOUoC>5hb4as7iZp*k81S^#86bS3ScoNjAV~tL$Y#2j0*fy-a
zPJJ{S8T!u|H3r_L(>ACxgI2F(+Wgy%v)&LiFN26{NFR6M;61S^pEXRm7?KE<Z1??%
zTP~R7z+J<1q&tV_ONNeZ)e|&evfMY?ruj$IHO4<?sIZ~F at IcUQyd`LRrcI&MyL1M?
z;9*EgMvUdp$X*+OvHV+=vk(ZJO=chbE%MX~%b5dh8Qb^h=Kz|zrNNu!B<WN8M%=={
z!tqSB?TTT9GP(Xc$A0%NQS7XDF-jCNg1~TcJ>5IuNF=~k5>5wIOWSV5tafgiQK6*M
z_WF&6)^zhrW6<MXQIX|jcpm>U9(3_=mC8snX?l`40niQ14f-H5?&K78DsHER=M>FP
zX;SOBuf00C=~EjjW!Agkjf;=f?&16vtU#;jM}GLGr-;)r!O5g<M*g*(XxF|4PPH=y
zrCKV&wSc=vY*|LUqjRVr{A(IQpBM*QoZ0P<!^(CmG0zB}-o}JpsMu7*Nij027iu=4
zf!?#ia$P|`k$**)KpIf*H9UCaqfd?eYsXTA8Oepo$x`H_aohRj{WylTDToq=3j)SZ
zP?iU88|<x?_r}U=6TWN#yaIsfXc~!?vVG~iXL$f#SNCGv7&u<TP#*6bj?4gJ?BVrI
zdiC-Q+;@*<w3Er);+%GR0=a<PF3w%2C}5nj?vdnhkDz~hG}oKtHcxZ_FTTKa<>^AX
z-W2q2`c*4|0uB$^0U>tSJ4qb*8)y9p-nictDO?y<?SECixL}M;w)0OuYEPCQ?k697
z)sYJ*<!&EODR=vIDCKTnDCJ%#<z6V|V)NjIQto at Bl#5>VZ`bpyd*DE6!$a#1fwGfO
zRW!77{q+hT7_`24_#o75wPla_y;0VQjC9`y^PEf%7RO}_6%%mFYyt^gbNI$88fn84
zNx33=t7j*j3L>u`?zXEB)SXY|1V%Zgc$``C0sK{+ev8}c+4oxe!fo~8IbtlR<8<-D
zH4qjZ7IfZmTocFD_?=rb3v@@icW6QG^<qMJ$r$dPJ64i_T`DJulq}mQa at kLk7@iHR
zs#)Z$Y1x&|sI5NA5Rryki}w(2<oL%v`zmMB9$Xp=Q8&|;jhp1BQ3M~3FPkmz+}s|Q
zy+j#!yd-1GNaMNTsVWIDnC5W-66RhXHXKvN1GlKk`QqI9Md#lWMD619s+Z6Sgu={_
zf2ZZ1JB>E{R5n1IIW67-okqLeauOOreZv!agipyzr1IT<1ex8=taDmgx!;mJ?lDwx
zAFrx*-cH98C(EWKiId||DmN>iv-8N#pXRHlh2pLZaq2XAdbom`9?r^IRp5s!Sila4
z{*3>BXLh)pi5<==<knLgWW4(&PWl7FN}yFewacfaD)7UVlGx<}Zn at 6n0ihFQS*OLq
zDNclN%R!01BDWk8xaD#(`_nhbHHW?(t~vD0am^t%;!Rw0SR%(==S4uPe5Het;NlFr
z#KhVX9)C(Kbx6Zfhm0(Bh|E~q%9e^KQz&Gue1T3{iMNiM6EbgIPRmV~6D+6_XlyPW
zpPY#lkIPn^rB7nQQ}E#N&{I-jMLcvVaQwEgFLFGd8jpW=$@uUTpGZmMdoqcM{5Rvo
zLoz2`PS5_Ai*eOO!i*+*JR-QM>hY!G3`F~(;6rf=J`|_mlPKD9yOQ)N#Q5bqY!)O_
z_ at N{UKct}WLlT7_k|_LghA!sB1BO3NoNzgSW2;NyTJ!P1wo_}g)girJUl~ANV{lhr
zkEIes2~>h;H!8tkAJ9<=aw}>?C5SXsf<dK2z)dXBr^-og2X4UBgoJTA!Z^>Nm=8Z0
zDD at y|fE3h&5%Hk7mVOn!!5G`1;v-K47^fIi(gQl4nH?}l(!>y`OFK2Q;Pm<*j8qVb
zq=M+XAQeQ(q=G1!R1hVQ3Zkcz3ZgWmg1I!UnTvD(89DR5KWajhL`{hHKuw6ApPCRE
zsR at yhnh+&X6M{;9QqC5zN^TWSvL&0T<VH3^l*mSi%xr|Y6!SD^96-5*;g?HZbaE<o
z(KIxP=o_L*MC^daF(9^X?-qo{XcE}-HT;Mu1wSH6$B&58 at gt%nengbSkBIickEmcr
zly09ML5lc|aUTXcp~QX2se&Q*AyRT5<|OVz4ILuV&><on9U{`vAtDVOB6>0%V!SOv
zjz3~VwCt>1zzbm2$`<qD0%&GKL at C)2(O%gQgX-`&L$C^jPQDJ|y>kfkQdsu{jzqyu
zq~J&tLWH{lnxdZ2goblhODqDM1jer5)Xzd%J!T&X`5kir;)$--^VtVqHCsg3rl8I;
zp(C at FeQ!*QD8{sizG<dKq-9z}I;KTx8w3rcf-*KS4h9B&9oM48ZUYn&lyVWT>O~@u
zlLh$IEns7uQq-9 at +wFsw&stUq_KfvvwSDt?=6`y<p4_7KXEa~Vx9b^6+$IIcmP^HI
zp}^at!fcdxOhJCj6-|rF<90i{f&(ng_j&`+=x_e_`g&udTmSY=x!8FUWn?fbw3Lyg
z3yRfj8FxYPBzq$D0M7}Dp3Vsw6i3SmNs3c0lH!yL*=ku_nMKgKzyk0>$C#duQKnS{
zLPjI+;tMn5ABve#6a)@N%?-l~8RIud#wb!T3K|=H7}smy?5*X2U=qFB-`wudAOy}^
z0GQiIl8L!c#UyYSbF1_VQRE9z<YS2<<GhQplA;);BB&!&={T{o7CsLa%2u{olC&U!
zOA#e;DMm-CkWEo#f}*aU6n;06fsq$B`K{I)Z?#ymzZr{Tp!FrOI10y6nape_ddC>K
zqr`;w!s+<J>G;Cw_#JaP8W<g8ZSg|nxL+d27p}(ray5q5S|wK_QBEoqu!s~()yP1j
zV`oGO?2MrySzu=*xl~J8yMnVRpJeS5(ePp>Y*f)T3I?MvI&lq`*&K6mE=Q%ShQ#rR
z5;z`_lH(DXI39CGj>nwNXDw&)S<@wHl?#<(8s12>58lY&&QSJT0VcZF_<#M@>rNBz
z)9tqMdO>t+$*J60a(cIxoYJi&mrQmUDJ6BK9Z|)CiIQ0`(SBJlRUDYXEevsgE!f%W
z3Cfi6g>0E~T7NuKq at XG5nIdy3m?Cq at Op(fbc(+9%aXEmc7;k4a<zz5WMaoI!Y}sqa
zjf#&l-X3Z`N~Oe`TW*SJi7L_8C8`ugc$}zGQDK=X(#&It5_l|wZb-v4nG?=!!orke
zfhML&L~j6TRVNgxSA9jPAfl9SB%O1|D(T#cm`t<Y>o_fQI^9<HZw_f2qu9 at QbnDP>
znTYqkQ!2Q!XIZcun+Y_ZKqHC_G@@bdDq7A|U5 at nRqCw)^jSH8!ejsq$O;@^YiTArA
zljvH<+^SqY;l)la>0&1*UhL#d7dtueVkf7**vX~5*vTm`c5?E?PA-0}BWI$#&B-O*
z=H!gGIXUxfPR at LrlS{g@$(inKa>hHGT+*FQF6lN#C_G+1<;xINc<fptm+r<SCkxU0
zlAQLsBWJ#V$QcaYxdelE&S3D)X${^voxwY&H+ToL*kFNHtx>|BptMVi!EW0d$Htzt
zf^ep59UpNl+qh9XXCg|?r6o$u8BOCkt!X@`F^wY?i!#!)C?gY#GAOi#LLSberE)22
zS>i!a;!X~(=pV_Qj11h#oPA#6P9{Yxm7#2zQnj45CI7CFZdh4Ts*Ei4oYZ1BQgKDW
zB|2Zh4 at si)MLIfP^bOPb1{$hF=Sv#@#Deirw)26#LQUYyb>VIVzPulaOyEljfP1})
z3s5Zc1``DdDyIwtB&a!w)s)eoYW6KN at hJ&bcc_XJH9RpE^CzSMOC?r*o(~nN_)yUk
z`A|_xKGdj)R+UV!a=8*N0)IkkDpRx{DpRDSGDSuzQ>3Ia%_*r&b4Dst&cQ8=q?`}H
zbxK;OP|VuULX`rzn$me75rj&s!p_{FNY4$L;}L{)8*<2MD#;)%u_)3Liw0Y2b33{7
zvj{KT=z6ibyL&+JLA0!MOYJnq04$s?z(4>Nm$9n at zQ9AYgB6*g*4!OQ6gBUA)J&*B
zm-0-gf))@ko9cXIVmztgAmKPq$ykByDvvTJc;c6&?W$$Fs*UP9A$a6D9EG{AW_64)
zZaTHraC9~rjLc%q6RVOhHIpblD<?%eftmE}(2{)zgc3)zn}OpBl2|B-Qvv#}SSXQ_
zg;H3Zlq{5F?7|Lkg2!&Dnk at zUeF|DiA at v<;DT8?wqoow>MK$G<a}`-7{{%k_C$Q^`
z5mCg5!4dgDb2j9)$rs+oLqvEFJxCgL-E3&$MyM-qzi^1#Bp~-~fMOMLAtCUr0w?ao
zLs}i at tWj&XBx6f$?7cm6WObYm?>KHpk4}sQ!n$ipOneW|8|}XMUK)qMi!dnCkeQ4F
zocs0U7M7&zYrIX|1WV2=e&GnEx9V1 at oG-;{g})cHFY&Oz+ty$xyWxju8%BOoaiXaC
zNs*49ln05UNXkmxND+=twL>Sy923a*x{_}Sd>L21Xs-QPsLoY^1ed>9mLd4$iw-T3
z1os=xpq)?v2kUR$m<%rgQ2yiMmvX#n-l&^Uek at _xUu@eTV&%VBO2EbT>cfgb2{GS9
zaVc*1&U#7<KH;4u3uUF8t=K42u}-qpinz(gsAz*7M5dyRh-k&#v{l#8{veT_mebM|
z^t9;d^t4Ezr_IUaw8 at mUp}UxtvR10YzA0<N)1`s3R+#Yy%37qRtj(E7Xw$RRK8 at QJ
zC2`xLWNur&t(4rh!iG$Em)fJou-6-&!vRmNjVmZ{Q4$4iXwQ2b1 at 4o1Z-0C4U1?TC
z+`Bm)^X at b7@}ji7yy%6OSH;V#VCCf=bjHbeW7A6_;|(rg&1AeeITeYFH<v)hE9M^?
zR`?sW<`JgcTCb;ZdxuS|+0-{14wud!D1inTnQ4Gg0u3-S(*UDn8epmAVr;o$cx#v>
z(ZHIy^KSn{!^lW9jJ`jjVPVQhM8hbVXc#3D4F?+z;Z%&Donuofeuxd`COIP)DV}6-
z-wtAA2Ow*`GLKNDgH+%jq+vZqNvy{xf%O=D71m>vz<P{KtjF{fN9m-RwXlX=wacN&
zRf-qmwM5?ouO)gquO-?CuO&+2walq_EiYQbL>XX5>g~jkiT+p&nS!PrW5^_<zgo!_
z%6Rmb%Gna<XQ(176yMrt9IHDb$|e5W at YV(g%9v~LO#<232l-+6sGTQ2<g{N#eaK at A
z(l3;0N;rN6AxiePxR?@IUzd~srYgo44p(96#4BEjtWm5^L0g?dy6O~CRHtC5PC=?p
z5`SdKyG5M4qsrsI6()d)EwWQ1SSUgq4Fe at IFi-}2?K}LL+cz@`T1p|Sy|PhqKt_y@
zQga)nAg0VEb5FJ+?n&_rA(-GklN5wL`?=W}j^8S8J!p_EN2h2lC`NmklSwa=sW9V2
zn6meu%zqi0W!3zbuo#w$cGfPTjFq=a0m6?=Qpw$=Gm=UUW<^I*nM+SnX_lO9rt|qL
z{t7ovWf{H=iBnl}3tkeHC6cHtqbI0u`$JE?l0;#uMFL4=m^q0I(?IEGV9P{_Y?(-A
z%Zzhna>r#oMJ9SKicIudQe?g`IEuJiWR$4G6l9LbMCM4Al#^oCD#Maewu9q^%(aMQ
zu0 at o@wJ0zx#>g2}1dB*Zu!!OWi%23^L~(*eq#{^EF at i<m128A at NXH`QqK=O-Mzx3x
zREtPUwTKK<i|84s7P%LC0 at We`(kv9RHVg{Ou7p~5GD#RpAPGYWBw;x-NthJIDd1n7
zH%tO%3wXnXgZX24!{V%AqTTWN$ih at qVIoqtn#nAur4W-!gaafFG<D1q4p3(ZV0B)v
zNl at KJ;`2-5A8p_RfOa2 at V**GnR$DZG=Hzh3(2+(4C)Q~6P2CcKr)$6nSU5Q-tHH3u
zEERwnstgRpRiprcEpY1Zw*WD)3578>B4ZTLk0*gaPLAE`HhZS#Z5l`V+m0y|NJx~2
zFp0e`7vrvreQXQ{J<+oRkl^dM_;_`Y9|I2D(RkP!3`c`ToHQyr1yJ?5`!}*3c1;zD
z(dkLyv~>C&Xtz}@kIV16ag*ao8GLl{@?XKn4Bq6Z<k=I<F7!3Do~cXA!S|r&;EM&3
z2SZwBzPNbDQL=*VpN=m^#wYQ4{XRJOWTA#zGqeH_?>#)0jxR>Wr)tpOnu9OKXqUhl
z_#AY6u`&!?GgIXAG4sVHNyN=(uJkjJ^db4FghbLuR=g8}&uQ6(eAX&PD_)GX4{2EY
z(4$%Vki^=D(y{gt%AbJ4OQ!An#@PHem2$O|lFd(&P0i*f#oG&;pEAvSHJ7g-+d3^-
zr}+~Nn_q#j`IYVGV)Hx6t*1qh8Q$CzMn1cQtkP-G#-##AzH$PaAJNZ;_dbrhMyN=t
zQ#iFxAa3Prv-!m(2u?hKqVx2$e^00R!>0rHf^z-EU8adKq0v`_{0`Uw(SF$h(X+Dy
z=FIGX83Xy=UP%9fyB0B*oSxzj8Cdv`mi`aL3HfxSdz__#qutZIc{R`l=44vA^pty8
z8In2oqC&OmQW(<H)gdGCTqfDZ;GPY7qrURc+jLrkF$tzN1O5aDL8KO82zNHaVJ;U>
z!-OdF1ENRp10n;~l1y%j%v5q2xi^1H);^S$wU0h6BuHK5a<(AcZ0$(B7wSh{Jl|Tt
zDc~sx`NDd(&bm&!$qx#$?KJBOT0Rp!9+H^!xJS+-&7%{U{f;N&1DnWRN%wNvY-2om
z#3n)s>%a)Y7Cs#(Uv3vpK9rVCPY?|F^t1wI3O|WsFQ^dDv6oYD>_uvL5=7f>bbGPr
zHBV_<7E#S$hE(iqiCop3WXoj^a_ifssf!aYCDGCS7L0Z18)B@>B at w>mb|rj!Zqhr;
z%(?dnT0E4<SeJPO>s at h2(mOu%!h_RbTo+HI!t1<qzagSLS)kzBMdMU>1Z$pD#k%vh
z)pc9X%d4kapPrw3&%C(h)Z>R;Fp_5rt2nn>fA!g4<AV-dVFCggdGHoqI4)=N<?GIT
zy2hs;nq-V9kEh9X_?&Yh^;_NR6l_g>C^uXO4^2Bsppqc)<%>a}-5NFuc~c?0M$tA3
zbe!&)!z#Hi<~aKg#vE77Q!kK{68!vLnd2gq!j?eB*5VE_(%KYSvpNzgA{Uv0qwq8d
zZYz9j7O0a+ymUFfc!YaSIKpeV=frS^17)2Q2$@vA!Xp7GNaFb0aQ6amn&qcnyt_i9
z(djEMOV59KV*x)|)N&1cLXppJR;37+hPIst(h2SWmyYfYrK5XONWI1X0N{L__6|KG
zIb3*Nz-K_0KY7E8`!QTOjl|2U9XR9|9FbL}q+x}!h?pc3#6{F`AuAj3tQG7IQnJBu
z<Znev{#LMxr4xMm7I@<FX#JUY<$NBZHruL at VN<q3TrGJ66y8W{c+<F at xUVFv^G063
z(XEe1eXy5#tr~?=Vrg=8Yot(ig+SNXCsr_+B{B8ww~BEM$-tZ_378W}jBBCWHnqib
ze%ynO!7+dYdn0(n*KWD*4MLq3oKiIFwE_(kiD;lmK*S92K;`wpF6D`V$F4^2m=fSD
zQ7Q^Dlt at 9AKtLuqmn&Gu^x;4?CIP(R at b;jmYc0Y)CRqF$lrb#${v>G4=i?|tTF_3E
zj-w3ihocN7K!mc*IGLj?_h)g~${b}uO355$a!MqIBBf*=Fd-$G2Mp<Wz>onJmCU;e
zV}Y^@SqY#c4qmEb>q1(#E)fB=4sc@{4I|Fxg%a4jf~M1AsR}KoL`{tV>#Jm+DHMtT
z>?AaU3Xv3P5lK-ZS(nos58g at V^5Ad>xXp`z at g>rUn`d!$uc&caa3|&w<GGf}I~E@$
zkcV*$NEa;=US_qg+SDad5Q0#dKgn8E+{UGX;6y?0%;r-j8`6n$t`s9`Pp9Zfcv~Ev
zzj^g~bA?a3H>>U4;{L;{NAi{-1p^sMWFQO1-J`g}a(~_vgBdb2kOhTIVj$xU^h3!A
zuOb=~gDKTm94yx+K$(S;sHao0fFYqUW)?7{U;#rq7BHk`0YiEgF!Wd!Fp>VI*H?Ph
z8#uy98<uTYkc#<oRyuJj$f}TutO_NNRpnBWRfSKC63D7JINYLD%$~$c-#>rv$x5wQ
zNUS8Nt>dCxtJ8N*^i2;*w8w7;_%LZmL_wAnZVQD<C2Qj~s|X{y6t9Vbatb9;PN6iE
zQ^EAr^DGIQTfo|+O2Ww26iY?N)|At+H37jNKJMqx2%ja_;Il;7z0v%3@<FyUKnA0l
z#?*^X>@n2gz<Q$OeF{Jzax%4(a9>Am(PGq0ZvW at 8cH?H at ZVS*39rNv8-EphseC)Q`
zrdn08WCttY?$k_3$D>rSs<xh*X+Qi*D3PitXnQ at K64wu%mgkNmD0UtO-RTZ>?0Stx
zABtBkxbHOnuHIP-9+(z&uRNL^;vJw_ at f8$H)Ykx at X&EnAsT>2<&`>N1{4&bDI32T$
z#FkU<IJ=QE=}Ax?O<5x>6B=$3l*~dR0Dv|?an-A&BpF2^73>J&8O!b|7g9C4eeTa{
zu7J#+<DaSV!r(`>8?At#pTBME at bMczkDNB1xtbkJVjl=6<-i370e(e{9)fDIZg4D_
z{UTU_<7@^(tH;?4f|y!1gPfMlfCmjw0xg1mKyP$tG|_PXu2MOvYOE0FPQU-Y({MD3
zo;T{AH8k3j>v$esWc6k+e8#Bv2IGPjam(wtRh?%-y;GHM4+G1<{Q at gj*OS}%;z38!
z5IgA(M-qDi|J2vgU4*x49fGgi0G{$+q{i2X4bIZZ4W088Qt(ev-^6{ll{Ch1-NNz3
znSI?xx23^^ueWW at 1HOi(z0vJ at l|n^#J$mlI)niK?_`cC5&rLKmDuaquu4<?kTAo$a
zWa(Y#d`-NI_qHyiT50RbF>Ianx&;l{O81?e+z-l*aPcYL1D7aE!|?L%Ok+Uu?3Qw6
zAFe+7OEloo&V=QzRxE0*7oZ<mTE7rZK%?Rhm4KXq6$inhez;sMb2pRQ^<*|*NsXbT
zWr?l~&9p2+HsbDj2`oqbfyu0M84w{^rr9Ply#!^Gm|k+Jm|mLox at PsnN6mih#;{a8
zA-B#YyBt{&j4Ut6#PWhta}foKhRE_FDj5)_Qh at f#`65d}p=C741X`F<8EywNrDB1Z
z5rhN at ei#gK3ZFQB$BqX^q4#f2$`!$G0#bkLy_brXlO%?o7RizdG~Ol(#Bh at -1YVhN
zGnH)F*g&IQG~U;GGO5d-6_qpz;QD!RO>XL+A>1$zO{r+GDr2Q-d5U+prK&|as4Cwq
zMNT<ig(tz8Qso4QV7NkxY&1y8MuSXjG~u)avKi at CrPIP&Znv(P$PxjKumURyXk_{s
zfiBg+I<pIL40j>jZ?|NXaTi({p+0p9n~=4XiFXDi at y?(`-Wl{{-kESS=Xhtt3$Hk{
z45zC!+HMSnAv`a-DuV=oJ<-cuGwlo+)ulqV2;^EYy6u=bKw_Uk3G6fBEu?~dM%+j(
zRWuX(jG*@ra9-lU)YcqI3A>9%gH=)0gmw&``h~N?@tiG^o}=JwG0wqY28fI<$isD>
zZjd)$%%`g*s!gUJ?*QzIzb*0zFmdR^!5ivpx-2+$7&CzlN+hre&E$_Em&x$#Ffq$j
zICjY+lA!!4cxN(6v at u#P8fiVr at RT3mf2DEer<LoChOnD_ol}tL;1;FZwr$(CZS%B^
z)3$Bf?$fqy+qP{_-?=kW^Ds44->%BTpHyCw%D?woD~znt;z9-P-+2X<iq86#hA4NT
z4k;L?G|rgJ3 at SD$V~Z4rLmWCT$Nn?bIEZ3OdN6;l;v^Z|9vz12LEZKu(2J|uUsHiD
z at qCjdKiu4&8K%UQOw7ZX($x3Eb%U^zU<e{WeZUk(8pbYx`4~K?v at n4ju0{!3_o#|`
z-B4?oMWR*+a-v2uqzzMr7#r1+f|jK$bx2xr(;bR&9w-rJHCbKwVMYE$ng6THsz8*?
z4Im%KJw)n*aUDbuoe3d~m<I|b;$1bzxkFB$;{_gt5V8Y at tLX!()t8aRjCYXtOXP&K
zSF&e;ARtfnn3qIdm1iaoMt+;t^8XBj8I2wF`%FWgMSwj}XN&_$63MrOvKP at JK0k9;
ziqbXy+4NRtIfRF=Z}KOm)v&Xd74*yDWfN<C;<xv)YF>xU8mcAiYP!OTKnav%AwWz3
z56-(z at jse|v+KhP7Yc)+2x{9>gb<b2H)F7d9h;B~rY{Qf!yb32e%l&Dv)d`-)%0o2
z^|~FXl4vY%N!~&g2cJx5039eE!G;qXtcgtqO$P*ht0?FbHQMEcU*9ceK8=`JlC=+_
zfc(5+7bWvzxg}uQg*J6_>Qfl;@L3c at 4afybzkz)9rvR-rATwbc<%TMa_BF4?2kUBy
z1`tztpvnM1fXg<>U?Kyi_F0GvK9!6MuDkO}ftroW%t)=W<yA9I0vd|zWHz9d))i|I
zm;rP-<;?c!Fz98BqIBf$#ZREEQ6U9cMxB7WO#Nhny5!~hFvnr!c|=y-CyI!{qv2Xx
z8L3`ywRA(qXvS)%WeX|9zzKC`FvT&N?pBzH!)uZOV8Lz)aRW&cm;$*&jy7w9x`s(N
zm~t7WKj2roEEplkp#55MYI?44;l%xyF2zS%pH6k{ugW`ia*y`yo75uz;Qsm3QIJWw
z0E;kf4F##jIi;QqVfJQ?2QXbJl%pYC&iql0U}hS|<j2tflvdxfMIWats`lNe!AFZq
zDT6uEP!FEQ1S*lf&m1a47T50uDp2nT&Zf%q-EsY4Q1gQ=oMO_=W~?a&t(hVTt4YT9
z=Il|Jk2NE+qB>i5-~o>n;CuImQ)bo|h=^z(g?*1ysVN3*mBQGcVZw6y+p#CxPqkpP
zg&d_x#QQA>;}l6y;}onG8ZiD8cbLyrNuW;+W4MJsVPBXQ3WLLTtjHpf6kx)m7u at w`
z2N3WMxO~`7g0B3%w&^6|CaBe#rs6malRoy7i-3$EK5)l0iD-i~I#QkkKAG#s!2_K9
zlEHuA_M)(ry5x2+_s=SM^6wzb(^Y=!5yJcsp`uS@;?gfXWshJM<puSgFbzEw#FO<(
z&{14FqBi~6+^cSneiW{>K}n!dtYOVTTS2qaW#Gb_$K=ki=;?|uUaK__uo$3}ZxJo*
zh}P~MJ#d%-3UPr{8*6QQ<_V{f0AdxCG1bLjTD-%pbY^@1Y-8F+f7HdgmKiwI1o|e#
z0X3i~AI0{jld*S-90rm3SeFd&fv&K>b7Ii`jLGto6Vscn(7$G)D7a>Vq;JJ!eqhB!
z<h6Z~!#Uk-xLmnN9?xlP(NiWCaqp6Yw`8esxY at RbJV6lzFvb@A0#uDFG*2(Bc=LFM
zs{*P?h9ie_GfP&YV);|kMzOF at khFNFGR{tqR=tAT)-K3XoW}y}I&2_%|L&V<2X8wU
zCJdDys!ZUUX^g-(T?C;=1}RLR3^r`XH8wl-4Qtgso#c{- at w0%nwe|ApoGczAV5M5Z
z^J-gk0%Y*zx#<2{_j^vky9-b+NBYJE_+bL0?~_T4;rA+O`ecZc^oan+scXP#`ol2C
z<Slh8obIVJ-2Y?^(Iq+wCfBy#p+)juPRG-<X&tYpKINJ?3 at QCwnVX3q+~HEFN)zj&
zCh(If2i5xs>}TcTC(^T3&{odWkwvyqmrheS%r|dZcl)>xpE0W+Ta9`l$-9pb0Qlr;
z|K at uGxXST{N;pvIP7qqzz{3e?h*5!43&dh$eOft`32tF>$#xp##A3E*AmsKH5YFho
zE>Iv|6Oyv@=Y_ru$%X0!BT46$+Aw%5jO5J)#f31N_u#KsnH9*!L1Vj5|0%mrkerkv
zH!Ve`E<&a*L8i8NeROLTt*#Ji9g2c!(ZCz7Lp5O$2CLG*`j&+{O^maxSwiV0F+7dH
zgl#uG9y^V=`xi>#RS at mL!-MZUI8cSD$C!wu$N0eEHdGc3wp$YRlN=_F9FH-O{NYo$
zCm%J7F8h%H7jid4WL`jJh55>m2==N_yOjG=z{%b+Er9rZYWyOzY<{gr0FpbF){Dwa
z)M_XOUrk}xOAG&LqiyErjWNOlBfl8U=EnXfe|wi#kQ&)q6eSU{R#`m8Tn~A^bWai@
z3aT9A*=X4BE6pA3a%7fiFN^iGSo~nCcCHFqkA8=Q!B`9&rhF;Eur*FtM;!<zeNITs
z)Ob{4`?QC7(MW-XcCj$8Hb0nuZI_DXO9E(X`#@fuPY%w-+;@1Ta?LKPBlT53zJU0Z
z%coS4gRt_<P54v!V0ino;vXZFU{3Y1bgN{KUX>lWc79Wz-V$cOo!Vo1UhbZ)q!DdC
z&^<JRPs)L=Vcw>eb8p&y#Ks&|5g-KFk4J#$F#-c~0DFOw80)8y--HZOugNhsKx<N>
z{}I^s4`nIQKyQ)(@opxQ4I(~sVpuGt1c+P=lt8Bp$&&RF1^hAaPt(rT2w&92N%cN;
zB}BvwuvxEfac@?YPvv>l_nLqe+nJSJd%MO{f9Ye$GbW9kRwS{20!e2#AxjKlhGZ~d
zMmTX8*00bK$=+NH5GP{}Ak=goFq98p$UI~KJbCzYgK5*R%h^deNn*ASE<<U7K(q$R
zAZPzUPj_d=<bZ%GQ(SS4Cn^soTdl`hN`QSbK~dpg3}Zxx(_%I`Q4E(}fXiQZgo}}$
zw;QlCMFHt`5p*iP%w^zZUQV_ at dP)!rHD#EO&m+-nIY%-9#mVe(H42lL%?K!HDvd#p
zS!;DU3a**e$j|2JF%e);(9 at mp;LYB{WTVNM)vYu*(b7sw=69(%paC;j?}`l2uGQ~@
zN_9qPevzmiSMV;}i%%C~7F~VK#1iv7o*jlO%Yq5U_K at A%YnlTN##R;<#5P*~hPAjd
zDOXm5iF#gPU#+&=O$A?o17J-SKv7tywRNg1c&G=;hvy&W#xrl!Y&w}%g$WqOY6NCD
zMFLQFk2ZU|7KtwHI$Ng9Z%ea}IbV9xOTy^3l}N(Gp%`XQUO^J4G1hJc5<W#CV93lB
zw+aJ}_`4B#ow?gpTE}d%ul*Q|fXx{4L(Po8W8E^9&h6X5a+4<LCTh<II!?$~=<2<Y
z^mgNGE)q)$uyM3!WZNY1kLWIQ5F9TTB?VWivl*sslR7NKrKWt-VVQ)0U{BH)f*eaD
z at L+~S=<4H;2-uE>55eO}a|5Scv~!+;Sy1v1!1h3Sjl9@&YTA at Lmi7&)ZH$UQm|*X;
zVRXvSJy*Yfx396W?)z?I#Q2eiOHBpJq;2R^W8LwZd^+9Av)qyD|C%D%`!=25{Wc{L
z(6^}UC%3Qk3!NDBse!U<-7P#C7GwDxNOumGG21RhuL-qs at h$Ju-|9JTpJN{c>b6u-
z;Xo3I^7N>jAV~IZaC<{b^>5`&zmcJY_;#v|XxOKLPvsa}5H-|aMLBWhfN^kcF2THx
zrh|ALMnU3p#yH@(b~tzf+%2A!$y at oWXuH%v6(**NAy`LjS1l#iIUhFTu+ at q2&+j3b
zA^i<^jvJU0gpN)7HX(nuIaP83f3t$^#O(67f-oEx^&!7B%m^!Geq?L6?KtVH;DlF^
zY{`FVwq7a*cGh)=7Pk*K;t1%xE&yShws#xoC)R+HquHMA9obv67aug_%L)|Soxt5C
zwZp&ma^e`Ma7I&fqiM+*p!FtEBgHVtF at 0=30mkBE34P(o7D)?K3WZ-lpR(ICd(l}F
z{<Xo}l)!R5#`5DFP!;@i{haDobqBePpP~VTT%++>#<tIM39ZMkN)KNtuFRs-4LL5H
zU5J!yadR)cD<DI{<42Cb<%L>sKh0afhHqwS*J+0bz&|Of0s=I`$c>4VoRLK|j`m0@
z<s9 at 83(qh@!M-0u24r5;N5^LGS5eaTDVQ-AC`<bG7w(;u3v at GM#oa_<9&?50X1lYv
zI1fkZX3rU at Um*Tt1{!B+VFGw$0GF*=7S9H}j$sp7))>ob0q8A7e_gY3(t6*0?#Snx
zwP};vnhWh2lFB+^H3TAL0^c6APiyUf^N`!p*iV6uDCWc2bPbJ$?h<Hts#aV9cRjDd
z>qH$ct!Cbe#sELfo&)r7yw+_ZLAZ$m6z4YTokMd`>9}vXe*yOS$|4x9uZquuFnbOl
znpC~1_g=GX-j{>%H@#dEa;##`+_W)jK<@<7H9I}eDP9~#pDymyf!O;RPCtm|>FWKn
zTCGvssR!^gV_d#mcHzBcNKe>chNKY9Or~-mqor~Xh1S906_DRgcdT!CiQSRL{yw%k
z<j_qBRaXE&DDZd3QS4 at M#RRPJKnCi!h}Qp-!I at N2Si<yaSbGJp35FX_@{1bh)?(Qc
z;`a9w*e!O=c6~$sAI-ZPEB5&<cL5TtXX<qE1D_xa-VXUAxt)<;&mBRn>dx(3*9|3b
zt<Oe3|A)5;#j<5KABRubL32j5R*h>uOwfu7I*6mF2M!t(0M=vhbsb}JVebSPBmjbK
zT#<~DU6<?4HfM|^$@03VfA91uK<yiO@!U$C@{1gm=$xb<yj{%qGL{E%wAdJAPIP+@
zOTrM=m0rEV$ZU6~PQ`}Xid5qEP`C+s<P-K598a2T3P}$<z#T#HW$|=kYAQ|}Yektd
z4T#`su_vxuKEHJlji8meHt2#z#9MD&6H`#DMb~xy>FFq8@&ml+*v at UuA)a8*!2yUi
z14!A!w#Kkj^!5dJw%8;b`Y8>gmreDbf>cgmUGf-g6t5tC0}zy#D5RmSpglT&hpw*K
z&d}(>_Q)8Wg9i`oLU-6+_*UgP_gyxfEc=UWx at tHw!_&r#z?O6AuqUs2h1^>WRw at _C
z@;w*z2^`3cSr(Fat~OTV1=b%;$U=IEN9PyMfJOUPJ#X!aqJWq0yP60>0-+1Dq}g{&
z<VGJdM5)||SO|eTR;^R*DoOSb|6Ix5pqaGZ9cDyR?i&l^4x<7tiJGB3ZXFcnDjJ1$
zYj!P}LvpArm?2A0zvtWIt6P_*H9EXFU(cf%({GqAQ>EKZnCe3kM-r6Y+Ma!d`^K?_
zP|vDqg)7yq*8ue_QoL1-%cd3o2$@q&DPCOyR+n at J+lv+$1Z*x|c<L(LKoFi*{P59p
z!9EWG at WJE=D*@4P9r8{u#>Rg8qDd%%voBDAz8ZV7S&KtFd5fcJPqnrJZ$uMx=Lhte
z4*!wMchmIljmjjsi1tz{1Pv*vzVZ~PC6qN4+6ILYclBx#6ZXe-7fDx;-}p5ScSZq^
z;HU+ at 3(~PgF+D at I3~aF)`c1(g80b%D!Jc5QMA#@_*QU*C^+?cf)xTv0$44>76~Q%B
z3uvhxzFq6pB^96(V%sqi^<1GG5JNu;KtIB-wObUw(G8=i8E`9iyvC1S at TPDfr%FP?
z?Qv__PJ~%CWC_7hGWB`*u2N87)x*LX=bb6qvuHv^=DTV>bSQDRi&kSs8aPFx*<xKs
zB&hOBOwQtKjZi{CB->!XR=_t1<Qe9|KO8#W?J=7MIyKbv!S-R1KP%Qv8-XF*DF0D0
zfFS>0DuzL2R%jeQ%(AEIx#wP+nrA&%tiFQX67)km6sQP86e#K9<bG`JLgx_pEDg~W
zOxQrfCns|Q0>2K0{dJUn?ilFp^>+{<OIUBD-K(mA*S%nXbzmwU>vHt*V-E-DO1701
zx2G=1MVcdt5G_q-zjn7$Oqx3rEZ-n<$BfiqsdofD_+foWAE*Zegxt-&-sfAJ{G=aE
z<{H6*C0kYK_RtrC+vm$kIyCFjGIT{Mo;s>g&}hh6VNf{*r}uc!_tb2Xdelyh?53og
zPD?4&zk>71r9tGz%+3*=D$%OX_TR%we{qO3Mt;rBknjl$L0}3yUw}D-z<2*-N%>A;
zae2l5HjwL=IszVyr$Xstyi4{LS^cUZ=5sZqZ(_CqT~f$ET2yFY(GHu%g*VV}8I6jV
zXZq;|bnkALZRSR>D`08d_l7}zp{rr(08O=_bwi*Rtk3Oi?OTWC=o7Y$AB)&AfzP7T
z(gi#V$C%N^>@Vc!FI~oj4ICs#udfnk_-BtJ$kSN(C4~QAhVv~Xlj#k==$0-x`1=&I
zGw2jOg_yM?+Q-CBaM|c|UQh#nLN|8t;df4IsJ-dd&q{LUAnEIE$_vs*qWb$`wK0Zt
zVYS4VwfZF$bK^c$iBdpklIe;6FNX(>;}#fdsScg0yrGg#WJ3puE908E+?KId8}7i=
zncwcv1t{HxROp_q-71G at 5#7Kxz^TdS(IJ%1dtW at M^yu|Zq6g;`JAUBM55N1-2igs6
z;*cq*e0OR$|AQI-9*q~_oTKkwah*InLEc>YGwRD-PR^YI7NO4KvzH=Hj0k__24!h9
zYd9>}mK8}fYj<bb)wnpv9ocxS?=4KSNcX3A0)1I>bt=+{FPp`)i#ujF$wX*cdhnb6
z#~0ep!(isqB8ge=9ef0t-TVWrcX+EMVtF-+H=9eBd;ik(n5h!Et*W$lWcmUPcXORn
zwNSWVf|GiZX3MKfRUJ5ozeBu&nG%HyR2%P12Y))OSM$yb_fE43y at F;CQsp)pGnza|
zl`ERC&AJFr0l^R#EH$lQz;43d)L&u}jtwP<Fa)kYkXv*Z#{3r&EhKsE#=KnSn^j{K
z5hH>AW3I3@*S(g=9EfI69)?9_TSTue)~Q5VgyD!QYV49W^ZS?~C at B5R>tMm*&PeqL
z=K%ZzQbFJK_q27`%mHLz(lG;|^g5bL3f&?{MZthEh^61v_`ZdsBof@#f!K^8Dw%ni
z%J92<kyK)&!pcb&B5Kbn0plxW+W%AunhjYI-*j>@w39fea9+KzJ2|PS*AigR43IO&
z&rJRlLA1;cH`0(ST$J$v1#L(MDbjGbw;)Z at SaGt*P*DYu)FE2F9Ll-nBBU4N!$8cG
z3+0PtY^9((VOL{b1y8eV<J-z at XYLRJaVV0oMxEA(R4?_jY<sat at 5a3*bNbfV6+ at cW
z7zb;-DWBx8>=B9^_Lw7NP;Yma2XJlCHVQPkl)oB08$k`D*MnuZrYcpj<@7#2?5}@p
z8qVH(zcQYuS`Ns{Sj;ebk|%_fDRC4lUD7aIC0C`!nfGQ9HgLxR3utD_V31J at y?VEN
z62py(87yZ!N<?Ig)%!MlP4WH?;J!IFBU|N;&fh$M4;aNG4r;dx_EMuAHN4nBgQXni
z^}%l*IPU=9eeMG5{3WuJd-gxM1 at 9bzej?%#EEpCBV3dxf$81B5I{(s)+J+j9u$aAt
z^AbQ=jEah;(l~^e!D1Ac!Og|~0HA)k-IlgsRV4>eraOTFK+i^#tExBTwxT<iqdYDV
z_JI5+kD#n!ucs at 7n{S}~X(+FR)5bwa at 25a{whOAv0(;>%iC|x(1QR*lVpzZ!t9k`V
zyBwm&)R=n8d`*fO5wZMLy>{UAIk_3#R?euC(?ZKXl}nPm__q~YM8#DKBsnfenoKvs
zQe2ayoLpgDoFJv at vDK!SKvj|;wS;u!KvixDRc=WrtF@%krAu36QDey{+eSqm^4z~p
zECYc%9uya6QcA^*#tZ{F;^;i%|9Y=6M&wd2L8wV0x{;J1IzC23K1Q^Ja+UD^&K=kz
zN#u=u9RQ?lXvH))Pj5rFqB1lsv>u$R><l6isg1+){JfWq<CuU<>op;6FRM!-LlfDD
zvGV}Z4_`|QAZlp`3d@$spAgOhEs9(Rf0ymAByPY1eX&%e0GBN)-3R>Fr`I64<^k4@
zKG17vlmPIPGu*Ma+F=a~98)G}xxOV6WqiJ0sizz#IC85g?0bFo<<ae}5V$xl(t$}l
zcU{fXj_EI&+R&<8qIZ7Xq*aLR`}d at V6oCy1oT2K@CC^HW%5k~zQp#+R4a!;ErUBqh
zkv)Q=aL>K)0?Wh+O#H;h^MKwz88uH5OIipUrv2jN?HP<SbIOv7T<~ekrNA0W-IX1c
zMOdhH<+ZKY>8%DaD`{g%W;s7F%IcV^V?a=-)eOe&^g2Sr&C}ij=7t>gHX94%3P+&(
zaf$DS19EKqErgB-|8q)hD~Zwc=rybc9l2ln_%_A!nq~cVfr9;X at vc!4W$x at IKI}i<
z5A&^-fPD9B4M`x$wLkF**H!8a>@#3$OEeB^smPG;e|=n$J1`-ZgG1c?xVIFmk_njX
zr?&L0Ug$Duac9*TI&YWPY+JHG2<<eak{H-sc=Ly4?-wW>{$79Xr>$tuSa{0K&swk`
zAz8q at M_)4-%(1br-PWU9eay~XKigi}vH5e0bQVKsw!8a(6q~{Dt8;k`ogOh`dAMK8
z;uemXH at 7?AQV(NU%brM5kGcp3&P7mZUNBo|UWBT3Z(CmXTINblS>`e}teZ_%J|8k)
z^z7tZ`gE+nw at fURN^(_u2D at qf^Auh5X4tAoKn=g9)lR07cd|o|m=Sf-FX>)%6mqar
zjZ@{NMU%g}$4 at x?4(|7vL3yS>eDoD at c;8nZJ7ZmZymxLG)uPw??2KFTMK*rY+Ha~6
zG{YxuK-X*WQpb6Yk&&ti<omihJI|G%tTBy{?|c02-~axqYrT=0!6P<PcWCC1N#q?K
zrAyDu6&l1tKD9)MHOjg~X2_YoA=_Ab-wV#<MP={UXrL}ezkc3<cKt{UU(<J6`lW|c
z?}?YGr1VJmq&TF at pm5=;%UQ2%TEA at CmtN&$6UET@#AE*sefi=4u#@!UCABBDZQTN|
z$7iKUI%}}ZQNdng_FcL%aRIC4EA|ThW~zE+RH4J!Ed6Hm@%S`#zU=#D;M0><qbJPa
zx)gLUbpzslp%V5b)bjlc_FUBj%JB}0GiR=jfL^sEIcQ{?h^B4t(N7m*Mx;_W5LC&T
z)BG7S*t11oo{SG&2+&j;9M^Np9ydBhxqeyMfBErKSrj9(RP=_zD3iS*lEGM$DY#RM
zB>LjsD_*Ws8o}i5v0}2k9=lTL2<)y^==q;e+k3ddox8pG+MHVu@{r^%_g4B8(k%Yv
zGRX<$@^?>HR3ew~X0<*4S6os8R at fb%o&i}zRAO2mdsrMJoj!)BNAb at jG&)U(eauzN
zVJ*T at 6}p;pPkp$^Fge+O5VF=#)kZW#OXZ(gUQdd7X_Lk*4tn!(Z4q&Eiba*E{0KVR
z#nxJ-k<PLu-I=$t#)u<_G=wi4n-yuQbEl^sMP&~()Wuh=ig at l>97F3y4}zAjcF;18
z9CC5v@)|}DyX{5TTE@>s at T>>B&;^HfQyE`xDp<#SHTmGABl3Ch_WOVNC~S#I6y&BH
zE$u-ru|l0`sy at -jNY5P{{RB7G@<H*em+<|}S{$KljV3lx8nUhQNfDNaQSI!+>9~6l
zq^ZnDU3P@?b+ztiO09Jp{@7B0xQYK_C)KYBAaN7t+rj9wW!kXg!rI|Qe)6&5+UBQO
zs1}gHX20!3xVsJxQ!m&%TF%}@-X5vN8Ux at B7`QV2p9XFWJE*<- at zI;e6US at I`a3g4
zk6vFS{_^K7yG*iG0T7tJzj(XoIlEhK0mVq+GJTfE%jn~~zwk4e+%m_#`OM&Sks0bv
znTXs}mTuc#r!u>jdcxFH36NQ}_Ic#DdjEf58M2AmWovd=n305Lrx%6Xn_Odn2olpx
z&0Q!@l?uKuyCyT0f~Tq_A&+3=B{C<6+BcbNrhXIo-}cB#V6LESs;0!l#c2=pLJ>mZ
z6lC(!5vzSqX+YZIbBMnD>`8dc?r40PLj}{tZXwCit0(LdlY`V at feJ{rkQ1f4+tfRN
zi=dnmYuUhaSqfdCAqjnlr5M611vh8KS}Ex<4Ay~|Yg%C`B$IR@&3Bh;IL~d*sg+)r
zTg$HOV|~e>$-5&Ww at y$#F)47Au#k%ND8|7Mz}<n$cRFtWTfhUw3PFYu))i-k<vwj%
zT38(z!T4lt4}`XB&EU^)PT;sX-7kBlBjgPl;8bqaEi^m`*v<rP390g<CR*)KHFSus
z0V2`{h_=M}tHl5XQo%Ci#*pNof9}Cb`5CU0LQ`^pFJag9WOe)&*yJobc^(DK_t0Ak
zl at x;9Xo<8q1qsjxE*^UOwUnA_^)lsg6pl(VWlijzwQ?bHq~*la15%utB`T~FowSEG
zChS1N`o1VuJd_ at O_T*KVUI^a|hqInWeP&<lyRzTGbl;k1`=a%3fQLE{!M)|s(O4&u
zsjYiYAno*vcmHKZ1{a^)=VbIi_VK2NAI;rgSkH;si^usBKL(dC9xCS~+Lwr%=S$?1
z4|+(%_7xrIjTdRu>hxeJ{=sS44c4raFBARW>n}Uxs+|#|JZ$iKuY3BhdxgT)3Aj1r
ztO=BRMqbA|ILMs=;Cg*j*V!##SPp4~1U!K=)D*ad-2it2ZDttw$)m}(yE=scFJOSf
zV)`H21FVq%zzLK*1;X=dX677>nHm1OKsiE*QH=CdLIQc&Y~T4ul^z=eO6%ZHB#`D^
zEJH)Gi{_7sQj0)5^7cEnjhVA3!&Ex6F>|p at pFJ(R{zt4Jhw>0m+kO&~=XeUU3JySy
zPc>s2yjnSJqDel_PRq}phqgkG at FeE$PJLzUjVlGft}J-ZV8Q~1b35A0L~wGuRtwNf
z(4y#Ct;L=&XPkaNM`xY{rm6+G*n$4bn31eValt^K1De9Q9@<R-jkWui?dRYI3m;Ej
zA9=%$-R7Mu*(+Gr5HFvejuc(P4%ywxR!w!bwq%vxybshpx8%z2d$b4#MI`bm#>&j(
z(s$27nKY%6oQcw$(5318O;n|#6Qk)cNiQ>l={h`gAeCd;V_3glNK|?0qXn<CVAi)_
zR?g{+PjEu9<vF6r^;_iCI8>d{f|z=Es6$;$@0ZDJ9l2dOIMl*rzfyTLI$wK)a#4)_
zGi8p+r8&BXW&?j+P1l_=RbWvcqa(V{jX2EAwTRr@$X88^&|E1do`2;rHTU at m$iKr=
ztiGCoi4URH51611#$_Gc=beRCSEJ9?7&ACu9N3zGAoadsM28zX^@<L4`pfqJ5^J*J
zy*I7;_k<6du{r}yU0(TvgH0z}g)n$=g=F~1%>t93!K5XcelG|aJ$D{wYXZ4k^a5SW
zNnNkf0LigSOVG6(7b0m2sI at h^C8mxdIwJ=oJxqrL@=@E?j>DtW8(vWPZ$^nj>j~E?
zK9U!l3j^;9NxVfXE7SQC(zZ$AH4Jx7&Z8T~BpCC-uL1J_gw04V6I~(-GGGZh{4P-<
z>H!MrU|(U%5a(k$E#f~xJ_-FAWDICmi#?=vcQ2x1m3c(RTM2%?8bD^RRE+~fep}F2
zw|W+#`f0($rh8!`uP)rgPSm18G+teRQeo^rp59$=!tnq<K5ah089RzUZRtJ-JUvL&
zC)JPLP!9U(L9Xyw-G9aOQ5Wd*@0aegz$&}RfOf>^KZLF%kMvf3^;dme&3<ruo?J-5
zLZp%xob}cy3=A<+-hz*s{C$@ADO>>K!D?hy9zcO#J9B(n^+#qc3W_jPk!DX$`-dN=
zXG!L+vjsU`VEp4!0${&|#^CdlSlEVMaRFstl8)TK<IaKIaOL%E2bkNmO(sMGoaJSe
zsuO~Jq()mdV6?~5Y+BZ?vx}$D;SXa<tNw!9^N%IMRuY^sml%2oSti%E1lD%qoRe-u
zU$5P6>fm}9*rJ?q*e3XOccg(_W(`*KQ!Mvj!0o(Xn-boy&eH&`AZHihMbrggiwM4e
zCjdG&Z`;qF=cJp=!!Yji7$sq#S~mckVj8S~typ|1A7~BLthl9zEl5H3Rry$Z=K(eX
zRPk+-&R}KC8pxyD&DtNW4S}<7R=dPP24^{X*J*waG_yr+o2Xaxi)t=j09%yJ|7ngL
z&0PaxHusAyqf^ma3hs?J#f6qy;<aLTf^0ZeBhQ*G5=7GaHX$Mn6q4%G;4dl^r7qH^
z*Zz7{IifpgQl}q?iP4evHG5&(<(k*~Y}ZQ3bNTP=>?qL6D(dFODQwH8wC145$&(C<
zcxg{W;pd>5O($>T*&OJO7<2tS)8=vwY>%oP<5yExc(Hi~lhvLA_a_fHt^(GX9&#km
z^<Fe<(3e!hHq$I<F+yK_;}JTPdmHG5HTHEgOb;styL1q0eA}F*zo-xkRR8Jq?l)D*
z3-32o=`$)tNVmlZ3Qw<bvG0~9$mT4fzfJ-9a5>L?j)_r4HF+fr%E at IL(Vovlupd|4
z-n#T!07VlM|Ef;u;r!{?vfInMVSStSn*X*Gaoll!nF;O%oTUjNG&4;+dANUqv2|zm
zD9e=_JNKa2_qO at yEQ>^7h^#vi3+@=BsXo7r(%o%EwILIM?s_-aDhtVDwrqhNQDabm
zbDG9M((qP`ovvTAN+FcXm&lB>Fez^`VmXJ0Vs#8~UXUoix{3Zgx<&7@;xb`z at k(6R
zMnW2&#eDgR(nGJo_RrPzSl$8PYSMx`ECBA*kg=n1+nyO0l4Hx-yxDCF*tScURh=z>
z-%#7}uH&9b1s at Oo#Nf74tqmOAaQVKde}w<DE|mmlQ`zAQP4iSMsd~6qqY)`-Ze++`
zxV?~jY|e`&6l!D3#ZEEx at cpIq%`HS0#q~Fkv6QHgF(<4`$$8_ at RH2)^;P+P^gS6OQ
zMq+eMuil2%X<7A&E934*GYIL5G~!oO2nD;1Ngm4QB;E6ixH^JOE9}fFUt5^rALfw6
zay#L-r9U_Lj=bkuhKD}{te2QxJ4ArgiU0%(lRQs7*za#?o8OqnMtkdfw<tnxaAPC|
zK|kFXOQMh=+C^3U&}|+>ZSAXhgkA0VbNX(}FZ~U4>=-6mzI!tAed%~r4?(P7bDNvH
z9m3wZ0{3s4?LE|Zwic at hd{-j=on!a4&<`$AuG&sp=1W+C`9{4E-^I3TT(rlXp)2&o
zYuJXG%ezV(7hw2L?0 at Jlw}nRA7TD8P_0oEJ)Q at j4MqCSet4Vg1fB<Qm<F{VZ%j!(R
z!`$D3t=>M&)V{N4$sKtLq69P>9DG>GOy){)db at M|&DJ!%G^$QEun`B*4*elp$m+Pk
zc0O#CXZ)l=ad3gUQr0y0onuTsJqsLts3IMEy<j9h+gF%6qu@$zDryDAh2)x4%DQWX
zD*QfGq5tYLe0A0e`ubYWZbHf7k3hcte76-$8P9weIDFHVrE$J%^R8+~y*_gvrEUe|
zsO4#>Cck8!{O(tn|0OvMM*m|c^^#3c!38{rZaGVAmDN9${^dnLAB&t+)jmp!CwE4e
zmP+cez5NZv2=k~vEgy(pn!~ALBSLRgLVs1FN19E^NBwTyjW*}4r61u0WSXo2{u|A`
z9WrlMHi`mK^d&uJF0o$tj{r|8Bt!UiS)mtfM6jNxvqQfEE(&4vEU(=6a2G_3Q?Ew_
zJ07QHQ<914yh1CFA%xtmqR}gq1R>~x{#IleKCrPq4>1azln5IG^WTDjr_W!tz at _~x
z7dLX<!RyT<WEb6Sr~gLjvV91W=f+KZ+x(z5rctw3e#NKFDOIv@^7wYX;K9WE?Ho!H
z)%mCjPx8zlefl77dJH-f?7*Sj5H6;)pKzcDp_doS-a&f6&D<nddcv)Yq*n8<JDCIf
z=q6oqUIqtqt%t(7=-B7RlicTbsNq004ZU&j3-T%+=RL&kuUnIT0qGsZa>R_x4y6nm
z)jH<AEv@&Iqq+qwXx!u`EB4SX>j at h6P}!WIi6m~{=j<75OG2U$#BGWMv2=mU5h*xi
zIxm?7M6b*ek=LMD09(P%9o?q1#4)*qE0X;mY0|(&(_f1_DK$!RR7 at WCQR1<n%8e&E
zC8cdmL*VH3SAcIi#(YJ?7NiC11ckzM4FZk6 at nn+n>Xe_Vst2hvkAc201)af!uPTbW
zZrF3~^p;7#XEa5?sHKImUh9%l1m!y?$zUMf?@Zz;B#H(%WBGeP9>Xl3NKb_6?v-_P
z+X`Pg0kzt^n1!MCf3L6UpxFn-lOk)ZJ}1kQKwI(COPr%!dNL67XBY4>t116>UpsWE
zu#ty}NGI4Lbe at 0Zxn{t5E==KBth62Tm`$)v=B=!%qzUWIxg at iAIvJjJ<|M|2{O4lv
z?dc0Pn<V_vL`^O?^=tRjQ?TA^(n);_P4xWJ$)@51%504Xu+qmVy-3G<EY=()QQ)?U
z$qz$q50OT;2Bncp-t_tV(M5VhAod|ZE?U=Z3+4mzCeTCfC;PIC7L6OU<oU at w4}a{%
z1|Gy#vKHQs7RrE3#Q4kmcTnT;d+R)4?dueMaP%Q|33UXj3ct4>U;Sz(k=?k{w-3oS
z{yn`5$s=GOOBsSiiRL|etMQqg#AowQsmntTH75CG4Bjtg>54RaXYg}2RY=kGI`DZ0
zFdgpvyw~vO2d4X;(3 at cg&F~=Q at xyiAp}W3<8!FtGdj^J%e`4`gUL$f??AY~o^}gx*
zw!hE7*85TQ4(Oxt3CFprx46D&`+9$t;>aD+|E3&lon5Tt^851T2xJ{xyj^rWS-S9V
z*~Zv4xA=Z3i;*AG^9L0e<w6zmGv)}P6cY6YcWYIlovIGP3I;knLEAsxp;vGRP<etL
zd5LNbkE`cfoW^=LO%0vAjjRtWk4y<`fOgN~41v9c1y|S3-Z?pcWQ469r1zv(pNKSJ
z(|^sJA1jK0^nvcMAsGm+GPypSS$h6}o?>c#T^Tk<UBvoosICK?ou6*KT|5a-cjybz
z`ak(CA%0N~paWsR+oPI4e?6T)KY+l;XMR-Vp)-}B&CJdlCrAw-4U2{+ at P$03(@Tw3
zBczP{aH<QORA~1AXQg>kL6by4Bauz;{EacfJ^LY6_mdmcrE$S2bc67m>iK%J>=u1}
zNJGk5+*Ch~muheR6JJfcUtKj at Elb5Y2A;}0NqMT=efSXjVD$5huaOYdd(m`r at _B};
znf^`X>f0-d$kz6<mMe=;tGxKU`eX2qbGJ{?mEWWb0-9-1oWj>5 at brW?Igm6WGmZ=!
zRrGZC#iluDwqR5K;$jRu>*~WL292!F(WV0?+bXrPQde%N4f#+GEfLjdg7CY76MWRN
z=z0j)5h{Sw1y(@3jHjY&U2>1aTH5sqa9Q;|`QRX5L$<xy#F(=jJM|dIQD-_7DPY)a
z)#(W^^*bhN;q2Hl>L--A-b57(_kVTFS^)!;Z>srZ70mc_Yf^4Eyf`~{ti!Q4j`3>z
za*s2YJoKNS8~pc>O{*uF)D|`fu1&ijmQnJ3w!qwJf}v5=X4BuKeS-_)yj6`o4+;tX
z`m%zSs^H{iLUV+^v0AJ9inWRVh at S{H0eraTD;RvZvdjT6LFSAF*9!L{tH6`%2D<GR
zyc=`pziJMCg}+&K^=q at PAcg*2FZBJv9+HfCjg3;1dRtQRp{3}~S at VJde38Fpmx$U3
z>WYYkSX7kz+LySTzG*<(Yq1Xq(J%1#9IT+NGy+yYyNwJ1#B_d4I-_LpfkNBHg?0l-
z{&yUV;#D)}5?ssoZou0{iUQ|9@^qeYIO|G(KQi*V10)$Fxt%aC1G$LAhi|y#Hb5=;
zNNR>%8^3!_woZP-KI_<aMFn0XZT0}`jMI}nnQGpYK8+qZ#@77IfD{yz{_b86vLj3g
ztkX1gm?%%>0Nw5G+B+nm)T(X6=2$kk_n&t5ihl at VPLP$Ba|=J0kUD&2S|8S|T?;!2
z=&fTaR16z64KpBJ)DUny-Rh~K&$s-tN^4`HeBv9BrEIf9*5pxi56t1;$tlApPW062
z{UST>pw#iVE!bOryII4gJ4vX%j^Z)HZf_2;GG<M_-8%rUlZUC}?Gf3Bxt^Zip?B at 3
z?d(?qft608t1Ss&!d6J7v*I0sC}e<69 at zt{))rtLSL1*w_uBg`0Eq`fM75vI*R$=O
zowrVAQ*I{xiFW7U%+DG0dVoO2Qz=ft4`AOYwP_ds4=C<8J>SXn-D)dvuBDfY)^v<s
zaR0^FJ+OrikQ#!QD(!>L?$e=<|3mHNI5h at KJs1)?NHOW_c!=IVB~!S;`*L=Id(M2B
zPKc$Ge$@OH64<tGQYuV>1Djbh9u}`O*q<>A36&!QV*BI3kHx4W`{)^T>$sdGYKYkR
z%-ty_#Oe9B;HIzG*1o@?cDFp5leb>4EV*wakd?h3`eX}N`+F!Sp`jqzqHRmgwjb`n
ze6naS3{E$7Qe1r_mK{J7k-Ag|Me4DQ#!k0?z(U~~7zyK~>?R-#FGtb{OVBi#$4lP=
z<}(a5H7AC_vF`(~-+V(*DMHa3&pxqoTY+k<8r$D at Hh)~pj_G)~Mmq%+fVk*l)Hm^s
z+%hSA3~nf6)P2Xxl}$WN(k at LMpnV%uPWAO)gVF`olV~YTsDH5;2c<j`QW_6-qJ&=;
z>epaqE$PrJl18gQo|zrZvkMxNBX?Ex&OjI^O>?il^V^+pbL5sCKco~Ub|#a at B&B3_
z at As2TA6OWMlZu}x96`)&Hr?}3kCOT+#z?~X8CEKmCOlb_j?uYuj<@XoBhdS!<z62K
z#TlYgA`TvhFME7&=z&C?X>7q0F_>NzPgC_z;u5EK=(bc{Ay;D~Bt)c}Wg+u}y2;r5
z<RGED4+^U at JnLT}h$$7_ at Uu%{N^uIVo`d$1T7s4b$6lx?T^!sy6#)U8lUlrnr_>uw
z)7<?XRJ&WmJj6&NF$!A5l=@F$JJR8mYAetz#Y<+zW>7WI_%;z4mRwG{-Xbj)&ef|J
zC@=&D%c5dygFcFxWHjt+;bv#xGqIM%>~ORb0n5CH;Ck3*xkf89(~;D2y$~sh+n at -N
zHwOp7fb-tWK5 at Awwx=3y>(W_Lx;(qu7#+w_iHKWv*qauOX^*g3|CWsxF49b*xQaE5
z8EHZJJkIgTH~%bQD&7+}=Q!VPVIy=_>^25cC}BcHVy*aj-X0YPtCfGejt4JGL<7F8
ziX8k!!5dXQbm`l8dA9mR0r}vtPeK();Gga+x@$AO_X%U+1u{<DoljLv7w)z|f>ud5
zV9DOcYrP2J1*nKJ$bl}lrI0FiZ6paOy+-?VX0^KB2p{{X!WcX9%vf-{xZv-5bd*ce
z12u0RCo9c3z{(w9n%!pl;a)lBYj&`~wh at biTYcYmWjMG_hMwk&k2AE~7`}pz84iQj
zBiQ$qTnF%xi7{Hq1671us*lnrCM^tV;$g#hr18z3%hod}S(@-S<XV#TIoVzK%&EnI
zN`iQNvW0WW*AW*FQQsNdPlQDv^?*-AsJ)P$h=PyItH~V^-x&>(cJ$oYsa7mp3pl->
zFtG1XPQiPBvv9Yuc0=$*eEkFa`C|O*;|fL$csSu;AU+etyHj#QR>Jb#uAA{v(^}Yp
z08OJNBVf524q7j at 9<flj!RV9BziDtOWw?0$h<ARb(E9dvhdqn-^Wfh=_=c=^I?g;V
z<eTdX>^fzec;BA;2`K;cC{s%$d|pVYB06 at 8rQ}laa;xSo&JG*@l&4k#Y1TtorzQ41
zj;cx{vgrQ=4(=bsXLROl$vLznl?zCvhV0a_dsj;J37H`CE;VcZE!6m<sks-@`h<Qk
z<ir+jB0Vllk2~0(fu at nh8>{IiY4!)!k at p8FsZ%F7Ay-4jf;jP#-!$<GWO51I%Ga|;
z?;E6Kckt}QZlqOrq&5cko_h1NGgq{#Z^lWL7-1!-FLTnnK7hgKRa;;=bADxckSNAT
zsYs?hrMGl|Q)WJQ7Uv68kkZkY6zEl$%rR)?kB%t?IqbWWa}VZ0_2<W at Z_H^K)!bK+
z3YaICZa-huF*6I<1Ttq?6nO*Y#TMf-K6$8hQ|Qi!;>!WdY;0xrp8*2JJ0+&?&Kx at n
zU;uHf*T1pnUyk&Vukul#SwVTe2dB6ALUkGk>mS_*?uUIKjj83xqj1KjU|LYJ;y652
zK<R;ttgp$m6Y>)er{v9FerxyQi&{PzH1_=a(<Lr9Jd9KOqnf|BN16%c^v92$bti8M
zHYIZ|P`W#->8_PRi*jVhp*{=rAYj_&6$u~ZWn$_R_%?<{Z35oBJ>3{`ABaVmCQMC&
z{c9EwP4H1cR?GTI-c%@%)sl9_(Y^y?geZAjDCBfU0;&(ZAOLvw_|<p%&#J|uc8t)u
zP1p9hv%Osu^g+M&DB?+YDI=aoQT|<JB;Hw}1%N_iGKe4RfU>5pP=cKi$2mS)jK;`7
z>9t9q7cTy~xS+wPE4p519l=G|Bq5)h!ipGlU?s7dhpzj3Ve?8 at a_H|WG}I#lK@(N?
z#<~7H2POB-7h7&UynAOa4Mb$T#eo}|C3BOY;JXK}<}OU_#xe$)yIUxu6{}PZ2r%UI
z3as#P`H*^`RAx%5 at Udj;S^IN at QD0&^^rP5l*DdLO2wgk(TctpF?B&eLA0|)So4x*i
zh1x%o`5W?!9xNa(Da6g8NI#7Z#aP=n4T%93h?;gSp$KxzP^}n5`hrd}^sjKfVJWXy
zY_lA<u{8C0Y2XP=0V^Q?!l{Yz7`xD*ybSAfdy;5RG{av?Z%uClqHfzlKI>yq1V6x+
zPO+}<{YEJ3i2+QRr_U*PGPlsJ9Vh}H&^UF%%$l2eG`DK*>Oq+L at H2aU;JJIhc=117
z?4yXQTfprK7PO}N9FuZZ2sZVnlkzD7JN0i5+XOg`73VI74hO)XTL2(i*|Az-1rkGR
z_4jgnv_o_Tm<x#H31#9Tw=V-_d{kLNSbT^a>20%m^JucH at A^_~T{Qrv2f#-hDdb~R
zkj0J#6<`Gw1B|ZV1xtgP_~0_|L!r6^fl^;K(aRqG07xWM>0^Zk+$w6YFX#*?!WkF~
z0N!f6p)VBe%0B{g!N?!YX1V{HnHL4MQl3uRo?mb--Z_u?VCC`s1LrUSA|m3Hcb?c>
zRAd!VL>-Y-HJEgDn53(%YR=7gCgd<5V?vog2O<fs8#|)JLAyYsx5*IXjAs?&TasaP
zUM==R6dy*e9`e1 at t;Pvbk#(RZKWg_Okzmbi>|L#K$fHTge^6I>wXD0)Hp%j>ySe4Q
zzQvL5D71%??&%b7&8O7G?nJL7LIn|zr5kqd78&6ro6}!HG_pGNk7#5&S64Kf2_ukt
zv{_CXO-{!`lM=B|3e1Ng)(T@(ucztcZ<g}q3Sq_z;_Jv6kf0+ at 6SjB;ZEgZonG!^Q
z00`WlRhm!u#4}()FT+rNjpT2c!hSP>_j9i7;XZ0Egq!1<u=YKAC)6^n_xr$rF^7?K
z;cE4Vt0m(%!u at V955W0m0u+NYUpY<p)z!kuKvv`zK(rGR;j8Cv9TARxHy3V$3D2&B
zULz&|uO1GXRh9H*^FIj6%e|ujv~i&V#RWr+XZon+Wh&@wq!QsoTfr?y;?9%z%O2IX
zgDA1dSf8x&KH$Y6=ByAfI3un97L(wqVAWkMiRhEV*Xo^=U}O%#A3s6j2TWqp2Fg>9
z_L4Bl(u95v0pX#)FYx#Dd6F}!3r<4tLLPCRF*lKk;ZIjDIZEpED^&CHTHRMkzHvMx
z62o1<PX~8fQZ^Lq<TyBO)Hizv9IU(E|MS)?C9Ec5&FU09<OuTN5n{piI8x*zw9%?Q
zcIDQQUBIbcjq97|#;-9{Tmy{!N3jT6=_WK8t%jM~aBA<z+P4Fy!nOeLl?AtQn<j}%
z?dWT=cX0I#=r1Hz()<wfn<gvj2WNh)%mFtzFek5dgojVT=BrNf#?Q}~+3TB at KzQum
z@#NL^<p#k3a{F8#s at FHmExM(8s)t#DgjqiF)8&Pl#dCm*)<{8lU|^1vIa5#Z34GZx
z!TMv+y@|uC3r;XiafS*&^<B1=E4KBqJVTyoxYGh<!h`{R^oPcf7Be<)h&IZ3vr9vL
z at ZsD?80NCpA74Qtd?3B2cj1A4l+2WbDMTC_ze`J=uSdwucyqeNEyS)@^SvRq`V-rJ
zE~k3g3Li(Z4}lw_Aa-!X#Zd;FGlomAvLq37PPVV~BMwJ at jOz8ZI@vp4$;pmp+*TJS
zvb)EYjoc>p_ at Puya&5^aUIz)?s6}y4RN-`pR9C#~eV6`@XZZK$yVWtag?gfhdRGf7
zB2F`Y(0*_Wmf at S9d-!VpTvchy?!KPLnEQVbzBAbe2HxO<KU7R>(CFNRc>3PvU$ANv
z|MRN`GdnSQ<64ish<4d3p<Om&Z-K=O31rzC3uxJzhePzlWEkUl?J)>NgpOj$aWHDa
zxb at LXrM5(465*c|z9?$B7Te^yl=R{jNef!-J};uDn2qK#ABlBx78^xch5-xz!vg7g
zTLW1JbLry0(&mFC2Pp(zMU0!0U*^T9;urB>8ca_{XDwIa7ntvJOizVP()?Qge17#q
z^a$2hdD7t9qjg+zH?)+wNZU+xgS6jscXsL*;4HV~4J)bk9sVIA8Abby{DMM-fbgAq
zZBsDrBP2!i5wJkHSRWklut5v{fxS3*?|$g`$%fEBV6Ydm0S8XpKW1ssD}Q4N_pRDG
z0(1>0^}yytGozI1PKFz&4Mt?og2`~$u5a=}p&Gqc?&OtSrUroeZ*sjARU}@n at u-gw
z43qnV3hf-mSwO(Ef+Qm$XZ`&bviW4tA030k=3n>JHw^pjAGtU<+#Zso8N%*z;LACM
zUC5_>i`iZ0RWV5fpjxwa7xrx=${)%rPZlnOm-+{6+rwFT=eJU|Ju+o?)MVNDgO^QA
zdnQGmr6JM-`Xz6cMhnRuT%w5fc7NOgBThr{5x$xRad4f)ky<EmgnmD!uf4s7)A9#?
znE3+^AauZ#QbTJoYCq!&iaHHT3x0frBVNGJZy>((_Z;S)A|4IrY_v{Qpr}9vUEU`q
zMipb^sysW at YTI0;Q^QU<WaV$>bp{db4H{0tk3^ypa)BA?IV42+TpJw)6hpD)*WU{m
z14WRIP6;zov)=I09<Cn6XkV;WQT~aTy%LjGN-Lujq8iR<HiUKQ1tCN7=}R<yuw>7F
zY(@<$5Qi}Whe<kgtvMt#QmiZz0oyJFCCA`ov0vWZcnQOhjf{*mTAO}&^07p6yPP#`
z;5g9-ZlF01D!C~(bUJAXQ_?RrDRNGZ+qA<{i$)<6hS(3FOsD#iZq>CVGbGdH$hF2)
zqi@&Zf<U3?)bKMMoe=c>L0<Ve?G+xBWNG73?dBm>!i%Jiefre_3c1hgIbo`seD7QB
zoHWUe42|H{Om_y1ISa)Pu)U`6lu97pvFSAa#f;29BYu*K#XHd{aHJU<TXD8VP<ZLW
zsVh_hjje>DNqU#LIyHRaz^9hJF-k7wleHxOJu*&)-~2trM0M6v6E%r+e)u3DLCW~C
zfy&~uQp%tnOq at EfRQ1%d_@(KcHoMANiMNyQXmQ{*&<1Om<B=N9=p%k$)u-9O+8&K2
zBc!fRyY{uwz^edrn7rr4KqoBZ4$jtRv<yuwLFK9FMQt$jpeV~1th86a)h$Z at 509<A
z;DgFQM^ne%mPf{K at eOnoyEiHE&?d`O)vw>$BAbMLzp^D0cKk81fliI*srrsi&ac^J
z$*G*>(aLovb3UG1pM0QT?%^)|`)`EjW?!G`D4bX#AEk3)u;c99$DO;4yR(}}8S+LT
zY&ClpkOwAFE><$~HEnn=#jgHj6?LE505#WUrY@)UL}RA*1ZDn)HF)HTG5G6-Hdy!i
z>WZqZg`EG<E)UbN|K%AbgZkN)KEDde9a7f!@`v>C`N8tJ5B{eU9#4qhz4f}92sNkV
zx8y~s%2Y`(rct--=~S!(f;H=UbUhVW<yA;t)AdBhOBdqr-%ljo&}Gj=mEQ|3q)?$g
z^eIzTl|#QOXh0EW_?7+#S?3sBOVn-c*tTuw#I|kogeSIb+qRvY6Wg|JXU9&yyzjmB
z{kc_h?XKFr*PpIk-M!X)#u(<vB&eW1k(1SBCT7$GmufU%Iu(w}qp6jQh);=nnjl at m
z?`Dh?^*!cZ%sJvY_bj~Iu;OzQ?_I$Xu9S>3&o9EXNxtLvd_#hpE3n;N`lg<_Q7R(a
z1CBrDvk#grcjbf~xa}&JuX>9M@<>40dGdUaV_P$@NLD=~!Bj)4^5<yzAs<YHu8=mK
z%Pl=sO$_vpwGvyreCMHyk}rZ;CkX#Ao;z~9XSZxi_ig~W)ZB;LTh>nwlSf1fDu~Nv
zc#f~D?*yINmzBati_5J$n3vVyD?l$NQ4ya<yXo%svb_5dW&Jm+bhfBaeTiz*snsW3
z!*CkU3t3anSML*b0JPt$xNRr7JQl3&m)0x~+3gpV+h(UGzvI|;wXR%QGUUpJ(^}q&
zP at +0FETL~?59wGRk|}?l7(JBaf8(s2jzHndinkD?-1QK(HJ<~4Vx?3={lt6mQ(E1?
z`l}2ZE*fP`+Cdn?j$HA^hu>8_niF|g&Ya07%6JUtG$%`ir!^=HBu653d2>8{KWyVK
zo6a at S8DiOdSL9L4#)le4Zo;VdSF`P`yO;=;`<-O>6T}EG&SvPm-}!D5OqrbXfE|ie
z%jeTBLd at Mwr!t?I>#Bb%{jRH)F>NeMzJFrb@<_b=7suEJ<6ouPB2{oT9>r&Of-h~Z
zdN7dpJMP!vyX at c2$Niz?XRM$NUs;c(lV3+mGBc)QRT{Z{@szRsm^|Amm+sN##*RAE
zlxyN(a}VOk#OuD*#F1nf*u`)hpMPt*&nSzRUUvROy9k1HEf?sRqXfV at 1A$BPf(}0E
z0|h_?2PhNk)Ps_e>ff9M&v|xt>hH0|x?=|$aA<`JCx3O(TGF3a_d;9jbQ~Yt=+RGk
zt$2TQRh9VMXom~9Ep at rl4-$4 at B-`o9RF>72 at O3+@rBj9PiQEP*rMjv53KjYgc_rDK
z<Lz;gfB$LrN9d6M=UeO}tu<Omn5;Lc|4#j>`GPfgAIwmKlad0Hq$NCtD(sUIz3&)-
z6;c(@U;B3mke-qv=%Ch{y#p2!v=h{itb^1HYK|wXQU>ZW5XLDeXt;3BKD<4P4Tq>#
zrZOz?R|A-skAzSkpU)wrt4iLCaG|zA*8N#6Rc!Nyo0beGfm~I-rqHv59 at UHGgQ^P2
z00c)8Tm?i+m=z9&t2Jj;&`=&ub&m2<cr0E<YAoJ1OH#<$Ki877j~>B^>F$o4$)O%X
z9^-y2l<KT$N~%PY;-4_&Nd0j18IDM*#vRTdZY_|NN_gE&cfEqm!r)fdh%d9E at 2;M%
zqPTXa_@~34O}UfzrrRk2qoaQ^Oc=hRu3WH|MpL)2KfCjqkED2c-ytw|x4%LW%Kou<
zQ;~S7K-BQRUf_0?H-XFNRf{F1sC+W-rjzqlu=;~^;s at QJ@-u at 0dBViQZ<3j0mGre9
z3|s~3J7YFQe}wg70ly;RE?sibu0=T6>r&9 at jo1{3)P1!tIK)w at g!_}Kj$**xo_1It
znsAryjMu!V+gkl~r0q`GSg+~C+Zm6_{GY>kjc$at(%QFrZGSG)&1Ul)yw|_}8Yc<3
zFo}WT5h$e9ci;I4`>9mYX}{C>*#qq((%7DGLOG`HSTO at 3cj;OJ`;o;Ng*{QMTgywd
zmO}qz_h5wLNoFC~#C89Lpw;Z_Cx}y=UMs8)1W?v0nDBhyXle|K&^%D=T&g%X9C-*j
z49HhT^hO_Xs&b?F=ZV&NW}s9CjSFUK)k#}$Sb?rra#0}Hw#*?fc0O&aYRX8kxW+hx
zeEUC^%alCb{OD{KN%#hNk)9Sg-rfO~r|~X#x9F9H5X;n6sZ at 85*m1Z(H6kQK2`;iS
zT1<|sG~(*4OUi$>CB}J`YfR9FW<Y|EqxI+^rkQ50#PfAGpRUB>HN23~9`(Wg_C at 8F
zKa<oicpx7x>4TwnVFsjdv?8lM*n+9^=MW0%Ur7MrM$9Ml(v;niAtkcOqqezLlt$u7
zL5re0{<Zj*!@KS33Hn)^bmE3 at H1>Ou-ZO}TFs8a=ZlX<?7!hwEqhCsrO)B3r0-jm8
z;)H^EsDlqKb__V2JO?<ASY#n@!m{EwrBh-_T5>_elT5~u=&0kbZu2<QAZuV+?JW|w
zd&Qmz!B!3}U<^hA-@$AV7|owW0)Vv~t<W5l3s2v9S;ntw8WkWgu%C#j+p)%gmN^<A
z{|cuvG!8AcOe!`{2MBPUa9tA1+gKR5F5fCeQVLhXvxoR0JK2yq2c3eR3zb3!Fw2Cd
z1x*SVD0qvbND|Fm==K*bSuS+G7szUSLZNSL^Nf(6t at 4mj;9uS7-<yjapvX$Od4Pb^
zxX2q2oO%EY^KvBH-i?I!2+Emmr`cr5bs<=Z_15!36iM<FdI2h#ULe*kj-4X{Fv)!|
zw!cy;S(w8Zyk`d`NBVB&LhgHZmp_;I^rr$qakc6i%eTrkKs%sZpg=?r5Nf&$F+1b;
z11y^Dtz9RgQwm-wdAHQ_M09|3N0dz-=?Q8GKiJ6J4iuI*X#E;}(6{@g#TqP?syiF$
z)VEdB6aO+*X2Z}?%H$-Oj#qT5$cv>W)l84EABrNgFL6no|Fe+F&#7%JlJVkYJ6n5j
zET3HTU#UYx>$MU98~e4`Vu%fH!FojF>BVE32^$mk9m|fV`HK4pf3krVy*5QGU{R98
z3d1>{xeS>ztW$m7<5=;aQghDntU;Y-P11JnDQAqYxs>G1V7K=z;SuPRJ0sxPP)ZF!
z%SN#O*GHR^YpM!Z_fG2rlizhNst>3pt#(MtWhfDt>17MF_IL^dzg at z;V=OKH#93*_
zV2l2PE_0H?&0hj$RP(>hP?J#IY%r3FIkH-U*`d#6gTm#qv0t(tl7b{FRfrd3^or^F
zbv}eP>MJ^$vVOvdRbIw2`tK~&fZ7ucPH?d2yNNZcY|L%5;}t|Q;*VQjuHPmbnrz)$
zK-G*N4$JrjEcMO@)IY5x?cKG-;RCm}+c~fkcmsBhR)7W~v7<ez^j?E<{xM9MY<!@f
z at E4vl$HSO`O79*KYN|0t%`#caz!(Nh4~5`B)e$noEoeWF0ot?X2E>mB+$)vLuc>{Y
zrM)j=-_tjj5yMb#L}vE!GjJatl=RZn%6%IbK4HNpj=@OVCG5tpe|{qi9pO>nbpi>)
zBQ|N+MMoi3rx$@-${7dr8E?elPmQb93&ExL)N=g>fOm25yddb!{i|hDX#+d|%VPG%
zBj$JT3Jz7ef-+O{1KU{*TfBue<&TqT<)_!?5Uy_j5FB!9NQ=PZ?H^7NRPW4oFUf1M
z#PMJ(ocvliw`BGch2G?DU7M!xY=VFe^5q^f-^CHlZ(aGgrgBv=k-SZi2h1euYpojs
zWq%d)$~_fiNmsn!vL;h4_k^iDpv#^C!D0{afaw-Rwuq2km|D2jE;T=dlqy-6BO20$
zkT4k4;bKA4WEfTPF+PILI8y>Ktz2drm5k=j{emcPzuTcLdojr)YcDX2R6wtM`&W9c
zYOBKBEi;Xw3yj;Tq2w1y4?0Ky3CVYt(Bt}=WCSk3-D3G<mb)cdf4Wf;X(O?l+^%U1
zhw=wyPz1ON88o~e27vG-8Y*<kuYiQ#)wJQw|B{a3qfTj)P7q)=b|aP;`;`bHEv_r>
za57rE5M3Ms5!7bw<M(eX9 at N0_dbu=Wf-|>{Od<p$gfaJf!Q9QRY_t*&^HzR|>zgvO
zmeBrBlw`>6U0DM{4GhNc20j}IJU3bAw^I|Lo}v382q?uT#rYGwP%@&s4+(yVYK)eU
zZ at iaOZBb&8$n_DEzsv2`)IfTlC~P}Xrv^DeT-NQIE5A8EGtJ2O2K~tp>V$&xT|_Kc
zf?4FFva!f%m?hXa;QS4Tu5c3nWY;|?3oFVk)J5}ENDP-_&)yF3h6elmn+c3;rAWkI
zDQvL`Oy^UgRUuq>?IpgOBq5SWU!%}fc at kAk<&;}t&_Icua>oxfG*F=q*<IG#z5qTK
zQVJ3#vMuj2zQkIYi55Kb>oF1|iiJ%~53Z;yHcI-6)6fsjuD at -<>y-E>2pyv_7PAhZ
zbu+PYLf*=4&T-0gq*_G8e)U at -+3;LKB00JbE at Q7+E(6R;Mf`8IDQha5uQtSOIxtfa
zJCL+oZcL2m*h3mLyi0+coR<StbR&_iPd9OHt*T{T`y|HXXub&eagS`F-J+B~UEIP2
zD8JV(KkOJ<cYXk59ru{9MM6(xigJ5$mG1akB0Ho!rJARqxnz<dA6Cnma!a6bq9r3f
z$&3V>ci>?hO<k<TR}Qp(BH;Vuk(#TbUL=YI4w3zF8_5p;pS8#^>>I?5bzd~)_S?2s
z9K&(d?N%5wT at _QE#ojh|0o>b#!L6 at bu&>}N<I2j43d+f!mi7KZrnaqM4S$!-WHO9#
zL!~JB?%zZ*I;baZ5kfX{foHL>dz%olQA1D9L{u+4Fkm4t9704$Q~TD7i7~dHmXJ47
zY6bR*cc)V(Zv5U&?p`e^FqYzwfPTw{LiQB(@QUU_<`fipsFIRoxXZY&f#Zt}$+36R
zeV8YkHA!p;(_jI*O80;<Xoqt=W-f;+Oce}JL}k7+ at Ve|dN+{8S?u<I~Q-E)T!cG(E
zXu{icQev+qknW~%Ob)szS;!<RAK%P%INdq4u at -p=W%$L?@YLUf9Ll#K(L|g&Bq_lI
zT#`zA_huHqSV^S>UeR7c_?ducHTr&qD=)TmPLIBjr*q#9a2KX#{o`bBYLrS?FQ~TH
zYz-T*ajH}#aOzR at ePm^{(th+|X^nIk4J=wYBbqZ95%#%yCfCe<uy+Q`A>DNQBKg+D
z(ob0)4o at SIzT%3NBz&XMO1J~IV>9fgDALEF0q^4zvwQg6<iqlquN6ZaK9?w(n|iSn
z!Zxv#JfkQYSRJ&Esfj#{>XFUkirPzK at rtWUwo~E0VSr;v7_6(XzmUSEPu-<Dzk}t!
zaWAb6YIKB8qxAYGTh!DZ>SXh3&y(H*F5h(T{Z0NgBilS)N82QKudYw%`9lNc>|W1=
zI;<PNN}jE6Ft+6#AT>q!YvO5&4e;yGG}xS<5?BqHj$L6IhiB1sdnB35&0ISh7VpgP
z803 at g2Q7-e4oG-<6SJY%Br`zR?aq7q5&GG56G9>3pkso~`3QbiW8lxl&h72Oz5&Dc
z>?%Zsk;>aF<F6IEA at _v{+s6QjBxJuMoVeTfDFGyv2P}h`qwLc;wll3CFqyr at S~!^Z
zlnGZwA6HbzH-4PhCtsP)o(h%fi#MW9sbw`|XGh}E$yx|ZW*x_e<mbtQg(i@%#RM7K
zZXVh#yt<GXL=g}MagjeLxws+C?xsc at fa2z`mn#mKJcz&!z&_T-RtrS}xRD|<e%@ET
z=>~S^OI99+x7-G_--YP{?v%xY28A?`mZ6MJ9Q_)%$rW4+Ptay{59$3Y!Ph#%nbA>h
z%+U6^mv6$Sc%soD6_J5u2lx7e(!z<UNMq7e>#5IrW&7ucky$K%pA=rCEShXVjkbrx
z76|G%%wN0fkSn{56yZ^uS-6`P=+ZuL#NodFwJB=z0He07_rqL?xrKrG`Pkj6!{rFw
z5SMASDPC~m^HS7hTQAKT<t~EpyOb;5>r+>J!!!)vfx!ZK?!E659_(28z;kp$_k+Q%
zVKFS#sAWnpV38MmuuRpp5}My-&}HOba^cd%VUw%rUQNZ<)1q&@(?;QJ&AjPeT3PAT
zA9mlUQ@!E-Wrk|=qAlqmaJ~e%CG at t|&<xojdE>bA#P^IE1AN7)rj>T80ev2w5170g
zXuK>yz8$%@w|`!6xVlI$oiUzwEW|vWJ15yYwR at CCEi@w$#R+|{asa~oUx6`8Jls_Z
z>wTGNSvN`N2+ynL+ull(xupy7<xiV7q!6BIw}}OceM?9ttgnv&J$5sA@>uu6Pj`0x
zc(qIvOmX0U<cO9X9oxJ>6oR9Wzv9*|;(3u3`#9OHe$Q0ug#7rDRK!QM?Lt*^(j1n(
zP8xJ=YqC at UjwaGBXj6nt__s94J9@2&cfA*%0k;WcI%8={O~W_#CZHKU#g9Z|G8<0M
zKh8D at 9N+b5ABC*(^|o3}62ZeL#<wuC)&x`S2RpUPh#$1POxta{M8`_xf~}0IynBxj
zVSl67Y*H%RD%Hd_oR00uyHmR!aP;<EZb~5IvWVwTpkqPk5A0N#*Q&HL`yP$i)<`t7
zE2!!`>iP3=9a=N?B(DwKVF=p8R6#lWds3rb8Hc0^QtnT_MZ<jl`P at Q$*F6q1;OkJ9
zOuq^^7#K3IYnPQf{Ko at C6O-5riu)1_8OBc9<TDWKw4VKrC?C&fpBtZ!Z$r at sK?3!1
zFwdTGph(HeRqh%2BSysyK!w9PJ^bUx8;EQFCBy$s%S^>uj*3ZtbOF3EkGyc)p9_Uz
z?}e|({C?QxoT^|kj8_9t=v?I^I)5Y@=D+yo`TO6-WEeAgKq|lesu?rwxS*-*ZcJ~*
zJW*7tOI!a?uvC)REPOaN{4uU5H`vXkhYpqdMokp7l*jIU332O!UEFl^?K^45!s#w@
z>`X<BYbtH!C+XzUQgn10X|jlzclrmdF`?CAk)mp4Aso)sZ7+5s1I=tR%#&1G;MZNK
zI?gv;0{%S{o|!U<2nVAx^N#w8)i)vQaRqlJd9(W*#y$Fh;8sv+Mg8O{YXU|gp7tBR
zY$5G84g;+1rw(gIAhU*S{f#p)@0U*=yT4wcrR`r9R%?V?oFGV73^hY{FI&RpI-O36
zRW0vo179G`?=iEWGA<7ry3}Tkll2sImyS1}gbxLNeT*z0fU0%=>I?D0 at kgT?VXg=y
zW)`a>HY2gyJ)^@bL(HrloTOQ*+|lhDTG~ho4#)eI;=!>*yc*N^^8m_`6{~PdH3Jg$
z%*MU=#ie(87}R4aQ=}<&6eD<bvS!LHM|)&9Jk6gDI&r0+Yn{!?tf3aB#+HW`Qf0%`
z=RA~{%EcRuWc<FcrKg)sU-J<N73v5?U38qJg)w!#*Vk)u#yGq5`RH;g!n1HFPa~PB
zt<59~JwIzZL}X+&?;o*Z)%e(22ygDR78~-cb7NRrvD{n_G^O6e!B5z(7%V(Rv|#qj
z*4k#v^xVIb*Jbt1JcaG<B&Yy4x->WgHL@&=!{`kDUOZKb#ja3W{JzvIlLKk5Ms=#v
zayb}TSw3TL!@-U<*e3n2hrXVKkud&G$Bn8c2dFSOh04f^OcvE2Rzn^LibK}F9w-!=
zXuO;fXpT=jsNOW_(X_j`-NO3{$kKt87Hs>`OJASE0Tg(G48Ttv at +?KYND?DYZ=XuW
zB#BZU;#sh?XeI;>BWHs#jP~-SMjcx5&Je%+q(_v0#iQT*3%XN5de280X1yC0Y&sDP
zLJDNP`=Ckj2|q7{8C+y%>Ce^PPa6&`z%cp7D#+`N$Zq!>lV7P{I=S8j#f8%f%L$si
zS`^xbq5tg<QhhUs$@5rN&||}Z-U?Q2oB at y1eW{?&WGS_o3Tl%Nvoc=I9@;zs{2b0_
z)(3)JH2}z$&s&DyFVz)Da-d=bvJ&o%fXBjNY+*&0;6)ug%>9<>NQe?qLcbLnBIF!Z
z&GqkF=VW5hYFB3*<jK0{jdgkUnS&FEOfDb8z>=yKTJlOn0^eb*E=lNdJkJ*bYkiDA
z8^0OT*d0oM9hlo1N|e1Qqaf&otw~H#g at j+2hG4+G)F()EsEMe5mh_~;P^#FDu#B=6
zGXuF}1J5|rVAIhq60bXtY`tnX=dV`zU>CUV(MgtBzGC^}8LniUyTDKMGe{=QZImpO
z4pq`?jKh!)&5YT-z%D;b5r>G9cBVIsV`pHcNfS0Dqo9k*n1a!Q==MdSC|X#0SBbI4
z1q?N;$zE%TEI&$Pp0y&fOHp_a9mRu-DzbC-gf=-UoJUHjsf|*yb!5tlL|aOBqNGk0
zW8_#_jx7=fy~*U-p2y^MO%tCra?*qs at REn}fiY+cAjumANcTNS$Fd?`Ldsx&GVct^
zZYqC=oO2-|s?lxK)p;in=4=M_h7mBBp2jtawHmkxTT`^RR+!+?kU!*uqO4C^P*!6>
z(!{T|_((uURjyC;-ih$Z++iE&f7~KVjM3$;&F|4OYt6nMB=6t6SojX($+aJu<@*Dp
zkanR4dg8)d90!m;xZEjEj#^+mHb@`=P`_Q%F0Dme2Vj}qDwwA7m$q}cz&vgrFF=>_
zDNL8a%9&aVe=RdMo~D56%i)1Y)cW3vDl&Y-%uBgV;g4Q>F5wSuoVff;H*-G95oo#h
z3RUtJQb5boRvViTzGFm_)vY{!N*<Zr#V}p}4Ma{1{D)~jD)lPXiqBk;@L&7X_8x5q
zCp~Z};kY05QQXtV_N>C$+MYmv)4)!Xc~~9bvR?jbKgxV0$~<hWsp#YV;S$iJG!rY_
zXf9!-kc(e}ITJhEH1OTc%aeH+c+K{rbl5^bpiZVb=jC~5z{{uqf2!L^0TBzc1Y$|3
zQtlepZR=ql`R at PLlt-{;k5e3yz#Qq|&eG2qA|2%L3}!{)6^3b~IzgV71VCBx{(R}D
z9~U1wM_P=04`u0%N<a*sBq4dQaSwIdgZVRi?SE&F{rs?6BD|;QXBfmG`5_Vzt7mKy
zX(%KU5XUtC46wNPVNyQf57wU(A*zLn2sB0y4*>LB0^h?kVjkWX?l8!2W&}j|k^zx}
z3Is$B+RjB`mC_EN<3YDB$m7Cm)YL=;_F-8wjhNBoqke?ZWbdWN-DJwq|6u1aM^E?O
zZw?MUAO6#}b<;&y8c8vTy}GCOe?F1<@v*3<^>^tFe(Ghs8^Iu>5Bs-y at Z=89idN#i
z*l_UhYt3vyh|F6O*PJyvWo8O^P5S4JL$iev^fQ=RX5x6Y>+xmKnCx0F1z?V<pP+R&
zv3ZxOsoBKRmYG}w2j2yFtkY~Vq)(`pHq^@!SH;x&AX79*G4;5t>Rk>mHctKE+P9&#
zCn_veb`8>`<NR_!G4<1|VLi5v<g#n#zQuqS$xu6{__xyd4$ZwLim0h-kSd(V#nK-u
z{|YiIe10%=Ycmi*W9QC|+MlpjE^yNFi+>T`6;>PsU&@qCED)v1irm|L-h({D(%RWd
zbMyTs?c&L at 9N$#&vX5_Vh#;M4#jdw(tl_+Oe@^kL{LV+~U!dPb>ap(TE*61G<PF);
z_h&c}0J9UfPreO96T>)FV_^<jw!m<&7KIA-y}h{0D0N7hBin(<_Nc5wv4{TRi2_F`
zX=)1K8P_*6_ZJy{G3lT*{(?z!s&1hOY?-ao`O~{2MW!f-(TlRa#R!uOLkW##robkH
zYPcwICU86;Tov>8+a?X}{`c6HMew((;LqtIE3|m{Rk-x|esMS4&DDz-7{7>dIFZm7
z^n+wPwl7$@5%?EP=c=6Wsz4i5iINW=zPFGb#?DLN*swK5RQ;1G#mwXClL+ at pf^(+%
z(MPZUWW(%V-4_I=Q>2$f#+x-%9$k1nWZ^9>1lE0UmPr$wsP<%>0Jj}Nf`p^)&6ERk
z>1W&_qSG$2W*h%56$eD0JqrHhmGyN1={As8JJ*H2=&}*%z*=+vdv+h`EZi=2-*{!s
zBih?1g%!tXFZRvl?VR5poa^Jzmo<mc^>W3g%-<N%Pq_zrZV+tT+)cG+m+O6sd~bHq
zR4FZoePto1&i#jFI7ts5&A-AOD#LI}bDKz;=j>Db=ZW-HS(@BL`8=KXpU+--wt84O
zHPB5ZuCcLby-NPj9}x9zY<b8~I98tE1Q8UcD at ZH{$LJ9+(C8sn&Fop=;}fiUhap1!
zLHpsko{(Y)&YHb)#wY}a8LumD at 0d&Ema&I}K&(k4ye^}(cdg)m3##oAR+zzQ40D%J
z^O=kuK8(ylJkpAOXPCGy5i7o-xf%u^)FdMaAcr)voKW%Lb%sgcH^uQaqKqXbrfkaA
z$aRLqF at ZyoNJSY4KBr6Qi@KqDi-xzuI9RVo6R39Gsb7EEwcph`vgKQLkKEK4Us~Tg
zKTzh6)G*)wW7nONZrcO1l!R~F6TE&=*K=4!djyZ&HRP;u(ShFb{3l{N+p}on6u(C|
zu<O6&<CSKJ#GYXzPczi`i}z_%O^7jfZa&d`zs|e at 8qp4U;nSd9N^0tRthi at pqSc&e
zGU~6t9zzkpHaV4L#>{JJo9lk{idbfp1lrVrTZ<LTQ|l0c&&L?=0&2G~diRL|%osah
z2~PrXPGJ->`&8rb;-KABpxLKj597KB&aJX?gT9vO_=0}V?A!n(NtK!Q!?NI1btENz
zEfjUUyp{GKD*d=|vO(r{<5w$!+4BD8Cq4<rG5Ip|Z27e#N4rr(PCH~38BXnW8AlfN
zwqhzUw$Y|C(`C%2(+oZ<&K7f2c|WdVxL7M_HS_LWNbPLMEj~Y8H9zCXVGOT;=&H at Q
zpQ78p-Q;`A#@1&K6xS-zt2SMH#hy7Ec;8Ys_087VE+e|eslB=f$G8^mY+=k`ap*{?
z^|uMEJc%*Ns$|4&+3tA85a|G4&+y>NJxs0Bh4r4{jSb^Ff5>8ikONOc@=xLMqc{zY
ze<qq3GD0-_ZdpD(1CaewpX+5A at r6gAj$O3XNU}vpw- at U@2N5r;D_4Jj4G_N#a&e&Y
z_d*!@1IBAvGGJQ!rgAC(s%dS7hA9<8%tZE-VXp7Pn4OA1j$qeDo%_f(5%M5Q1?kos
z9~rAO!PK{;rR;axEFykP)(<BJPA-F__NQv|cEqj{j at 7!@#k6J&h(q{I#-4v_wPMjQ
z=lA3$?)4-I at dgT8I(y)a`~G0Fj<e7+Tux`!p=6zpk87Tfuac`LH8v77j&N+6)u#kO
z44{MSRJ6fo!l_qa7Z0 at _{GBb(@Y_0Tm3ZqCIXdmF5=<-$+Fi@<#<JB+*1cib5-YC%
zla0}I(Asi}k{Ua?HR=qWV^f#iZur`^ozsv+t4QM)&YlfD3*OwjkM6N`UrAVM)in;W
zATw}=eRnke at sIQD*n7{eUj2NhyRd^Rt+7Uut1lw(c|80iWTo4kA!N(x6+ at 4$*=PLy
zk41>9>vFtGq=%K{;7?+M@|a%Hcs7?NApO7=u9W4ZAt7|tnQ*eyk<CvgaKSixx4E2{
zlYSUlK1w=pp)qo|`2!v$yD}yI^Dg_GXG7AhG7|=7S>@j}vCG*E{?vMUwlUkT*+VdG
z9 at DB|cXuJ8)@cd~nyXhAzTX=Y_5ddR%_~5!TbuD{$Mq-Oe%7zRQLrX*$+g;cr#Ie^
z_AQO=qKX8sJC<-Y51eNf<Jh1yY6(q0UN8IG_*utxh6fD&AUw9>Cs580-WK)((PSV<
zqIqO+8_$Op%|iRxO_L>66cez>_BQ;3|M1e49fb6dU3R_<P+kY2AHwbA*V{vWbYH~I
zcm>^h{H(ApTSa*JgJ$e-{mJ^f7aj!WG6V~|$p_juF8;O;4Ci09#<W|$j_5f?Y2@;F
zpA+*5>t`u}tOLC4!LsOXei+-ZFjAuuK0Elc7D|llA8M?=N?uc=YybEx`o(Sdofj9n
z{%Q9qx|Nd;d`ov{o{gPbZ%^StQ;h*4j~`sQ1aJe8#qgq^pbdW%U%+k&^Y8J8{0pDU
z!BoDd&?-E<HE#<a=05jg2SenBgyk9zrmqAf05co32x9vVGMk_MRC2#P;Irzv!I`Lm
zuI$8Q6niroo;jZ(_1CD=RN9>NQ3<bl+}R7h_w3v-K$BDxh+P^y0b73T{Wo$%vW}=^
z!^<Zce{bnuYy<GL+Sy4?rM!wZXF<KKt+^z3try+_>61TW7<c8^Jn}`fqjT2QS~+Q+
zGT|t2d$Utg%$-tT-RHtlkU{L*m=C<Zh!UcJOz!X}rPhw2%rEa(BRpBzTH~}Dp(-zS
zg6t*flF<ll-fjLy5#N1<_PucgDz|dio~?bDi<QTyVXsIs*!{{OJ*3$hK*5r)x7e at 4
zD5)OF*tM4K6tOzPxg3V$1&x4G9 at 8szT-T8+ai>ugOW19K609V4iQ+Ee3u-AJxG_JI
z_u-Q<i98kWavFJ=-v{&YkNP^<z(Cv<6DqPw1nqfbXp$|O5;e3q6UH%gvI@)B`L at H{
zLFYyZ!P-XVdlJ<6=4eAo?=ylvj*5gsxDIQ66og(}1OjhW8v!IlH<j%T+_W~vCJ=)K
zN-~H1z{AMVoP%cm77$tgh0|1H%_A7bGT|bPARb_NT at b`lgXZo<S8O5>sHkxi8~ep5
z?EZNcGOPE_b7ZJ17>n?}jSi#U_C;hJ)_|BNFk!w|_yW#y*3{exjbS3bE+adjud!2i
z#cH3$|Ezla at hDkQI7Dh}%Q`_;ihGPb{Uc(b-ef;od)ge`S(0W_+_Ed~Ae!blHn)L-
zDA8HwcFqAqL#ml9ct~c;dFoI<O8xmoDnW at rriG3C<X#ZJS4vp2(6h4%hTBz9-!~a;
z+|R0d0-Gc^%8~7ZL-}G`bn*lNPY0t2Hpm9qU<c)=+BU#aVK+gXs~_g8<T*IP&}N$E
zKIBq0PO0Apay3W&Wy`N;bJJ5yQT6l4ebhfVxLy$A&$aE&oY083$w{TlZl3p=8b at XH
zcmw at FGw4apm)JcN!0Q4PxN$}zYk-1_ET$4lC_m~n7#?ztCsXoinI#)UdrWq?je8~G
z=qqA4s^1-S!$;R$^g)Q!Y;>1h6*I{ZY)oA*LM99Y9wM*v;6(OB8xk&!iZl4G5oNPF
zf=&xmdok0OA!|db*jA3_;AomrX=4fuN_g`DH=d+U4aq7DJZXggfP;BLyP{A0R`T&0
zY*p#EN<+R4{wD4ecvF#YrFlb%CdcWm)vW&2rau%E`!!0T%cOOLAV~I^8DlEoznPUw
zVjz=Jm&0L}ZO<ZFgj&xo=a5WZq1r7jH3}p5*69v%!2cV)YE3wSuUd&e1stF7Y-d~>
zEsf??PF~(A1ksbQ$#O-Upf7Mx&m(vvU{f^d5etiYw2x0BPV%;%7n(GT at acu}5nO>O
z+;1W(NBG0IEWd4)dXUi-W;`k<@!YuV0bc(yoKyF`Yc|5I_LhVa>7>Oj7;#?GRYS1P
z3x0#Ypbq>V&l#JCq;kg==s5dWml6VhY=*~?TE-{eVvdO3)m9k#gn}&ZEVmF&Xy*{)
ztc6(LSHmSdu0z3xDwm-SDaE=)Sd|z?DWq$}8^UKdfrp=;8-y^;R0Bkq!7{FLk3OkO
z*9p*gM<XNrI+eClmb`&RXt9nUkwt}Sq|xlU^BF%TLb?fZ2BBGiOO)Hnh`T!h at zMx<
z&LQ}SA!#-Tt+jXA`RH@$`w<(us4k6{^-rE;n)Pjw56O<e5}SbQcI48Z?!22rP_6OF
zvO8Zol}dtA at FD8Eh6WylB310J)Y3~ieO<lJgvI@`s<h6^ij%k%ZYQOJ_#Uq`6h_FY
zT(wD^3&?5phzoLKZFMTOqrEF@*Cn3YgAhbq<X~dUL~7f;9qpGz3wtYuLY-RpWS>Sm
zWVdfjEa}bW!NG6$-Zq3M2MQz)Y%4H+xiYhW$KiO8+XIBH)+lG%2z66Pi|R8+T?WOj
zYtgb5X!#C`oN0y>wRJquyp?jtz=PWI$+5F5nV71?lRMWhGM)U=DopZI4yC}S+WYt?
zVa<stWO__|^<5hl_2`QBAeS={-xJISqgG&^@Mo$D#<yqOjH_fScr<NVmuhMErspXd
z^S^Q@;%%Aq4M$HaP&g+#_Imy3k!^IAo4(l~EH8Jl!r)_9VauQ&uPqG1(j#Oxx$3+#
zh1 at gy2p-qRo@nfe!$(wqM1!i7$dZ?b!Y7_CS}`IXWgV%1qS%sX6YjL|9JWkm_G|x6
z2sef)ApP(p7<taja`WmqH^glct|nDXp0LC}%G-Q4*8)M?cp$SrhR-j=KuOq8s05Oo
zbUnIS6Gmh;?UIhshfK5>%L*Zi+>^qAD;P$7N^nfVjMzZBGw8@@UT<UW58 at A$;aHbx
zv+=IKGXuZ*vpoTe1mD~Q-LQ>5bP{318RC3~ps!O?pBTA2g_fsdNn*}6 at E;EdGN-Nw
z2dGcy_X)t_7oEOb*Ki=qPA?Nzh>VPP2O_kDefoXRGWKM4ha*?pC6cBH0YSvEi>El8
zBAU3;#l)8v3tA$l8Jp`<<%WFQKO;^lKqeJ?X`-wo5hgAIuQcL7irC-$5V4iUIkC=j
zmJuUDMW_KlpYt$h=P)lo9L+z-3w7nsHsx6cgMTJ-V=*R&qkNjJ`gN+n1>bCZC~OvE
z{*MT^h-YC?Ri+3j4msl%D*-vKL6AD8GNoGXqv&p}aLO7VjWI#dDgoqSW4b<KhOlM1
ze#NE-@%qHcY)DqgPG5vYB342$TUtWIK&i9>$dcJyRGamoA30(Im;uKm2?+l{DoQi9
z;Sj0JmL#Qp%(&OB((Y&H3#cFH<_Rs)K_tH(C^*s;-*ou2_U{)p&i0G{^XMV}yFF4i
zUFkEBJ~QbpcPxiB-0)AzfIbn3cOOQ}m~*@K4A5PIkZuE4Kgz-`#c2#ywR~K&(dwBE
z*5Bn&C8=-Gmc*xs$`bFQKYaJ3OPMUi35W0a>UeXj$lX&C5s{o%C6WcxMn at 3eB6OJn
z)P3M8ff91i>_ilOn#m(X5%-Hik}6UJkwh5h+c3JyAh<B2#k_EqK>-o#An6t>kM<Ld
z`JGs-<yJ+(LLQ35kK|`@>-wbXDF4xEsU`=5s~sj<{G38}lKQWH3*`>ID$|s!hpIQ7
z22PWC?u6h525;?ju&~j0?KIwINBcc32Y$t{?<3 at Nj6^!EzyDWx=2+-KyjX;PJq9Qd
zY&L<R#PGP5vj(>50t}!P3WR<-Ec*iZgsU at 7(F8keqahs>{#x);Nxvg3$!uvP$#id1
zXy&_vp2z;93=;y~(@2rprvnqhVuk~Pa**Z^dQ-^xL`>gL5nc at w-C3v>?1{z3P(Eba
zKqB(4E~*vD6=1C=%bheK*uXFj&!UBK;!$7|{jF`N4g7*d-zES?yLoU8RZuZ0HJv?A
z>gnz)dY}rvoe$C!YILj=n3r(Fbv~&J0&2{ZvDX-da|=<m*T4ws7+(l7=xb~OhaI&Z
zQ}|N|1iMu)(<s}2v1*+LqAr2Z at ckvWp2VyV`MoC(czeB at dFACdDNI7q5yQ5YAPeD1
z`XLa*knrt!3VWcl!;lb|2+7R+FOWk;PYKi;piT+6NJa|06uF{g2v2%NeCq8{;zr(x
zcJ7UN37&&OlH7^!BorB_dlYT~oL>=}p(GDuQc}VE0qh6)3X-Un1qzx6#UcC+$)l97
z&ZCs6Ag^F^UAIc3lx;w-!Gy@%V9ECRUzr5I$n&e at W737qA;U6Jj%obMW;2BLR5+m{
z3k%bE;7rM(eUAjA1B07^4MVIb9DbSqF5HWcK4=JTh<&jDOANVzf|w$a+;xddGL)oG
z7^LKiNyMY0K<f2{c=-i+>lv~83-Wkfbo3XE1vdI$SvXw^!L$T at +`9`0e~o?MX7C|8
zE+(Q$MMQdl;UwBsZvrxb5=U5tx;1(~%4O=yAReo=_tG*6Lk4q(B3u$Qx#2J3t$x+&
zR2d2DnaWkI35X81SE=V}i8>srsl%DMs^={YAPXBKaKZM7EFQ&4_X4%0U1?n^k_z0u
zl-bx_>4z&~hb(#w(0lhg&EX*CDb4AOxkP{;HBySAv?w`QE;lI}VR;jdT7+&QnzWX8
z<pkPo!GakXWnmmR?%&2ZF(zOXAG+YC(*8P7+Pnr{dY9bg?K`@m`{pH&b+3sgteK|#
z>85&-+)bYT{Rp{SrQ}^Psel?ho^~swDfYgyetzfxt)CmaH_qX2lo6Bzq9#I!sDwgJ
z({4`n_Wk77eND?q6?vU(6azdSJqKxThfCHW>JobS1V(vcJ%>nUzwF|Drcr#&A~(m(
z00$isT%S^B<^AY at j?S2kGL}eh7U}VP)@^+7`&w19+{KbVfWNXgJh#pgF*nP%{mR_>
zn(vOCRF}u at O75KpVtXEVj4+J{AvSrbm1Q1}R^nMC6tjet&v?n^5ZDGLr%J at ec5H@l
z;~()m{!w9Kdc4&Fol#+G`Is~z=LdAbAp(&h at t}icamUtA(g$N{3`akPo;5#|sqW>a
z?|q at Xv%(4^KsBCsm8zR})xFL4RYYJl9?*MsnSWzBz;j;KAM_0zt--Ee00kmZ4}WDS
z>sd*BHfSNq?cpktD3 at b&mE;{rOpVa?d8L!^fI-%wT`GE_9$tM*mNkGnYxbx_Z>pLM
zQ_lX6Fkjn8R|X%m1f<PpF#`9vNe^V?O8KuLq<r6 at E{uZyzrg?-X)H0yWa<{bwXr$M
zUakGUC(FiMPzcC&k|F)KEckl at b>8CsFv!8_hCVSG at O%o*r8 at h6lZ~gKx*q0ZPC6g|
zQpDWy?C3o!5to1MV{|m6$BNomlh{dxKsbap1p$;<ShWvO{PJbSudZ0XBiDL at ND|(t
zCQOokF-OT4GA&0)f$k4SZOe;%6bYss(W0kgqo+9D5-YGnLL3X2));0 at OdV&%)unf1
zs>a9~tFJ@)1)!3!jo-6HPMp#tYN!|I*GXQ9>X>+IYueR)j6J1{KVu^DFAfJuoCQwA
zG3nC0uzB~s;8<9$SVYhQKctsmYY8Ia!J9ctUKlg01@%P6itB{d#finzv7%Qu%cjcs
z1ppEbX?h#goK?jal&VU;BmH#4Ts_{!b_`}GqIl!nA4i{6d(a!z at DS4%t93(~q~;ny
zV8bA)F{S$g9{A__#Shn*NcJz?xFFs?KC_Nsq?>e&1kBnHpX7;XWj~nBxG-FH%(#fx
z0DQ@&Iog at eieUb=_IFnS(Q82W2 at UnW1ie0@>`;}Wpp#hoDwJ-48KBT+2qYCPPQe8f
z;mmWnBv?Gg(D%zJlzn!o_Z2daE^<uj6>t;TAuG2#i(pM@&lEF45w3;5`m(*zQDygr
z!0tCdGS$uk)@!?gGRbfJUuGKy)MZKtn-=EN-?uH$E7r?O?kuIcX0%1GhQ57+Zep)c
zJ=rwAmXU{BWy((GxM?ujbSlukm~OQ0!0SVRk%N#&nr(B^?PaZwnwd&zPUq4lvM@*I
zPSy&za6JCPsBG$Q(14qO_mo^r=c)yb>`n~YU`r0zfT=^~E>M|73KNt>N*7A5+fp>0
zJ$ONyU^k;bg$cc%9fw_AQRJ|Tg1M;$OBRDxc_z*r(SLkX+5O1>Xp)nYxsl|Um{@kN
zP^tt%<|}HRzQ)XN4cwh-5~U<2iv{L&6VEe<3*GIv_-5ZjMV_H(?O##uvKh|bt2#mm
zp}3mH at I4y3^|weeM=wcvrFOiZ%u!h{-Q5Q!g4kMp1imTtu@!9^_3PMA8KbJumxDCE
zANO2;8Q>{s{PQ!lM6f%?b^fRCqp4uq7wQ=k#=Tx$`!9d>BbY$_*@9cEutgy2AjT>d
zvNjF?6Jh>p<?Y at d_4M%uJm0r-ody(+P<Qa}>&-PtedRE&=^830faaH0{@3RcNL`B!
zuU;xH;WqM4U)mIW?IOAqq%ja8-<>A5qEiTJE)t6C;fzp`MBWEm0CP(auV$c at cYcs4
z0;LYsD^ATd)Bq2|HE7_-m(k*HxyK^y=~-{7`EISPJ)EswG6#HtnX{{j&*7eKNSI|p
zBZi`hWk4qf4oTTNfnLAxGJf|rG_0MSI_Dx}2Rj*CPnXW5!+5Ly#hBx}e-tA1e_>XM
z|AkrQOa2#Ty at Zbs5*)B>EBXmt{+!F-xyKoS^592<9S*ICsFPycGs}L}*?i2(- at kDf
zv9%p#>;EyMiQ{oUpApz=lmmFWJjZW(#E+UZX!{Z^4fZREd<6rvJlodyj}X)wfLMf1
z)x!xMtub0s7Y^uX)aGU>x5Yk(Od{VGI>Nw!xZs!6v*`arvr_&u)#9p(7Z9>I<l<~t
z2_96xOMsn$fGIv`Td%o(QvdW|>-gzv5uMd4P!AY!jU;VP>$4CrpiIj^mE}dBJtQgR
z`u?hvG!dI8!^#f&_2#5F?2a&gIxUoeKP_~zK?8_mzTy2UAIP!XkC9b;9!AF{RI=<0
zN1w8S)0W4 at nw#zn8c^!ts(thvXkfv4>g58nD+JUm;j(he=Y8$v at B~3{mf{a3I&5G<
zhN+im)&mDd+(sNf-4eFxS$X%-qVIA=13Jw$tnvDE5O0<bs-WrI1TWpdek8<67yUuI
z8p0S*B$^8)g?(<vz7kl#B70umff)?FVPuttXurXO;7DSiJS~e*A!<Gmv$9?vQ at i?1
z3`B at 1yXUmB4VGpzqbJbXZN2|#+aYh`Mv!3W<0WcOgexD>`O)eSDV!z;QU)4EKz+e}
zW};jsp@{?ELz}Oc?;_7qej)6t6|+AM>qMF?;X0F~&jfMIDj(Xa>@i`h=4J=`sS&7-
z7BW4p31W*t4)5`y$J1^D)hm_Th8L<N9(WQggI*NQW8vi)8(2*<JzdRPIsYc?NZWp?
zHzW+;|L_QWRwxge0l<mP^^p(MQ4@*{YZLXT!sb1%y8z_ at uVtZc4+$&LP42~4ZsdQ=
zLxfTG+_Q5^21myny99qB6=o?xX*6PiL%J7MD%!Jr7!cqS9*}<HDhfh~++n`fAVHyl
z+O>LKSr?D2g|$^Nfe7ur5dFQ|?P0G1=eM>c3{=CcjQxH{Um3l1loJ*Sg8c%uFb2Ma
z5BRN$AqezC9KZjEIDWx49lJqG(y+n{2vl0u8l#%;FKC_GT}P%3eA(^Rs!>Q#;~IV^
zJJ0?`m0LmN<cpokyt=<<GOn*UKJ(-|jR&k}3?R!c00T=4+*2D4WZQ3`Py$cen%~3v
zO{tSNMR<CGp5P2-YRYHM*?beZ$Z|Tf%Ao^p#wS=b+&&ORG}e)<;5cy54~BNO2g9+6
ziU2&g)S6{@5}R;=c{pq3><5om-qS%%)Dq@`C<M4!MuPE#toifJ7 at E8{#|0ackC9~k
zS{@|PPIsrUl(I&?eZ3gn+PmBGKvxtd3X*>^Wa3`}1BC=f74W48XJrj|>Q5ffPCkIH
zsDIP?44<cFZm4vZ6sLyGY8DB_(&I9YfthzN**qZ_OmV<YOl#=xaebF~`y_+mAXo~d
zg!7ZHaS7-b#r$Yn7^9nrJV^hwE%FDdDZ#+<g@}%Oj!9F;%xebz8sKff at ztM;88|`r
zFhf_Tvc;irx at lB$3&m%Q()S4TDTBx<Ci#_C&A)?Dz at -CF^*)|UB|*)&r!9}{)5UA@
zDrVUEStVXMK3XQun_)-XShqzNUN8BMk<;q$V@#9{b&f?^YQPqtqmpMaw^jajsQe^L
zXGtNU49CgYTEdwjD75~u*({w|!ht6qVVF+95$3r+^8^PM%z6aDf4Yz`1m?@yVLYZ)
zy}y-i&IyCQ8rhC`G6jfwHMkchQz*#cURpnhD*SAVQfBeZ)w(LEzw>GG&!NiYS=9Yi
zc)-UMfKI^o0k489iz|H;brJ4Ti=|*ZRz0g}nsyNVZL+izf8z*2M~FF2dCo%QWyOdG
zGNIY7J1tSx@}^}2#yN9X?iq~$X;3f!>qB at O3BXa-x0ZXZ=Ha+{lxRfhk{U0DGQRKJ
zXu&l2Cza>nAwmi<Rf2#|V&PdQe<#Ml`N8fBRGxJ_tM@^foSW0Ie_wF=D$I#@t54dV
zj8Dm!!UkiH$&TB4pJ6VC?UkJ!kA2No;6MFtMo!T%wpDsnN)cVC`#!+#3o7U6tjJjp
z87IM>LR8a?BYBmIh_&$ADqpv5^DYZ5wgwt>6jc-HGYPG^rZT#Fd8&Z*{})jH#!!0n
zRwKqZKnZg5cjlvyzWE at 3A&icwi6KO>>IADzI~6!pi3V~$UNCXExkvh?9>E`UaPI#W
zV`~LqscGmp7SwQzD5Q1&CT!+*f1^VP&%hg(!g-%a-(L%{m3{&3YXaps^iDAz7Z?>r
zgeg$4`o_5tj~W9di1>0ADQ~QJk=W_MO|tI<5zSRLko5SxJwHx`TQH`U)cde)x^c7W
ztlp~g$>fS#<hZW`{N;}kE}pUaX81J`V(_mD9P$wIllTFTH(c$}!V|KzCiATd!|x;f
zo!9#lYg-uE8lv)imMa0KG5p|lA5zigunTc_e2q$4X0Ao8$q5`{V-#I_0FF2_Pn58z
zH@?t_nDVhd%%N<}we!B=0`6P_Mg?8|qfJf?Wf!7F4?N~p)(X}u7*ky;m|?6uUk0s(
zI&q;?Gpzg^V)5tJp$v&j!X8-v8_AA+{(77lm=Cqxu2Pq2KrkXu>53^U0nd!Zj4sij
zDfGdbi;px at Y7?H_DZgVIjrQ|5(;At9`du-e@=T)Kkwku8gz%a+iI3Q?s={=NhPZ|)
zN{p8zPYL32?^FBoa}r;XJjFcaEQZU;fklX}gCF82A{;AkUJw<Oz+{}X`VQ9By0Y2g
zBk%%a0UZTDXbIyMlW_N^M)nsWWwODN3zvSm35$>MLSU0a;9Wb94|z8v3gEi>cH<r2
zpYY;DhP(8WhNp>Dqh|X93*lLrdP3bcf{1h$4kFc2F%8N%z}*&th-4psaI)?;EAD23
zlhM0Jfpl-2J^XH^6ZY%crzjyvBX1&QkO_9E at o!Zp(wzWW0X}E9i769qBkONAQSNV+
zw30-TjS39naQy)3Alzc{D`~=C+FNX+NVmm38cW0O22jP{z<ZoL8H)Bot~RhARQ<I0
zLCm1rqP2G3Fa3oj=9jj%fF)QlynjrZ?4AGWN=&Ud;OGg(n*E+w&svldPBy#@b(4s6
zkRt)8VQ6z>)!g#uhgExVLiVaH3N`B(uic)!dUk&>A()YAG)ye#FY)0bPX8%UrpEE_
zUo#zveTfhlE)LFcAM~-dm{EdR$Wq_79T at q&jNu~t^k-k+la+Y8?EJM1hy8a(=`nMo
z&pxSEt}*<1or#+#XJP_kJ`By4&0ryJr|%q})mZsXvWapxwbJI at crW6djk^0(N&C5)
zuBVUAO4s7?i<rj_u6Eqfh5mGCMf(*x#UMYU*FSr<oV(Jrv1{+CiT$g`SPn^+C)pBr
zW8YHalD6Fvjwi=1mf%Qc*B at t+Et}7?DaRH~A9pCmjXy~-0-!-Wa)WvLLj9X^w-Y{>
z|5F?;gff$+exn@=_>4kli7zQRM(+X~?{QC|e8^iy3az-y>uXM1^`%nbRYYz-xkJ|A
z&>L~`>FxXz&>KSiArh2u2uruYutNP}*Ntl-6URdHrYw1!@@=gHdQB4y=|NwcGvF+^
z*9s06@)y&xPSO{1x}dz`eI;By9WpFa%6=X-_lfK;=Z#O&7qwnG&3{vPAD3(Jus4IG
z=mW#9Bk=}^)WfDgssI`ZC0K-xpM{!~S5q49XD-Qa*TE@))}-0+cr*$UQSL`dBY(ns
zG}G%8=(09FlgBf?l9Ujpsq0(^h?=UsGgT9MKAL}zqdT=@?h<ybwltRr&t+RXbptru
zHE!+PWVJoKiW at lR_0bt#T6|`T2Q{36$?L^x<%(dH9D{_9Gt3_9tHPO6P%oo1u_O{=
z#2XvR8G{d6USR4_cXRQr_Bdw*bim=cL?U%|f8H}*XBC%pHq|PZuknOC8__t4_Bc&w
z5hf?nYYLScQN?NFWU~PI0T|a6?9C5#ID<A(8sLfa_ID6yL+k?X;WodthBo8#_?Wzu
zC6es@%Sf&$m1L`}J#`nMrc-bcD;<ODYc2Kl2Pq0@#MU;;>g(adh%&_L(j!3T5NWE`
zQ>B3fhi^?j@%i$16-XL5(0&LWZ*k(8WImh~K=`y=r7Ks7PYmkL(%`Vz7A1~8ofZU-
z7s%MU7~7?FZtwIlHeT+s9~Z_iJ at 1e67k6-JJ+*T0ix+ngkZq at Ub~RX_tdxq-Q!NE&
z%tT~>xM<!7a0pC3P+;0ON;Da;)eH^pp6&fFkUX_zqjLnJ=hCv#73Cu<0qDInaSovm
z8X4sZUN0%mQ27Z8SySwvKL{|0UX>vTlyi--cCcVfEd+<cBy<t`9fQu}9#>yZ3 at HqV
z7f6?zY9aiwK2?!EZ)`58OS};Rhz(3(XKS=kFbSeMG;6)7(`@hm1BO6(zv2xtN^^t!
zn-U-JI{rRXp2BV_PvP+ at PvLn~o`O>4sp<$YPYC~|TIET}bNO`@p9)ocPX6$UkCiVI
z&Bw}Do=Np-LqESLKHrSuQz%l!r%=uoN(RM;ct9hw2lR{L^P>3to?WfYs*jx~Ouu&F
zJEnZ<-*0Y$nmtwfd06DqyHkb2yJ|jR#C_^LQliYGDt~I*r}>K7&{H6Wp2Bye^%QN&
z;}w#qewz&40thH&=E-MmAeo>)74!wL4AChRsVY_$v8zD?oq<KSN#HI}&>5&VaaCq^
z7JXD|I9vuIk3z6Nqg<>IX?OX<Fp(pi%FboRtK>C*aVYXKMEb)ntPEDjIhDQ~#Vp>d
zSL?|KKh}8Vs1&k#NHf``xu~L;zFeg&;5g;3H*&EGwz62!=Ut0cusgDrRxM<)?w4Ud
z87*kHH$de2kr8|buOQyH$&8_IRN*q=K*mAM<8?+Q3^ytV<lX`Pi{4elg at V>IpAQ}u
zS{DHMXmG%Y&K9f5%wNCanld;T6scOwO<zg*7l}vUUS#ueOi^e_vr{#Oa7w{mcfDFq
z!Od_o%MlJrvPa5;LAa)ui)6Wxrp^_KD{MvxF?Rh9GdOn1&lfCyi61YX&H8tz(#Z)+
zW3*7s(^GUcy6sRsKJ%=)RVclCr+I%yg5SM+7m;(zz%CnWW);4C`9d*aP&AauD91?*
z8fSFa=f70gPTf{ZvGER at cr5&Fr_qU$v31E1u_zrPq-G0clYv~hk(!8%p(U%FwW}yo
zvg~Z3z_vBq8c<HR*8wfN4~>Ec?*SZGe<g#sKHuCeCJ(3sFY*S=c`QqwCcvPEF->|X
z#|m^`E+X83 at Q~(q0uuyqNjuKC)*6mGj&}j*tUvuJCr|6B&Bu4-u*51ule!DNj1aw2
z1VCsQGJ;ePkmaR<!NuL^DkB}y(`Def5H(_yOY|+I+L6~UZfwM$p;gk+7>K8UGGvB!
zwDE#<5=7+oT>G2VJuE*$WrMHb`uO)e`3*XnR1Dqvw*t2>AWw%~1EH(+L$Drf at p>B^
z?D)FSV0=ba1>#!8MmFAm*h;{XR5TD3pouDiak7fmAqk at pD*O!s;B~Jz8n_LDFCHv?
zf48J&2)raWhQ<hGH0=@eqpCT$K9-jYLt{iKs at g&vH+Yt(ti52xNH=|B!%apq7e*Zi
zX^yxJhBRd*U%tM2MQ7{`K0}!wcPJ#UxsncpOep;!kVV+f;ZH~mOx-1v&!1W)?V%5L
zx=eW9mkuw}yL-ApaVA%qgBE5BF-|ASR#$}7?UPd0E-*5^J+TYm|6tw_e=)pvA-4PW
zVWG;v+tlge<M{S|vmMXo8!-1BvT=mJqaX1<%p?O;nG`)}bH4#lnz0WKzwmN$vsir|
zliD605wA0b_mHPnm(Mp?eL;sfsoY<&UWlU+AxQrX;=Xc75fJttZ_p3;XTknRZ8D8_
z0P{cg-gj!f_Mu$rBgyS=udSCM`VH55)D}AEoei8$2b9dQ+wQp+9 at nMtpdBAv%Y+-8
zZ1AKBZ>JyE=m%y@?YQH9z4i780uQd&{y)%beEg!1Bf}R2>}lj|{%KC0A5qm6F`MWC
zPVjgQkVQBD#LY<)L5CLl%U{r8EVmBi1`bM<qobcFR5{M-7N^bp5Fek~0hbV>2Btto
zA#W9Mg#X;YQnj1`WDcnmThig3(BT|7j(<XP^cP+~2;|3iV9O(MaKY!9%wu_}!U<?z
z9YV46t5X<7UY{zbrPA)}layS(2rHCr!3tF at C|9VWCD?eNXZ!F98g(X1e8Rr<m((&z
zfrz<B>)>C{CN))4f6 at qHo#p=44`eb-hTxASEet`rv|Plf${%B;$1Vp41sFilR|H at 2
z0e$)r*96^6HmHEECd-dcFkBKlRKgZTWp)??M1DUTlrpViQI!_y{VG{+;74WeI|$oD
za<AFLMY1AI at kxJ!w*F#4Kg|3)`dpFpE*>u%1TQJ)OEf{yMLsO@;RDpCrUOQiDPE~Q
zU at aKL$vemS8qvLElSP{qc{jOQ{wJv51e^PMf)`DAY<SOJV^Uj+s6Rmw#-vPO#AR;J
z;WtV#TFO_m<oFgGe-94smw<5Q&kpc}c|+bK=KeaL{UipF(-~Rb>D3y78b(}!c!3Px
z!RN>hIi_-lG(8eXk8B4A<MDd(ncfpE4*y?1%kspkFp&RX%@de=TJ-^)bqCxkn?-lH
zF at r+F^$NtGYj43O%PSGVt88#yEs^VvQmGh{$R5BsFp7<ngS$bd^v-eT;FKb<pj2-V
z{hQI+XV77AYF?4!&XMd*OBCXCEtU~lj1`ZySO$v1Rum3P3 at 7H+8|cG&b$_>kq}?q1
zTPOcESfVVN>-4KEj#I-&?kJK&#A{hD0d`h_9UqUHE&AaH1V3R&pf^Dy5Q6~T`Dw@!
zFQ=@1ej?_U$1Q8~>BcJAiC!q7So*~+jIy8S>``*!OZH;v)G`t-+W89ql3n|TJ*uJ}
zqP#%g)1krYeuD?(%M<mNC+dHgC+g&iF!l&q^hu9>Cn&4R5P!Yi?WH at tHQW77cQCJY
zgzDSR^Mn`QpvGLb;1$-2nw0{x9<>zWuyJEB=nW1I!@s+Zdl5K2z~7_ppuzv$dpl?x
zDPN7#jSUxykn#x-RzY!zW5^-iBaeb at 9X>1$gGjJXLg<kqDrNb?p;`24vN#gef<yR(
zHG_CMtQm6q{Ev*- at DV&2wJ=Sfsmbw}gzq&+Hl|}RTx^JpJ%2m=Ja@?nB+$ahc?BP3
z#~*M08Q3-e_L8Uy;WMRktYv1Adx4L*2(EI0B+5Off4Ob=iTClpvR~hXLDuWykB5iN
zTReSUH*v*}P_7&}t58Md4L(lie`NXN!*$E`#zVX&dd<dQJaC2$;^F~{1B>u~kd;S&
zeS=EGY7(WwetQjk&^c5hjv)k?N+Xm*<)4INu;1{QDB=Wy+=@r!NN<w^J)Gx at 0lS<u
z<iervUY-rI^d^j4CgN$q68m?U$zT3Lj06#`+5QLK08bgbIA1;B)sQT>Fz#A#6urjl
zB&7|3MV5>Pwq|ef@{c<J#>#UK&hV5Rj7=zS4Hq^Vm{Yv!fhimOb^vcWi^QNGK{p)F
zm)xlJaN_q^aCrsKB`1rYj6Kx}8O6z8;Qhs~VJ)XVfE!8Zw?i10PQ5;WuCvNVf!zn>
z>R9e5qHt1V1Sw_tsu-nRzEtG>9$zYN*yF%2`b;0$;yn;6s{fqh?G+%cS2J{2$mj1j
zY_{E#jS4<RaW8>|aQJSzg6$KJ5<r9{!a?g16BPcNwkmofEznVs2BbdBu=yW{OrC3^
z;XAk2=^ugKe;B5Y8!~@%MBEI+EHfEMDQ%8q_K?LvpCw5?7%DK&g+X+r%VBU%vj|ME
zY+8&R*Tt&VxOc(w4;LA=9N9OYb)H`mjY&VznJ)FMOmkA)-R3#zJFFY;X`cU9(|UN0
zg~Pi1<_o}YKgreemdqFyfw*v9qY<1K*Y`_=&o at Nz%)tOy<B|1YGG7Lys84Q9l3nTs
zJ&>C8fUE|oSFWFum#(DM=eJ&Y;;QX$vCza;7#ZaN3q(Wjr{KecD1FLy<u&7jP0*j@
z^*Z^FsEy&J-~l<y;9nw4fyo^h1YjAa>=NWOOa at JO@_2*h_?Ue=x#Mw;h>;IR%Tfou
zi%|9bk02gDCUT8#uhZy++1|~U8!$F7f;gP}Jlq6C#3M(+dSRD{D>UN%BgewJ6!-Ri
zv7L_z`HLLg;`o+zxs=tp;5nTxn=;FW0a8#KC=5HOFK7B>eL`<kf#8LCd%t1<ufn!%
zk*RXXz8 at VW&nUqV&7wshV)XtMMet8t%~X2`Y#}+WP6Hn-!ScXKx42ynyrBS$hQ}hg
zaU`JS=@aUBjjosuIkb}Iy_|gV38GCj#lwqD4tq^;;w-~yh;=?p6Wr-|np~X2)hY=i
zzq8X7to*e3!*ymu*BP1#9H-uBR13VXOG+MW^DU^N96*=uN2Jzk#1lKD0ZqKW(BFo3
z^s9Su^ys|mn!H+FuhGU?<iDIWADw!=@ANbcqfirOE9G9kul^v_YIN&ukF{K*+Yf*5
z*Bf0ta_Aq;QP;(_|M4}g_+v`Y)|Q~})q^~n^~Yz>tmhRi`=wAlLO;P2!2RYhZQ at a>
zTdLFpb>tB#k_AN9B<=Pfz^&mGPwRH0(v_J11XYoO<?TRu;@6Y~`i7qKkA9%LFx8w;
zsDcVMtRu7u6e;ODD?OOpl*%bPJUnXVxXK<Vg#DYh9=%?fIs?3skK%^_Q(s73vA>1l
z3vW|+L`mR2aj`(N)zZg`{dD0^mI1%ke09GB9Vt|Qg55Xp&EmFS@*U9C#Vwg_<&!CO
zn|kCWBDI{qj*RMeV8l<j&{Id+;et_}z<%5*jETeLW05 at iDxQ|g%F9RMTw`Uc<o27r
z4cws-5W7}VF(5DTS^6`2JD+aZEnOO#WO`EtrRbBPHlI=($R|9_hX5Ca4*RVkd0RkU
z4saUQ29EH=U6y!2M1bAV?YKo5CvJQnoF|y)S)GXQZ%ExvA2FnEr%xPGx6@}FQc>b5
zhLl|(PM?LqrIg)49YoH7?#00Y^}fUUNw5nsw?H>g{>6xa7Zr{^s`rD~7LCooIi}zP
z+y{>sn#kWdM=N+q at IS_6u^!8%Yzrxe2{S#MrtjQuSGUAG7MvFFX!5AHm^$-}kU4R^
zfUN8Ffs`+pvbaisBn((LMLkC6VI_)DB?xBUZf!%S%ojP)azdgknl9C_(mNzcsvo9D
zK^|=KQpd^{vQ}9$&OlSB9Y`&UHHaE&E5}$c3<mZ0VXOj;CG@*GBIGtYkgJ5Vqq!+6
zl8GnM^FSF6Q#qljc#G9%mUnM6oi7&TxR!2Y1T!uVwPMLuj(FAYmJD5*d|sb`#U)VH
zCSd6ku%iU5yfy(_pFn|2z|tmA5E2OEw>pCZcJYn>B-n)I=@G>@XGeVK<&VNC7>T at 0
zv>=1tP)^A&9<kDF;W>YpgszJeJrBuVG~OTNzm)RDS+S6}sEZariP8hJ8yx->g?ihF
z)$W?s4*u*AlzsG;xzVVGB5pD2WWKL$aJ|_+VjrZjp0W|r6rO7*<Wql6?TWR-GpbkA
zKE-kW9O7e&`z<S0>+K_SbrR`G<7xYhx;mHmvyP_i_PGbsWRU|j*FZ-f48Lg|oncJv
z+FdN#Q-%{u;<*Ntko<EFsh}yIaZq_T_gmly7Zxe+yngvjuTr09k65Khq^ArklE8Bf
zDlYNo98$Cqo^e23PPWsV+3G{ENL|*y<wa^bxvTCxl4ztSj3k=CGmRuZ at iZeT50Abw
z at T1Bf@u=F1x0r)NcAGoH<;;ng=0}ovzr~3c62<Y at h{THuaS=t~tX~^M at +F0QMj=1F
zy9dtFplQZ<B-IX&(EmjTl&;m3AUc(W%5kA1@^qKan6es0CvhS=^71M%D<)>`b8wGm
zv-M`Se$*Hb<34eyhv_`yh?nw6zl2tHT|&i{30BfzZLGu>P?B=JK6vecy@}gq at i+X*
zu+h$S>mxZ=Di+7uUKdA7$q6(8+x7g*&O=C!{)AB^C-qDNNuA9zj-^-=A?<4;<EGmo
zfF9i7+MvUZGaR(uWl^Kndc+8$J8=GM4KnL#gUs6BAhW*CAhW*qAhW*NLG~5YJPP(X
zTTdQwZ6w5f;_wR7dB(9N<?)P%39)6K^N<R3H{!q}pWJVM%sqO*?Pat*`%wFe<Luc7
z8Fj)}t#aPCJJJ|b>JFX9VmxwevDnWrsDzXme*hjzmJYJSA|SdM_`xnGdE60(rKh23
zix5TFL-77(hrMzY&$E}E{6Rkc(K at i=AMFD>{;_aSfV-p=MZ5cadw5^45ukNZe;hVN
zJkLeAuO?Htyax`woAv7c!wuSOruZ=Xk9&W!J;c>HMyL)hz<9vU2yn&Kd^v*`EjT_&
zC!|+o{AW1AkicF*2CX_g(+22G=9`Yc2gum;W(<aLmd at GeVKRWXuWzZq<O<$of4-Sd
zZ%C5h`2=$WC-x9LhrZwV$F%p#HlScwCw9Q406t(XuN8xt(KHvHNKrRth-dWbetNT+
zu6<vyW<sZ?NN>BD%%;;2pN5tvAW7C1D56ciuOP5A;NP<d|4vxf;4c{vhmRfc;K at 9R
zKT<|K at Yi3iIlP=$5_r_4OM#4a)NH-$G*0Pz@}-X@;4zfHg=^HsYRVpq!^8Uz{uU6I
z?(qV3bw6Lsz%MO)L4qEE-m{0bjsT_Yu%Zz8N3L at u?lY`%T)HWC%wm<mGF7t{!vSL+
zdWW>tA2!^B8K7$(y8zk}Jdc4t#?HV!hwlG1j^hSF<G`Gteh+^~;k5bNaELT$yv0+s
z*Bw*4)d9HaR*f<)mMP~g;kDZWWJ3>0vZ(M at y77F5$J6}!fq$T4XaIIaA3PNf*d1c{
zYeB84V at _m~;|zrq1?2GPfaXI&g2EgD2n$K1Rp-(<qJ(gOphS$Rmd%iqOl_{p8>*i&
zXGnuHda5m*G^Kc>MyW}?X-?7IJw+GnzT^RxslNFXHOZ$aTmC3?v!MI?9#)<ZHe!dF
z9>#g(3KYiQ6J(A$?X)Wq!_TowMT(!ZPkb<VBKI1e6SDs(tWIY>U9TdvrU<*nyT2od
zTv#JVgWkyV8bkd1GnENzNFjC)0kZKIpkv|n>XqYRedSdMMiXJr5Y1^e4<7nWmJc+o
zk60ng25>w6mpl4?H^8pJ(TGz%KD|5~Qve;-XPY1on#^K;JKr*uYx$tbmuP1=gFA4Q
z+5#Xj9uin=ay4Jfi7-v<dcIxaVvuKWkQxDBpWZJfYjk&yPe~O2hi?6wEd|?IUc(+w
zKmj)dX$KO5H(U$gS-GDq0ICL`l5jTU_(fogR#0oe$a$7-0+e&qo!t7|W4TilO+g~m
zyZT>f4dK7j*c(jnFI#ON?m**#WNDFU3f6HR<twl4%Imz18ucIryaz#}2QoIY3a|6l
z>wEz<YX_%j1i074Z*?)hLT?Mt&<12{U&1~Uyid4^R!Z*Ej^L)CJ9CfA;9(mh!KSTN
zhYaX|qyNzeyCS4Uo_g?fqSNY9NYsM^E1##Hp;+&1lC#co`hXmA5 at JONp23MpIPZca
zia`>SFFPe6;HpT8!n%Ox+~yk3V?w+RGi-8qN67)?`Vck&9P?t_ at 74|qv^eA$C(WMv
z;DasUANTV$O^iZ2#R>(e8(~VtR4IXe#7gy)uBXTey*r<s24g+HkFFP=7a!32^)6!V
z5PN8PkfV;AT_*grx-wsMhvF3A<@Z^JIUp$jLcd+6&gep>kEw;aGJ_BTow(rQ6S<~h
zJJ(5HwU&!(2IK=2lmJ+Zf)ly;{#A(8X0d2jwpXjW6p@<sJc(one&?u(=VJ|CY}Mxg
z0>4IWueMP|v`EB)K4M215ngsd#3JpshvnoJpJw_u at KW7bz*%OEdK98k71xEhB}3eS
zzgaEr!`Hh){9c2UnU0v={T3RQzU$r?+Nf72u})~L%`~i_J_>nH2azhYq<se;Dxs06
zN2@;K+ZN5tqJ8h)%<n>%Xnm|f5X*{U4FY4Sp_FXE(9UPr5Q6yQ!Mvquq#4Au`F0=6
zgLyi^Q{HG|(9u%&!3iF#E9_Z+tZn-Bey`2V3}vkT3M+b`4k~t<CW}wUdE*OPJO(}i
z(VdziH)|Ixaz%^`Q|t<+m at zJSoDmM8cw~?A`NgBsSI(r;G;Z^LIVJsq=ZZEOc{NRH
z$}(ha!yc8q#x)Mc7MpU4B<eJYijV|M8$%M09wgG(R4<i#ADXI>+2ofNX^fo(cr#)Y
zk49m7P=B at A=Dg_yPI$qx^pv)dnnu4N?6GAO4b!aE$vA8_Q|wF6S=Y{2scVPSHN{T)
zRB{DbQ#0+p`(K;2O#nIpng4e45n4gB)n>~UTRzBy#%E8M#@wp44`zx~4alh=&((<f
zh8#4!NH5!6Me1}0jkjbty7b)VZ}Hy29-T3bqI-XP^<)J>Zc3dx_6#kkXt-X3JopWi
z1fej*xYKXAZPdqSM;5kGX_rHqhOJ4%8xGqjN<x)F-;Q(!O(AdsuWe%~>_~Oc7a~kU
zl|++QLN#fCx}Z%0XJEIwZ#i9pX4zVP^4F>?J(tX2mkN6x6p|du+2*##g<h$`?|Yc3
z#+c{UTck-&n!#BjcqbdK^zaJuUeT=teurD*s6zep)lFW|bSIVlHH~K3A_rb4JT3)K
z|88#q{x_}$wc8{{DIe~d at feROpwu4f1K6G#L(vkzl=qg?e1!ZT-OZ{>#m|TP>S9f`
z26DB+66{_tsY3G6^~p6+k5Ot74fcrObQ0vQ8lyps$h;!QFoFtl#9H8e5E`N%&%7gC
zV{Pu{J6*{U`A1&Ik+{!r6-U$E at ft3;g`>_(%p~8BVDKVD+e5G4Izj{+a80&8xWS=b
zaNHeuKwNM*Jwl$-#YwGzCE&2XeK<nx?QB2X79<7AZ}BK at 3(ATh@>}f0Z9x)H at mr+j
zws_6ov=FC*cH_)(-;Z%CkIyCVFEJ<zgby9(Z#}%8SS7+$6?hTi8ZnZ^C9k0d5$lbn
zGinb>idY*tI4B4F%M7-(Gx;*Vy}u1&ufTT)IFB}z0BJK{eprzF(Ux6b98*W|`eZvH
z4AJ1AwL!Nm9h`to1 at I`vCF4LcH}n#AgYNI(mZ5SixzE9636wLqM)3|RQDApK!s?B;
zEf=)?A~Zr&Xy%_rfL?G}ukNF>BPmVY-%Rn?@`-C%SVeM!si>So|Gvc|?uUShgGEBX
z0tmDta7{YDo-;U5AJ5A$5mv8&-}Y`k4noFw5N-*;AFOphqV1Qz$7=mQ1PVVa00rv8
z>*e;#!e6Sy!_?N=)Pg#MiLDKZQU9;7%o|D&7`1g65G6OgU$1|n0Kf1nP`?FIM2N!i
zat#8WV++y{0#Cx-l;y at POl03=O5dl+;y%FIIMBB5k6&o9Ri&W<Q1037gy2e#p=q<Y
zMQG0Tj)NH7H0fDoeZ<H>r34AU&!1Fj5UwRfgOC~6_yV&6#u2kTZesq2P(|v?ImRRV
zaB~B`40OoLj(#Az#*Kx~z9v~hLBTcLp{_B1BrPV;T|RCX2H(OYmMAKdez&Fa`*FGB
z(_*f~<x{JGH&(SPu}wUQ?HE6+Og0k>x+S15${;OwjYP65bHDzD_lEv!EFhqwAs}Gj
zkb^RI=tHaIQtvh{@m^Gi*SCMlr6^1;bk6VkpV4%^+H7*6?=Vg%So;GCJedS9a6uhM
zX#?#yd|?D-A<MXic9>|B(1(O<IFmv+^rTg?6a!5$1m-|2Vku at c#rQ8A=~yT&4*DS|
zaF)7ao)C(}G8-c}RuF#7N(w)I;=kinHmJpN{nMXv2U5|;!M=a^Ls(;i&X^!4S2l3(
zWKMR3bngU4bg7&z7DGbE{UM5 at kQF!>YbY3OFwn-tfeXCfkGNeM|B2eT(4iicYSb|Q
zW;Sv%sRl#f6U~o>Ol&MnKnc!a*;l~B%@2r-W<c;|$p*{*V?DAXeug>0Q7_n}u8gZY
zA3@&#2N4c%w&{17^%f5=N^Fbe!c_kKhOzHLzJH(p&oPvQA${^y5y!6-CXL~cIYN54
z5M-KW_)6Uqy6X~z{>L`wzkcNzoc9ajk3t$}d1(!nRU|T_k?jYsq>tNN?{1T}R**=)
zv4Zq|w$&&lys73ZKq*|ZPAyBhsg_HW!#bc8W{(eoBN-mSS1Uqo=d<^HQ~t?Sqn3wP
zrPdL;B`>(H2#M=Gkf1?QH~2(J!0cBWAD=kk&_YtfDf@(Pi;)a6pvc^Cm4htAohv8c
z*U=Y+{O|I^AC(09Gd^=J!B^1PZ0>L27hLLCjo_^OW4AZ_k&q5>4$4IRs8oplQK>|2
z^%m>Q*AJ8*ak5yD$}rw*IO9%NSdpDVvs?oMVesyPM1{8(ISTI&Q1+~{nXsU*$RVCR
z$iZj%tI5^k0UG#r^@;k7(Tt9#ufnZ8wDH{Cjz5v2F-C3Xn@@II(UpHQ-K>9NSfzz5
z9(NhLPy~GiYWOSj&CbCyJz76vO<3J>&y=XqB4C$3f|6}~AddWu=b;bYcJPG;A4ld1
z{Qvko0!su*FUC<1q;|%X$XJDQ;Fk%oJpmo?tuGGG#r&g>dgpHIh&-b~fXB?t3ScCo
zZ9@{m197z`hK?1Q;2xX6lbg?zk3K#)Z&vqfpkagoONTP_?Q(^sK27Eea$WKH#$S?z
zKCGbga7V024<o*ZaWj&pq<;6qQ}lrvQ0D(6grLv_z_2;K^2cGyhk*P1e-Y}D=@_*7
zhA>u=#Go>`10K)@{AyvKEc{z^2(N>ni1(X0d$56SC-WtNk)~CdZ~t=!<B2{jqG_$*
z3`LrWk&`0_pVZeAk~yJZUaY92a8QyQJCsi$)+SIk(?2<)V={OzvYo6y_}eiIXCIy^
z^gCm3<n<ff`nc2RPz@^Ac-QX at hGXx2r`Bs9CS^k(RfSW8>|BRGa^X*V`h;g1q(zcC
z_L3H6UUrwQfseNz>!y^ZWZA5q7V}1e-b%qt&>N&b4l1iB=q)2}@(ItsUlyw?KVtF?
z-sT3o!Koe$VY!{-Eo6b~i#K-s$MJ^z at m~{s#-Gl7SniH}{~KZcjR<@vM9EHXCk>fv
zU#sX`@xLD at ACz>eCaP8W{h09)mMSuRgf(U<VEr(ze+jRtj+Chga6Nww^-P7N0B7)5
zQJvJ3p3#Aa!*x#@PG%1pj^Z`5TElsa{=&5ltNA6~rjXa}UDkV--Eqh9hK&LBmZz^~
z=qd5DPnn)4iw)bw2=*Y<gMvSkwCK(@yNC5Q*p*=jPiFs%_i?fdZegDJ8@$g?)}%FN
z^H1~5ikW<IK^v!ZHr`A&<SjHj3dSlAWVRv}-))E`j{9))6G>!6i^34Qp%dwy1N{%?
zjK5yPsT7}R at W?0oUsxuHsV@`s#XY$;P&N{8=BMD;<6*1Q=#7Tt5d^1+c6y%61tTdK
zYaisAFN_`wt|@}~j+~IiXFFfOOLVvZq1`dxkf#I>=x}lkUpJrU+vyEdTo9uw%@M2e
z!7-j)>lM~_=36|GKdxsFz-h7ibg(XF(VxYd{wZUf9&GNfNEivXfT`m4jtb*q9$fkV
zII!`sJ6O!t2kSx>{e5lWpy>UlHwfU_ at Lxy&1LRhlEs^}Q1U}AEv#$P>u}`6-c#z#1
z+hG-XJK#}8M$jBItl6=$wpd)QuGn>7t-gSFzC(3k2$32>hiYnfhZ_Qd`Rd6-?`zc$
z@^p5qUoA!bt`zmF{Z{p>Y3p}zy!F3q;kQP2IC#&r)<_9uv}BZqK6na(7dkwA1OB(o
z_V#*qu(|t>Ec(|P at D10NokffFuZ(gA|3l!1nRCMZ25SSS^dlNr=na8A3GYZ&*I|VM
z8CxeqcOi6$rxgABy%(UT1h1-D5(S(D<;a=f6G>2$Ahf6teI2wuZun!;IG-kj9|v at k
zAk3D-s2ULR)UCmlnZC(lH;0s*XSzPPvw#c`4*>kX=?VUyg?}lg(0Itr7`Q- at trn-h
z at fX**wU3p?%?(FFN5)@)jV`P<vT<YwLxi>=9!Z1$NvS1q9_lo6P0rDv4Krhqh2wTV
z9JuV$|8S){-r(Uj8xw_UaknPT7*<0{$E}UMM!N|Q4h9YHTwO<FwoIdYLakU6a;eiV
zyVWU7B~_ISc}B`rICVS19*fV_u<=UO5my%2<>a+Rstat$!W0Mc!blerc620|9m1J)
zHJ_3c#TCo-JfYHwB?GQpUPTBek49P2m6$z)#H~&guui at 87G2N%#S9)EAD}Rj&n+>5
zPWNZ~ghcwYT_N|pGk-goFIYrjBIch~IYsx9EjQ>^syZ at e%&oqc-HWpU_-Hvv{S2G6
zYQPdkjCR}Yjk<U<J6NsPQD4%V1DkP>T;X!qRjjsuo;++&;KZ(M1Z}B;W{6Y=u>oq2
zZh%^f2DnPm0H*5H4Ar^ft1|?1)9RX@*1<5w>y75Bbb7IhsOJ}Gbd9d5#POs!8haSs
zA?2!JCkr;Rs9MYY)Jhm>Ppy at xZHK(DTd<1@!%8ToI5PIr^<1t_Qm&KrKITu#RkAr>
zZ?<IGlBE%A2y?)z*bqBzK1+p&5teu$d(W|YN=-ob9)-3GCFC_{oTy@~FsXg5!hwcM
z`|nn<*#`BnPc=2!$8Kj*73(YLEpp(_iK-1gnNI?ew8>)e5UicEV`_Fts}cs)2bF}!
znO1dQqy{}jT~p*p470oEm|B|(vJB5c^vZ%=6R?a`$DzCFuhdS$bvrqTeO|3+D9?qE
z*{uz_(gX$dlSAbrOB7D3`PK=6=uw6{cqNW0)p<vscFJM2TcSaM+1Ln&#^X|<9nSZ+
z@<2S^{PQSG>o_NcKJu<6L?}(TxR2!0-_b;I_H#eOrN{fnl}_^~33oHa6aH$3UJjTm
znbE<us$lZJ`x_MH?MdVzm=T>ss2g9#a23JboiK at 4QNSzN`6vh)2e6&~A at SzLD_r0Y
zDoXsw06v*35+$#{zYCW}j-eia_K5j|?rR>{8ydq=|8TlF0`=hlp)jC(*&t!#Lz;Z<
zuglK>yo!@1{z?DlL<u^MEInm;Y2pm(a)k9vpL|?;N-+bYC>$a4JzjrO*1tb$dkszf
zNtjswJ4jkxe_1-Le-H;r|B0<3N5`$9%`7e*v_=>uY7O^cx=7m^?t8bbYYh?>Wl8Hc
zg~SzoD+!abg|boEI$+L8SF}#A&X+7m84N;F_QQHJ%6U7xrWtR7oPT}l=5Uj8VZM39
z=5Vv;&EY1#IatQcp-|XubND0f4eE6m8CKu>3KAErpV-H>^tZTZ246o%f9qE`J`b`C
zaCr!SiwhH%NAS0P-MF{PD4NSZu`k?GV4B$k6&rtMIYu+{wD?othO59we*A{`2$!9Y
zn at YJ_qTcy>B~Xw`HOqw<3NOymPIFw7ngyPm`NC=8L^;Dx;9*4O#Ex9waX*2j;0~UZ
z!Q(RagdQDyL2q#LuP2|$a9SK*c#z at vtl#QkogJ&{>_e;92dAqXj_|`9^#9<`@gYu*
z_zy?l*e7&A(<I|%arh;R64E8^`S2=fJYW9<7loYp4zCxJ58z-=Y0oN at _N?-|s#T$!
zwTb|WPks`}XjUr%woKjMcCAyL6c&8ZN&F*RK^#4FFApk6zkz&ML2{lW(opx9IBSsl
zV;ZE+8bs{0RS4(ss9vMx7dnl7dd5C0R|pb5`N8)XtIO}T;}Tk>QYG_~{2;9oxN_zi
zt?pZ=O%vI%F>;|lD6Rw73P<Qa=$i{6Jgi|53~tM!k0^PK0FI^PF(auN at pvxgq4e|z
zDSh~2gD)X{y&-<HN{GJYAnvON8~-2UyEWdot`G6P_3Ho3Pyc)SDvRbMt6V&MLxK;<
zb>|OkFwc*G?(h|bI(dao(JKPJ at rw3latfvdpcBXli&dn+YCuA#+w}sc=9Bx`zt8^%
z!bn4%6i7pnA8Z+xOZ49?BSmfJ|Gk8=l9xiXzk=FYxRiNy1>=#VIOyQl$a9!>`(yP1
z;i>;Ep_VZm15A;2(H4{m>`Qq_NSx{tC#OX<fI$HW%rb?D#tiiXe{Xo_eLK0kW49&&
z$pq8YaOimZaOX!)zJf15MX>Vo&3FNy>C2)+{Nw200Dhn!et>tgxxYdtZ{RJLoC-%a
zIvzvC$M7t8yBdF*ueXpy7JWH7IQ*9?4?K4M8-^$TZ#=%c!DrAQ-j^dhrp7dr at Y7G|
zR}RPCoEz~WM?W6n38u+6lR96TF_JQdKoG(ONK;KjvOA34OdpNIB%la1YjrrhVg8~n
z#ogqCFPB1BKqAXriJ)5hnVmpKoTIO6cbWoRyhqPbE{$iIrpol`Of8<;wsNN0MY at HB
z3p1Uq at B*Ej(RiHIaO%(v=L^g_vbjR{gr_>#17T}GeXOi~5&V<MHUrVp#pBANf(S-j
zvM%2HhpmnU5UMn7>x3j7rU=OsvTBP1QzegR^W+gN{L2#~lSGG|aif0Lz-gALi$o2a
zvm3Jy0RSe$1>#ByARF3NtE*bgBMeHY?SJwYV4~1BUR~9A=IAJVg|@%xvzRO&GkZw1
zr%fJ`#PiJ^DfwXP6e{YeQ-w{A{L2p<rX95h^>&R=N?S!bb_NX5g94k}floynpe=~c
zB!>tdOR3|uX+jm6P{(m8j~(2mvUu&)XHDF58h5IXdp`egBaGB2veO<PE`e_4O9fXQ
z9pXQJtguOoQ^F|_{3<;D<U|ki$H!LbC at 7dJ?ej40;^Wc|3Z79F9MaxH!BuIWhiN~t
z;K6ze=p(}bK1Q|H?Qimae%$2!{PfBD`FSVrXZ7SQ<sUJ5FZVWiFP|`ZFP}1bFQ0Mp
zUOwmKy?n;Wd-+{W-n;2M*~(0WcA1zY!oH><mskq00IO&ba}W7J3?|3Km~`+4(e%bR
zJ!)T~Hu@|+m8+0suoS at y<6>>5lO;KNP^gG3FAMjD#1QZ!{_QA+E<#iLF}P89T%!Ct
zWFaaJB?nT7{sWix>JF|b9yUj5O%L>?{O0xaX0m>L!ETkJ{!s;M#)V2WJ|c=qH;ejY
zgt4HZ3AXaZYzYqr_=#6*dir2)=&ypLH-&0mNdFZ;(y+SIE8Ttz90^x=&b<OyIEE*1
zxbQzrrVmF%@8=vD at 75~-<yx&buK*LwhgXN>rA*u%4=){)`^6T)>#iGraR<(Ugei>6
z<^%qB!$@1fd7c0qQ2JSdXvchMg>+F=h-0|al4?_LycH`%;cX&NzNc0VtR!611=alj
z+k5l&G?F9__;2P at WNWwGAR!6RVObh^7Xh+(TYv_T?Vj0w>OoMFYRokhSkg at Qe)czx
zJnP`_(Yx>SZtspoRpp(Lk&%%RzZkFV<|6cG>|&AFVak};X}7}yotpgd0%meks&Di@
z0Y8VcTM7}X at 9WULO8d2h@0PO$<-Z}+Cis^{kICKNcmG|P+ObNzeOUbXF_+mn7oTT`
z#ph at 5Az189l9F~W3Z>#3N;<#8pRr`!+BF#p!=8tUhW+6uNVDUlQPjX`*u-KQq$UFj
z&DjYNMrnep*Gb*@P<~(I5=T$H&;EYod->gstnXpEzcD4~M)uR@#iUq=8cgahFtJE0
zNuwfwFj_i2ES{E%%Z)2ue^bC$k?lT`2}CXpKH>jRU{|8Rt_k-y81;6gT08N3qJbcP
z3j5H##4r5`BGZs{Nz!NS-I1Ib7W$gNgt0V)n&wRh{d9}QSTB6&{^LZVL?q)x5DIb}
zLqek<Mn9<Z+N-`=ySRPF`&LwnGZ3Zt3;Omq7k`#fRr!Wh5{21aLy7*XQIN0<zQ!6z
zoVG}9s<*1%PZCQN)(h$dtsT+^x3y}JAf*PqZnua<SO}=Y7xVyt!k`V7AYhdv8v`>9
zLMXHYeyB1q1G_d@>6P8gWaN)H2ijiSS*C{B;HTZ56R56Qt6Z1cHLucY++5eX^;R>h
zkw+!1`Z)=cs!m>N;yHvfoYZrfjD44 at T7hRV{F+P1%C>&+HIHzzIrknqi?8w`p&W at 2
zxA(37bMc8~a7pwlU`o+61+#4dRW)uqUBsf0XjKx+3we$~<waHoLyybSxT>$jk<}Kx
zwQ;zZ`3xgQ!7szP0hxv-zz78c3H^HyM_&2m&!UhMzx^iE^V{<XW^<0A27BY6pWRZk
zaT;lp>KMhM4aQs-m$;QP0Ef<sI>(x^@fifI;@4S8!8t{bDngebNkh<?OoTX;Y~oeg
zc`e=I|7y+Lne8+T^FxXO_M5O63Um~&k3VHe>Yj}MYfQ~ojs}_E(I>@pVrNGivk_Rn
zHTe>6c=9yPzEbRgE~#T{o_`pdI%UG9OJXN0z3x+c-LQMz=ycoKd>Efw)yrzV1Fy1*
zH*%T3?oIn4U6vfHc<P$G+dlC1e=K0{RRA$I+f*cOlW8i3u>`@q*M#=Nd4&C?)0r%E
z4I(2Y9Vd>>MG~_`GsCGnLGBFi?w&2D-E~P2#-3 at gD&1Wb5i<EJ#JVW`tJH}LU?u(D
z-zN~TJ;683Z$wX!7DHoQPd-aYO^%?P=1t+JdD3H>^R}LXZ2VhJyix?}&X@){pFewH
z at K4{uO_i0UkdN+_O+U at s>uVQYoQ-72ge5{LNGh8Zk5R&VeGJWuCJr!wl0Xw?%$_h^
z6ztWobpG~Z at GDucVDr%4-+;T at lge~ozemg^id{a2wY-at+;~pU<Lj}ETr7q0C)_09
z^|YrB at IYbJ3e%$;UYs3w-!`<}X-CE=2eW3#{i5FOc)(7?e}M3PDvEk-cE}+w3DliR
z*?mh0 at CZ-~UvM_K<5-tL%7t<Wz{+RXCXMV5UBZ<=C+NWl?7J*}jz(l?uK<FZ$1xJJ
zNC;|#=g)sD{AwN$YagGhjk4Em$qkXHL=`w&QQ*ujaOM<v*={wgBBjx`JZa%%7z~$W
zu1~<r)r!}>0ajyrNbO5a+_n?XRwV8s6LSYc?5pLsq8^iVmY7u%Z73(P2VyRUwAT~&
zA4XJ(Q@?mCijx1DjuTq{s_898rni_lz1IA$E_G&?I&(^m&#^tpO)NTLrk6}e)17N<
z95*<9BAV`uuaTwOjLv&8I`7Nsi_Uy3GYU~?b(%7Ph2$A1tkdYiTCFRnW*`yni*Bph
zI<@%cfZ$hw8i6DibG+~~gok>AN4)!?VDP9);4*{=M+j~!LzE!!EW+d=4_1(WPaq9F
zN)D`0<bJC9!yY2?&YygLtct2wRjcUp;ZF(%5V)_Qm_3z8;o<h6Qs9n0y8b_*$TUXJ
z|Ndi7=BCk<$VT_bE&cIi@$jgMk*N%31cMW at lG+lXRh$!4n6OthU5(CG at T!|G%SC!V
zK6YzO5>xd&;+vcWKb|04)oZqJRclt;A9EZ9L>|Iq|I~3b3V}f``5^arMz at lEm2!w(
zcgKdkI3jBq6XSvrtH0Ml^olVgbw?$_vJ&A8yyKpZa>H7P*+00E9)s=TXzN1g#tTy9
zS!sY`n}=|_JFx&TAw>y0`^LgvdZZZo_gpw)!#dMt2tnEgN5mL+`qq#wO at Sm;_R{1^
zvQFkuYUd(Ftm?E;ic0xdZ?tnVCQxr6$6H0z!Odwgj%`ndv%1{e2vy0l&GOP_&n|n9
zl@{OhT=C1{_tYgsBaZ~zL1^;i2tJPF<!lmMnIke<4?84>S^@<pIZqO<#lMJ~5L&rr
z{hFIB*FDs$Y0OCj9XZ at c3I*z*x16zV#98^c at 32-ng>s!yksD{3Hc!>h6qabVZ+9qn
zis^%iaj5X{F^f#I5_tY6WdKVQA$Et1%JeF?Q#69xH#=h4$JlRv&e~KY4k99P at J&SG
zAR-b6$=u<8p|Bf#jj$Ue3A<7ZsJH*(U6q^F>ss~u3j}oxD#~F2;zB?~1^{BT;;>*x
zF$930O^Lj-Jw+FRXjGd>M2NeYwS&)mY16R{zogy<s`DDR-P*^P`VG<mdFfiw=Smfj
zoswHXz16ODTDR>=4I%y2Vy5kS#$No!g{=9p-m+9hQZ??4{1HW~0nrb#?7k(9OJ2}#
z1fkv)<~8med7*dyt(;rK#ck&oqd27dhjS4CvxC*KUg4(ssswquRqE7DTg!B7#-Ihm
zWX?QN$q21P)gz3rT)bQIgVBW5J6^5b)>=u~Dk)L at Tx&P+v#?~M at kC*IGklPgiGkxy
zNT$$NJ*tJ at sDHpwO#jx?$$n^ex-3$u`)sTPy)o}2%SG+e3O%gS8}=7?S<JCoWPlb@
zmG%~c-5Gu{h~N?x4VQ!&aSs#eaRr`{En&DzH|!_%Qs$#SD8tZBG{Y-z49F>4X3t2y
zdD*h3<O13xs7=^8*ouA}4p{bG))cHSXB0JvzG+8vG%5=y at L@7RMLd}h$t^t^w(3xO
zIxf?h!+sa!tU0ROw65(-4BGHc at D8JREUzr+LIcMJ9#3+)B}DM0k`mA+3|v+nR0uc`
z+56;P-K21}>L63#8x`pKbIpEVH1DhS`;vKoVZT2x?_V1RruY{e%d*DG1EfwIpnUuc
zN6p2B4HJ&5JZIgxO&4=>;qcuTsbrHItx<V(mvDENaJqK3GZ;bt+1k;78^bAMoh>bW
z&)V#+C-Jf;Vc5TB$4i>8ubD1fxijBSqpm{kEPdQ#L(7IqY69e=jL=5{21em?Bn}G5
z$1{cB^elSQtUHf64&6sZVoD-u4*Pd*ZPWw=v^RMgL#lJpy at Ktm(W>5F*YLydc at y9^
zO%5{g&6zfoZLizMNZ32m+gxObr0s=6nD}5<5iNT$URk>9sP5j(W1{$X>zXz>fjXfv
zQLy0>kA^)o_*H(RZrFX|oIKp#HHiDoPA$9j?&f+cr(c(EyH~AtcFRElvc6Yqol3iY
zLq;aHVJ{iIMhxBTVz2AvPIgO;<f#$d&c4{j5bYaRni*1}O)L#5!?!Xv<icY1hAW~l
z9XJ8zZ$p2!8%}$Uv9Ub9s at rt5CQb`0AIEq)SZ-j5zB2<A|65M)-HT`kAVXfvCgYH;
z`2NoraTCzN6?Tf at uy>dE0dF>7+ekJU>^<OtCfTyjGSYLfNI@*W?0A=*1Y1e}^L^;S
z|C^A at ZWyMBu^(B)f6oJR8}+I%86PP2gR$9*D9l3?{X9}iqdI&x0AWB$6=apZjsNEH
z#s$s|cZ+)#79mF;C<FH2;pF}vp0?o+h?R-TbQS=m(%k-(qbhdag1G+~$isxnRYJ>X
z<jG$^>m%y~j<YAWw-I$g-K{UT-B89B at Za=-n$8tDEuGwl?4v*Q$0`E|6?qZl5iQy}
zc2f!ZP^;w!DGW+={wKUboAk3vx=v{zoDkk!-gtP}sa>0+GktPuh#h=KBcZL1cHhzf
z;f~Aw!@<rvYK$CA-wu7-xhcP^d7b)SYrDnVzJ351DxSl9HvLysyge6<@<);ryX|tb
zb6IP5WSc)BH_NK1?N%QyFY52CF7O1J(K3Z^%VUYYXyHkZ4VM})S=6ff?J>;U4;SI1
z*M~Lldr*CrZwx at fV%6oV(Fn&CwSxYLz5yAW3lwP4afGlRLZ#Ep1BvDn1~9KEE{|##
zIKIe+$^#4=ZKc#F`v$eLWn*I3_*r$|?ky87_0&*>qU7k^5<BUr>m|bwW>2T$$3WjO
zaZhA%al0KnSu6J&*$P4!!Z<hj8p$6&%-K;=o)xSWsk9R1IXmJ^CjnMSF+GFXd;vQd
zY)n186h$ix;CuLs3fL|F%2C=V5-62I+Kg~I8B@$NnlFNC at pTwFg#JMIalwc%bW6eU
zl{o4Wm-FNcI-5|IPr(H0++&v_E>m7iV|=zJE*@>B2)*$$hMmh$NJ!jFjS2<Wjl&U%
zV6Zoc at MJAYK6y&M1Uc;W3T0?BFPh&!D+VSn`BWxrgrmv~#Skr(2Cs_&FAOY1kryH$
zNxi(Kao1N<Gx_8Iomg4nU?y9fiRh@$qk89aixa02tEN@~<Ox*zEJXIlAV-86EWHzm
z5U!ky!kM}!3m11GswT$v?GB$UdpOMx!I)wX0(<I7#>B>ta*^@hU3)jNCPUAao=Uv*
z;FqVuX1KI=6D)?#-EC~&*ghJg$FXZL8a2Dt+p<>oXgf&FNMbgyPA0THctjyV@$B7Q
zrBcQDXX;Vbu9^&F+Fx_am at vGKvo)9Tne!`aG@?oq$-#n2e?C-ONHC^oO7us2zS?q*
zBM<aP1M3al1oUPP)>VNc+BE7-IQ&u3yKiCGPzB at Kil^G7Cu)CfYaTX-(I*%@767Zk
zh?aD<tZl4aTV~9!?5{a!Bnjkr_lps<r3iZ}I&AzSV-QV-J&+k+^z&m6PYXy46gV*p
zqoR$~h|ixAl9Sc`daKgCt~9D=aSPqn)E`G2RpPfda^@zGcFl=fDR+L4$&nk?Pqz5_
z6B#Y_ahn>xAZwV=tmOp;pN35YEs=+l-hkqm1RP_Pi{V`o<Baykq}L{BL9<)LMP+0p
z5 at gGC;4H;bhY^d16U&r*#qjqr at n+-y2N(#s+BvKn>15Vp!j?_HpG-rgnqzfYTwk^~
z9EQIC3BQad9zRHhU2lMI?IRI=V84F&LWV?Hgf>e$DM35tYoC{Lv08{<S at qL1eZlo$
zeZWWAVB)am3(cHX2kIMC7&?kq&$Ew5R*R*uu43s;s;64yY7x_p$oeuhVuGafe_sC)
zmtmINIm-V}tF0CLudHcYc}WKePsOb?<C~yt4g%iaLB#oSK#DcV4oN1^RYlGObfwBC
zlGNVt34esX4Kost`6e(bOu5X%mZ@|Bee8APXGmiA9dC*{Uj4Fig^n)pt9{#%zdpb(
z9-RFj2V40-?VQ>TB7R?nx-44<g*-=JU#2sNHmRdGp^>N#SP at A?54 at 5{HXcZM1ENPo
z1lDa?EJ at Uq(Ws%*$WW`JquOG786;_p?GgAcTI0y9q-c*f&<qEq{yr>`&<~ejaKsa>
z&<w{jd<85)T4AUeK1OVUQYlHz%t)<81Sh~h3Rzmv{>lNz(Gc#AVtm(26*vTj7$i1?
z!`-diDxqpZAXMa!*%#v>I!cn3GkgIu8j(!a2cE39b=+x(!6;zF9T3M1$Olx!zypM0
z&@Ojtw1y|6=^R$Bo=Qx&-~Aw+Ug;h_f`Xw6;&o&JUleH&Z1f8iZ!)D|0<o~0cUwF<
zDnMW7vw$6px5^8AwGV&L55Lp6SXd(I79_PA)@i9C&>2%c;e>n{RpJ!j(n`FtNKCgr
zZJIpahCHL?Ip`V5F!cuof|f1hi;NkQ=1U&^(4Q{owE?q&NoAtq;Om6~UE5y$a}V~!
zXK at I%{(KkA!~M|jGu#u3Xe8&8MMV(mvjpv at yUE!U?{^PNx|DOp=Hqm3*yXf0>y5HH
z6P&Y1%|lnRlJVV?+YRD=cCszhxoFy at HNjxc3I5~rC-xuLA6;j0{7lZ`jG0NX0*;Op
zj1#ePOk&-R)9|X>aeQcWlrJu>FB!{KMeLOz?_^$s<037Ig3qu$u&wBBrVo##5U`C`
zWV^NTik?*vhIYjPx!talPY;pGCsaQAL*_RT>l;Y%iIX6Fv^w5X^0%UNbfn;~kBL}!
zjt}z1l0-STi+=kS%{K{-8aheZsp-NCLJvoEHo`3`n<Kkq at _#e%9yJw|vBcxUc|URe
zR6C*-$Am$})lNaoWk*^)W_+;vfkhw8tU7o^kH0JJS-gD+DrD6yEq_xRyR&Y)%)I=d
z?a8c0fea(GL9(j;b($EwaSgB4yeuK{5AT4;W!=UusV^T- at ChF_yMLyz6#MhZqW>87
zXTCpPCTygoUB%ba at _h|&UtT8i_cwSqU3z_bl!B^Spg;-ur&yrXB0Jt~-BzwZx~tWi
z9-C`*JLPJn;_ka75Ohub1~VtJ>uOLej78bLcJRIgivlRTbb2r17eRiCKw@~!jQVoX
z6NkG`0V<KKs-U4`hU?&4^FQsHXkO4#g$+1leIv<3+}_Tl0>@)02rrqH;KA+6;T>e=
ztMUu#Nc|qSpv4R|640mS-e&My at rhl6#g(3TW0L#^C|#=xHAH!GdiW+eHV%cxk-Oc~
z=*{cr=iPa@`yx)y)ngwOP;nG2hia>x*C&U^jGZ+I at i*kyO;2x8xdhxoSe|*<8}$1z
zbgtB#BAzq7jc8{13*&M<9vl}6kjJ9|T$-!WYQK}{VK5F40pwbm{@rc!uM!*VVKM$E
z4%`N`I10l45`JiZUO{hm(gX at Cu1R6>Vq`?M<I~c?X(0sw at rbZ6k2LbS#sMT#)DMjW
z##Zhgl=f*CgYW84wgp?W&Dh?z4@!8F&>Sv;1{nK}oT7Am5PR3Yc3xrhSDQ7Go}IPi
z()lt}SS3=CqE3wppbQ(`f9wI59EMZ`<m~&iIXb9v2dA_CgfR@^P|0D;J_G|eBQ{VH
zW<1s)WMw{-x)IgP2m2E3X&LdvQ>~(*c#f|CT|lD0A*Hm^oTJg3l*9WmB5LBF;%jwy
zzs4#q>a7l5u*xk=`76!*KB0Z|&{*|TYfM(&jR1C- at i<tFaC$(f?LSgMdhZ+c#&GJV
z0-k~?pZo7A_Bh2!$BkuIK|HEce4|_C(@nM9Eni-jJ6DJ{VW`{4iHM(nIqZdxK<tM{
z)r;rnXN7nv$to8)*hAR_X}J{T(n7Wb`cdR+<5>Du)mdG4E{<kN*9^Fy>Jj0sSJ2s$
zx7VM3`N_ui)V=n~*B{EibYLr}N^PCS`qYTQPmhzK-53dT6YF$*Ky at d}!>8U0bZ;=A
zwkMYeuR&;8pbr;~A)GSjfziLHDg44EwnRKgO18lwTOtyC$tqid-<iD3ipTi_jO3L+
zjN^CWv|Qjxssz7i&!#m|f(m0BBBs@|M`<AyT~^)WEG4FIl#Xsr3Y at rfG(9QA#DF+q
z<P=n=UGx{uYNVY0im{C*-(Z%bS--+kc4 at H@o7vLo!QnES+2hwv1XSL&td*5+r2Kzq
zoL_DL`v=&+B9eI`a3>HCuHLk77T1iL$0AxLfu&>Qsc at C`Y{c%>;_C(x(d;8=N+_>;
zGKb_y-+LD0#pn(XhxbBLxC3x$3ToYW?OM4Cf_t-DZ{D_UJDI|B?IfN6?Q1gdty+qI
zySTl)thI~u`7rHsi9R34KX<z2E>w$OUq_l&YnMAUUG+&Z;o}7>ZVS&xg-B*)T#5A;
zF~LFV=MsKCay}!pB|=<MX83$uNc&73J1$0QziGGLwaX3feZ8z2a8g>90^4wMWW^2E
zQ^!CVjseY?1?~y5+AiaRs(F{bQI4jWjEe{|jdB_axqF!dRZQW*SY+v(4Btn2`R<)`
zpOlcF(IAlN%SH(O{Y-;ya(E;tDk^n^2>_<J?*-%g$u{qRobGRl#Qy7<bK^dqspJ|Y
z>^s;|xEHdx!vYa>>v+r9iQ8FVA2e5x+H~_G^h%At{VL9RUM=S(^j-o<a89?+Gv&WT
zqmADR`~s&EAB(_G4^VG?0{=TIo#b(XiXkG?;*}_j27D#iBcw!Zc}Yp-)Uy_LZ`2Dv
zc@&cqO2w{yXxF>7^2K#6uOLTuC*$D at r$@)BXrtMRKh|I<3rERoU3R?Y$L_`T&u$Nn
zlX`G0+aIP^hq4-9BW_%!`rfJk)w at KuXYL`HRKJPT9B~j^b8Zj6)!ZH*E}L8U`oDT^
z50iRu_&+wcAloHRE-Y;2t*+(gG8`j+E?<^&o6h}7bndZRr<u&wY%;>h=Pq%N;5AP=
zHXj~}xEhLuqhp at yW4uI^vuGyqG!vP_rIV;?UnJCR4`%u1rq-<HF_KLOwu9MAUhw#$
zlzBIseDcS#C918Z6Wv&9t!P}NRc_PIH>$l*I$XQ at C_R0fCd5e1At`^DLR5|0>u#fZ
zliQrDoO~0mQgVlF^<IIAzcoYASLWEWjTbqb^kpBuEx#%rtt|OlvZe^Vu*vZM1WDLi
zu;D)cGnDa#Q+Jfuhok?oy{2 at WxYrnSIyuj_=_}4Fd%=e|tKwg<PDTR^36EbSdP80)
zf>9-X7l%kuM$a<T%Ju}qI|&EuaG(R=?FsS0{|NzH5t5f-E#WW^+;6lP&V%U?)ds at J
z9g0c6zd&FB(gTD&MDh(rem;tGpJU%74lE>rj7ED at Uj3eZo#6k`i-_*=CFG{mIb?&J
z at ZoT6or1~k{3p4%7Bg-cs==Y0`A^WSr*Tpj^H3HP_T-b76W2Q#OT|TipB5pP)q}QR
z-6J0_ID&8lqmyvbN$|LIUSZW|i6Gt1B+MsTb^RDu?C!-alLr&eaavLF%#i-J1)>B>
zShAr%R&QtW?Tp`&U4%@I;94pR{&usOuQUBMjt8FLcq-0QMk8ZkG^2Ce^I0Z>O?)mJ
zZ;+#BGVx3&o|(immDn!3$i*-=VFUyB-0G=QN0E!OGtEq<nVl)kJ83*~?2Hq=i at q~t
z*v&**yT>jG$gdBThCuqLxA|o+!KT^Os(J{riX8vN2Df19=ubu?^cplCzoj%ERhiWC
zDUpzp6A5F(-+4k^t<stOohG870P-RWp_o at q%8Qcwo0)Dw|6r48A<ew9R`IU{Mykwl
zYyjIKOLZY;IZhKzERfMWrDAl&N{;AfBBRbl*+U*lZ;)EQ!Ca^jT`>zulkl~3putp4
z;VFZzmz3)HcV0%d8G7$YfeGf6FB#(OI5KlSX3IvDVPYG8Y4;&YBHsrfIm}#!8c`a8
zNHJrZ$F%P`tcP8s&XRP7sMd>7O5D5DzI{~wrICJ}l8W&B#{gZK&!uNHbz%1{e$fxO
zOT=BIVKbe-z}DiE461P9t^8ugDnPvDeh~(v>$cK-U%poEzga8CkDP<rN}!xSoU6Dv
zPAVKK7%-(z<z#ErL2Zm>&vE|5>}J_mOY<-p`5<9o8n=DpbLxzc@{QlO;p|vWA{DQ#
z(q;El>chD^?ECR9{rS)KJE=Klz8hr|M#UfJ)mdF7GS))j@)Gaja%3ob>?AKGCFcy3
z{KQFppm<O!32Pdr=ADY{kIy;ul;;1}F*!_U@)i#=zf0EdgJ1J{K}8*@$rKu9S<SXY
z9<c-dL_LvteBq@;W?jNc58dBMtW+cNCGFi3$83tCfn>QX4A5t*dA8HD(>{i~wN~nR
zlxF0u1ft4Xj^P%y?#8od$E6s%mw_e5Br>B(1A3;j#|a%xXpOVszK!QBt7BUfKD{z|
zR$I;5nago7(92z~|0!p+Q@!IftDMGq1B1_=xZlIUff5LDiZQ5X^Vpq>aYltiI7*bZ
zJR+ZXvg_#$<X310CV;PZ1hT+agU0LDN{V0#RM3Tj&>y2^mWo$^`Bv^^gv^n=kx6Gx
z?3(uTq+^5pz0FO{i-o5hLcilC_f0l9?Cz=faX1VRTLb?Rf8ajizdP|wP4?3XYLl|d
z{h**JY}g$9K=iRA*4pr7Xt4xFzmFOmm)k2wZ_sdZRM(o!K1UJN-K_DgFKvrE`LZo8
zQ35p=+c7CLyKHN5ca|l)inFP>2{CEzYz;!fmPR(2FW6s_aAlTnDogj2=$2wj<R|WL
za at nRet9~T{VMO-?vjXH{I#q6ua!(D=wTyYfXYm!xll(hk+><}Y*e52Q`{QrOLD{`z
zDGQxXmNQURE&efVREaiu!T<7T=Xn(6^vd=jC^iiS6(U<l>7a>c%Z{rOTTDd(h_Y;@
zmKsfQ0(3ZojW{{ABY~CUSkEWliH!rbt<S{2*^$5&=nb!iw(KWyYI$cCOPt8osR1&B
z>RB`yHcL^5h)H(@(<ILg8NM2El1q|OWJ8!xl9Y0ij5M9;<T7%cQfz}fIGxOTvlkUC
zh-2R=@=?PZX<71Mb1nyL%;saMaCFd~cWCzRS|BgOAc}HPd9pLTRR_D(ryCkQ at t=qT
z<sQq;YL2esgriHgnA0JuumjBWib{ru(b4nv!+BhOpb=97ho;GtBV;Cif^_V>+$5{F
z`ONwo{YK|UJ;bVY-*$V?eD#Shv-H4+-+wm~T*~Qyb)SP?WP%k7SvqwLVx}iCI)_nf
zxddIn26}+CbpRWRYkE>;bHDYRE|a(-Q>yr$S(tgb at 3~8L#Vo4{KFEm*9EE%2$e298
zt5;@pQf(8;KWIYNQ|icueedbpctx%=RquQffzUry-WBxa#A!q)rIB$$jm549B-%eA
zg;GKs-$SJm)MMplK9!QUKbuX+`IMA3kxfIg7km5VpiTDvT~LXzg$hha at f<s=`Mv81
zlUjVC0NfcPo^Z)pFxWYFvnhGaeXqvC-bIrHmL(Dkm98WeJDnr%{vM4{9oy=cotRj#
zkg~?o6O#q+_lE=+;y7i}b1Cj&gzzqoB5p4oHEUowzt9D>bQM&9%4oU4*UI%O31ljo
z)>wke=Jkn$<u&!>z%9p4RvHR!>G|kvl@)L%(Qs#5J?g^?HcG$r#wxgR1oz9bYkqs4
zZ1%qt>&sfX-N^)9_FlC8^+1|tYqWznD6 at tFOonAvgNM62yaIC1;^g3CiVnvL^B$Lo
zWt0_8<HT5rR2PXUh;<UK2aEr&_&whS!ji&)xzE~(^J44Aa1WLhVPNqaNn}oFXBnGK
z(UsWNL}jNkH%8})--#70`A%Sa!ok|JKcmx#)JE(1x4)CIm53Ny#o8C&2k5mE$Qo7B
z=SiB}Sa0IV==GTjM6^PUkW5XHgeef;Sh{n}vhY|_0IMZkVa^1qidLI5y&%?$_sdKh
zXZp1{rn*xa6O80{BPFR}l!GK$3O3U6crdH}R~_LJGn at Ck>7{MbKbplY{)S{8{E8UA
zY^ldczYfuxczH%IyPV6#zg8O6>w1#_h`JrwAB(raPmD)nGsRG^bj$87FJ9 at KQZUjI
z7S6v@?4Qr|9VX+fiY#vlN{Z>z4*OTH)L^{TjLn9VJTlHA$++?5cDwuwp$lh|GD(3a
za|dhX)0tE8;d&Jxeo4iL%PKxuui}$0srV$J;@|b25u2rmK0?76E_H>*Q-^1kL^d9q
zS1)#zGJ&ovO0ruNgMy5d6seQrzzzn|ecDo>+bU^xbRsz at Fk(?m5^}I%!l~a6?gMyW
zPcB-Fd&Vsk3Z+cee^q}RqHa<BSFb{m11Aan*PMwP+Oy<;_#isiB<q>klB|ne-3!Iy
zh00TGV02R<vc=NL&p9EU;rvxBq8~n-#QHg1*HN+L)LlA0be`Y1HIz&ZB~?S|=vdZJ
zEXW#)ho**Np>(uC4Tq+NLsbJbQq`dPP_+6`Djc3{P{WC-;Y5#8gNl28E*4ZDN>(2Z
z3vZ4$sG)eQt0*3G71@%hLG_{3Pp<*}fb9Q at 1-FU=GZP1LCbEaR3Ox}ARwqu1Z%Ug~
zaeSzgAIqu8o|r0BFAn<YRgjIj{akda0NT{a;WyQhg%QgMNlpbh*#(Q7jt@=_S5}dZ
z>1#v=-e&DniiLD;T~(xAX~fmLwj8?75k7ikwDVi1d$clozQ5P-apOtMHyE`EGi`1n
z_ftzbfRkixtH=XRv8V$4Ur{J^kvh}6$2cu$Y#BC#*usDHkhkQKh2(KX<i(q`O$|AM
ztglG_+o-;hst-9$o*2p+74~(78+Y(fRfvoyPyA(dg(dD`QI6?G6`tr3ZRCj+tWjNG
zSGQ^ZkUhx()zzVcAB=2zeFv(0n@`|@p1?z>4|&8o_4RdqoAwVF7gu+pt0Sip;0 at 9G
zFkk>jvl+e+wi<yQ;aU&Iu&NmUfnk*yhGnaPH$Dvxof229Zz)wFh9lVDx5%+z(SL!u
zL!Z~1FyNDtK8~SF!~)$uaaq<VI-v?yD;RFapT_7vA-M at ESLvwXvXF?hxHK9?GS7_$
zWQ at 5Ae03P9Sc$23sOaHt(1MgdzL5U-u;s8dP2#3eunema10opvh^84n`GcM}9|3>Q
zC1{0Z<{~4g#^lRb8;ZG9=XDnz#;cUu)o7Rcz1bjM=E2f_9YpR3Q(}e2K+rAKL?j-j
z!aGkuJWo`K*}&)OIHJzh7*OY5E0uUi{KM$6B2vtmcG|O&%d<mLQhjwNgS0qFSR)`=
zOHu-7;bdZX2Qp8ba at D9OV6wYQDiN05os%WV>}RW>+0T-(+1G;1*)V7)!m*4I at Mbx@
zo1J70Kq5Q&S3*w3i(;HW1POd|dX$3d23zcFvBQ5Hq(G$JX1Q6FaF4Z0#k>0OCn52~
zu3!lhDi6GmLIkct{wp057CAu$M$iM-&1%1US1POnE at -N>PzDiM{?Y0R8T(Vb#(NXI
z9p4k08C{G4$D*uqM at ARFJ;n|%y&>>$_;W0WG65NtV3>t~9`_$7Xeze*C+i_$_-{Uz
z51yaDh*BAs6Mv>+X~oj5OS5*KZ$Y^6@(?!b5X%GkHHCVQi-_h+|KfmSphEvMAxzQG
zRT@>V-K at 55yJE1I;r$yKB$Ml81f?7+_WXW-*n2 at sW^T=7a)&nq-mo`&@F|MTZe|Y>
zv2XIZILylz(+LH+IWFV{G)5eQTz7o%JAH*R2uw at Hz)`s~lzT_zrcl$d>^nL;MWPm&
z%)d}TJ^3ARqw{}4mtDe-J;YI<f4}D_ged*2F$x8Wt_Tg?d<2}V3B5<DvJmP0Vc{5q
zO5mRp>i?IzKx2VIZm1%`lX_b~OFe{?$3j?&l);~%yygUo*-~I-_*=2aEq1LI``a`(
zH`ojfT8cBIElg=js86p8h~~a?__`z~mGA8)I5{~S3YsZGX?hE<_6X?yoaY-kb(4Gx
zI2ZCa%!injGyfr!(Cv>CbQZ<;=OUQkb at CJg0@?B0AFP1x50QxO5)j at hg-s(<f#J;p
zKUMXK`(7|qSB1Ngi+g;2n9L_=7J$w7WG0Oj at AM!m1wR;9kXLnJft+A0_4j4(0(~wz
zzjUBC^h!Om2xQ9IIk$UDGq-ZMuRcIY&1xG&__KuMeQh4Eu#!1}dYzaD!)5m8ksSO|
zhDkU&K*B#dDye7{I4+DRpBjh=n~Xt3ckcq2;vYlY-2O{KWn`@;sQ7fRxRV#Roe%YD
z_sT;6`u~7)o;VdJl*z1#gfaRRQsj6D_mL~XVj74khOrYN;t5ii1EOrqi?6&nkOT^;
z6m3cvl4yQJqM&}iImCVT=*@}TXH8`L(4TvQ*=Jmp*(t0l9oSX4#7avjm{1&1>n)I0
zgxF3oW`dJ0m{6n&EECgG!*yaI1!hc2wb}>KuiL?~ReO)??Vy}?^PQaYecRpKE_00?
zy+i?m%uZG#o1hBQy+43ou<|UZ`fLp`$ah7D9kHhVESNsx-WSp;o<pmMubOc1wkU~&
z5<dE5{q#9NI7o3p$vH+}G~)bg;T%6w6VX8f+KhI<a}{KrTJcpln+9W(%GwxbGYMmp
zN?I3Zb2-N5CImkA=li|cXvtYBl41ohM^eX0xOluK2`83RID*1N@!<5}<g}O^S>osj
zaeLuk8CPOikOvi4a)IvLi(ok44aTB|BMr3+I#nnD^ZLh|!{=utnLZ(x+qlmdl;`Kp
z$?=;buhzY)wH?rF{$NVgaPH25t6A%EUiiT<*A0z!%_Z2t&k~jT2?&UTosOnxCEgQ^
zu0ui%P%mfPy`vRJu+@|sFEJS!JJu?Rup$*fa|8Xp_a#KN1ROe=WKFV42Zi34t|EZY
z7GWKv074fC5W0{A2#pj#!VJx!jN$-~K8|k;;<<M7=HTN;OiL;K=^Hp$V%k_rq&h2Q
z at H{=#DR*KmuxXIee+ub^YQ+~!q1B82lEJi-tvQu;mao|9(u=b(zDp at _@Ja<zy3ijM
z+(<*5oj$%`#PK4ULl<&65>r?R9!$nQhYQ-x=#WH15VatS$HrV3TDOjq at w!y>>Q&ZM
z>a?p8BO*a^lE0o54k?Y6$a(`0lIi5q$1_jqyEk>l=g5m!@KG5$^gnTgy4hk%-g1qg
zKLd_&bM*@gf$jkC2$V3oQ88f{XbewSadmR6$8Zor734KQ*^5UMD at pLfA<1KGL7U$C
zi%O&3?6$pj?Ok4QdAW^;9XpJy(Cy<lpNr&b62_rmjl;=W!(dIKGYF*SIxOPA^PkAT
z|9AHPcZ0qDYOs1}kC-z_a*n=ul5m1f4i9jG_z#QGaYYXvlt}A9*Z!f{Mn*<_j9+A9
z3CWfjmLeYS$+HwgEDur8oaJHX{s%twC&RpeQ{GV7A}1u`&q5vi{CRNi%@$)cWk=&E
z#bw|pgC>M~vuAG#48(_K>J4tx>oXhxZ-0$)#cTa6na#V&1W^!rBOea|eLuh}QmI)v
zIWCcAh5o8jvsKsp8II+%Spefe?g-1PtaNI8V^-lj=o=kMM}|<XMyK#czc-uT`Mvo%
z#drQvgYq$Kq{=0IBq*feZYF~RE|wH<U1?oQC=aI<Pr-OFd0M9lTmp9SngS=nsf*4@
zs(1d17Sy-}yDM9OU6BCf2{py?_wML6+$z8~1r(1X*>~2 at o|s=m8eo0hK~JL83B=xu
zo%G>p$OJTzJJg8Se0}rEWG$pAQW}a^rb76_oc`nlH7q+PCn`3X@(LX=(40Xs4F854
zYW9q#26Z@=KL5HWy{o8VyqhDq6S=mh(6T-nD$9cK$-7(J$4VhKIQ=ADq1UOF%%{;P
z;Pw4IldV5~m_HI+7IFl^0TNIPep%@#5F%BB{IM$znUhRLaQHslB_s>>yIzbW;fJ5@
z*oxXCn*a}<voiY*NG at keronVS7}Y3BGVlrpAoORSef*rK<T&7OUcb&4kHilCEy-Y>
z$$a?Ce4**aYhGM6+rue-a-8Tt_l9SZXR|?s$_Y<!Y{wGidrmUP5~{VzHM-g1^j+Lu
zqA39fcSXv?1y7x(4Ff}VyA~04lX6=7_5<%9agzr at _lH1!cw+RVXP~3DMJhT|se;)*
z<afTug&kTZ*ipW0_5GH>!ZiE{o;~aBzwmssN>M8fDQK%43aK@$x7xK%>$Y8i0jM>U
zD;;$LQc4>D)ZKV6FW7(VTGUsdT6?d21!BE}QjCJx?v~RkcqJQDkb_SEM37J7DH at Ub
z5qdaeXLBKa&i=9RLoP#=pBHAA*ICJVfl{#bzS at KN?0NKtw##DS_*lo6jYuQdYV$;k
zu2HS)p@)^Hq$Tcv4n>7Mfbn~p%syE`)QQ{k6zRb5&M5E7{>gcmkv~Lo(jA#}E|(rn
znL8q!P$W$!Zr-DwM<4nVRN#!~S at x}T>7Do&vL$3<VGbl77$M?Td0>`M1dfF_&*|4F
z)P=k)I;Kk2<J<&?l>skiBaHFUXQMDYl72!{ZzI|iiv`l2!rwRYDlC(54e(=lDw?F;
z>kUC(83m}6Ul1U3_2%T@<nRRNi)^ekRnTB)i8?ANmn+3W at fro?^cu^<c`)h;PMTQ3
zPI?8FC?0i6Gc`!bT&CT$59UCS-UnR+Cf&4x?(37kl#0&>R0U7h;cK3*BXfjhqdZK{
zbMYFIpVC&ebjn_z3b`#s3piP?fRls*^t5t*X9iEP`|zoVhC<J!QeHln==q2M&-abd
zq&taRo;zR53oN2DK(u{&$|B|A+ZDwf7YniCtO?=*yZ$T~1ii74AKWqvHM`8$rGwY8
z60gh6lY>g}<VY9UX>=+=zm61GD7<!?St*psy!7kzXOHV?uO2topFMtC{n?{diL(9-
zsQRFos6RU-x%BWvUK2%$Q|~t_E|Npd7+9%LD3y>%@uoCJidu(YXE)TV@&ip4_*y^C
z7-F?+TGhFM1UHM3tVYaHt}auKx(U~uUN_TMgvCoKP*Y41r?_x*dQ at 5#5U*G$ys;zV
z>5Bu)t`EhCpV4e%yl*A~>NGA-u{*ls_(k6Tg~1cwE)L!(NDg<$;uYGuBz;w<iL~!<
zR)T|G;wKQYc1OMG6wY<Y-~D0lC9Tr=WHL;S+NXqZt5MMqe8D7=RmJ7o2k|oD(}KNn
zlH>J};mK2P9LZ<C4VQd-oQ`{`AKCLJ^)tqpPW`AlVtw6mmi6P73^Awz3AW#R&2pob
zaguGh3EtP*oqDU8*#eGI-1?S~5|WU$$v at h88FcgE1kV1lT{fU-<b<6U&LJ8GLYj?B
z3ElH%y(cPQn2j9ob|`hs^MIN`W=gVl2aIoJ_4!B_;8?%#Wt+G$j1H2e4^l2oYt-_=
z7UgOc4!|AJC^yURYK>a6D^>-ulQS#t0-J45mQm|uipQ2mYgtAOHeRX}&jW;}xjHiX
z8nFx#2TE$46VFp+(9u#I`og5B0dkPhBxr=Cs{?B4fGf{^|1)GDM-H*AAjAm<gkWeQ
z*!MIQ!^u-#Ji-QZ=DHOSSmr#jgBX)M*134cSc;CiC&;#tLjpr1vZKxn4kG^Z-11TQ
zf!ZwC{YGjx7m#Mk)--6`2ipbrbzecv(D^06gG<6}>cXI;xdQ(%{gP24GcY6yV+qc@
zqktNWz)N_qcSv^~k#7g|4eiU~-wuD}dy#}sN79D at hd-glLVC{PuL=RlS&u{uvg02b
z<??klz!UxCiR)RK_KMQdFRunwVxw{nKu=}p_gE at 0pg`$_;M)YibDuCJwqwc~T`8>H
zk%DTw?UG(26OR3A5RxeeNK3eREG7%qvKeA0tHAV?33~!BPRx*c-ITD}`t#XPf>y#W
zaqcj4w<Fc|$BN|-MJ$n#O<sxm<s~A-HR_#8ju(bBPO*DLhMv4KsIuSA1(ynix66*w
z!YTZ}-O{1(LBe=NOMi7P{@X1+t>NYCYYg~ScUz8XL3jL9+un$`9hhF9aA at Bqu6qgt
zJeg_E-A`uRk02kTjC|)yog{8x#>e8z+EdUT#<HjJHiYQ|*|6z7z8?_Ds2W*m=hUwj
z!Lq5=^MUQOW;=a0HgBR6D29Q%(w8t6oTsG{4G*JSLy-sRX=#)zT477L+SEn5-GH}A
zi+C}GLx}I;HPiBqb>)tUfs1&za4K~-3-^<=SGb?-t-}2xcM7#pxE~9t+4MHCjA34z
z9b#FstGwP4>?!HYab2-G{K-s;nvh`ZPDh>?El&XDg4s(zK8vu~UO!dx!3iZWl1SW_
zaMJ%o(#5t>^($oi<O?Dl(kBQ#ik-%yKQ%im3)y`e_Q(Y=65j+_O|#W4zc1G%DDlW2
z^`|e{Xy+rv$mL2pb_GzGK%MeNzydfzoi4~{bKHaN1%UX&p{v`?3(7>J2>;8w6OvmM
zm0>;${Lgx>bVUf|B+vLJtYXq)lP=2-JdYbLIC6m at Qa=9mY`vA3zN40}?M1XC-IW{@
zwYp%%QKnaf7-55L%2gIgk<*_TtrHuj@@ibq(xFaukdVs4{#3jnk|xrMqeudaqSFYP
zi8z^3U-6&gb&p-O?p3$dx)z<=o10d<E7pcg#5+$3wxxH*kSRM{${CQNRKisUBdICz
z`lEr^hJRKFXLvq9SbBE%57{^v1Qd3fq at 557fmN)L4bD}^YgMmUz at ux|yXp<^fhWg5
zTrP$~x?pfWre|B0uY2PpZq(~%s(HP^XMZ*iLdFd(SKrs#-Fipmv7YTr*da)b#X0ZE
ziJA<O at Wl49^1kiWo84NwsbJW(bYWc<>too}O|$I1FH1?ED{`)38Kjh(y_iqNJ~jEa
z+iKR{dDVJ{F#IG?i?+Rnfyb%A!u9D*3f8ucL$(10T4;mV(T!?Ua;93okVMo(l5qrl
z^{zS{^cm{h)Oa2+c7ptEG7c8gq5mAsS*4uS+nej!M~a0CdF9hp`T8<hFiRS`59MZL
z<V^2D4$YdmFUx_m>EWig2z{%U at loG!&_1X^BLhX*V|a<}tjb7#Qj)}p+=T{B<^dlK
zgHQ^=1AWC7rPJRWLX|yY5CE*ut*;DIa>+2Xt4eYf(X#TcHY^X9>yq-;Zr)n0yV|U@
zrER-euPh><Gi$P9tFzXW0GlRJbS+VxE7nrVVxp{TEGG7=q~(O?tyBV($D0TRrm~!s
zy(%{^i?|toVb37@<$8Tvk6T>Z++u%UbX(Qdsi<RAuMyf_AiwM|lodPcL~v)K0$}G$
zx99NtZO_bk%#8eSuE#rvE<h>YmIo!Y=Lj-cGhme&`;POqtXQ+9{$TdhRq5 at m_J_z`
zyRr+4lz)iPvel1-M7)Y~sZmyR>-1WQ<u$t7Y>cTu%_$5@{KkAJg&QV*UX|U-pObr%
zL|2b at Y(2pxDLe5P5<UhKKePpt80XoG>ZsS-?!RDTHrY^3lT|x22nF`0={{aLkM75-
zoVA0*XEk-$<>sQbWv1?p%fo3-FYjvo^44hH<))=AZQPYJA?8#2Ogd%s(FJklJDZf;
zn4F6-%&(8A=`z{x>(Q9ANvyd`$ZbOJLjPKO>1<BQSBa!71#+NHC16M9O771#$9E at 2
zmJrFNHfEQpC*-VlRHHVSo2w1y=G(1*LvGbGTd^CHij*W2Wf~~h7+%1!U^W_WtDG+w
zb6xKjjQSt7B9;qJZJ%LBP?-?h5ta#0<EP#Wn%U34>~d+XWvMr>#~$uoX=D+XH8wr6
zeh~>TIb9~xf+5uQ8f2ki>XNo}H4=du3EbJ8gX<qGiznYeq5^D+r?Yj%Yf3!r;SI_*
z{rMJTWN73MpbZ8d=N;J>bTrk$xS>DxK`wsWb#)!9ZeIBWsZ7?p&*E}8dD`tWe1}^p
zIr%L at ->Fqyk6l)3UsZE^S<Umrn!8kUSJwPpi8TsP>Yo3;33bZ0>@8avi-S^RVW5w}
zcVwOxXDnLhfZh-ocSszSoE%(t-tWaPbyFOgzwUhZ*<ZHv(J at Gxx&{<@JZalYU}=Nd
zXH35?*~sK#n*!nJJHR2{Y2Yi6HK-AJZQ7?@VC>I1i7#$vl=h{0+vYElStd!!eYXfH
zI1gR8d3Y12?^yOQKG_(-cAdghj$G6LFVf}7G_=Odek*b6?5mN?dCHv$q11(GDZ^+=
zYieRe%J-BGMHg}roIA<1M57C{*86$VuBO|Uk}z}<sx=>L8 at _}Tgk!g!p(fpPZWi~e
z1FK+4VqW{Bs5Z*Na`epG=rQ=y$b^_udU?-QSQ}v;Z}z;LrOA&b8wJ(b9!{<3L(z{p
zz7LMYFt)j3+%Qn~HqzB(lRv~EZhs_CTHD-<{a**8-rs^>_lE51dM*=R++I?wm9tnv
z6<pJ4XHIaM&Zj#}14-i<(Yi1-BRaaFUmHegkNC$ud!~aqnCfh>Q{?6Dmajt-w4tM3
z>qFDEodZTb_XR;%PVSS(%@k*i*luynrt>aDov_>&i{ad=NL`YVCu2y^VMKhupa*ao
z%Q8N at HsW~dp*bf7E43Qv1%qcNxU;g#Nv}3gz)D<Bx|vD4dVP^!(b1f)xR$o2+Hy_F
ztJ-x<?bb6&qJxH#?rN*^bt=;GDPlG=-IxVTrYkwXk{fMh^{D0?YyK|d^UAgktL5Ss
z3X*wrm$ORzMw;*uMv`BPKhFO@%OAVR{Bf?h3x&iB5piB!l{=p`^GWz7IcCC_C46PR
zgeA_?S>ne0Zm#)VcP)N5Uz6X(IGv&-W_5nJ7PDi}lYtsN`3hk^zZV1SrZT{JIs;Uc
zW~~;HeF}y{v}C1~!SIpy!7RkUpNL13TX*eu*I4^qmp97uXKg9d+hAz}-}_&(vK0^2
z)U*K;-E1J4iP|G+8{wnl!j$|5A4K at +?xzr at 8Rr`&SvTz;3xDDNPjeil%H!`+K7$r3
zO)JtgLDYJ9!!q<KAq|R?1CmAFu)vtd3Glit8RsIW!nAz$2+S6dO$aj~Ry`+-z7`C2
zVqdvO)Vcm#TS6+%v7CAzpS(2`xyVHP86J`iL!xY}_=O}HLn`e~mpUimZdTBvqc6g&
z;$Py9 at u0G~GojhJ71!9Yy<XY6wrri025ueU=|X~DwLhL}spNLdHs`Oz#ca|W(C<yh
zpmyW%p>jpm(}j94Y~c<3!}ocWc17<LO6gJQjmf&T{k-3O7B?5yry?tza~E_Cc#^Y|
zOCGF;L}BfW(4R9QAs2gZsq~V3RM7KPGaDH3diyW1&xPTnAM}u$Q~c;&9D-!E&k8Pw
zRMiT_Vq^L1+cDN9!D^aq4|*00PlM|c+8Js<$snf~27cBJ#M>f%pl$_nS!?BfMqYW@
zUlZ1KYbpa|_{v2)Z9H8S=LGUCU)QPj<PjU}6~^S~r+?e&N|vBW4WtTgL(X0z4%ac3
z<4}gUb?ol7ypjb;2!S6KAqWnryTnjg59s}(#Dt|b=_v8i at k?)p339mtwMkHEI3-E)
z*APEptVCY}1LX<LA2Tu(AD2k`o~|!NKUo=0LjOzVypI`IGINr25{HA&a7m-VQjRki
ziUX`U8imMcK#6M&Mw?$#h!}b6Kz#?9q8~N#N(EtbCU(BUz&{DO&1uqKNO<W<VU at 8G
zSg;8R%^OIcP6 at Fy<kHD|2D!*1EHxbf?Gxf2-HUAkGyC2mrYlU|NMK0mFT)XVA7um|
z*o1p8Jln`Gt<#9L=+N~>j*z8dx6dz*Yy<zEMZajp8+_b-3s12WAbTNN90+PjVj5**
zR~A)5f>6dm>BbmP{1egZE7>7 at k#jtbVRLj2PKn)e1<h!4&!XwHu-Zl4T)hI~0sXq{
zs9)FkE1NVjuQ);Xg0E9jW#q0=``J7(@oWa$!q`VBh2HEXw}yD5RY<XOY1V$k=qBPv
zN4l4LkdsMM6CPx9D)=e+N5;<Rsk}tZ=wiHVPKo-d>&%>?#eWa(?*m2*i?gF|3Zk&D
zfKhyjI7aC55 at O^-xk)!!_I^jaLu4zxAzt*8FQGxHLtzaa)RziaPrdP1+&q54&0o~6
z`?@0qC7w5h2Rj)Xn7?FzuxlKl01ZK&#E;=_%!!QUsRVoOtzx0DB~J10R#GZ9-QGf@
zyDAy|P-3*2laKB#Wm4ns at 7HSm0G8uk0yf+4-<7<|5}Xt1=+5`Y8n$;&h}ttyPY>vT
zXz7lEncCb9wVeZhNUG}jgo;~Cr|>ZBy(nmiucAlP)~g)fU4fFYrN;Ft<a+G9#!ZpY
zM|l;<lj{#zb01<Z9yBk1rSDnP(SV(r&&9HAwsDbig3h+}R?z0H080GfJo!BzLSg};
z$Q^UqBP3|GBXjUi3K12hNQnp!ZNoSeLx1j{84F9~$LxM?ficTQyKS!NwzX at zZ7%pU
zm$0*=Oz7-FC};PYcYsSGVnoHDX;P7a-O_kVv<uBx#&u4)?MpH+Yoil9FOaV;5=05o
zfWetvLrEu;*q`;+YaticsMnVkhZ3hoTUI3+3yJ&WlfR4#La#*qX1`mx*}tvc$Qj*}
zv$2c{G_bGJ=*#O`^DG_r7dym(m2K4qHn(+M6_xV!^(jS#Lxh&`+zVgE{j9k<b=HfK
z>)b0 at mhLXwt%jp?L-`PklL8_JGxPe>g{#ktS3`=uH7cM8?5VKDJ0+>%*(sq64TtTA
zF^oD1)9Myb1~Rr(kIpm?W)tAN12w_+3Wu{ev_j%&a*XN_WFh~bh*X5x%%b1hc(Eq|
zDof|3#9l~mUCcIJ%sC4WLN0BLt*MkL&442JhSo6>I&yZz{p5hTT(;hLCEERSR;o`W
zr;@Jx=DZlkEH at bVa&+Bq9E)-1+-w2~Y^ovs=&Y<7pTaJ6h|m+WXGhNb(~dRvr|!jl
z!p>sd;PY}qor{t5?}E8O3bHT6v(}R(i7U$o60`Bh8o7=)cV;tbEo@&23#pocO7Vg!
zT!g6hS7xZ2-#eGp?xe*Pb1?Y^^6&hQlsD2((<-(+b%CzyQcu+Q^~_ZOUr*?oYBpIs
zJTeN(6t%Fy$PfQRTL`9HXsov)=1W$@+*%O{=TWor2;fo9rmW#RT&Aphmy&*!BAeTs
z%*~;fLU7SdmbDuALiWj5cUezkA=jE*Bkuic)_zPp`f63!Q}2`S9$)P>fvV6L8hJ#G
zH2Vi1Ry~_44XG0;A|yAh2PAV($7)Yr1{RsyUx>sZuRLM1#bp+XR>q;o4CErOxBo(R
zo4{c>n96BV3bI&Tp5#NUkW9)ELhlCZ>`pb5o7L-DRT()aw6MFnh251c?54GF{*^7n
z!msPipQGjK!~7a$N~nm_Xeth7YtEqG>l7NfphNA3mP=u+eH!CxQg{|iU|MYA4(2!n
z6rFapbx|k9 at zJ>**S7dy?v1D`gt0H6zjl8fd=BO>B9Ctnj`~^~UMokU><3KT at yeBM
z{e8Xr3zmq9J2dS^{ixh^%ISTuUHB;5<~~W$Oob&mZf+VxdFy7lx#>i?TZA%TIVwZ$
zZ$Ti;q1K at hNdkrE!@^1NjbA9R#4f9}>~-YCcF4KRp45Fk*JeJ*U9D5A6ufJiQN+Gb
zPX*T4YAWD&H0O})+E9QdjMz1l94Tl1seBvrAe{s{AL`x8l`}(_JCO>W-y9YSK>aH+
z7ju?WssU=Sf$6RokCO>$X!WH`1RPjwPi at QkbU0U54PZ(B+}+(0<FU|1Z=M4}Sel*e
zMnOz~i{|nES8jmv!po!6LDs|~$s at bHgweXLqpvePG+XGPUTdo3iVC-3qKnx16ZUmk
zsPv!L<#w*h?OHX at kx)$J5q)xzK|4}4MN*W&s3|`#OdxRwv&*#1-FkLw7q^{X>=UG%
z4<d28EO)ay4jsz20kPXDCJ17KO at IR7q(ql&)=lHz3eQ4ZT!?a6TweYvRTcpYtV`Y0
zaOz{+f+E;2rN5=((%G^j!`a$&$PO3FG2o2#qP`kd4cX at _ja4y(+!p3c03PmTJc`iH
zlJGzOE5rVfFuwLlP3^Ap8JYOlrU!Tay}}Q~*9JT|VgVI}k8`fcja}CIhDm>j*%VD^
z`!7F*nsnBPm88M~CGqd60{qO2SIS5x8Y_s`JK7137t=jk!B9q`MZ$)2-Y#Q&vN{V_
zzI*RV?WKTZ=VFERZ{)gBUy#a6V_qpb2GOgjGJWB-C_7 at TTl3=G<&B37vv!?x?=PuP
z6OW8LO2=R{k6MSod9 at LNL)XzjMwd*nq_9QSHSb#1ze`88z2>OSl18=dj_PdVQJt+G
z)!7=O3eObBq5IM94EJ*H%ZGiIJnRV`CaZ?H+MD;j!1u_}Rv4XfR2>}|Icw<b0-O=F
zR-n6i>#<;90;ibOK2XanGHeovwr&$m{_jz14cNz%uJ$zt3)uk>YcTvtCX!KE(H}w+
z1~n7S)-sN-9=_3^(cZxQOm<iLJMwvH?u9lzPD*3sqmz@{BWl;&GL_+xtWyDc6MQj(
zDaRZl>9d=`>`C#|y}nLsIcY+=SBc)6JY=0(*K5|gFe5lCy!)8B)vJWX5c6RT-(~4#
zY|xsWV}9;z6G!2MLgZ1<-j-Jd%iACV-g?Y_e?KYiU6eaUB{kF_L9Se0Si3>o=i&<s
zpV@`aOyRCan;Sk)EyHAM2kA<p#nbGMVeVUC{yOqIB=(;j5uUZ`UoOK(#U7h!$npL9
zTLIEQq|g&9`7b36QH9@=SiT#rEa$$o4Iv37?aC=r9-CA4+t))4Ln&WL4|6)sx!jaq
zkuNqA3VzjO<V~|tLdxZ7l=kGER_2@^ft4;sm>EmrO0gv30DDN=@Sr{U=_TFG!Q1Xt
zz2h}n)!S?O at Vn*pz3gO48=R%Ul0y_33s2Eh_EmgTa!Eifo)=j^_-I!Yt-;Xk(mFV(
z6*t at M1tyVSsV=u_rW_t0?;5uIW~Y|jdUtb87FhB<3QFzzO}E}^X164ti3BdQlb3J1
zSFLt-%Lz&5B)G1ZJJ~JO)zd9KcaZ37Bgj3j8 at uiCOCrcUe(MNw(IA0G#naNkvIuf-
zO6$arW8aj04kM at bhHM4+O>Z&F>G*KV!^g?+Y4_uSf3LRsTK5X2-fk>HlKG&oGsKlT
zc~>nH(l3sF6+aV+xNcdSbVXs|)kSIKy at LOD-{PJ8nc at _xqsjsx!y2`NBAE)cv=M+E
zVo{ojWmMV%rM)Cy%c^_!bFy6PETuO&jvc=uNByRza-2|(`i-cl(B8&|$;s2Lm`txJ
z6TDfO>$Ylg9aAneURsr_W_ol)nQD{{O``D5H<rF}snZ{_EtU>Ba;Z(moE+_%%29ly
zt+%+AnJ+Q1<3n(*Gx4w)TeoXv>*m&?+f{sRtk_bTR549DPOwjNsidpZ9$78vVyxYG
z;_DjFA4P+=P4r|?csF#J9Gtd0{1OI1)HqaDJ4o#8MaQW{Wx8N%)edSaxH7#k=PMSb
zHkLVCd(CdJHoI%A%}DBcCF7>9>+Al>SX9_FNL}<fIaAhk$A2JLq*(goMV*?wepC7R
zUHY1SpkSMGKb{d5v6VAnVW($>m272ASlvr%jZ#=wIUA>unDU))NKEHSqA|6he9KF6
z9nRKhgEGZq_Iy~3?w|?KcIAN@^?|T6OFd`iB$8J<T`$XQG%uOL^Kqd-WfYH!Ct`+i
zQT at U0V(RXIQhZ>;aW}k8#K_u2Y8TQ0CS^}F5^=&|%Bdo9`{I^|if0v+56)6(6{mFd
zeE8RM%sS5`#<5K&CTZ>1eNG06usY^oKS+n(Sf;Fv2%)?eZBujQMJ0=He2oYM2lA%m
zBU`c5eDYKyJ3I~8F@`eYuh<QioL0eBQx<joN;kaHKup~ExTY*CJqOx?N!A`?S8Cdx
zS!3K at J;t-x7$;;}ImWEQO&uz`x$aoZ^jNgjSZMZ-^6mX5XNGBi)DL?5Kldl&``{r#
zN_P{iI3u`;6T*idta&zAS`Zuyiphb)ORo>|uf-1k!O-D<60&3E?wg`lx%`vJ%x3{R
zIc?!P+Sq#i`Q at +|KEeYzn-4LV?QUk^<C#0e?eC`2sMO1d4PS0ot~|`yZoHxPCnw8B
z(uv=GGg&)jcz0aLL2DlU;S~M|(doU2Uj*tv(9}dhq~qDeX<=Wt5bL8J^kG8}_o$H8
z44x+Fwc8-;LC6_M=XiM_>H$p(KK}|-6b!@`g=p{JZ|!{n-N?L&amu4f)}tMr{OhSF
zt*9mRbC^E?@;S^G4~cx-(9RE24hAjk4-`iEZUQGe{InbSfK8Z<kN~_<pY!4gQt*y9
z$W~g-%lbPnLM*vhoaR_Lu+)c3%Fz^-R8ZI(z41a*4gvxE8%yI`w__7Hhp1~ho1i`F
zgu**Bdx8GLaa*9JbYX9=Tr3EwwH7{9A!g_&cqYoF17u|Z-bsaYWgh|=!w2|sgkE%&
z%Xag_8I61K=ryj};_*SgSfr89U=10l;ueUxcuW at M99bI*Ta1VBV;>G2!4Pd>$7lt0
zvWsbg{R!7Y3xcGJHHKSc`XR;GMT!YuLcY`{p3!Mkyh^8??ceXdrD@)MOAF2)`u%wh
zZ at K?lr>kB-f7FOBFS609);20rjl3S1W~*B}g{4g+Y4ZixVkT${QE$~d#pApPCpbp^
z-uNdp{pbycFJds^VSjy0!+vtChn-rD!ELPiJq)oX&`t+-&AY_|N7gGItMR^DNJmIk
z(MhKcf$I77249a6TOq75?s)<2%vpn-R>YEVw#v|h8%(7A2Fx7h!U&1}d at q=wgJp=f
z4l2zA)$Jzvj_CZ=EB!2XMR6mY-E7{+|LvLup2$m+lC9vUNm;&vr=}NIcmw}0N~P1{
z@#$e9nXkUd1DDw0KQ3dXn)dtpco}1`$axpM^f^ksNMLCmG)?9N9xTrjL<H?_#k*|R
z{*uWQA!qbU?WR?^f=_P>h1+YC!~VX2qv$aB<cr=6%bty}ZKKH;JCE)Sdjy*X^++|g
zvXQE^8aLN9(g~{udF<sd$T5>El}>1Pfj`G`v1PKsXoev(RC~&mpKouf<P7}chvWr3
zo@~)-3jKe0bYXR$g`at`HT7q~1o$gj|NYneRK~PSEVfgt)ZQnQy1S&*`<ed_Dt1VA
zcaRp!jbN at hBaE$t+Rg2W_+3suOnV7u|F!P8eUFEX0%ncyyr&C6HxGS`rW-y^7Q=z!
zS&uys;?bfJL05?F$-`GKgv`JY`4E6^47>f_6fGdm at R}A6oWTH?A22A4I^Ua<l(k2h
z_TgV;b%r<{z$M8MVllPup>jFwyi6hQf+I;7Wn~w;KkwsZEzG{mpzkZD*3F}plO`<l
zN)ydw8s_b58k&4;BfP1#+gV6McAj6zWN`Ce$znLs1`LKXd?WT^7Y59wbO?LRX`y&}
zc#_Oqia=I7 at UIg2(}c4W#xZ9($o&SCsQ3vAJG5IKzQKx$M}_<wCS!-xg#{JU8;ITz
zcn3K|u?IVzI6y*z#llw!!n$tLbB{6tWz5F)3)=J;6Fz<F4WamL{1<l6e<6R6N)Ht7
zkO;S#67fFUzDVXvPTu{Gs6VgYtmqFSj(kyfV8i^wdUH at J&>nM8(p-iOJ7Kw497kIh
zNsgl~-2~a+IDCf~j*4-P4ChRQ7{B&AFpVWQ)!6<s<}15zfmrd9UtXPZXe7 at ICL@1@
zcl<2&yf1qf<xb7({L%q&gkGs<x1=55Q`%g019lQlgCz<B>+1>zVx>&r9EWRij#w!u
zkLbI at QX<Ph7Xl=G_)|P$Vi7>P{xh89LsS;s^$>*SMNB78uvZMkDComE$jI3K=iYF^
zelN^ksDv)=N+DiA^vM7Z2m{eY7a_wI-O~vkLxA50vk}80!YY#^*}18cSPa6ftD=w!
zgo|K)2PZ2`CmKE6QMO#=0~XLIce=H9f}R3j{lHZ;YS;Kw`*>4p*BiBFw|tGNCK8IN
zkc)cvqTGCkVW3evv7>s1Tkc|XCvNI3Jda^(aL0{YwU*~2e<)1Nd$IsunCfK~1-}~1
z5mpu!L7xIC<Ryk6nMA=LfA*;e?6`@YJ|0juRJ)mZK?8hYjc2{_(b4#zSxeaOAzE1D
zBNf=UG(N%}O&UMQ9~-I-7fJ(G{XHsSk||exUSp}Kq+hvK++x;PEG63Z;9uTfCwG6}
z{daYk!$IzT{P-pZA`Gw-DBqhuKfl?VB&7RTzpghw<|yHF0F8V0Abn!e&Xw1x)N{Jb
z at X-tVm~<zW6ba3$o%S9{oLKa~i40zGAfjdOZbC8I1ByH1<K+oS3q%Ln!(R>+S@!|!
z-X~NfT;_`~x9Qx+8q`mjlX${4=pmlzD~vHx3RE;wEaCz0==JGQVVN;T324c(#^6Ia
z%yAz!B7C5smWw}o(Q0)&-FEqAUospa!-p7qjLKyC0^NR`8_SGp?=x(E7c;y+#Yo>m
z0a(GbP9?@P{3IjDaB at FKZgD1FCJW-mz{`Ob%!0ecobUpGjqIbDHk^3wU#K8>iT6y*
z%Yey_LWPF)u6Zlo(Y4=D+$`>fAnjZOg^bY;1?t8(;UjSRJ1z*bkQrS^wnALu4Hj)0
zXTlHAQbownD59h)ktOB at o1F+aOk(3_Vlu^yIYKoCX~E>(OC1B#RlIRv-;c at E=Q9w3
zB}n!Q`_uhmn5QxzwfIo)UbSw!qTKvNd?>fu<!1MnGeT3Hz*qmX1Og4<$Q~ffDuM=#
z=P%F&b``Gy>x4Yz3s~^oUl67BvfgdhIvsJ at YKyYCDYv`z$}Jq5#m#N|rq!wK0eAOF
zPtD=((?|NAW{XhR at TMs=z5fNK*p}QB#FXd(lb^n<o<$~Ey166d*ts>FbdnrTU~3}%
z67J@)`KA13j`N~E?(gNr@#`bpuR~G(4AWZajqYZ_;K4^jb6BLsgEx6`+bJt=(x_tO
z6Phy(BPSI8ghFNFhltfFYfWOQ<cd!$L2(1c2%;s>5lN}TcPvNR%lgMgjYrOs5EPZe
zThgx(gyV1uqSIs!B-)#b at C5{#5o&hl!B8!qng0{sR<H<wtYfF%{>zTL<1220Og>!n
z5${*NVOn6K_UZLxx*LpbK|{(c0dDv{$5j|%8TTY!8Pb|TYP`ihRc|u8VnXYenA#Ks
zXxK1VYb4LFIVM7ljA2?FQUQXGQO3m(S~gld!)Tpxi>xs-DmQ`QrSF6Op4AXlW9gXK
zYXOU5*RVkVYhXTn!GaYWa-&h%?^G#`U5G9|5Jp29(wG6o!;%=jkRsWLWOA5gXNZ-M
z8Xo2rW33@^gglxwF08Pb_-?H}EJ7{PO~%kv^e}k}#mU|tEB#>wqM$gL4Pfa#@?}<_
zhES3i&I4yF?(H3v2&xzF%;o_K;o$;GKwn(DW^PUp&in_cJ`{bteHIiy$w$|^J;B2j
zj8Rk=P<LPh84km|toxzg7YBQXdxyv(28+HQqJRPXvAB06M$oeT(C_D&R{_HX7XK{i
zN)|vbji4JY?q-mkYJ+k0Y4RDH<$3n(;Rs}%E=ZH$eYOQAa#G6F;U`#^`VJ9#N{Fyf
z5sExJuDu7|!Xtjy1Q&aTPK!77rgu{=M3PLxAeyA;CJFnWqA5z28HJJtgl(c>m`q0g
zwQK+)j4VUu^ZK%Te|z_v{HLr*r2c|rLpost(Lk57R#TM%1Aga8)e(dqY|3mB!u^8-
zJQ53{SugyoH7t3VIOa&;REWd;)itWQS^+mG$k$#ami7QO!rZ6S=o))dZ4U{xN#aQ~
z at K%%V8Md;jdp$%j at RN}e!i10~kazd3;jbPlPqcrHg#e%y`DECeX at CUO<JfhQ^E}Nu
zwup)zp-$)(ohK_dt!v}ELkvp?Gp7=Efeqo&fhv?%A4#*+5A)&&Q*Q*0g0J?NNx}bb
zfq03m1I0|f$=f<Z`AteYw7cCe#(h#pNFj`_{CRM>+h*xoOLpK7doNiylMN>S`knb}
z7B7uWA~^b%n^mO}fU{ov<GSL46?Rfnf#zi%j%p!|6mTB&EQ4r<!-eJWKCn2Uox!C}
zSvS{k=X?F>W3RxoC<`d$W&V>~LS)R8CKkVQ6N_Kp#L^!+ip4K!;=vy}iV02pPJ4y+
zl+pcO8^QrHXMovgQ(tR<MkFR=w)wC1QPq;kY^$HfrIFRjz;b`U_|F74gwo*MB1{WX
zjh at C-g^;=v^6uqV32s<IS88ArIB_aogWmGbt&Xt*-)AMaEa1#ay!&=49pR)^<r3|<
z-6DyxbW<l;NRo*_TmWe at DtpT@M8}Jfa#~lf;gz*b!Pi5#7m!ghIA_>QuabMCwJCPd
z3HxGlF1?WcM*7`WwdNImwF`)_)U`_~E-9tBb}6MLrIgk#<zPuE2NLE at 0Z&>R4SP3d
zU&ZRs1S)g=Sw=)>&oX<~5Fa#ceq9exy;S3Fpyb1*o4>IOs9x6F)_Pg$1xko5Hd- at E
zI`hdin-j)C4k6ov;XsN3A^CDhtJ1`wgzPCJ`9;IFj`!uVp-pkO)We+OYw2?0n5(7q
zvy4nuF2BT)a!V!NTGN$s$@UQSqjY6MIR6n|t$k=HSllEboe}ku5(Z<PP73L;I|{t^
zTnvZA6%FH5WTW&a%JqD?pJ!w`mN|Lqq?`D7rj>79tm3ge>x^*J$J43Vaq*O{ms(L>
z*m6EQo}Oe5iQ9`3`Il(0ll(tj&9$8(&CxXK7^(?zGr!P9c(?!18$6)DC6=%l^b>C)
z64R}?h)B%y6*p8%%5$!&l6^vp$8Xq11OFDKRYL~K*nR6y|90>zaHwaA274}!50&lF
z4&x3#`7_pjN!=Z)ZZ7MWEd``P8XKu8(}&0Ybm8GaPHW)`Sp~zU>Mg|U-C5cy>+7NW
z^{7~KJ|881{#|H{idgfCvF0T<U|A6d-=c at OiUlWG45l8!Xh;yP0LFdPn>x62^xFrq
zZr8%tB0yVZ9rZ)3s2mxRAPa*tH<YU-Q=*iUgCn+mJv@;Yn`92gg~`$klJu)rg5FTM
zWU=+zZ{i2E=pef|c;L0k89X0d=K|bShm$9d4&ZvsFmZqQ$r~*~*cUl?RhA0Bhu1mT
zYG%;*o;f?b!rEA56>@quWde_raK1lz><46KmC6I6$<|;2(JWud0g{Vbg8>}SHTBMc
zzO9ByWpn9v?R~vd at 1BZqGV<AIBh)uw971p+XtR5NaoZ7-`+K?{wrm8~oncxt(FwNa
z7CYuaH#z*A$l^0kF;{_cgk*`#p*EOi*kb(266+l2`-+Km(k9I4 at tQN5P|g}t`KE|=
zvOD;vsOFNRWUwF9p1_#G13omvxgS;_CHeE?d_Fzh-+y{~+Vf|FJ%1Wb#(VwAX#ew|
zzyCNN4fk1NKM(id>8)*pb9v!)iq+!LapA}@!>M5zLVdDZp at e~mEzacyJ+t0%glx1?
zu3ULPUr3)Jc at Bj7D)7I{`t^0YR_Vq*R9ZK`l-sp(>_fd#epkD=u6J!Cor?vE`@vWX
zD9R*9H=O%{P=ILNEQ+O*=i@`ldtIs8w`$}jWDmAwSR)7N;NwTvxW)_;eo7uB5gDY7
zDSL at IjhkRC+FoK(vl($OF{(+X?i1W~c23YDJZ4mb16(c^3x%98|Dk<L4`1Hj#Y|=(
z!&SX&r{)Zg!8|#2?WWUe77vb&av4fUYXqMu`EE2h8Exe<oVJJdUEZ)iptL)&mP=Zb
zC5OcUJtimSf+MYVD~PrI=6$=Ai}rN-c~(kJ{=U_!wpzuUJCb3_z?9pK3M>WL_}=KQ
zx7&x7K+=sV^$z5nA=<92<i at d-Yte2j*H;s9N{Q>p-O at A~{z%U`7{K~Hnca{q-6J%C
zp}4M{6pmh>VEl|3?7b7w?v4A8IUsHHeuN#^*U{Rk4BaGoDz%yQMY;0xb^YB{m)YvG
z!?AyU3O-%Dz%Tk%5*NClDg*Sm{MwXNxh{7)66+7eK9_GRmi}V%UALprnn~2iC-!hB
zv4 at 7!npWL>XgIu<ELh-t4etpFcaYFQv0ewS%I|Ab{#Q`=O0FDFx*?5!GftgWr1WAc
zLV2f!qm<KS{t(ZW`J*_`w#K*IhV8uNwad-QRSwxmf9Bl{nTw=lg7MFx3FGu>1ZkHf
zY+T%U&G+?cy-Y=q?xx-tIu`Ue+fGV0ULjP)r#t*9Yx$Z<HwE?A7;P){hEs3l{0ald
zWu-=}98XS*OChI<$A`9+V|3+_*u{%K$&j%x4H*@m&}lAc9is^K*qcp%3L(?%A&3?4
zn)}hJL#y+}-QQ6 at l!j?+xQO>4z)A)I-V86XW2EAw6`V1}<FdC<2CX;WZ7CDNQ4fBw
zX%Q+#s8BRg0)dh&wV|j)Bfb43BQ)01CEB2UE6cZp%W6WMNc;#=LDFkYHY+XR_BocS
z;p${umM!M?F+yh{=iI<EkpM5gEZ<&ty?V1-Yr+}zmrOC12H_secTC{MF+gfA-3>jh
zvN&_T%aGNC+CL7_`hoAhv=ifHy;(zh>gIK;@^cmnGAOo*)%aFf>Z(I`THkftB?r9F
z at h!>X!)nsqfMTsp!@WCNEn`0n%?+pdN^Ti=(Fr2k#dW#)vv=F1zjVtJ?PMhL{T;0O
z-uTmI`Qsy;m{z9F{tz4S9Kk|F`*5DnhFHPHgy_&ANE_K#a-#A)r25*+REkB>RRGQy
z+nyNntV-!XhKJ8cH|iB>`HmqH(-=dt!D3Hp40^#QP at ew15@J=4`oo3<C(Df0o_xt<
z3WAw2mEwcEU&8tgO=iwhT1NLs?Dp&Nt(KiMj3iCFF47q`4G57mAUwu*2+<z>tnYC|
zc8lxWy&G;h-l=p~2XE{#(PSn)Qen_-3xJz$TfJU+6R6XebusEaTO$pvPU3)PPL`zP
zF{Wx=WTvn&-I#R<a^qXxq`6sj&zs)Mf;$3|negj1dl{n!>)tJODE=+DNAyc6VBR#A
z?m{a<=}br72t(aH_#WS8``={5;+$Ht(6t6;&B;fb+wVX5iCrmtVOJE=i^M>PmYu<s
zp72>=4a?7rm9ZKXS!GXyM0QwQ<eEOR$mpv^K#nzBW|oM^(S|R**|(V9Mpyf36K{G=
zFIKVls5Jn=f~i1IjQYL=Vc8vFJCuzAgO4=FDUO#snS8m-f468NIQ$SPA(tGe!NiS<
zl|L9{qh%z9fQsZpvxUTb%K at PihJ<2B{B9Nlk8dgvwJIUqMj^&4liImqE902eHi^U_
ztL;X*<_yx*K<l9XOlb?)wEz4BFEMH=-i5qP$Fok+mn|_@*jR^PDTUKj2X>;hGzNBt
zuT~T|g}M5H!;{nE at iP6u@zIg39}vkU at AdUbzC7qn=PDF$=zpf8IY+Jv1s^qo at dJ4u
zVF*`C%|JFOcz0uv>$pyl<U2{O*}B$JE}rH{boRv0K*wWo<tt|uS>iX=HwdF~a1;(w
z->{y#0S7^rmh2U1T-ST3D23&2-%CYY*IU#1%zqY_yGO-?QbAsiLBZn*j<GCn5QMP0
zU-o3l@)4b$u#P?)aDCNtMh=p<Zk<|H6ps#yDu*o2abDMruK$GC6MpY=Fnkerli3X9
zy8)w9uul+_{+X7K)*AnxBkcb<!v3#zggtsAx<0~ui5qml%!|$fOE@?v<i*7#oMXyH
zS)fyFvAA12D7+Tv8EYf&<I$s9ySRO4fd+Tpp&SnUF%L}PA>7;B%Ly40X3KE#(=DM=
z{oB7`x?D^kPAbV3csEc`uA_$>jC#AH-gFvBhncvNQ^Id2eq|rOwH27D8dLHBifJ`t
zm}@&}m`Y1jq0yrv29Z=364A<B1*<jYa&F$&tF_jLdbNvSZKadQhpQTvnaQ9ngY%(U
zyP+It--n(g`_tgrA3C7ZreyEpmu{_-$!5(fpkq@`PV9 at 5oTcP7(AFG`p4dsRKVJ}D
z*~3IF4l6RI2B52SZ_C$IHi*y!cb$#4L{-kc%SD>3vSn_{?`i~?9Y3Gk-+7;VGcWAJ
z>Kq5-`-#4e_tZruA4%}ssg7vRaBjkrl4%Ydp<e9Q+@!op?tKns*z4q6(XUo!oD*+~
z_T)G(DglkQJk<^8(1wmt#k?qp-|6)O_9yAX-EiS2y(c$2*ef!mZKX)Y<!;Suwm#5j
zsGaPs;ByH at I(qpToewgc<2`vPG+Ry7Cbh52m0C6BNC-oIA3P at xIlNC8?tprzITam5
z_vSBCRdx55o0 at k6>!w!qZt5Rv*Bx$M5aN)^=G8kuO>kgswu;>N=V@;Y;@dQXL0xGg
zVlSR%y{YpC*SjjQT&dKqDKNX$Pj*n!EY+j#SxOH13Zw199||k|*n?AdW_vUWCNX?;
zJTs!&0yy9XKEHfd1ro1ZRXSE$#JjOw!ys|hdgtc4{7WWNc&?SqN67D8)XN>O=)J*j
zW$RnHig=0FwMy4(*U+9Dk?3t#=Sr&qBkh4;aC6&*F={u;*N~)QIZVGlg1nu2r`u|K
z?J^v!;Ct!V@~Xt*+dxhg?|tj~wgC&c)`c`D#bs&g%{nG3Sry&1KGfPCuvkcWEeo;O
zV+L||kw3I+??B9e=D_ztDgOPkb$yLR;b*H27p)fJNqLoeyK)Pa<7dNTGjepjR+9$t
z(tPQ3LA1fR;oP$fMl`otja8PbRT!g=Z1hFJ9$@HhQzy6rb^$4h=_#P;*s_8%`_|}t
z)Eqf<CQ<XY;k7P3Y)vPVIf;GXS~_yaF`qxQ>s<o;Y?PbT>~qczQht|(7kQBlaS7yh
z-y-Gb>~@u_DrZLKL(o6SmXd=jtCqWEtZ7wMVn<|gsNla`v|21<Nu80bX0>IkC6BlS
z|MWfU45bkXNCfQ3Afy8ZVMbw5V_bl2t7DXcq>ngguyq297(e&}5??cI($R!UwS?I@
zF5;7OY{LT#$e?7ot14t%hJX6A2^JnMSa^|4!P3Dk?Mya>$!+sMIVxSv?U>zBv|9MP
z`&Kc(v>hR{jXS})c*V)#!A<RM*_my4HmTv^ED}ioS^xv&si57cv_eGDZG8Dz#*BgY
zDh+zjXQ7zgxAxWzOqJffB)oHXX%>UHOca?34EkAQe;nk*3;(&BPU*)f%^X!)c>b|)
z@=P$%o_BfMtf02Z^GNL)YfL`gmV8oE@<MegXRcmNKhFh>?e5!f<d3|eKeq3vtgBi#
zjZ~cCsX5Cd&Qn2N1y<}=J-8Tzdc<l}RdX~Nu2RhEJSx(-U9(c`Cx-+k<#41mki(v0
zt2l*Vt&tLPDG9k=n|kOQ!b5mE(r!AjBoGF77hyWFy>bY7tERc$`f<4UIk at 2EEaZ9y
zu^Fgi2t<SjB0Q<Wiz$WcB(F^u at Ifz|J>7?WQ7n`W*GSCnBz(V~Fu4iWKU(HMiC^&r
z5&DQ$1oHhI!t9`8kCx&@_ at qsP4MXrz;|V^AY3~7!2U*tKOs4QZRxwQG^T{a3sQH-2
zDV9s3QbO?v4+wzca~$|E@>w0aQTKEwZHo3?1-BMM`F1+%axt+TXK)cFm|-SJ*Y`Md
zQ|3g>fUxy>5#+^e@{||-$#B#QDVodTgf9%<;}YJ6uQzkakKA3<6&N@)Cx)q}VWCLX
z^y|;U-n7re&JMno>&Y!KDrCU^MrqIDNfQK)HIjkUA!#NSQQH+Du$cjI9~t+0TTCao
z7s2*7A;b6u9131eNwqZ!{@K%Ewji+_OI(K(R0^tj1>E#?PTq&`kkVp5+0Lc#ES+oz
z(j}ZTPsFx0ICkPdynQPU)O(so&8fKCkeEA;KmH6H0D22Q`KpLJY%*r$FDSH_6TiVu
zl$At*Q4eHa5vUww;et4o1}9FFqRr<76e-*mmbfD43MfW&Mt;r3mV3va&lNTkDeeW~
zz&!Ra+7Pgua5 at a;yyoXm6UG4BW6c*uKbw- at +Vk@>ET29`4a0psFVHE7WEWPS^~Nvr
zN2rDsr4tQ?mACL+2xjK9KMU?(NW<P65QrKSw`a7SBOlIpgmpggLyYv$8=`6yT0xpj
z`GKIhR2`I=j-tev0#fEvQzZhKtRPu_GM&n%Y8$qx%S$*7jx{=Gb<ij4GXn0ij-JX6
z>6`Mi{6X(RIY(wtcl##Ii<9OhlE!3wD`Fd4E>RqT?E0Nk%!^gbOJXrE3B|l{F;q}C
zVIPGOEu~W$a)%na2K%NCfpN^80n29B6zGyfzZ@@n at s^fVTw9fj_ at SEB1ZF_`Fa#{Z
z*~AT!o|rI^xM)j-lL+39FnE6;m1ug=abdLbroAv^{r!lxK3YT=cLwP@<hx2fOwbMr
zm2tWex=qTlp$vPxVxD?0*qouy)xpY`iBDr__7mL-gcNROI!9yuJw31-zg=V##UG^T
zJ_=^VQ%wLfINEUN5H<azyo$U-y_I>z+*N1Sf|!-veMi~(70uUq(lk?{cQD+vFH8O3
zX(D+^X30eFw)DkqrEcU1-5F`Top#1vQ&X+Cx~CMpZR%twtdz)LmLzDN(YqpkSA=Wt
ziTeB}yh-KwS}aCA`TBNBLlCleg_duK-Qr>G=`ny=mvG)akXie4y5G_lHB5L|!xRbo
zQsGL<3r34C4<>|)xQw%sQq1A2F~*5fm$np9r!aZCLMSlLqn(ew2tu$7C&LBG6{q6I
z#q*B~IG at oUwceGiE%Y&yG`o508Tms}8goQ*(`sH~+p{b`e(RA}$0jYkv%XWr)tzUF
zrX6nV0z8>N5D4dxg5a_x2J;`Xa}CKukuLEFTzrW75x%{YVJBhUp2kX{ujmD6iXx2!
zAPNL1;RDN<%mySjOf+ry<M}M0i+m<apevr)#mvv`3D$WKY7<@R1!HJZfMHJ_#*-Cf
z0v&>6*@efJLy#da)Wbmiq?M>1aQ)FFX84(x-O^2(O?9AbfkGQWB~12Ec71#j25V*)
znJI}XNa1*8j=a=Co+_?b&lNV-MW|66D7CWbb~eOIR#@DRi}^0FAWC42>~Wn=XLuny
zr;_-L6YkG^ILL=^UfL6)L08+tnW7#}dY|NNbAMV8i!m99BUXz1QG(ux&*96spBD%C
z`;mViqNDhdIil=Y9(XD!eVmtHm$3~ymO)$Zbkys6y8lrtP;F68>fvhZL(?|#UNf(>
zMn7{bMIF=TtXq;5N^8fSa(9w%fQbT?e?Zh<oW!cJhA>PWAzk47KKT?%RM@$Y`%qq}
z9SG-~uAbHP%r76><r}g+mlJ|DCQZt;H}<3v#tPY$7RrjHLA%#y2@>fxMxINJyeOOg
zXHg(N3jh7~o4c>RJx}4H(F}4tA{KdO2WR{aw|=#k?+9B8PUhxNk*d;Z;Eu3G-xQ9Y
z)+o)=sWw-#cvcbC>@+Wl(#P2vLvM6ESPm!p?L3moUKY{Bug=AP$5Xq^%f$RnP_&@2
z1#A+%#C;r<B;#;y at dK4yY$H?E7_WWnQ<ihe at 1!-3XmyA-&6-PW*FEr4G^Y}4HcY4A
z#(%A5sSmnY{rML+Dj4-1{5#l3V~v`|TSSSWx%kIwk0}H4 at W-U)Oyh_B4{XaKj{zZ{
zieZ01dm~Fe$t$J<J2?oc1UxOK;lhV4ui7ZP`#?z2jm362GU2i@$LmtD4RuMz!v*v~
z0s+1^1lotE?dfz9CVEw2KtlSeJgfZK%z}s1tJT(=M$d7bn~GXoRITAhv0VH;=`*dW
z+06Ey;>0^5r4`Jl(n|#CVoK*1F4k)4?{)>M93DnEiFxMwBcq>n4VISd%+$YoPG(Xb
zDn&dbhpf)I19XM6!&Ab#B^q(^^2K*fBgp~99H-Kjh0_CTK2(8*>+pnHei)hCPR+Y%
zvo*u}M%lak*hyJnpGQ4!GWExb06&jBWGS9}+=lN;DYGwO{C5R8cG0Owi?8z9omR-_
zpoisPRCJUI at ZIuNj*aLKC!zlbw?f$#5ZiECGoIkfCC%Zb7+GpEtT#heZ=<z_t2*b3
z at ZYo8g`rT_g-|%|UQWZM!xSsMaX0nm6OUS$tk`{^qau7(+FN(zPy|Q3BfJ-QBup0y
zXCpZqEA9ERNQHf*BQ)~RIcX)aFf_6R<|Jimbq3<|ww#DPn at VN36K4Rr3q&|0i97Tn
z7Y!bL)h>5Pt(o&U1(UG~QBm|Oy`;}Pt<mrNR at st}9oGjSqKS1bXAQwFob&rVRF*#Z
zY($9=Ljm+xHZe`!A0cpAGK*hH at roXJ2wp`-<;+S!{*@@ryl<eLNv-|9R<*y|6eYQx
zvk_`ufR!g5%2<p?pvVLUBO+3d=`Ob1I^f%LNscvf&ze13J8n;xQJKqBQYm7mk*};2
zd>)RZ;g>2EouTX$d at uuI*r)H-;lNI1y;dbD at yAZ4-s!$c$<67Se5cZAvBgfLU#e6j
zJ=iJeMSl5CKsk{n?Tq-GH%B$K7!nz_1+%%rHUj5aS$vUB#R3)``luD9Gd&@mQTTzo
z7u5X@)E$fD=(`+=%c$f?gFpoWE!pNXXX)>whiMnXg|QwL1RSmIfzNTu2X+Ig=7>ME
zH1W`eYtnt%7_4IHI9k9f&<4Tk8JbeV?sYVhc--z)lw+<&tlj-?TdXB~jvK8dBuX+|
zOGp+oUQ0-mXu!5sIy7QSNEkC at 6TgX=@tXBc8LYvph>==C;qE<O(%8q0#Xwd){EB`T
zo(~S<M;^-u&{{>CI(b`BRB at lszS?P`##!o>zFfO!QP)GMP>$)7)iqmIN-);ZNO}@7
zQhW-l$mInEMwMbZ8i{~Jn<Zc1tx9i<H#*9m%Y~1l;-ERXr4}-Y_6e3zmc13qG!D?b
z1Eh~&@TfIsC#*lCw^Tx_+d9Q!ydb1UyOr{&QmwtGHxJ0z(6Y!=&9E(d?(ZTSKkuM&
z_WIM8tT`72gS;@|q+`l*H0RSsK%7o>1)*AH#Mf93wg!r)XWZ44au9^o8d1#|<0TbM
z&1+r<gzAW-+(ik<eF^n&88+>liXSO_ITCj+G7I;2)*P_s>^~MD>UwzUWF<>BX;9^n
zAU=A|q{wzEGPt<y{IaBeIecV at X&`VDYZvi~jq|Tn&a#1m!pVqQA{%pOHR)0l<+hE3
zk#L4}1Ow|N%iSgEXw3NiS!21#O;?x_{BJ at 1DB2tbi}~$0p7Zl_V8yOJ&!QaV$q-os
z!V$`zEovv(85M!`=4H#fye_{}SP|kkJQ8Fw^3&A^wu1lVrrd;WhOaUr-xP8ue2;ul
z(4F?MsN0g*o!444e%T9#9AHhub~wI_G$SeWz8J%dd&&&|cWtB>y0Nr*g5*TN#KY(K
z!IS1JL5bsPZk5Z0RJz(e7iTt|uxvGxIz&S&_K;Y^0W#rOj>qj-!S+&+C+UZ2Vz?=C
zwwbKcGSu*9?Y3RE+LanjrPJP=F=`y#J;>UB3`OS_X1dc!+9tIDBqx?0yZ_#XIST0#
zwzyXm|1MkT9>4yyV<ro)=Yt77XYG{@$*kphN(Jc0rK~H3c}RYQB`vXimFe&srnI+z
zS--8+ijCK0xqe-%#&4;Uu5aV<HJq(tL+q7JMW)n9^D88&i16Vs<plF%g9?zy5z;6B
zYo~kFG$->09kyfH#3x+uE=LNnM$*L!NeJ5!qk-jtJ52I*@jX_E>QTUsl<*iV(Z7oI
zEFTm5Q?5ngB)>__j99%^EjGwRq+?N-iAe1^IY22;6RCg_5$tRitRTS~{~IAqJoV=N
z$HC-b3Hoj{$qJN-X!5UsB26yJ0opxGM3^`}Mx0&v*TC$4kY$N^FoHqEK(zyHj*j>c
z?FL1xpvV@=_6<!cW<JK>C8v5Sh-2`gbrkE^u{`v1M<XjVQAZ~ogT9L;cgl at 7-iLCx
za#d};bKrN?SD|_u!P_mjD_0b{9YOJa&`;b{gLbaU#$CAlOY7EwJ73vxYQWNN at 2uHv
z1Ib$|mQIdLpKVOuYK1;pU3SsVTdnRzyIy@)`yw)40<jxQvo0Zj15n+RveqEw5|J|e
z%i#Wh68{EN(GX<>_L%!*9Th>rH58&JAjg2=Dn7FJG?>RwaATCJGhsLrnZ>QC)hOS%
z$tNh1B_(wUg3>}Vco$3g=Jo4XI(WAkwzwW|r~Un9GvlUQmp0s7UxBBSR-z56b8uRC
zeR_Db3{<Cd^u`9&(Tm at La3Odbz4D(?lZ;M)lbHpM5ktIrE!zILw-|^@t=%qnTVl4?
zhcj1iKKajiFx&-7d>l`PlZU_$_wHxk24;myV5pTZf>~jJ4i{==BbXJ&|4D#aSr=wy
zKjIjrr=v@}xPb;VZFNeOcC%#3g|`-SpDZaS<33vE-fKfi#d%d6 at jIVRcI2IKjdYc#
zSBsf%ti(+SdB*UOj#ZQSaMHt3Rc5yqS_v_BX#$!GObjG2o+Kk|gqtC3EP)9b1z~>)
zLdX(uWd1~F-7f|p!E5W}zNjUejD;M`(Oxj=(^AL~ifw~SpT8P7ix1T<fqQoAjanvC
zJm#>?h$9t>SiDszz*BT`E_RD&8NP90n^{gSg;*M$td)VT>m`V-6fkdK%OP>qO}FL9
z78Fv28?>i`JL3_NWBUwpTRHde5HS{jj$`R}i||E)7+^H!Z}XqK6x%+MJuQqUM>^UQ
zA{)R8pUP#UzUHE~t0ow^nlC)zL80-eg)gBrX(EtdoW)8zFZ9FDwO_<<=J7+d-RX9%
zfV|&p49w0T0V05*f)IxG&}hA-$Au2azzP=QF+%Xfjd=9{*k&`q7+Kpk{V~?OD3@*H
zzm{Dn8cldmBb}pR(PRsG at ye!!oNIg~6~yLLIi3Jh_CFzsaT8>vR8J&gcm*vV+<DiQ
z8L9npEOFNBSRW4iv*g|+o&8no*gGOdmJHqjOLti-Lv+NWbxC&A=&X#-Q4=_60iPEm
zy7p0iNM(@t$&d=~nJ4}JVupdDMCZEo!K)zFIr<KlPGB{cj*i9EKPi`VN(26d-03}|
z#}!Mv&~GjbkMayo_Z*BCBWXPY={V<M;mt9WizS|m;<08Pu78&5iTE=HY$kQLe)ZPj
zin&xTFqa*w?E32cMhYl%dyAHVJs%*0yE<!4yw<>cWcw1D$>Lja)_}Wf`lj8gxS6!n
zm7c45@$TxnE3+vsid=T!-z^^4-76`ZY91nv<JA+wErEDKBc{@4vo<S7G3V$wCw9@@
z^p#!M``j58#b-yhBcLMEcw3`QhPNhOYK1%{VJ7t`^~qfmL=-6(j{Jd)J3Z6kjiF$)
zda%pYn(h%n+G8cG$C4;!2qb`j+8l^hNzkWeLiKfk^jop&--}<G)>}p?9_8^0u-mE_
zFEy<5ysnhP*bEToLD6>}?ag{1J<iFU$lj}$AuCH>qlS_7sk&uSttzpSd|1fy7ZsEj
z$HE-9^K3Lmre%=gL$%(z#OrxnL5Sk_n|$?it#(tsuD`F{)SK_}5oDn&;MhY(ZtS4|
zLc%9nf$kEZNrX}9{hgaS>CcDR80(bRg)Xb=kI+BIl at n$U$`XuqfaH?64X>w!!eGD5
z!CQ50uijxQOsw8B<^%fs7)xN~zX;V^{)#v*74KcG+qu2DX|=njjuq<k1&t8N5*CY>
zd|ywF?4G>&cRuCNlUv%sqBHkdyuxm|d)qmUz30ff>YLWHF6P`0*nG%}+s>t at m2$)>
zo80ar;*aZ}6m6fOom1sTfj0uw0&8%mxro1mvimi*z)72#F2MjILt>{WJ#Dc8aHQ2K
zcg_uYVDmJ0Z0$a+DmTqjwAt!*rL^+9yVu`DhZq%W2x)7{W9AUJmuxey$IG>uH%rPf
zn8zCmwaApwJl)18n9L{8MLJ=~?y^by_YzxW*IgfnfMq^uD65YU_v at Hc4u>c<;+OHn
z;|C5)K at mIr0rRQMd4zH0wau;lNgLeCdmj6nF}G#oMEjevPE5kcGsj-tG5JdMZ3JQ{
z^-U{)8}(+Z&8EFQ#(Cdz89xpUzJ6to)ryepm~3t9D;6-Va5Ry&@4<P~cP;ph)kkvL
z=v^d{98NGMiv(G>a$8s9p<SJB-9G!hy2PwQ*hct}y-TC5g_JL~48r%=5!pi>xRscd
zC0q*-eeV4E6T)K@>9F<VfF%J(m_3WK+}~FP-LL}4^U_`S`q!B=YiI}l>cRa%jc)4P
z;eDucV&ke(;$*~5H#85M2g;DY+#ATGQ8UA}Zm^12un!j?H`3 at xzzDax4Z}sK%qwqz
zT^h(mLPJDa7>Nwwws7gqv05k_#)XLR7g#S+7TV<6*d2?!%c*ipf*06TZgOAjR+t!%
zAljSgU2(MP#Ha+WqCNG(cr(@hvg=~qfNQjzZqz%KYVCd2-BY5;vRi7XPBjs%ck?XO
zo%<F*vvnPk at HOQsCLtwWmb}IbIt)=+Iz1?!9-OSWen~H-w0lq##lq>~;psv0)m*Vu
zq)3<Wr^NTnxP_>-3uTFI3~<iQN5~Abkxv-69EBwo38TT#;WR$;DL^&IhIB1KxcU80
zKZVl&l6Di7I$)pv|Ab;r3E_-1RnifR@`?G(_uZ=*1s*Vyh?3Agc>^IaB^OgT<DpVW
z-v9C?E?R&Fz#kYJi5j3B6vzYU9w8#APIIM1*dh|@A8A$5k6 at R2Dwy1+NW`0AJcGVJ
zo6}z`32`IF0|iDBpr9P~fqV7F^DrmxK^EiQ=Uy<x at jw_j6oe-<a<X(Zn`XcrIpQ=b
zl$FfgFsx%)w+!0rv~6;a(zsIB_r}2ghC>*wEp<`lpXqCI#Ip;BzCTr&hruUbY{A2L
zaQCu>*Dza>{qD{uyX|sg>rANrNs)H^pfWSCO4#eqU}#}CLaQ(oc|o|CztCt7siEB5
z1#Wyc%)f8OR2_H%H5V||sDf3BCH5DTCP#AD&E*voAIP?!eKj3CVv<l^2oVIYq%c4S
zH0a*%;oY?C_*3tbznD at i0EPe6GMrt)8L4>eGk>t?V=+!Iql1z+s4}K=qaHM57*6cV
zG1<Mr0x|1_+~#u<3<I~4904h46jahXMAl-$%H8>sklXeKOpjxm=+NE$MBW!qw1Nf3
zGbETQyjhbIrWICrvkP1f*ed>iGDAElpsfP@``U0r4dsq8%)RSMwc>rKx9iP!-o?9i
zrm!qQ``v{V;xjqH(a}++gk}*?-TrpeY>KpE<ld*DWb*7MYm>X#^f4tgdW{JU at zNNB
zq{2wOKIoT<2aa_?(&v;(OiCJ`zEWw$^raV5I3gnx*bk3R3n$4tS at 96&YzO}oi!^tx
z92$-X-n2jR3<4CqQ1y6dP>k><-s2OAq$0D&kiX}m)2z1NdpDH^DM&rWg|C(0*Q(+-
zNQb}~kt7#*+u(KE<!0xy*4B=DAiQ0`38B`k*2_(-0Vk|C51l$L8{La~*XtCIy^C62
z3+5{mU)PMI9~3=9_Tsj_T_&%kX1CtFZQXYADjA%1(E0WR(eQ}?+x`@zc95w7+Efv|
g7^Y<F0McgYyuD}0dqhzB>*oD`0cwzKr)9?n0MB3^aR2}S

diff --git a/target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-at91.patch.bz2 b/target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-at91.patch.bz2
deleted file mode 100644
index 7069c54dd4dba1b9bf718d843deaace8ca78ff9b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 67725
zcmb4~Lv$r<u&!g9J3BTy*kQ-E(=j`?ZQJbFwr#Uxvt!%7|2?xaJkOwNQfpO>zE$tL
zz7p0l=VBJpq*B(*>hSk~Fxv9-_j`f~_WS-HzIy*l27WqDR#r~uPFtPZ+)&F9kRx8(
zJT}T(ZHfqaU>y%n+waF+kUJVbt?C|l0?so#0|SfDNiICyuf00E`TfDbV8UGACuS51
z^B_V9&3d|@M at KuDD7n>Znoqa7uX+AnfgwYB+CKSodHibxzQN!BEctt#b?XmK=wpH)
z#bji?WrJ+qn0@(78H|5{@6x|Sh*~HJzWvyTfpG$!LW7D0xh4pPurPaAgwefTw)5L-
zoLJ$%rvD$<{LK32rJL;MR at 1dyO)ztCF)(nEe_%fMZ96vG at 2xZ^6kz;8VEpI1S9e^)
zj at v$MM5>P))D!&O*R`-ShCF}VJgz)+cEqxKHlKNxmiUin+*TO6OCd#wd9sN%YY3g=
z>}q at LlD0b679&W)uX}8lpSPm;8&g|++%PPkcj%s15(-xYVMTb_J?3lWL~_87M!c7-
z?>Dx`4zX8JODAWY{M&14JKp|1s_u67?_M|ZPcgK1Uful9><|yj{_0ggdi9mUlLyrN
z`W~;48CQ!F$cVM9TqdnYVlyT|E~00jm2K}SFkAm6J&hkHCy<4+u%bS3dR|)fCyIPD
zKW4PrrO3yuIy;pI39FIq3Oo6GNP1=jJ&~S{YwY>h#mvomyssgIq<fIK-&r^w-X2iG
zL?qVx_^{kIi9NRMsy*|3AZr2&bGE?DXMuAq{HsbQ`1`Xwp7(J+u}`R(=5OZgf)BPc
z9vyRnF#agnST2Q^>5xJv2#e>}R-1MmZ!1+a3oCAJ+or8%E7aD{GtFCrUhNC6+ at 7YT
z%kPsFh^<5&ZjGv2wpS~i-9As3yXvJqPuDHSs?%v#PUj1qPTRKG&b9SdJ_K(b?UOms
z>;7QCf;E)aE_b`ao~y-;?e`hY?PA{Bb*`T0&Ia9QPp`GDbEi?;Yg>ZB9WTs@?V}y-
zm6&-`WkROf#%}jqT;1to9>Vk|cbV<KQ?CxkZR6bUt(9)h&vC6xnn&lkdY6}tWf-j*
zxO(ln*G~ESSJlrk{L9xCT}Rc~nQ4_yp4%21OIw$hmm3nZkC5A(E-_ZFofp$p4b9yJ
z5;J+;73b=mTW4=J$5zMMZO<;+88XAhc7!vYg?Sw7dDW at i*)4$)t*&f$gpQS$tur1`
z8`hgs+^e-*+j3prJZ}Eb+y4?t{2{>5z+%8K;h=^V9}JZjNQ<e~OCH&X%KD_hp-6(E
z#?V<n=zv+NgGCPo#aZ+55`Qo-ig{7dSrSZPj*?K>;9E##Wf69^Ay0CpVDP-L^$c^g
z<OC?Fu?0!X+yWzUWjHyxL+X;*Ibf#fx`I*$iA9WvB@&sWpdb`P=_&a<RcUbfrSjrk
zZZU5>A4l0EafN42ybU`Tj6akV8VM9Q5D#oIy-)~W)P#@Dbm?b>FSdZPW$5A>I~e#2
z*uBwpJpQ)0Fi8OG*KjIU|J21Fp$H(%2gpEUx4JZca-fa55Nrs1%)THIen?dzxcuw-
zW-3=-VVwAd_ at CdP(~00)8dx5&A_?jzPu&nJ?f2+MI|#My`j`gDOwf;dbqo9Y9m>mg
z9=1Kyd;WE at Q1-oQjz-x0eO)XCPVV+$Tm{euYz_uSypclkz*+o&{Wc|#^CJiVbSOa$
z5e~PfQsJ(n`1a<$f7d>I>k-_zeXICxv0C85e*8v_UAzxa<>P`OMOTI at 7cWBi?QBW1
z0}G#y0)ouL)Gmxg)S7YuNJT?qG5<Lj#7o0faalgrQ64^Csd1cOKseiA+Ua2X2KL4s
z8*r^4&=axfWs#!4dD(?I98SjFUJif9sqY<j@!s#ScGSQi+HSF{>>>6V)(s?lE4OxF
zp>ubXz)_KIUTke_4ujU=<&D1|XS?8rSAO##1q!N(Do^50?lOF}zOUwo3a6TXTS-|H
z2N;FD|Jc!fGxK~km}V|pJPbT5eCkoE$?)=9-&oJ|n|BA&Ma}Q*v9Ne||Ja`VN|QnJ
z+ZW?MCd5zrqW(DQbtC;Et|9J)O86Wc`Y!s$-KfP(Q<zHhz*mn=K|z9jP8UZ7{~|s(
z7>n9yYBEkfD3aFSO-c|N*#byjYmhLq2wp at Oy?uih7tib<qfNyt8u8yu49*LMK2L@<
znTM(Smb<T4n#EaF6HQVUa3pztHPwiy%dugGcZ#F$aqe8!j};+i;UiK}7bhLwf7%Sn
zb1{_a(19~zk&- at wTiJs!2COsWwIZqL-~t0v)B9y*<vGZ>nw$vgf%203xpnP}%7J+d
zvEi&t4AE&MM&f`uhyyZHK&+`4G`OUb0W&x(>wrjnR+cF>EQDA8A}@!8d?XuZ0c{Ii
z$1xFi%(px&d<kV)K%0iNP#{W;G8BR1pXu1SaGHZm03HJ-U_??f2}iyHZ1I{9zoumv
zR~{rMze-0_Azk)lW5r%5X;D^U?2>j^v5ZU0h<dg7&OxLMEx at GN;e&a$`Bq&~_}ZU@
zl6#{%<}ARMW^+VuHKT9jW+_R1RX9V;+u at q5?E9L15RQlijh?`B85viX=Ej>52o`W5
zqHhu?n6zh9K!ouiDnUaYD6)7TsDYG-CRI`<LC={4&00JLMOu`99vVq*d_a(h;BTOG
z(3OlrHVVh0Ly`y=(1*coT3}U`-=A9U;ShmC%Fz$8h{h@^h0w2vrXWAKyyHf(;||wH
z6J9Tfx;656?U&Ai7}Ur!&DbnFg@)6xX^M}<s#OzUs^Li0T$Db7Ns?ynOp^h{&;gNz
z#K?lxrmt+!o&+gwv&3N<bHyCcKxGmgRHzvOpP!I#&@hJsXTsL5Gl&(!DpFu6XOw1y
zQ>0s0M$e4J_RAEAYO;J;D0ww$&cU)^IkVgci&C6PUP2g#C;}5`OW9CGQU3X>;But?
zBEMeVAaIh9UzcVO#5048W}4j3Z3rGsI#<*$7ONsSSO_keN0US$hK(e5GWwCH=kFh`
z?@uO<Ck*G4;2%ypAByMa3+{x}gYwVk4ty5Gay*laB7h54TuhyWZr92Z2zB4bc0%i-
z*DZAexhDl79yBM+SwCf^WMyj-`)g^c&x&khcq)`)1X{nLM#E%kGTo-^&kDo9eJ`Vp
znFJef at ci|B7BDc7{5D7lkaZ<u{L7~P89|EeWXeB0{+jf`1oEl=M#PoTqeLCa+H0aG
zbvv?&mmo<HaG0G+8|N}bN(!HbNWOSv at cT?G656^s at upDtao-2<_f)Qmqi))UPBKDv
zGQ2RL-p*8T-Up>^C0A8)g+ at yH3BSidRMru)WTqX6$+6kWP_U}k|J6hugos}Zw=gKv
zWizGo)c=~pVwToW&Go6Yb4p at GV&2~3$Z6zG*vdX2Ol%)Yt+menEIn*&1j at BqsvwZG
z|D<ibys3L0)DD5?EynUK`_$d0Y++^_kdKB>5)!$5+L90p!?~3sp0_j@(2}ciA9Q~x
zJ@&Mhm0cVLZ2<}-Nz=k3z0Zs(*=4X2r>1!G)@9 at q1N{rgS+EP`6N4zFQ<Sg<;c-Gu
zWJltsn4`i~ETo6aO<Nh||ByQW@~Tk+=N%cafUKV8qOqaMNJp?Nu?&nf&!bNeGfbo?
z@{cqnp^8d{CzDH35z-u~rX)y%fF~m(3l7xJ5Vrf5WEm|w&Uf?Vj;aGoPMDPzNJ7#$
zSEC<6Q&1^rlMR}~Xest*lhsQyJtGP&L?430$k%8NuPRqYt3aUHqo#?a5O>cyP?A*Q
zSSBPWD<jh{!)`Z)qsPKlfs#z4IOxieo;62CvyZhOnv-%IT0%z(08KZ1-QuICwFf~Z
zV4%yP%MSk<5QXYz#Zr`#!<t8 at GCU*tMUYJyBrB>4RZJl!r47i)OG^I>O*Cax(c-V+
zKL(|UCC9)9&BJBj6t+TUe}ueV0mAsDQd-n>QoMC32Wv<RDeWONQKk`aD5^yjVNMWQ
zzwI$d6_EE&Dj&#+mdi0G#Q;kuo1DWb4@*F1F+>v$SwMj9KY>LNx at v+EB*?m&#4Rh%
zf=LEd{_xp*|6S{6_oaBBvU{u)nqC&zg<`QE4eL7K;T=DHap}aSD$~`}W^fYl*K`3%
z%89LRVCRDOi@)UIP)dHEwO8*?*R2nsLJ=@&<~s&nV(&<n1LamejF{6dkb)!3mClQm
z3?yzu6HG6SIGL`z7;ccc{0640QB*cmrY<{5dNGap?Duo$=KK2iYKc{jUFpk!pMAp9
z?gzfH>7ankxzcY}6$!d at NqRPtn;_R?8j`3CvzI|-%q0ADadP6^kadL-H(e#g6IzjO
z)`O{};gaS%D*>2B9rZ|uAX(#iznR@)@^fUw?<&}lh;X2l)U>{&Aj|iUa!zxv9ej3p
za)e%?8bZ`c0=q)6$;-`;kGKJjQwM?pcBDa;+tLuU5VXHj at 1-?CkZ2(iE1)Eh=N4#%
z54MneCAWB|fuYT31RVA2I5ax-x1pna at RKL~o#=zDr+WB);^tqOSBEU9eEBu`y+?;7
z#mymX6=-Z at MMZ3VKjQsu-yF_^sal_sD6jh(N1iT&Kw`#mxn?$c-3>qq1{MS9sTosO
zP7nNT2`F^VR7-0O^%PG-KUsr<@K*^t_GCDoR(^QV2oZxRW5x!0?eZQ%i8id7fn`NP
zaoSJXdp~xLt4>?2w%u^0XgP||=2Ao}BL|4cz7ZUbiQ*mCh)&^hDPbP{yyeiuz_-Lm
zBBCC(Nu8Z<#GUqu%96o<X8Fom at x9qU;Kjn5#n2&qI$=3h*Ah9 at e)GF4>sB#oE#C1O
zdLS(*9Ep at nU<%<n_YX}<;OU1C0nKXJvF3JUhotRTfs?TYR<tG<>p at jhVlL)sF+lye
z&-9uG!oDiE^<3tC&S(25vMBL-dB;5?{vR`hr?Sbr2)_ at C*e|^rV`+)?8z5bX;!Mio
zN9HTnDEtNaW|j}A%nyL)#6cAE(%}+|1n0{gs$f2+ah{BZiS?m>Q=+}zSVzp<2sWf_
zXr>qtbdqNz)<*vFSIA??wg54Qdtv1x<|p(}v0>CJiCFE5N?0fO>`^81hvhgu2;n^8
ziT{8VoVMaXT*$yABVhSAkdwMM%2JG%g#Pz#9&BGFdPfi5%#ZK(fX>gQ_XVJNI?P?I
z7_*e&XpcL)9tf-p^tuQf&HKeR6w_Ty>qQ&3WU<HSg%^+}&qre+^USZf)Y3JLdPNKI
zoB%^6dwA)4g!yX=36+D|a>{-7mf|Qk4j#)U@?%PzSzM4m#vH26*XWm3rgJwga?NjN
zxwx7<IbspclG;Q1>Z#^~Z9 at 4Z6rv0pf2yplodV8IN+B{~OFvpH*ym3Z55l6rcY3FM
zuf0d^e(jNrMswQ#qZw^3-jbU>+vn&9Dty0IOO=F|r&BVi5ex`0f&^6FUK4|hB$LT1
z^iHtkN#dge;#o-d`ry+ICbJTta?t0YvdSbwOkqg0l&J#l%M}KM(mZ11aDDRkMksH(
zmVNoG>LX{17DWLD5eUwT!<aTIasYyD&tLuag{Ql_YrQnT at iC-V6h_6fI8{TXE=Eqd
z-5~#T3|Xh=J4mYl!89WR!DD1G8R)zju%O13=zx__bgT79Cd6zsXMa+K0s!l?i9W={
zJ7<rc9dCYdJ7pW>9MVB8ESe<ZxC2O2tZ4dXg*$(JdSxToUEkupHGWySBtzEeq;{|>
zkXvsr&H)&)%_Tb}m12}h_BG0=8m4H&IkgokHuZda7vBAPUvj{{eS4{E-#e%82WKdu
zY_Wz_46A<FFw_-1A2lj^e+79?79wc=6i!!a>X{7xq_5&wLsu*}jO6_pRm{)xWFW`7
zksPI1<&fOv<%C2Ns#TdH7lff?$?K5FrDW6M09a?viWn&y!7BvS=;4yn{c2o0WSPm-
z<HuV4;HSTl|141AF`*$1uT!x?1l01qEo)dZlDnn{+AfK*398Rsy?A%-htO<bgmI*0
zgBV%X4M7_9qCbos-|(WaUCgUYtEbeLPF}t{-<}8-1to&^M at HDEMx3!GgfP*TLsUiq
zhahy~wFjH$Wb~9kVUqMj8kH+i!2~c-bTlC-5ih^t95g7wK`0R<QL5kqGC`3<50fyJ
zQ1Y{0W#kThS~_A|_9m1k+|bh#`{9JfZY0!W5y5a4X81`e(gG()m#fizra14<GN;WS
z5S{19I%k6f4rFvNv$WL!#86!OU|Hh@=x~1<y2hWTtmx9SmZ`y5jPY!|@kfJ_+z#5P
zHG0CbjuPbuYy`pIXNQYe8HUo5{^7J1GF1T~Q&aNn=`5>(bb|^@ovbR+uU>U-2fK}$
zrb6p5FC|%}?^*|<^SFi?%a+=g0>rm34tw?$Yvb~TDj0$U at w3Ur(7XvNkQb+%wRcbK
zu<#ylj?^g8=ygY;`3tO4dDYwo6b!+Mvhl@)ppyc92=gm(?%;6eSaNK|;Bh%57Qv;z
zYc}r)S1C(0FCOPy9--{ER&#C9L4H0fWtW)*Q+-^ea)MRhLn-7W_MJ{qOr^+Hn)rCi
zARQAKe1}L_SluZXp^_29(c6Za$8^-f%n1wbWCfnW#|F%!TSh31u~!)JG at 7@~NtBm3
zj(wJrDpNxPQ_F#p3~}+_rS6!y<G#O9oC?8tvc~g6(_fo+`^*iJe^?p(Oiu}^u3}A@
z6$~UFZE-Mf<iXpY+f;{P(lz_t^osbA5gPSUClzWZaXvp*cVaGc%oOs4QJ_#CzIsAK
zG#cjnvO;{U+l&z(W^$#V{!f2u%Ts!_=YrpLQ~PHKu@@QSufIo_$&D)+IPaXj`?lRu
zI<xc01z99qlb2{Sd!#%H)4_b<C`H6~B4ZU`T(stR@!JB8CxK?Ey!BU-9gx?LVph=l
z5~`g$J}sZ7MBdxS&Y+Budk!jYNv+vqUsmE*B$!ZyaUYjdq#y4bsIlGCB1JlRgWOFl
z&rG`+_A;T~vVx+ScwYxsh%Xo_dmg1x at z?I8o76d-jk0|OimGz6uNJNR51}pykErfy
zuYx0inm?#?=%s!7Mm*Ev*`P77MZX0-Q=oh#Iv-)6{~oBFA_bB*$VI>)CL at k4=erSk
zdU7Act!t9yqNNInt+M1+0TF~aeLe&X-fDt58)Tg)rh*fbgXk-gY3BES^#`zMTdE9I
zp;PsTvoT7_h-3f>sp2N2(##9!ly8YAgX+B6_X*#Tp#~OQL80MEN6|@wj*7c5%Om}Q
zj*#|KDrx~9yaDEim<m*X3~2HSD9&*RMdy>}FjQJ04D-m?)RJTlNfUwc`h7}L7zyx3
zz+Y_tX!HFOA!Nky(gVr at I2IUw6wO;~fQb(l6^Vdc;pN~K1e=(Zn7Ub<WhSIFBjM7v
z!H2jM=WyYj2xD#3F+9i(`zbP{LJ`a>NE0!V!&%IbpfP=Zx$ajGb9hPLG1oQW#oz4$
zI1 at 3Hrnp&4(J<JocO%JiMYH4?At`VGj-eC={skKU3Bw`q;sSt+Dn*h0*fwVxrmQTl
zPOvuTtP({jh1W(XVRRsHs6b{^sVpU_3PS{XkzhAeXAO~iGE7iRBvh9{MGuj at BrOqT
zRBFhBF*Hm_C3y%d14kbj27Y{lTV4hYoC+Bo$03p8o<rY1e_yC>5QVniKM}H(^Dau?
z5#=#{C__3Z(Rj?5)<8164`t!Mk{^i@^d%UwXv=h$_y+S?Sz~)Z at I(};z62ByZ#iZF
zBt;;mBO9ltPLsx;V2b3S?9i<mS01qJVp*T3mQ at P>Mcm{jG5((;&?ycZ4bKxa&Oue!
zy~Q+~fgyP*XspLx5YUhx;J0w);h`DQbY(I#Zm)>QON+mY{yqQszG>dtkOxUz81}k7
zj4)(dJ@@u^&wVI`nvH)F>3wZ`XCGJGp7o&WV<|ppV~e41E;lWO&As#br8-@|r+a+q
z?iz0&K5>XC)92y0Tpc(%UYk2=Gxd5O{xc-(^$7bcO2C#MWbhN!VcXMJn}*6_?KdP|
zn+ieoI%uE;0yHemy$_uO_AQLdaR-!tFB!bqTRaYyY9S!x72UD?BPTUvWhAaW8}SLN
zh0OTt at VxG9^5n6o{Na|XqakwOKNOWuGXxa58y`!4<^C6g0 at j4Hz^<yyuBwtNem7bs
z5GC-*OpN4xJ-gm)F<MLadcVM?7>XO-cbb$xqVeIw$ptIM3i>OR5dU-kGPgHpyswwc
zgy+d~?FQNTyeOFf+MJa*ZyCvqV|?Eb0f+4O6VtUl&zLzhfCUG-ED*F`GH6g;Hp09*
zPOD^`CC4p?72GEyLMzOy0+Jt(iOv{DhN)`dffDO0gDXgh;7reu;>B>s?qAnDXO$<A
znd(R#vR0)?7NLf~y<~IGc2=yH!jR$<sum|)I~)x__3joT&_$^m6eqwE2lcIHL#ePW
zxx9Of7XP_0FD|N-kzfEIbGA=Cd%7tFdNSj4vpaFJF=6a7U`$`PllD!61xn5W3DO;<
zjKCZZrW7D8sm7BW=k?2qphZ>GX!0mrIVB0k8Kv@@pwOqS at 3R8yAr(c!(m=eD4viJ2
zoz$2F06I<I++Lr-Yeq<4I%<#+km^|#O6e=R2LE~=hGn;RtlTPtluT8s--N*2ry7Sg
z`UNxsca@^4sH8+3TX*6vW|1Gc#^C=k&wdr_(P=!Z$2<`UK^Ah8T;Yt5FGgAcM<e;;
z*#=y$7%wvHG7|Px5EYL65&)#Ri+B+&y1hM*9+aF9_*+kcwSn5jDUg8RHv3mmF8MV5
zu<)leXn`yef?gycUXyImN_rde?CU?rJ|{_F+C2F9uD**K at DwN;%^ezzq at si!C7Xf$
z4gUM#ZR35nC%?>GGoC7_X-n?fGlIf6z~roV@|D@(Bx4Z(6W#hO1|`X|u0P1M-_zb9
z$s8Bv9eh*tQ({E#A(4f|v&(1w`z;d%|Afx&bX`EMbgS)7B;b+Ty}sWkA&ONz^&QBp
z<j*-MOXfm=0+9=KDU5wXGL$i_wv?R>Us0S_GHglMG_ndGKkLoaednUXu9UY}h!Ho!
zkCy8-vvC3UQO}3Q=jRRf8QxDYMYm|9?cg{{-)s at vL3kV%HW}+N3aIdD%0INOYHq1|
zFj45--PnBs_pvjS+V{1dUj9%gR_8hPI!hw2kMkCK`u=g+sIfbKt+Y%&iW<Jcue;B6
z%d>ID(R}B*p20D2)c(}Z1AUpK1lOl*<5=VBtG?J_IT1vg;M>|m`1QRTo6*_hz%H<1
zo8Iwc?JFH=5M`2|NesMYTj-u+aPhRuot)`)@nR?HazRt5afmP|WaM4&Xymoot?WK0
z`{c`gwek|N`Zs-vbTQ9u>b&2|cd4h;P_CqcRU5p2wRsccS7bbttHW#Ulj2+V2CBiC
zs*|Pby;tQWEAyFCeA<qq7epKupG4gUQ?f)zq(M`HJmn5!RpJA;n-R%;JA+|9%(ge0
zPLt6*+c?G2P-U*M$Xs-Pmh3{kE$krtR7dt<89`{kqL1dCy#3I_n!~_`;;_jKlT{Ee
zhsALMzYa|VRTPyi(wRKmKX=0Og4+>;2WwJ8hC3_Oh3`DRkQf{HOO2o at mWhB%+QWW6
z-ew7Yx8A&AsWpTx&gKWF at 9hU{U*nQPj=jA;>Nfs at gP_Fbe*rQ^$x)gw$L`lnv6vdf
z!2~1Ex-g;{5}^*P9JAF1M6~35HlvsHerX&&v3%RVYx<>^3_4+cU{6Cg(Fx7$ibyI7
zD2s4whm3nR at w7JTWKLC=cFXM@&^Kx6=3Ro{IUAKvfv6$jsKs(&i5l$TNRh~5;HPbc
z^%1GIy|;Yy5yAwrCuk at iF1PE*{~j-Jo}t)PejKMLb4%`{-ZDJ}1ab#^#1eRH?IF2c
ze|<MP$2QMWStBikT&J(=f55dYIQ}Ckqcb!{?MU<A{8m`IOn>_N5;=4`JeUD9)#;qa
zOYZk2#{*X66=k40n0LAnci+7GF;h-W1vA|5e0Wq|&fJ`d{lVG$N<%?6CMF#!eq^bP
z9g1c;|6y&jvp~Dbqud?BxvmxG{<8spBap)5377J5&RJZ at 3gXh`$!F1RJt&I~djsNp
zCVfw(^_!XTQsCbm<6s&GR8%*a0J90dtPFd{9t<B!!bw7_^DqKDBc3bT7Jm<(wp{xA
ze;c4<y}q8Z)Hp<eBoqCvpDcWr#iXbAuToL5Qvj?*wCi at FJ6{ROLo>mH;<6^3xzPi@
z$k}<eoMSkNbBv{`oWl-lFdusE1?J+$ywfAcD$DQu*8yo;O+rv}Tet%EopFb;eW+0F
zKyZ^l`;w)#Inq8vKB)jVkBc!*h@$n5mj>jWe||DHuePFO&0;fCyVtK9WJnLrZ(Ito
zZF(&D)agHkyGoMc6-mhNV?R*EM9!M<SAt}AszPu<p;VO1smn&PVHC at Bx`gcs2eCm-
z5Gr5kyZWB<@WGl;O%8X>?zsBYHf5+p?;Q8?1n_G(P7nQ<cRAnJ0Xuomscs&Njkg=v
zKEzj-drL3pmCVk0g{bJ7Hm(I{ejB at H%F{@emG)KRyP at 5fH|1YD5znAOvxUyJmsJNg
z<|$A9RdVE)(^tMzAt~&PDNhM*zjTmGRxHgig~yVBS>;;5!YKXuMYIYY$o$M=Al>TY
ztw~9Ue}8hJ;5V%DyY67*Mo*MLDbZh+TA7zu;~4X*)dTO2kX|oV+zf2}qe(`J0 at CWT
zi$Tny!HeA--_7nfB$E^SN%3%4KLL2CN5yfqk9E%ztDk2n*v&BVQ<u?Q(q0sPICPdd
zdr&c{>Pt`7;Ytdx>M)J593$yGcBDc at ZrxjFMaMCYqw22{m#$!JI|We2g|DAV6B(Sg
zC;lptcx9Tg%!)V&6bj6cLS#m0ykU at 15Q%l~W6)s3Y8%kqNw8NxJ2<y?2GaG^KS-_l
z(P}?@RNbwvTUzcp{BYww4s|*zU#|}-Qcy+wc9Q|$Ydf7w|G5(SJZ)F&z*JhRFLg(?
zMU|1nF+sCkrzXjm@|$RyjQrB<;B}<!G^tt_g&GD#0DV(*s+&*Q_3XFIPd$((QbwTU
z7%4Jc9>D#V8K0=&C~?}VXOzP~mr^D&jV)hz)J*d7$?}Uv{-8|f_r~;0=)bhDJ>{!^
zg~C_|awE>8Sun{JwY&ts5Ll$3WEE7b6Y=sW#yj-dKKlIUb)5~^3VGo<lWppVPV#3^
z3c?rhs3E%2ER>l8Hfo?u0f~2%Gu56hhaiT<nTlLf97Y4^Z^*_ioq at oIm4OqB1ySVk
z>vRC|l3!nZ!Z!F99#a4PM^9~kWAb5rAsL!H+hzgGpI~x;95-#rAvtj69T+B~8riEn
z>RO{BZjjE#dB8dHbi+}x;Zmk@^_B?RI;ku#orR2iU)8_QI1<^}LX~kAGR;aDk;<Am
z^47i*vBEXBoyzRK#j?Rr%Ktl9p}fC=kOyUUvO-s9dkp^-`MNG`lGJ1DUCB&3uXw%X
zd0VnugMf%%U}u79J81u2_JB7e6Bi4CjP9cW^8ATU4njrbB!pdkSWKX3nMp6&`(Yq!
zl}VGZ>Sy-#mo4R6*bQ4qRZp&sUeqT+Q`DP(H>~+LtSeh5)j#+42Rk;`+KmF<hs^Y~
zQMbdtI(q6Z8Q&q2n#rn|V7V7j_vm(XkkS#TPb}%F4{)%>uzyjP&aa4-NS5d*uvApS
z!TdeEd5F)FS}ypAn|APzUk{`?CfUbzPCA{q{RqBA3hX)1QSEXgE0-S~*IPEeARKyW
zPoAD~uIz7*L at Z!f=vCsKFkhL)nnRvLb)97WUh7<A#YP5pC8}R=xp$*+a9-88=6*9J
zMk?J!b(+nryx1VQe&%0xbqG7emt@}9PKRgH(^g9w%YzLZ*aR*ODL!K<No>Fu;}xLZ
z&Droqn)0wy=x=UxSIz>$>R+BY at ++u-IwA!C!3(8X1zdLk1+|crI1Sm3*DFd3ZV<Vd
zNEjOr<zJGHe7S@`{hc*v2!d-!c0o=jX1wD(87p7J6lrY}AxTo3>>bszuAj*y1;y3I
zq{jlV^pm+I8y4y=+X4K4;<w&BqVdxc!}<32r42ozNo+vLRCN#B*O`5HQ2d4PauFO9
zQz$OnwvME8|1|JFc5)kNji(+%V3iSR2zwbCB7UhXL2z(d-*$0*J1JPKt(ARE1}|;7
zB+QQT6I$}_SiG~#k~z0co!uh7=b9Or87F}I1IV7;+JiB9zQD^KaU#G^=SeS(-G)@%
zuLv-6HyVTTH8J_I<e=W(?45XAY at VbkB58_hjY6<&1E`y|h%;d7{<sYS_E3}d_Fp<`
zq4pu~(TPe^2n}v$YNQNetjl?)5%DiV0~HQDS|U!1x6a5_v6QfZwHTdh`{olXwN!2{
zU+efDAq|Y72#^&D10ZY%A7#<hweYaWleU;+tYJ352q`9cfS^$5S1Ch;%^y~RB|Y at r
zu;qGJAvD6K)D<0xbYn&oK@~x2FZt{iwB2G=6|EWt9XsC5V=e+S)z$JTQ^E#ARYwx;
z9=ku8q|UoyG5P3gG&6Sm at LtO9{F#q at gCD5OsiVK9jUaW(((D|J66CmUa?cC^WQz{W
zg`;3!i2}6}r33ExJ){mhyf9U!y7^2!usy90jLe=KjGCkgcIfL|BnIR1Qc$zFn3l|@
z0ETxxiuREpy%NKRr~>+G){uze34*Ft*{iwGyc{pM<PsV;z`=chr(+cKYq54U5=5F$
z<;PoGqz&z;$;Q^5g|`X3z(j<gTWUpoXNfrNGU#BCD?+qSp_0}b6~rbouw2<$zHqu+
z0$M2HZiG6y4$B<x9`!(#e_M8{GAJLJ+$~zNq(*z0jF+c7m%|c~Q>lm4LB$gpR58rH
zN>=_C9w^?;6{C#_r;3}TBABdUX~ZND9?Hr5%JbC?zr2O<y}xg~vU_c6qHs_BfcC}@
zlk`f2R<3?~W{iE%aWnkIHG=u7QBWmWmY~twovb;NMm+xL0{`&zi9+xD=b;=?k(Eu8
z%yn&u>z5Fy08VTQ_p?vGGY|j9{nl@=B+O`RI{eGn5<`+cNb=<sWb)4qvJ*Ulvj`{x
z4^{#hj|Ck at po|0xI^Ha_q-CYjr#BM5vAMrN#k_T(2ERB5h38F?x%)0GoVgwR?m>-<
z%Wm7D{(YL98AiL-;+c5oh#!159~Kq4J_X(x(HAC4$!U11jaJnwMr9l)%H at uVrNccp
zQ~cqCbUIGg6_|@2r|b(g<R~=bxsmSDMtJZyp~}=Cpts?mCTuTiz_2#9zjc at I-7l%j
zO`vp4 at S6+q2~9aq1wI9trb8%D)WSFzE}ljjofZQxR5YSELKT at a!4QH1BgGmI7Y&+h
zww~eFd@@!D1V~tM9usV6cBlz1866sOpN26xPa2AfN|g*6B0w@(G8ir;B2DPP5FL&J
zE+sO6nJSneUJXul2yDn73v0HF4N_J}67YwDU=jmfI)(%qNpc=um>gp$A8o!su^ua*
zMbTe0d at 6))94y&CSQ1_uQbaNsqd-=#+M74pQ-U3PB)^xc+bSP5B7 at BZLA~%x^q9yA
z<t5=->@~gFUgDO9Pz}T`Usv?ri^=Ny;d4=~+s435idony&irPk(satfU_ at 1nsiJWz
za^9ZlE*CIg?g^)2zisuiZ&_FvJ(CAS|Fp at ed3<#5P43jhV%3LXcWHc&7kcWyi}Ji|
z;{o_?-JBAw3lK$9i3+||s15U*npU`3kWqN(J+URKx%zn6c()7`iUXuQ?-0#+ojr8e
zbFX)c#j;p`(A$T$iVNp$GA3mUasGyR&dG?cRrWW}i5Q>^8}*^g_Z4Ag3ko=^GYM5`
z#tOh&RFZYz6t=#a$=y#8R&_%fba}1hSLn{n>yb2b)(CU*f<m%#H+o!x%sckrS|&dT
z<^0RT)PN^=eX^E+!p(n5cH at PB2qj`Cr2bJmPaW0vF8YA`<_mdAFAfR`jrO4yym+Mk
zm$VV}sGU<R$;D(aO58##2}sr-Oj$J3(||$ai`*+TAcZ84%l@<H*N~rv7q+*T$bRY$
z-cvui+rPe6e&~Q|Dd0Jj{{~;Wvs3USm>_`U!$+-n?CjE%VE(LVx4WI$fdp|SiHl-!
z-wjG25xm+;b3sGi)<p|Q*VG*FpQP1HP!&-L#Rgyb6~nJfn`OTojyO0;H^lLM!VP{d
zMhYtx#|RtYS`OIGo!wgFnWK6;srqQ)K@`2YWJX?BHF@@7G%|^rZ+_Xh?(b{pqm_&x
zjep|f>i4zP=KEGRtIc-4eSfD{a3*>oG^2iKm^+vafmGR4t*|~)l!*9<BN5DFFS<6=
zdmssv#&I|Snv+a+6mDEu>K+Dr$LRUns#~CcX7M)CC~U$i{xskxT5k%b;E!G4Q;_;S
z`Ma(8 at ap6RkE)*&4|Sfn|E+P0=t at sq6CFwmMTn8FQRa9SKo@p|<0pCnRg69YP}P8z
z$n(NzT)MozlP4M)6ccRw2KrQO3sYA3xB<t|3^MT=QvC|N*k8};5r+Ws)el-ws(JlX
z=p0h%?!+`{!?ybpeyv4UjJ~-7LdLVEu(hgeZVzjGWbthF#(VEMVXjsS$WS?#8uo-A
zzk8kx%V?ti0w&pO&}60g0*!eKPi!a16>Oib-cJ8B`w^S=&(N<2ZcgU{phT~iiV}uB
z>5l!k5t{D;=+VdVzUh(cDf~<csf{T{Jf#ctL`GAq6nv at u<a~x>|I-m)W%>dXPmJ11
zoyII|MjDCV9Kn at +k-~_lF$@wr&x$smJA7T!g~+&$`GJa(9dD!nzI`5!`q7}+L5`Os
z_E0{f+QzCoKz!Sg+R8rU0<yr`#>S`>X1X2A;biKx#4T9sv4+Mzg^Mh)3{eGx<2MAQ
zGJ=h1?Z&(k3<>Ui=}q1&eVR&sNLspwXViq*-#KrRsdulO7zXnENR#WZ&2;zj*&hJe
zXk05YAdpm>{R(NrF#$;+s5~(lFcY?~6F%~~MFlU=oS{Ioi^NN4kd?pUBKg<$c)h|z
z&|}0nL#Lu%jk0)Z^Y3-oI_$=Ds`ARzA<JVMBm*|Yl^RwZ8ZX}g9BFX*u``37lNSHE
zHMIp)OpDAg`?(!Q>AGJ?<m}RgH}037G_f=1>bx*lclCaFeKDhf8z#>W;v@@$wT=8g
z<F0tJh`5UG6b*r;5P3_*|13Lpn=IYsL;Yt~dqvTXWRVy59SHo{NTFf$!SlngRl+eR
zU0zQMuVt|t?$;96KH^@Jl8k!c?|K>HuGk|WlI&FXtaECPbVpq}X4g!|m#0<}$T18s
z5-B8TV1>mJR{4yA at 7B98%mR?q3IyzsdKdd at ceJZj3TThame}6}AE#ISy284`6b!xI
zf30h+H(}fSN+>STKak&o+=~|A at U*A4dG957WCPB}oGhUei}UPzmKiSFVZXu>oH0 at H
zkY+grOjRjP1P`Ce!jK63e(Uz}6?~g9EpGmJkN|~*H1((dF)87!Z8{^op=~$I@^E_a
z)p&|gnS!fAcfDY7yT9^o=-HTx(RL~}2th9i3-P-hRK+L>D{`Ag&hmP3QwBbQ>xP6l
zT3}4oN=&Cz=kBqtTQEmJR64H%&Yhq}f_~&jmqJH%dRQq?V^^ZH!?QjQZVSwf^|tiJ
zJre&7LtXV`++K{%`gk=>%f)!{%+|D|adq}{2ho4FN$HQmELzqB*Tk5eIzGVN4<qD8
z3UYp?iy&-@(WEne^1hsF?mxX84G=wOjQ$zir1XE$)t8}Bs>|^OE=(W3ZGYSktBykT
z<{|};U*yZCfb)gLTt5h(hvel3LCzIqRQwWEKxr&2UMheapgzAp_8O%55Rn>uBfb*w
zxPF<FzcBb4(pkG@$_yeuj*K?37K6&07WEIeSS$}hd6vf>D8cPYKlHRfs-H9dx at rCN
zvgujmk2QL>E at TRSHxb&;pWlD{976Z*nwztF`{JyA<8ZmStOKl24uwgto!2aw3H89;
z20gIMpX!PXQ>ARZI~Pcv&y%aq<)s-~qE~E|H%s>W=RX49(z`uprmc+FW3LMl5&3}T
z-gF!*x$FK($V9I4L7n`!qyK!{y_<P at u8FizgMLn;Baf)$Yx!AJTyOWzJuP&dWG^$}
ztdc+*eaHSL%*>C~(p}4i>2Hq%$jj1(#(3 at 7j273k28oC@_3$~?j2kcE7oF*@NgJ!y
z%JHu~4mh3RuM~e`)|JI4m7rG#`#u=62W5~9Q{Q8hT_-9R43ogRORx^^YHh|D1gx?c
zRJC*=rfg-t<Gb0}+^5#fV=m#BSvaD1QY&Cr@*2II&SoIA&y&AXPWoWgvgY}t8KkJ_
zJT_6jm4%gn{-9L`QQJiWO9s!(VDD?^6>`j*zabrZTM66BgVI+wp0gU*ChF&A*%kKT
z#L<E&^b1HrdwP6`xK>Ixf0cUAoX_2rZze^FQWZBV$KB=o#NQ<0<e(NbwzTeGThLN1
zpt0~D44g_wPe`22E&Q8>4G~RX6LxfUOLAypu$&M98;>7Mb#<M^n|hSSL0(w<OG~qB
zzzHRd4yVm+QId^OV=q><dU`Z1j;kSdC|(~cgu~G+{3r#p=X7NpiS3SM%nm)jg0qGj
zgfw;MA05WgO4S^R3RTfmKj}TeDsFV<b8+hvz2=13R$w&o!Y?IqwR1jVbGP%`*6BE|
zJg`H}!9AErvHwvTorFVjQEq%d$zt!%am`|`N3GeeJT-mgWZ#~S5W}0a(X&s)4?!c5
zUe`dvn{m824fjpr=e+Ctd9}E%f5v~KD3#zX;~&xxSW-)ku++6vqm42LaFqx at JhCHK
z9xET7EiC9lqTr7FZx&b3QU^%kEW<Jz#HJujA=o>BW^8O|nB;ThYJZnblP+1gXO4e0
z1Wo!BAuY_EU^JSg$V0N3wOJ1+^W!e6gb+vR2<A6OmhU7$qu})AXGO7771T?-dN^&U
z2Wg%jg_)_eTYcha=5f*{(UfFmgetm`{|q`mqA6gdxpS$uklv_hucO9OCy7Cw+fbTH
z5gjiXj$B>YXd#-yX5VL=IXIhkL!h<ks`NcrZyq3wM^~{vC3({GT&|q4W1niZ{pD*`
zPBUQ at S82|1@%g(9QsQEDO=EQek>^Rx%afjh7&B=_8SdFGA`jErw0Aw62O{pAtSra$
z7h{RkuGPgr6!~|daKMne$=d)+5mQx?v>f{S&Te1Bft7&L_8-(+oM at 6OQI$mj)s?x!
zC(q$Et%*2FJ_e2PUwJBFmrurHFIUD%4Ef^l#)T!y*a%i5K{I`As1I<RvN0i&U2e4L
z!&2i7^9xs%Eb6W-j0p*kSR-*ZA?Wz|cV`NeFxJ6BTVM;UkGV5vZ{46(Z==I!cZFlr
z4(9yg2Z at VU$(&J;&7-cEQtDHI`osqxaZyzczrw>LB>q*`erRcyUH7RaYfam4Tx-j|
zg(qM*w+3?SJw2uVx_!t{II)zgQVO$6fzY4u0><Yx&QUQe3-|MnTrL4fBAkUEnQ)n)
ziskw?%w9P>UCUCt-S+erDb<+Ai%CtoA45AlPYM7dUB?`cbsg($>v|)fXWtnaBc4$U
zQ`Je?hK}0%*}G92cHa(n@#+rBzcc2mm!Ql;2nJRcv_t8lz|VHwnr&@Mn|J-WsvJAD
z3_4P{RB6hT7H7 at MP}jW|RU5C8LPwD3T&wB)SV+5QK9UMRJCT-&OS2?$M>vp?E&~WR
zt1fT!=dzN>4WC+6$?)d at iiU=s-;u$eMzBn(mbH}#2WDQ8$d0zevLes;H}v+2+vGXl
z%^&Q{3Y==c!lR2gMAB at dqFXUE)*!h6v$gx1oN%bV4np|}LciH>fPfP}J0o<5UGiQ@
znVX|rJ7pn{k~fDT?&PpaJEI$1`3Igr7wFJ{3yr3Falzn-8K8V{4#7zmHClO|M)P2u
zO2ADH?jegTg*bRK-7s2 at P&}tGL4P45j%_H}N|`!h-liH0(xfoKpF6>Hg0bVCAuW3Z
zX$U&=GFdCNsBG;9ml#E@)*tjL;q_v`r0}+`GNfqDUqY2~(WFTg_rG${LfiPRRJ*H!
z*UUOX*_V7?ML4RZgkMCNZ1F*(0HZ985N~X_{umtQG<Mnna97}Rg8rX}5z3N72y$RP
zHiS{EjZJbk96emAs+HouP|}V_Tw$_gV0)DFGZ2LpNrX=0-^oHgnxYyFP6-LKg;G;Q
ziZstpyG6 at Th%)hg%Z^8M4TfpB`E%B<!-Iq={vuOs6|0|4xOxCsu=iJ+5#1MGN^=|1
zJ5`-`g}zK`wKdzmdpkSuD*_2dTaoy+agAiQjKe3w7}663t)}R?b{u4R7pR0LQ%0|r
z-(zYF6E2K^#ianFDy(M}U@|3?4(;$#cvU7PB(o664#(SdZt=hWL*_U%FpZSVNwE(5
zGx`?U;p2gM^^&ci-q0#bataHP6}q31Ml8nWn8~3KO={)`F at BIwJh7WZaYeQo=kp8j
zA_-mWGN at GJ!!Mp8gA*Eid}~wrb!bi~UB1Xc7h?(B7mIi>;2E3(B=-J-6zB+nb!mo#
zq=Fy~K{x+CeO3c- at c2GXa}r+Iw;;=vdKQf<Syp{$qg!*U<hgJud=J`k@<dK8oC3IT
z8+Kdlu5=?4gyLdgxLkqV#>Ct+Dh{xKg7#lN;tLi=9eWLA$3f!`79$`UUy_o<cy<TM
z2D#m&+RD|I&8Uo<L-8lrDvy<m>Bn>|ek=I618Fe^vN0K5!f;zEV+chDjghAY8%Mw}
z?n)aCauU)2uRN at f<AL~W+vYFqz<@<Y9wm9G_#<oQ{2_DXL$@F~f}iSA3z|iiY1T1X
zF&y`$$dZPAZNLK3aV%)_vF<@Xxs<bJppw7sI!>J;R02;-^UbLf$8j9o?x+GlK09OV
zVB=;Y{M=c?L5!V2 at H`u19i$kWEQOlE)N9Goj60Pzo!iI_F*Uc1x&SlMDcnZN%ICl7
z%=XWR%E(}R#jRgR!<Tx->nr2!%5lIM#db!bCwt#aE{RJGuq+G%?RCTb<7YFpnz5*5
zZQ`EP9UN at _SbGT1A-&@>ACa28#{1^+iSA!7WL|RfR6P8$v4q9VpQs#ZD+i_%_=cLL
zp0P!;4KAmBYW=UK@=DHXY3kcitW`nytV^xg=OES0vPwjyBzl#Mrw`QOAQ92Ln-uN%
z8Gm&*=a&=9%Xq_1W`x^$d-=NbzzWc8#m~RjdF&#}l=9@;6=j-*;zET&x|En4d}jvw
zd&}cOc)>4&8G$)eVnUL-YP?d|bWK?1$(cV!#H38*yB?TJ<=+vTtP7S?06_hDQhH`0
ztrNx-I at y<G=0>e_ at C$~}HQ~-E$NeAqLp{~aW^#6aHs#)(g)g6ME7*6{QRksN?sifR
zeN^sx-da>{Y9^$)8&3u+#eg07Vrjds3kZ}}*EJK?OAJ^KgUMDY#T>%iL|ZykHzq5)
z7uWahIj(`vIp#=XsJlS(w{LC%rjcH=y|^Om9iDJLVrZ9-#)GiAt|QwXccYS;>aV_5
zhTo at OlEh4}#ka@)+^n5LS7{<!3KTjw?Kun%z_8+B1L*$diaFu!+{(^(pI-`)FCR&{
z_ioRw)CKhl5SGT{wVMI*CLA?D{-==n28N?EREIiyhjE#>l-%?86xII&K6=s>6%{qP
z|Ne{ri&u87ii#zxQu&mT=8;MrhiZpWIjd4^t<zz30xKPLx!ZtOK1$Ii1)X2Cl<m8F
zZmL8&iEd)*OG|a2pFIn at U2_~uQlyFj2mmVshZdZo*?h7+tli+1hb6SQXNg^fk>_+C
z8+wMHXA9UnkKWQ1R|~a}t^gxo!NoMY(tvrystir=R|ume8!XgRZ(;g%w}PIu3CvQB
zHcH*sXVy%VrmfICM<rX6+sKvzN;#Pp{(mPG(<eJ}ceKGWTh!3Va^&amx&)7^kPmb7
zMp&gbhV6SVVtd(}LD=<JBypQ2Li90cbYI+bY;&~juskyhz>;2=A17XP^w*a00dO)w
z@>%~zc2P at ptnJpaW1&ekgs*LCFYNQa1j#PPn9W=fT;dGyfea`-YHP7dow^tiG|JG1
zFd`s^2>L1uBxRPQT2X$YNCbGI>{+)?ZBiW1Ex_#F>Ea%f_4=RujH4Sf@(Bska$lNm
z&x^Btn_ at NNW}-&lEk`lk=!YD%X(V|<L9=7i55nx?j at WlULiisJgO{TUGzE*CC(-&C
za0O^F9f>rbI-0fMcDet^E|ZNk`KPEQbef$L7Zg3 at TAnJJ=Uf}qeI6ucPD0QdX)vuc
z-aZygTNDcsVAxUqo(`Z#>9zr1HYn3=a&$o{I1;-D8zut<fmr~$)#Mx8x}s}xCHa_Z
z3pzYxZ7dMm>(R?6Yy^oz7`I$APD=D~Y^O&D*AcuT3n#UyaQ=3+g=#i0X;IZ)r%2oc
zm`&<vo@{J8^m>!Qj8FDDs@%uPf7%N5A>PdlA at a%f;ms!z3)QxWBydHh78ThEoit&5
z1wCdpBa6QQqfYZdd*CYJicw|&&m`v0>~?K!ho>=lM^g9i1v>aVz&$di`RZTasf?~4
zh33MrZM}O>X99S_-2ls$jo%1*6znGr&ik@($=p>)YM!^O12F9gwVf_ez^MwvEg{`b
z;9Q9E3By2bzI65+Y04ILen+|DP)SjD8ql8CyrF%@n7u*_hm?L8<?nCY&={-8iuE~5
zCw&(WXZHQGENSOD&IAPe2E-;crXS*yPZpn-!Cuy6MED(SpLT6pk_M}lz=dd~ic6UK
zxo!+yG+`)GI?B|;A-T^?yJI%!!m|ktpHX_kRvv*VGBVCtlUwS2o~p*!Lyv#`zwmx&
zV1+ZHk*EWkl;&s^jc4}p8Xz0gKK%{|SbM(R at UifIpDyk2Ur^P1A&U%;U{571E*NOd
z(~?Wk^qr(5Gm<{>T)3H<rZOB0;T^4R>Sz}h>?+sCQa$_{r?jP?nt(<!?>MncEDM#d
z9{H$Tb at g$3af&1`=%(Pnrp+gZHo!JOAcIDeV*he7$oX!+_m1WC)p}?#4XIk0{0+ED
zYI^F++39eIwM2#e#~LD{1d(P at KngJ)8%>;c)Sp1t`^SKR?A@@Q!w#iQKa%~+=DDYN
zJ9OZ^4Dqxy*!kl#oy at 812WhTk?!E1})-bg^dO%huhsRe2bgy1xxSQ8CO@{Noh!dF#
z^d50vFDdb=+j25-f=}5X!dv8<>F#f_ewQ_ci(!LE;<~8~kKB=cj~+5n=hPE)a~Ut|
zGAXV>j5?VGx1-%|d#=#aPGPeJ3H2cbRa%40C`O*_rfaAYBjkT(NA-qu1Y#Di3o)^y
zzyjhJ6M1ig2WdzRc5f%H^Bg9;_|%e;h2B$lfq}2omDm8UM%8oq?EyX{${y|TO;!1-
zHAN{)D&CjA2kg^^GPZV97;6%3UTtnrigM7lVB^IWA+q2W`%P$USaz0=v0chd4LT7b
zPd?bgr2~J$=Ae7`BFZUJdbgK(pwNZs?nXhGPge7&9OFb!fl{1<d_;ob>0qo*DPgV}
z+rp2Brg0<*)%QmxuCXPjipImSf6S=#%`zsbKQwGm7xlHY<SkKuHnYJEHTl7h&N(CV
z5;M`eJ)2uaI3!)KTb5Y!lk+l==p2O)OtkB$R+JXuhJ!Aa=|8qsxrWz}OxnhNb81<>
zy|*0c&eZ$9-sV<lX&HFXUC#ebD(DXuKbA5K{GlYlj0gj0|9mP)PrTR^dz+^xgPg+(
zMk*{)46X-_<{oH88)L1m=#g#i at f-C*TWjv(*-sB9FJ4>Du#0kQ6c>x<$_iY_T3k(h
zE{fL^pDtx<xfob$rZ9=%CdT$-GUVn-42IEJp$eK<d$n#Q;Hreb)@cs!gjEh;oxv}h
z|MvGLkwD{gW>ueGhb$WtC3}fC>5KOm4>%LqAkU+zkkArrp!t6Qd_aT0dc~}kIR9_g
zp}t_5LNJLO))iG_0T5t){ye{b?)<lj{z20NAGZDfvtPsO1NLBk at 7Nn7Xn;WzH>ueR
zcgSF?uk+<?AFp|?uxzI(ut5Af-hVNT<xvf0o>rczSqpU8OpoL-<>CBVO|M7q(H}!{
z%v!htitS)r;F`o$$M~49#g_nGJww8jxZZkzd`K8KKgz;B_<L9P5)wjxn*88A?NJdV
zRi3R^={c+S1J+6UzE)H1zv1Qc8trX0{Sw%1XN3{4U+-c))ZnGHy|{<-iYzLQDSDsR
zCVp&75diuOEP%?z95dNfR_LtP816D3>-bglAGRE2 at 8|&j-3sObm}SqO`se4*GsMh)
zA*F%(v~TJH9&?Q`c at B2c>l@*l!{hw(`y{*#mZSS~k7Z}<{LiKLikYEs9kXn<5`M?V
zwvYFn)NaI`N9%63ZDq4-EI!JtD*E(6@%p|R-zqY^{?oQJNwKF#p4hcMNz=3WO_0uz
zx|uU1-Py1%?%{oZr^AXIk_k#!sHK)(i&PX)ZI*_Zb~Gv2snKxGi6cqLkmF=I2=j<+
zLBb8g0W+E9#zT?>O%$BB`LLh1l7^*-VjWV3lR-|E(CwIz(Nz^8loF9CA^@!@P|)dC
zl8P0jbfK*QpmemUsz#Be(guMNga(CZQXvqfKq5^vg(y`b(v2$VXcs1es#*%6sGz1M
zs-h~AshB9DsVFKyvbHf6kTGqIDTqsAl+ZLgWyMRS7?LE33P^^8iE$!Cu_8vpttAeS
z)WQTpL=MJEN=cA0vN{!{Es)S+7L!70LWY1MN&+CE3LR)E4YC_;vJ^x_u7os{6i}2A
z0TB{YLPRAR1VdGcbi~A~5o;P<38e~Bfzzrs*pqBJ(geWLYBmUhlT?8afu%|Ul98iD
zvL at Jez!WJ(B{Y<jZGt0gQ$ayNLu>|+&~1{m15Hxs(o#^G64-Pm*<B3*NkYVwQc{IF
z0mPa{hKEj_1EHkY+8rj5+W|s5WQe5O2-0Z{D at zbMRL~Te*rQ7jP#R4mY>h+)v<(fi
zXk8AJr2?pEXc&|V1=FAihJmCAl7~tgWzgsthLYJesvQp1Vc5Z=5EPV at 1uCTi6a@x^
zwh}5<lSzpTOQb0&D4@`3C<v04fTY;Twi-%lh-g|;f|S;fT_zx)+YJQ)pr8sugfu%e
zM$p8WjKN4yP-z at OVn`&?8XY7`Qc%z|=?$_bf`e?j3uGD_WuTzMl#YcgV4)}-I;1ID
zM?e}hrLa&mi=on#J7n85g&<JVm_tL05DP+-(y2pDD$tQDq0&&=GL+jRq+%LFPKLDG
zB^9EU*($V-EmdeplMxn^Y&4oQ2Cb;2+c?<J+Z%1NM3W>)XrQr^66-^)0gG+63JMbt
zn1s?*QA0zBaRElPqeWQBMQxIVf?bTbhe3%nl)3{>gfxW(qb}PO6u5$&uuxL%gsnPK
zB(=8M7A3*{y?~^V8<_yiXwg#$M1biGK}!&Z3}K3JNr4)qDNK;+B|@boh(d!yf&vH)
zjIculp+y4{q(c-!5i<iwM6E$mNwb+qpa}|yk{ThH#iW5L3kn7OODXwddv6Dg<@xc%
z<!}CmL+(U&&<?k%x<VvF??GY$2uTD$#86TR6iU4kyg!Z{L=i|#B at Iy%R8Qx|rUH~9
zDhddxB4TK&YJwtwk|vq8mM?;SAKu?@i2px;9Y^K-|FuiYK0hbx<5!ahJtWtk<LLC%
zh5Ke8*2y4dQTcq`*YEm%ffsjw$tEB`ae(^%v^t$oc&O!=<iwg9{Z>_CimIw?_a5Kp
z?Qq|_4E=h{v+Us1G>}XXMMP$)h5e at xZgGis;4^~Q8Q<als;l9so0ubK|Bw2y>|_TK
zkiY*iHY*w8bAF!&`8*!)xFdn9KI4RyRYDKj^u`4>HEb<xR>o9O-b9rXP=mJjlQt5R
z#*`my4eG;IrrCoZ{iB(Z>^}CYXvsP(Dg*uS*|boglY0A>foOqF?27i&v$r(K#9;bK
zLAI+)C6dx9?01|d8X6U*W?>>aW{!gse8t_(&Hn_d7jtVRkgBBH+KRGJ;YTQ%59WEj
zW+u?ROkrX at faMk=@j5L|`XV6VF><n)`Ci=#LKK4&RF28K5ak&|hXi~NL;vV>#VHg~
z4FnKDQbe%<5fl>)kP>y&oe?r07(P3!aZU0nb|H=YG$?*BLn*xt#|Q6&ybEf?2^53?
z-4jFq3)@!`k6|qvUyZFZJ8`$%MLf`B2qs!M%R`%Bav}M!>JuHwQO3m1^e$#a8l2-6
zdry!J7;cBP4-cpHWarmGV#N*#Z_K0~v0abbGBfRGjK~d0c#MyM#dIQTrm#bUGqa4|
zpI;IuM{jIHdmkdf{Zz!fi%Hp}HD{IgLsy5i%sp~OBuEi-)J}dtm($Q#Ovw7oJvBRB
zJ*^6mVf)Ay3k4Mb{RYA3N;Qd5Fk;1w5kvI<hs>@e)czebWG6n|I{H-_?_!UYK~)rB
zaM5~ZPd-$RSFvkF0 at p3Gaw&{lb8jUBSN(L`aK~!{vKaJJ(m=QMa4ng-QIA at 6A<|<g
zQR(}rJ3lmU8$io?sO~&VB at WX4U~?e<BNe9B8y*N6knt0&#|!jiE+^*OY$X9u3{t~i
zDHZfw%|j+SVpT at ZN2G2&8}3yYu~E%(v|=$Dmv?Q!5cm`v?X)o{si+AaLsU<tcgAd+
z`FYq%2I7Y!#-|YnxjTCOW#{Z=_~hZYSm2>6RrS27+xc(yQHB>4mJDjQHj-m at O;kg|
z1Y4}fpIr~AbJ+ekyI_9^%ypvC2_MNtLPK7*8$wQzGtaj>bc~*p)d)Vw%rN&~ns7wK
zgM{tnOd_%sBqFQ26R*1itJRqeIdb=Wy)Zj{5%=2tA4`5v_WZm$Z19Hv<CEh@(%+;g
zfAwuR>+n4MKSPRC`1~?5Mh1gP3 at p(&SF2yw!mAoz7HH>;qr(}|uH7_^zHE82sZ+WH
zUX33K*8(;ZS<a}g3RBO4j_$L&(dQ4R13}1dqueb<ZDyWx$BlLoqXXVBi!ES%{LJ1?
zx^{OnJUq`wRPv0E)$7rxZn|B=+Z;VU264b at TC3Zxozhwun|R{`DDNSk9nj{<W9nhs
z*ItIy+F{0y$rdqR255WR-ptIyNAXL|$IHOhJ&SA_dC)|&|07!X{9nIfJTvG|)Z?bk
zTnyWv at bbjf>Tjce`s;|tHxxL#dZ<PF`cQT-zK3)!!_g=sxEKc42zfCY9$v0z^S9%}
zpq9*jeu7cER^PDvT$Uw+n{p6%$`;26PKIc*VVJ?_g>a#jQ1|<G9)by+I{bNvtJpf%
zUR{he-Ih!H_pKVqXVImS{aO}=srnt0YKB_7^%VJ*$Wp!N^ri5TywpRKPiM!;@6Xy{
z`3HempWvK3H}YLPc3V7B>Rq4QJ|O#1El at U9Xq4={FQY-A;Zu>LoFBKljb4sJmHd4n
z>h&B&P%bP74nFM7x3$~Ce}KR7JGu%IqQf35%MQky9k+RTwFu(NpQt6bX+(^C=_+8>
z`*zR0BayK7`!dMpxGBEWu!6JA at A*!W&YvR;%|aU^5vS3^-#5A|Q6D5N_P;YN{%QFP
zxtZ7Sp_;qh+tmohK}hs=aH9XVaI&Iow8PIMvWkvu=!TM7U}p`VMi%x;gjPfJ`(6jn
zThK8}F8(i$nR^<o^Cs8D{wK`blxf=E9$uGbcXs+nRQ|xVQp}m=LDb789?S>725{q^
zi}wCgGwnZ0U|1bEnEl>`?bdU7b$n}!ZTj^XchzPNA0JT6cb4{@qhZ^XT>Ofz9_#%#
zQ;w~g3i~pZ30>%;j4kOZL048^y)tG)Hhp^`A5m%J&l{xkc8g)<;SxP`yr_g|>+c5U
zfz9mltechAWa0kqzovNB*nn?>;t=i69Dci3Xk_Eby at v9thMR(SbUQfkze9Jx=Ygsf
z>+cH at I;GA%wFgld(T$rAq~^fO<Tr0`N82xzzH=Lvh2(oIaw|g+fxxmpNS%!jOX}|J
zZ7)9KuD_$BKulyi$Ke>kh_KEMo)CCJlX)ZLi(b(B5xG2e>~K1FdGz*GrD3*@N2^9Q
zN5ikOju}Vks4}wuCRRY|1})TWm>+K!`a;4h7dQ0Gr)M@?^5Ny?l8Mg;ss+3n_9RR%
zqd^|djZ+NcO%3qTY^kpeoU5-7vprO*iY&ISsgQ${<3yTs<Xck9Zmz9bI<qf2?2>Va
z#u0<JgAPfZ*l+Ui>Eh>y!|;bUWo6#mVRi~k!|6EtN%=n`hZv7ZM_mx?hgQB+V-7D$
z2Fa!Ob!^y2p~EICZEIhBu|1ltAFbgM-*KibUX49>O8z_iDZnPKH at 16R#jJUq<Q?wG
zllC@<VOFh{%2KmSOtz{!&E_`cqU(!x?}wWSHw&nY>X!(`YkE1ny)6G{6}Z0d9PHH^
zbpP7C^&XlxYnKdd#*2LVep!F;+N|;1?QezSby9I?V=JK;<Fu5gqt9hmbXiWP>D!~r
zfZp2ZuvOsB&E at UG>5miLvd?~9G+$qB!dr?sR at QOX<JsdYx$3 at Jj<z9Ievd|*YdW9C
zn3C`1)!`mgIeQJeWt(>0vCV$JK5>}AAAWyDzt4?&HM3>Sz|0Sv{wJ at bvp82VqLWn=
zIg>oJRY$q9_mZn7W+V#SYAvxXI3#doE_ffur|Rg{rgYX{$2joUp9&k-9UR7^w;g+_
za&*gU6zgWtO0^{mi8D30g&g&iU%$d at OC0>}rZBtNCBphX4H>MOom6enjZE8JeU?yV
zw4PsI4vF?R(R!O;F~Q+;o^Q+niUF3DpoW=(NJ5YrB9LlX2<ihL%$YP2(hib@(MdGI
z=x`AP5~Tq{01~iDLlVUU4G>B}B}B<nAu&@45EDd@%_Ri at L?BaCQZWq7rm{$Fm?<a%
zBp8ZWnrfy3hLENb2 at R1n1prh{Op_A=Of-}w2{aNFMKsjIND~4{Bveww5iC?C1XU#o
zpb9XoNJK<TK<P2m84f^ZC{3^*I(VD_;SC8u6topVOCi*1V9<DnheN<8 at X8vdBq9Ky
zSsr>f2?RkN5U at G4iK<c;ZI(WmG=x4dIid%I3&<iwQ2gL{zy%*E0b4~KbN)x~{{Pcf
zuk-FdhJQu2`nDo%fgm9Kh7gf`_SbdQ*JZ3-eJ9ob3>UHn5(IgeU!I{_1ZkjYDO<+F
z_2j}a=`4&9 at RLiVbWk4O?Nw1w%1EdLiv03F1r&keq9`U76pAV7N9nSPQR)vju=H53
zMPV?}(9IB96jLmUR8Q7z1r*2vClX!-Ab)-`6txu|GH;U9RTKUB{`fdukPrv@!2VDK
z;{ZPhhRC0fzL5?$sRaonZeLlkdZGKbXLBD at dB0f)xRUZgRG4DJupFq-5fKmR3Q<1O
z#3_Ixe>l|;5gc+4 at hE}^5A8BYFtH|#1t6ip!v-n- at 6Y}kxNv{a841o%5(!m8w8LU;
zXn3Eb?>tIUm{OQgJkRV7O@<g80EQd~*+r@^#YiJdnEsm;7ty%$<m-N)y9x`bJYV$I
zK}#OWzVb(JWaSW|$hn4=#lP!3RM2D^XG7^nJIN`V3TSVL{5)W at -^_&WLm<RHVhXA!
zeU!lCj(ygWCu<sgG;h^FPt+f#=&0Mcx&I`w)-inpv5m&lw4k2K9hhwe4XlYZ{5I<T
znt6z6vF*1<&_O|K1BzZ$syh<1Kj>&4w=%A2MwJ9NE?`uJAhjokb2manpDgVqs?+6Z
zSC7XD8QHrM(^mbDZkF!5f1}()nQY5Dd^xiV!nSXWG`425NDP^<O9K43xe;#oRRvb)
z4^l(xgpH$WZl)%|sBIciHUv8$5PmFq$TXUhtEO69AWo|YGdBhzMAlHnq%1_ENbOpY
zNstYTtfOIWPz9+`8YGbGZth4b!1iiin`g(>P8jp`YV1oXD8<QGv$X3plwUCEgl?j?
z;Xpx=46U2q6LK at V%O%4biy|xAB;ozq`t!dfUd~RX<*p!|1B8YlMV>f<O%IRScl$lS
zevwMz$EuP)lzVEFE$(f6NjFjC=I+l)LsN7hA-Sr$@|&oPchuEhU3Sxqcyfdf>3eLi
zS=Dm<I8zFop?NM)Q02>B`FD18_4)ad<wKYooZ-^m0Y}3L(lsn(G;>yE3uC^?XqQeC
zC at jt}MrFc>P5x5y78!0-ci3fdW^a~zZvq7N%4BG54V^k6Oa};B7qGG}JFuOLZeO{Y
zJVKgtuC5V7cj=@HN~oadLEVvY5;TgFGa$@FSqhNvQ68PPw(#Z>OpskJYG6`>k}E$)
z at x8<M@{G)W;|Dgju3Rn~C03In5a&j-Mt>$}xJQNh-8(fYCH6 at LeaVZ(-7vYSOvXkd
zcSEL)%4?3l-_4}*?B**xtd{*KG|72mP)!p)zG9(NQ7E%|jh^}++sCK2nwLa~U;Q@}
z9LbZtPb79Exmd-veN#9f&}&3HJk`rn`gI+!^c~Tx4%S&)+{X5HD3xE>>O4qN|4*>@
zQ}O6ub<yo>Ia{B9%|0*EX^j%on`*c5(nivKkk8A<^pZ^MZ7+6aVl=HM8MXs0<BT}Q
zJp~a&LxuR|h~{+BkUYx^>OfVCR|}<1bocVRDvnx)s1GD>D>A2D8R1CIORS`Fc^MaR
zmd_uiq9EJfPR~cPJuPEur%NMGE}5<JR+=LqgO_XbS#&7RWO8dU_b6Nyg#%9Lje3pQ
zJ at 7fs;&TcQYg6Z04OovqCuUzhAF)CO(dl#By14v(KHk}F3{GLDpEA{);@X*KEu&d!
z)+1WDyrT0}mX^VKZ8gokL&dghQ#fg+&NF5oSjMMD8!oP<6w|Aktl(+EF^kkrb*IhM
zW~!S6|3(~}jbd`_RqduKA)@fo?=H4pVkFzO=Cy_&6xn>{HI_A(Y~h*psx;6uOqX*{
z17xhg+G at serkqsOnZ0K<4(`~kRJ_CH#)iGLF^yLDojg2co!)J$7_3W}yR1`AcUYLF
zF3naknP|ge8!d4*_|;uru|{)pV5+&+af!Q(<;qo0F!t}QPF=FlXHz-WGHW_APA;c9
z&Er*yi-)VMyU~Zyc!-JCr&X;~OI|2!;oDVK#<f_LI-jre3IpmTKU4~lB&YZ#e{6K3
zkmwR2BM6sN6#x7vA9xU7Fh6;P6u|#j5dwHY3?v3cJV`_7g>Zx*-3NLPLJtu|GQUC-
z#yJolwTKv^p%XMBskil*pFk+3&@zB at 2n0x?ksq)yJvLEri~2wd!2%uhdy)z0_E2EM
z`M$vWr at OFUj0!>eMD8#V<Odg+hph}jKTROx`O0^J>jorIU<{cuAZ<p&M$3 at gW=L!Y
z5Ikiy((qD&q4b%?&U0i+C1`vLXU+oqpTKE`UHkQc4985QGs6kThdO?+;zp7CjlY7x
z7{))EG7*W3mR-rx+uwu7ZOwwZng-zLFiw#|gtF*phK0B at s&=y7aswhOz_O*TZ^rg9
zsBQte#5h1&Qov|xfyIOji|T<wy$krm*ogLvN3iS_hlkDGbptGNfX>m}eWG#Y_H=pt
zgd~IbJpEp2B$Mm_2MYs?8rQSQ>nQRs?t5<n-!`}lqvzTtUC{&D!n7F$OfE*<795ES
zzl7<8QOnd2yp|$`bBh5$tpm2s^bttuJ=?opA{HqHG+1tsSYLDywXn8xB=59+N-0QW
zKF7Q4wf|W;tXBK{^4!1E8)IEo`{l2_x6|Z-<{F5-2cLvU$=Rjpf8i%Tq|CXWwxTBL
zA&-poStu`@Ab3(dY<KX)N4n80|EKm(f3C>G{+Q8UghLX_q0jMbNb-(eS(;iWsFUUR
zWA%6!YrW at xyhN+xDK$l*)#&N#fkhbcsEaOyJg)jC at h;&?Kf7&Yy(IGq750#WBp05V
z7<{1aElM$8KPpdzCjI}P^Y$WOXr`%VN at 9qKXkr=|pU|`vvoQoj(m<f9sHjB+QH_T6
zoLPS%y|@{%R8qSymF?S#VVWYQARb=6?=KUuiS18N=;&mPNsu0-H at 8;pGoGz7+4Ohe
z*X6t0Y1qMUUL!kianRU5R-QaC>89;7uLw%(<)c=ubkRnOU1nLK%h-fk<{-3HEg9+6
zqg|NcMyv4GMy)nik3-W|S23xA8fvLL8l6@|iYT at P(bW2?*Rvg3H5#qcuDW(=zUQMe
zTLpQ`T6i^@^~8!O*8<q<eRW^2Eqe8u?bEKhb?U!8)7*ti0R|#pwDa=iD(x|&_DZ$Q
zeux4(*&<*`CqA}9+Q5kTdJ)->e8xiFkm)Y^=9u_ at vObqrZe814l~Hp=xp#LqTY#OC
zb{94|{b{&hPDcdtd(p8(HXMtHZcJls%&oMHJ at 6)!$*?X}N{4r0yRc)wc|-S^DE%0b
zuJ5;v3+%F_<Ji%jOy3cqR3>DouvQc0NrP#&M;4AQ(&=WUY?b1~axkx(Y(@4P_~nf3
z<4tj=3s`MB$}?#s?%%`)!+BT^$f%9fwvL(AeyCGUqil?Kuj<K|D65ZS_DLe9Q09vF
z#4_7JY3L4a6x=_g4bdLgbt`}yaT3V8nF%N}fgs7hUK}^VBa}f40g!}I&&z*oc;9>A
z$2Syo^0$`<(H?H1-WuJQB~0$NZQG&ltD1M!7z%o<>D7LW>58#{%y7iS$dMVNVlBQk
zvOe#<3rPU-FcbA4NV+5v-AWOD{}@8bxuXw|EkamGfKVSnf$cv`*LZ$XPZ?KBQ4J6J
zwwvn!{$WA)LL!gg;CYNNNK{G?oEPlD|2~cdsY^g5MOP_nC8!!LBBl&O!dD*bAoX$+
z5R?FGM<p=?L8KigQuQJK30{VTj?e at Ba;GlVm3zuOgb0xBC_ at T>3}8MqcdRMDw<LkW
z8f4`Hccv8Y3)&n-C-%aJBv+<sPT+;4z%ncBTd8PCf-)e*f6z}i$I+Sm)FBU<$EWr_
zk8vgYi-*Y+!7nLiH!lA>_)ov5-Ri1}<y5Ptx;MRUai_*Jy>ENY_WR!Vz3cS<$bW#k
zp1I?D-Z57<jADpRiOz~BqKYV at i67Awp!xjrL7DSD(HrR;^bpl~?jiSl1VltcL_|bH
zL_|bHL_|bHL_|bHcxZ at -)`*CRjcAD0h=_=Yh=_=dXx4~`h=_=Yh=_=Yh=_>R)`;IQ
z4FCuU02~Lfcn<(wUm+k&gU~2oLIg+w5FmOy17kY_a8&$3G7<O#>u|&eFfj?30g at L2
ztok4HN;QKAhY}Ek5fKp)5fKp)5fKp)5fKp)5fKp)5fKp)5fKp)5fKp)A4W*?_lIEc
zLp$I&#0l%#83%H3usNI|n(W$30%{P%2x|^gAc+P at Tr3v~3jyQ#F7dLWFaiod$xLww
zgSmLv8xRP;abzF~LK&R-+!P at bVW<Jn&H;E))s1BB6+1iua4BY at bxrJWqo|SJxi=0(
zVCDu60T7^thEiw*3LOeUL>~U|4=O;HQ+-%p-tev at j~RG*dTM^E6sw{h4NaXeLX_x%
z0iN)$;WlH2o-_M?7gbG(sTh?(5C>#7gk24Eve&&g+Ew$z{`4HGEa8^vkHzBX|AYfR
zdEq^WeC^wehkmKV4)og!pJIHXc0+|uMKw)zZ0a#G7$N^u0+Wzc at KKvB32G72V3bHO
zIS+6^$SY2%8BYOjP|82E`y)-G0}OM*l?%0&5|7>Yc0>lU<~n6mrFRS{wuW}2tGYgj
zIaL=@qFDV$oy)CxO`A*#b(BEg{nWs0a-A84U0lvE4IHpEP18;bk!SvU+u-Ooz(Ese
zC_|;OWK;2OnGm3X`o|hgnY82|%pul)Q~ZmMfLfM<Qd}JJcFogs7heo)jwJU?P1G6K
zC9JH3o;YeoGt;S=y!;#4hQvmU+u7EdAMEXL*DIJjIXbQqT{0=WKj=}Jn0W0%W?LjK
zFdqg!2o~qQqBfoLUL~)`X3OBYGx(8N&$QItJ4`kscMWqx-R3cb3rj2;576ip5`O1V
zix`3`DyXezdx71o>VXM0uI~9r{jr at Yrhy7Zgh+b}W(5rxP{E_j%pRJ=H3~^VO+v*e
zBsv@$hXJtI_*0xAOJl=SF^pkEt-kR85aFHN+e!ui#gl;w78w0VIYTN7#q(J79(}Z~
z!H0piX98XmqEmyv5)^)frjD?eA=5b-s9hn9R`W$+kHAPsfyWL6r7ZJsmHf(LREY=<
z5etD4P{VQ$K!AEJaK?Msj^J+;`nVkg^!6k<06_qf#7Ogn(C*CD7OzLL4*j%_glK)W
z>kLfLevH2nMKd)$#bj3$8XGK<;+jhvtZ6-oR9*MA?_ at zN@RBrvkPW}y#3iMK3eY8>
z9yo1FNnJUfOJ3r$vn_#=a*FEx9He$3-EAOp-C*kgfz&b at 6gnH@tNxI|k--QMo$7Gc
zHyc2$ic%6W6%Llh<$v=t%l?$)ame3QeFsAND5NIiM5vVo>xk4v46ZQG8$7*MAAz0=
zXqyfNRBly6;z5cyW%55~*WnYy_xneSG5-X9*n^N}?ay|!xd_NKeqlmxyF?!LhDYnR
z+#;fxK!WgxrZ_ at +rPsDq6;)qBo<b|Hn2?ZV@=sg&{`m~7N&Lo40<@_R6tpGztOm;(
zxdSZikTWP6sLXJMwo;Z7*<l`&E}BV+t~MC!3CqF`h at ygqhb92&dL8B8!!7MFnh*+C
z86+^meUA5+G2h1LJGfrUI_Fs|eX{Ywhk2r}H@}%ri>H$fHhT9|VVLBD0P<HZv`fJm
z4yEzUG}28u?@%o-z!O4Wu$AnNaBv}x+Rmm^`Q!biEU%DxRVz*=a5 at VQ%aF8HgE$nJ
z|GO`GZgMk26QR$xjk*rYkMbYGk8!)Qe5lP|`gIHHr6JAsWK)+SljuTpbim~+v8`l9
zfPle?Gu&=H#{hN+gQ5VW3TP+ at _hUq^Wh-gIKio$U85O7>9KN$I967mNSHLtAb2`y!
z1Bq6G!(*2DofC5SB8Ee?mh98 at f$@uCEoP=(9^<pVSc2Lw1Udz at 55n%4G~5W1;s61D
zWjg$)<ek^_ftEoXm`sY=A)4s-LKSp-B19Q8xa_&xX|q;$=a^!Ukpd{E2R9!vK4;%o
zBG#@wR%^uC%h1R_TPzS4gWKaiF-%5d-_N`YRtIi3+p}%Gg;!th`z^8&-yi-jP~WRO
z?{D${o<JB}CQ_u^b9>q0$O|ESJSOJK_H6|Cie!H%c;(AvFTrX7{hMWdP|E!nSdf9S
zuL*A|QGH;knq)xmSO?6IEv{?fkuw4nLQoly%RKgX+}etV{J*cX`WKM=r at ld;#iGr;
zGf9Et&Zi@^%ed~Vus@{>V1KUj{%=CrP*4xhpP}l%HsJ@;(@<4ADM98P*{XtiaQz&B
z%@j7X?-iB at k78006(MOnMSVYGfgM26G_17N$6ucu_>7;3&#~xcgO=Kr;=K-TG&?49
z9{hWeBv>%4BevLu$^ehzB)~8V&YGrS-gnYU+(UT7GXR0 at ja&q at 7P1Zw$ZM3fxKsFp
z=snE`dvq+~3l=amBqGrRr at k0OGGkS{H&u-`=jg6h<kXLvaNS(8q)a0d4X%O(?f({{
z!j*w~2c at jwU49WEP|pF}+BJ~-ODh=HpEN+vq4n)_c$Zex3fs66gqeY+_CzYGyEfmZ
zW{N4dN-&4aAZ+Ssn6o9!fl*OIdrR)-K)2orCADN8=6%pDwuhS|&$6Hr6i#o*Y&LH(
z_H4Z0!qV55#TV=yNFw0*kmNegH2JK$m(i#dHiv~Oq&BuK5(!_mO(OHfAp(o29fk%y
zMinx5 at +fAy=|NYZfkpj{tA8bQrvV3yn1mEPgeZSCQLs`T7>FbTNvmUCa!H6OphLTV
ztEbL&`UwsktG?r}?3Z-)^Y5%QH8tHiK+ZQ&0fUe{H8sy^5mn)20-?JlP{ruLl7!t>
z!L~KF6DrD4r2FoWmLl6M>dUjJGjItVe=zI~0+7HyzcGUsJ<7t6^If2^FQWSY+yBXE
z4wrNWme6>_BQ3R1&5l|5qN+yzm^%y#0}1VDX<^FF at yo!L?d-wG)a1m&37I9=Y+)KV
zXA{cAKK>->sF|e0jCc0q&b`de-(7s9vheSUtE!02&M}IpvT#IHFn8*$?IF$zDP;B<
zLSBC#huf~O$p5Fe2X2*pVL|yOI`ii!?ceI?o+7e6qG&KbgIU;aMC$?GDtLkF2fz>u
zrai1J89-l(Dj5h`A|}Ia189QqueU5rW*ucVJRG%pA>=4e-J;z0^F7WZICtdo^S+*9
zCTsw}z@$&3SCAyiM&fa1!uy~zB?KRG`5Eob;-SV*1)a8B&2wBh<_`uOhMj8RG6L&X
zbl6j60#b+7H*cFeGe)>TZ5ooK0Kg4wf`c6z7>dZQyGvl$*_}Zg(%nU}r|G*2gaIr3
z(qUqvq7&S+Tn>5nLHkVpD9A9jX8lysUwe)h at eX!_rofec1#G?n`fFRTeR(7#eBNI)
zYq|-BWY?POpIrd(iVTRhg49rdFKjal>`)950c*ERj}q43w(P7-!x2-zHpFW|$6X9s
zKvrEI>x6`la|sC&B3<_hux87wk_+zE#)67YV_l17MM);jH|S??tM02Q*gtXfwn^q2
zRl3X&3P}bC4L+a4482+uXW>*w#4=j^Z>>M|O<45czHc+{JIVV%*#|{Ch at LTGKwv>4
zLo7IvKQOT6eBnd=DEuU7U*jLuka5_k0)xwzO68j8GM5_?R&+m90jYF9PV!TG9b4q)
zUk}XvUY>B-J7Yks>#F{T>51tIcELm(G7P%nJ{2N}g{?o8*4PptVAw;t4!Z(y+F1+4
z=@5ReTIyRyTBs24Kx#M_KIBX0FlgSrJtJ2h9`Am}BN3Tsrqf`WrXiZ at W?wQr#tUvZ
zxR-Z#XLo+if)sqdU%%x!JRBhW2Jo at -d%ik_qR8$z(Fmk9>FU#hu)g}JsqH%;aka`n
zhvD_eJ^P0(n$u=sgW|oxe*wUHTu7Z+nCU84*QXrAjzc;=j%!B-s*U~p2r)CIIjnx4
za{iv{p|2jRbl%;rK?W)4$!byk0`$4&ip`4JVYgG(t!C6U6-%nh`ieWCS5APoagwdQ
zppyNhNtwDE!dGmq73Y(RiL474_Py7ySOGP at Yin(`aXlvoDBi7%J2MQ;*;Z)80S?XQ
z;ALVFG<)ROdsQlEcKfF!N3AMeZAonwo?ioP$&I3<F*1TxaoiY&U_kb4aC%qMk<Zyl
zNl7PhLR;wrC?s$PM}U7tc$7Cl(uS4~fVBj>)n$==-b<(g1f(?9rRFSAVuUbJ(;ae<
zzQ5+9AhOVMYgAx1)u)WNTjIme<x&eC0-%j_J38sq=D>k at Q=fm(Ul92Qf`iClP>xfb
znQ_GnTJ^XH<=5Q;4At+{j3Io7A_M<7kpt$~kW<DPLPQ2ZFyKJLH^Y#UG%y}L`ya0_
zf*rFn6GKO()VAjF7?~y^n(d*qd}G!AzgGR<VfLNBlr-1cnokUNWOh+*1WPs*1(MO}
zy(XD5%Ua(;54@~8P)35QN{nmRLu?48D4SyiLhx~Ye)qF)pApup30l^_xt=Xe3t<@T
z$}Zd^Pb4ykv_#sC!6Mm*sTl^#OW47HNe*Jk_;FGEA`du1`)}IiF&ls{KD2e_bJ)r6
z)8LCUs^#_bJR>Fycn0G?0Ox$Hk6(Ono#2uoaga%e$+}McVrl;4ophzKE}?7>-YXi>
z^un^Sh6H*<dP31%!xFjwrTeGBw$&YFYz;U!UtwdU0hjqTv8jaLRui?phqm|x1cQh1
z7@;;p*f|Xc+>Q$t77>^a!{Qz>EY|qb7jnf^gfM-a$t at hlnnOc?pC=WIq|Viz{qav+
zk(;|xcx;f)H`ZQct9g2yYdEZ83e4M*Yu^6YZpY$#sT7zv&__s=J7zM_I(`No579Vu
zN2q{DJktA76t&PQ*IHU^o%a~6Mzl!l(l}aF%-%-aa|e(;c`W5l15@@|Vh}fLqiGgp
zLkI#C{l%a})j_Hn>2jG at z$n+Z7iwsvsbOWUh<>DV at zJd|H$c+U8iVCOfqKFZyzH2C
zFq3wkH|4s%AV7}i4G!KYT+msrF(_tDo?7I2_1hr)OkcK~OFPpicn~e=cJj@?Kbcxp
z_ at j{qA++KXMfN|7?F|LXbqecPn2=Gq7%)VnB!L7%z?DLYFU=u5yHOK@`>ciCRvby2
zduv;k-%c23Pi at uZ35*CV1IZ`5K_oO`ZSX+j*>vWXvmvo`Y#G4BhC8doiPeHei at o$T
zYYv0$4#u_|BQV*9=%AM;yaSz)37#1HlRT9q^e{9Di at WDIjI-X&3DqspFwOo%$M?}^
zd_m#7H<^Eyth~c`#&L+r2YI&4#){4=^?ZwIZ4EF5eaMQIvRsp{z1O9m?=%f8L^`tv
z74D&ts#rZ;8B54|Tp5OB%$7E7^=ge)h!Swo(B_;AZoyzeK-2DnkU`9vTV3wFl`cX^
z$MWD9GCA?qn_7?Dwh+PgF_7>;KnT$o2!|E&K<cQ7MWz}c5D7NYudd*N98~>^kjAQ!
zykk5s#v<nfdF;e7%IICWtg>DZ+(mE)q%n<k*o?g at R`iW+<*rLPZ!AHx8tc84Ai=G%
z`B2}N&@1C~STmG?08!gm5C+;oZ3eh+Y!Doo821dFET6~wDicit2JkK}Vp=NPi-%)U
z-tYp&w*Ef0%(_w%#$Hf+NYcE4(t8fD93=_>HZ$yvKn$|qL%rHO(E<md6Hw$BEbq>?
zIM*5@@_1q;nWV0Mig at 7N_xQ9=Q{rahnHX$Qh}I%|yv_UQtu&toy|cbr01}Lnwjn+H
zOO|P$dS5g6D3UC~k5XT<3;}AtDzdXO++{gNjUl8v9Kq6d4j*b%m<3~|S+&<R8SS%O
z<x!1<<4sA^rt%p#Ui7u at YC3LO+2zOM@fMfF-5#N=nyydx0+^8_1{J{b<(8Zhb!FYe
zCt at GLD9q#OdCdyHYOVmlQW{`)L3ndjH1;q-5rcUi#yB=WcBSGROljT?5cqUEblsB}
zA%gF)WRpKes6@){cNgeG2j($@)Vsv&56q4D205No7gYr;h;SCdkAhBp#o!opfyrml
zba?gL&l`8Bf0J|byP=1B_V-5`mW))iYZOJ<84?mPMMG1QqF(S(PEI8HUh9_(gVTmL
z%l2_gC88QPx^&_A0|Xg7JRk|u{7`R(W`HWufYyOpJ6RnM+`dLeg+|Vup!bb?tq62~
zH^KOFDWK8e!5={qEjQ<b7U_tf4!|g=F^<ed2(_jlx{m4!6JG==A_J4inQ2p2VVn)H
zB~UT}#RYxf2z)i`<Ce3h48hPh?n|c(ikZus>Ou7&6ytg)Jc_b?$y|nHHjO+~Ne5?a
z1psC2eahPb+S*d;5plA<4Oqbq&9sLfC|39E=TEop$@rKCWGZ0dP+isn1GsP&Qo<(1
zdv_aQ0^0_9ebNgiOvl#rMefr08Ak|Wpz&%3l)ln*F%u>wX0?hz*gUf{Gcyb2hZy=<
z&UyMp?0+#f2$32;r}*RYo5WA)5$2MJwzY&o;spSs^9&-QU<E>j1kpY=8)4<+^>~N7
zt*I1;l0z<FAd-&sS&_S;ys+;5Tw85zx0`17I7kMG#?v9JF$9uC%!G6tSs*ARH7qPC
z`Tj*`ckm}o!0b}P(e<koTn+?@4KWOXA at 7YEE+-BmNQzxh0GNVHeyo|f2UgbuoDLh&
zIyPrt9rcDGQ4EtQm5c+BTEZ&#DVK6}1%u18Z*)s8^g&f0u$sVwx&_~s7AgZ-RTx)I
z6~X=ei9<4z-`MUxwjWR;zs+|*avMd2C%C6l5CtL*w5h4`ALn1qF`jSnQc3-Ow%yZ_
z;)e>}?>X6r+x)EXJe<36D7*Y?`r-V4U(&AT*-xMPms583Owb^K-I#-Zg^_b_iT at wz
zLjL4LdKEROJEm^RsO|DV#wupFwaWGC7v}#%d8c1OSo8m%E&IQ1wrHkE#<|O{vVDR*
zK4cGK55V$Q&v5|#m&V|&@em4C_xbbAD5UPD6w=)Cy!dM%YvA>5pRR6vG_^})uZ0Y%
z<zxZ!a_!A3SdMhMUWP&ba&RhtEgoqUH;4Pe1Gm!FG#e+%Y|*Ka-~IBVhUthEERoK_
z)Z8Pw0IW3hYmEJSpG;OSbIMHnE`#vd|GLGC`!-pKp*|n01Ff?{RL1@;3S%T>!YEDi
zX at Nw{Fx%Za3RMoi at 6ED}&+YH}$!AH31j at W#nH0GLC{YeaBj-+UH at 7P)VT#5?E8h>#
z{G3!^>1r6)fxZQ(YA8EoMFA#73~^nNARBCFTiDMB%=Wg*iAe_*0ZYj87)xVcwh#rj
zRpSveCG)mWJ3e}2aos;FeaoE37>2*ANuoX1^5>sxP}C8^5It?10=*6L>D%nH at 16Z0
ze_0r{`^VDBBc70Ti;b(MDjJ>U at nj!!5yDhIvQKA~+rDZ2C(Xx&e#gzbEQ>{nFcrXa
z2jdA5dts|oQE!YdiRkvaF<|Cw85S_IZhbJ<qFa63ppA at N#b3iaG`nx at e|`SnZMIuw
zF)q_}ty42IS6^jHs`=i4isxu^T~XC<9s9F3!neA)2A1}Xn;zCjOLca0MQ1N#cr<sv
zuGhPR=-%+9^J#u at hc|ym&Q-MZd)(67nDcw}!iEc&K7qZwD<HjjInh&{%p9;S*Af&w
z80n at P;<U0jRXD{=n><^4CSa2vN3NFM>RvO9GrearHPfh%vH|Xmh!`+^KUR1}Bie>W
zEpL^>Ox$fRffv at tzjLG&@|-Ff_B9PW_TNI1F=ZJ(g9i*Pe3<BH(O)$e&Z#JC_Q<7`
zR?A1iO3NH}US>ow_qRa^-Z5JTn(bQrBnGw$v^%#J($Zl0vXfTX`JAP`H*vEX^fWQ0
zZv at N>21B%xe)`n$&c at v{Pe^YtvKdjdv;~BD5d_4u{)r%^zG=oKbi+&f!5^t^e>G(!
z4>QAqB}?IFo>W81)(V68t8smL#2}U+N_nb1cD2f34I&gohT^=pHt;*}^iJ`;;~l;(
zqMNEpsCHK6%#vJNpN^fJcT9^mjd9T>DqKXE-$SKGl+p4b{i{hn_4zVIHgBx4me9-5
zUx16OJI7uhU${y at -2bo#A%PeHB#ID-KorCLMo|&|Rv1bj<-dwFX;k1qKl0g#l1LBk
zvhH8QbPgfXHPZl!AI8c-hRhaqrN~L72!B|Cq>)prG$4QHAn1DMI5Pr&?EygGlutx&
z_TWc9 at iWx;-b^9byoOZcc0zXub*0!KD4~>;Uk+|0FHqh=&-25`riv<RR1SwEl2`(V
zT5i(@CwGMDrPO1=!L2Eyo1+zRkv79?BpLrG;S#~G0J1hN3kZzVI%qNzS27&vnW4H=
zV<NGKmf?sRx&{Iy6Ge!@RhkKf%EIsK;F*(!E`ppyO3o>h<mRIw at t2e)qA3h15{4o2
z<kWMk1%aaC*-Aq-Nlq|!B-XJ+Z~|ykKo#F_3ouZfHArky&{cxX7Hx(KM}KVO;Y0+a
zD6$nl^F#SRSrW~EI{z|%jMqo>Em;dRM}LX#Pxt;u?a*j7>iMk at p`OCEt}B1+1&`-5
zX)y-S{ku4SBKgFS51&%zzr5gF at ffXW0OKI?pBlf7nWlmI`%R~~bKuM|J at jscnPnf(
z-CsZLeQ~$xZ>->FLB~Ao7A`fjcs9rRQ#xex|0w9DEj(U&t!%87Ew~x+|3gNd7Esr0
z-w4)fDsm4vWxrCkgIuE$JkW(yS5$AeTWNa=TB=P$mwq=G3 at b@f*2<Cv^D8Zd<dq5x
zxi)kZF*ch^2#*bQ%-tv!Z{^B*DJWZ?@~ImoAGa<FMdrlZ+H at kZY2=J3IH{<tXGw8V
z_v58=E0Hc_tFFM^fNwF)HuL!-SZ!G?6DiZE%5!B4ZCvPtGOWmrvdyfJ^Q&+Ebx3=t
z6b+7z5DK!ywC6K8x%}}RCoz}LQqMN;BIoe$o>{d1e6+Wu at Z)2#%Gr(+q0h6_GD}$1
zIk#=pX}W9Y-j6tyxw%-nB~th4px`~nc=Nd?qk)K8pqsd^q-CmAvgSICCWD<D8%c(w
zRf>Yu)tci7>?qW7-Wb`!n=ClDL3+Iwn3xkTMOycY^<`+SZ8N5IkVw>X)QH*=7FxDA
z8UlBO)ErK;GoykyD at m62(^HK5Co8ZzrLK_EFC<@gno;44#csd#Jd<BX8Jy+MQp at Ce
z2Yz8mmr~NrHUAE8yM6F4WPVxDVZFxijJ+a){wZ#f@)nSAmNS(hXX6x!@EK3w<=k}U
zQRE}yldS5)@f4-hMRuX`RhAD?5 at P^5B2&b?!&y}T%9O9%=BI?9SN02^ZEi)eH)3xG
z1O1FP#eVea&9glslA+e5UnH-&^FOPGM>Cf;hG4N7EOAnfC}gl;j{wM{-Q2h`T6Ad~
z>uC2Sz!QU!(}K*sFzlNgDl%a-rvc=_oWG;@4HJIk2?XP<Rm9gR3k}q;%-6>n at 5@r1
zROd%E7~wrwS!NVc)DkB<Fod+m1vBW=PO7$12n-+12bcLclkRZ<c)`dlN+MF0AJhR%
z$bM`;;$`g}hy>swsr?)I<M?2I=%T%<0a`(o3Pk{+L=X6)fPHoSzn8<8yQimLXdY<D
zIFTq1R71c2BzG1FBi^}IWFjwPm3yE;3KZRSug-o&27MJPnJo at jy(Af2_FSh9*f-Jm
z%R(kKBV%jBk!C=xw{kbP at 8v^ms9Pl?84cdZDosfxou0SHyftb7sU;*v*LI>VDp+O)
zh&t4nH;%*+4_c9VtNl&;17Ws$b!>yEsqqsLI`zwRE|u at ZKgnwaC8B&sap;)|WYZo)
z+6mT#ph##mGEhv=-D<$h*H$jgU>vHrxM)mSrNJBjoRSE35*tRUIj~)TrXq{4?7d)t
z+<;mdlA)T8PNIxWbgtGI+wsXdJfajLa?^j>9IltWCw>x^&j0iBZt?#e6DTHxYy4(F
zU3lPm0vwe4j1joR9p`9h-B6z?AtAC2u?=xbA1WSj+E_e4VD+an_Mw2luz^AwlgzMs
z&R}3kkpQ98H1{M0ODbqV3SmSNfP-)}(H$~NA;iI2+KiO)9(-;Ty~AP6`*}dt5M*0w
zH&Ph7gb>zU43i^ie71=745EaJUsSa+k;%P|pj^x%6Lp0_iQPh+`+KfCYGKG)C<~6t
z0b(e2L2!JTpbeL#49-bJ2ssBquvrMOQVr>I%`*bRx_DcmJ4isWvt+VcmrK%I!-Tj7
z5<QVLOK?OlLKH0 at lB&fgad-)m*avusLm~YT&l0!<i2)94hXR@@sL+{+U_Jz(&>l(O
znr#z?5*7la6hsiA+#Nvf>$XG^XiE4R6z+f!EfOusWYKs$G&>teu453!))hB25 at Gdn
z0+W<OVk;pD5s%DTjS%7~37Ce8N?t&XAen>%Yzh!a4e1|&_i|vyTStIQR>49#^Y~m?
zEW9FGn4JOHZB{u%gLpd;c72rGT{}j$ys5l0i?9x5p}La7ToH+34abMUBoL4vbs!L6
z5g-r(R|7!EROB#H?g|8^17SWhGDzh|s6{=HbzU^FfI=u8gg8b41UGUwO;+P|fgtpP
zQ9vCN0(y-mX~5!aibR9E*N2F6x^N4m?GE7Q%@k2keb1jwh7)KET9lPcZ7SR>A^(XI
zd=5>aOqj at t6KrI`+0L0HknJR91GAnq4ICgeZ02R#A&dld*FbdvH&WmU;evyO#B{3(
zISf*;6B~x&Y-wPiief2(f@!KCsA3=?B4-96i-Eb99A!8Xgn|FLlmjUM41|lx$VeuW
zp`s1}6Junf1_GGT7{y at 7pfEn_di;C`<j{1UlrX}IR3IP7h+>_J9ZEfKBDw<BC0d5a
z;^Hk91J1Mt)WpeSu?$N-xri1h@>l%cyn;x4fjM%SfSj_x5X at 2D6Cel%phGYZa0V*0
ztl0IUWWLFEmJ4J+h##aEah%gbw~v$_V0Y@!;JH48pf>SCYD7Yu2qcO`BXCA0!9MUF
zibSS<29A?Ei^*eeV<$2J<1i+sPahAj>H7sLlA2ip&@N1nbub`;5|Nq-DBA<V{o~=z
z=g;`#>mM^5b%18cCAE;hyK>3=g^+5VF$qctjFbw>sE-f0SVnTgEhbcC$}=QG;>aHl
zIr}2$7h!)QRAtA~Ln4|(&2Lva=wKXyC>ad`41wKRi&4;+yNYRNv!sL&*wpLW_Yt$`
z?d7-~jNSol5(SGK!1)L=2_kh8C at qt8q`Uzr3qah<^)P6#4<9ij(MdmbtXQ`)dL~g0
zM(bsFB>r at p<b@;H1F+-}Cx^P$3#=}$3I^)ufQ&4IWVm>^TyQ-r`4n5gi)f~CH<hU|
z15ww^873eB%t(M{hJcp=1M~qQfKO$v!x#i&yui}-x%l}my`<_G`_;*5a5{H*8}(=&
zX_&$*&`oS|TqXp<#O{$^(_!4$T!Dytm&g`;AjFCd#zlf7;wUr$Xq!F`31ryFJOY*j
zvF$7nfqh0C1d}9?5V*z<G|1*pn4`#W4<&*~`IiEmSx!j?T%hI#VFT(|9>fnO5)u{_
zGys`GNtTz3lyEtR=sN*I!{=!Y4N`%@gRuVJpqGUUzr64dC}Vz{FfKEn1K>$m1p2Wc
zh$rS4aahp<?ov82ID*l{!LT$%RFCm54V&7;vwk=gi-UU6q<v7xuwiL--WnJpIZ<Z?
zZ-g`b>*p|yzhKHHWnef`cBD=^t{%UIXzc-=8SL?e%8HZGgTX&hA<fDM218&w0?j~j
zc`XDTt0+4M(b>Fkec_6bfRb{?M94jt)bh45$5n#}E-o>Aof5`^AJ8^RGq at B$&Ohi+
zCDO-q%{g14I*r4#(-y^<DhDIfvn3jr!J<OMcF!f$IXICl`ZSS&mle#xp%Nv9i`cVe
z+&<!)3tqQgfc?=7L`Xn-P>6)^2nar9u<A+R9(5nYC5%1$-Im0|)_GBgCt<>wj*tw*
z!jy(q7=!`=?1|U=Mv^1dD1uUyquO=Nc&(H|x-P&^e=r|RP)8RXPr5c3k%rF<xjFAk
zFRwU8ZXSdnG2LM9le;V-VwRUZq~gz_6oCb?;!-0kQrQj5%sZi}z#y0a$a6DL-3zE_
zs>wnvJQ5;mbA<p!QYWONWHcZqWPnKn5D_B`5g|!51T4d{88kM_Cd)_^0APVlDrF%l
zbhg`BwiqNyotp~~6a$TA#HMow*@%ilk73ii2%Pt&sdalqHcoJI5A0|=u1aSTM1#g{
zrJmikDA%zpY#c0FRWb*7 at Fj@q1eT?J)7b(;rd%LijN+DAQ42-1%_0<Wxk8XQ2<4&t
zNFjt9M{)`Z;ltoDB&OK~5hwNoq!kXiB8F^0*~h+vG`qQI2P+_KFlbZ~M8ML~0Q2BF
zLKX%EgyMO2vuWzSZEJ?w2pVa{55RuRDE+(`G`g?1$QEBv5AcE>h{;JKewi at vf(sHE
zh9)zyBtbw3bD02UNr97*XD~5i1_6Q^Gq!MK0*Qi_AZ}qXOmNsI1`L#tB$7)KNEals
znUib~(?*O;q_UDo$pJ!10fH+8r3g|prrCgrB3fj`xRxeJi6T&uCM1GnB$S~bi6MxX
zLLdqvLYf9;q9KV|6ewhX)3#SkN<;-V#*`>2V`L0TNh}ft5>2EYPXa)Kq*{^!8VNSg
zOC?f76;Oo~L<JHQoP!BGNQ~qp(Mh&t)<;g0Nhv{91yuzslFUgHP|zfkQw+pV5X#as
z1Q?A8DAd%HBnbqOB+W4M0OA=Snn{8p0$Eal0s<le2nvW{*c?caEhI at 2L@a5<kVsVo
zgu;_43^Gze#M3(_*fF87hMH(n9e~c*BBo{`*fTS*W*P at d9Jw?#12W1<0}LdRl!Qjs
z6v-%5NW(!Aa!VogEC&Lhni82M;RaS==#Zo>jaxXDHVqN0Vn;%-LqrlvNK_Lffl^CE
zl?_QSz?)+k44Y_VsTdidM4kIT6Yl%RcQV5;b7t6>Q#p*}OdG?T=TISPgplMIq1xuK
zIW~u!^>!wyMk>d0K37O`Ea!8Qq;&lB{poxE1@}+)<8fX0>-Bu*VJlK}I~qCkQE*(>
zFoKc_XJ-qQ!r3N?uUxKY_u at 2EEj5Ks5+RvdmOR#^Y#IV-i4_2v3J{SeFgO5#NAn)h
zDn}D4l?$ol<^AVA7sNK8s3SC+p3HA@$GPwV$0s{fE#<+2njA{qmZr#VEVdJp{rI at U
zzqUFCZ{uWTiiT(jS<7R!1j-?nWJgn>1_&ZSNzh2)BCt47qa at SPn-0t5W_p=O2g+kR
ziDt at jD$1!%e3TL55R&BG1C>Aw^I}<h!<klA({LmWVhSkqF9Xn-uv!d>o<wuG!*r2_
zK}!5ZV5TGm*qO}4io`01M5Ie5HZdMXVJe9w$Wqe0E6Ok>b{m{|1g1Kk0=%i!il_8=
z5e=lM8}U4foqmzVlSC8RlDs^6F(G~>-&BLv at jlyv`_ysKQ?By#EsukGa>EMZ0uw<=
z>;e|J2LhzJK*|;xpr1{~!eRSejy}8db-Azj)4hS9Z%%~;REh~0qF3$wDj9=6!B)m_
zFn7Xl!00dx0Sw1`*F at 5hTqW&YRILV*MO=obOdd)n)FlMDAp!~Hv)l~}icR>UatAW<
z9gWX4aWt|nxze-nhsZX`yKeVHQ;k!!SONM;xMi*>T3r$56VJ`89B{J%*}lOHHQ<Bv
z(7TjtP`^I>EK3VYE9{Xg^9WdQL<xEg2UnrMTvpZaIcuez48Xj4uxe+^g)@oEg}g2a
zT~Drti)VTSa@?yAkQJsZ4XI|OXD?_UH$TMXi$G?SPCj-BJ(uvXK?h02G<hoFoB602
zfOiEU(uqc?GEm-%<ZE$%wj6Gj8KQm7$iIkxp8;c}7biX~&%7 at FiTnC$`(vv9d6!=g
z5<N5J6z3}(VW<4+xUkZrtC*(>`9Oy6)f5Zp&BZ_Gy#CWSe-eKc#)R^4=`XkgpNmRf
z3gaOL{v)D0J}N1?i`eiqYS|$6Q3l&M5`S=N;1?vIsx`|hqd!A?>*~cP1e1pd$r%Ox
zGRc5Tgco%qkxN6Pwx(%G;+YN?NW0&_b+VI6fko;|+5WBp?ke6N+WBNTKgU0qIj221
ztuEEJJo2vm&sF1ii9W5uu8S5Ig at RLgScNWd)%YE(uBqy>vUitzVeV<xka(bu`rT8=
z+ at 4irU3xv`QJ~A8b{gg6!`rWb9|z%Tra<e$Ak!0>Gaow3GgdL?^!59^g+M#b0s&M)
zy-?Y%wa5IQbC<GDGD=wBDlIDq*h)ItuoEQUT#A+ at qHn)wubeUzEp3oX0$>FR^st_V
zU8<)rPKDpO<!N9h#5@|iXXYi#%_Ao)(yhxMSw1$Kwxf)@Wm6@#Vsll!WZSP}Y%QBR
zIHe0gp(8%KD*#?3gwm$5V&a?xQJ18o6Jq>jv5d3w;R-|;J6S(0W&Pd5pb(tY!fS4k
zTg5-0i7G~DMMRzmJ3Cui%4-8?0Jhj)SaQ^X0q~TUP=ko?t$saa6YkpSRpz;u-loXE
zwkx<YV0Ncu0Rn4&@bZ*`;6*Uk`$GIFZ|DjV77P<&!Bj`D**&lEyeUjCqUy-?-gxLW
zt3Y`jgVH>-Yj#6o1?@VZDj9Y~@mjXOxQI%n+I$xgYTvo#B2J1(Z}*Ho3p}<DLyd!p
zN&|uysIczlxdA87%Utwz4PL=B?|A+EZEbBKpj{!%G(omGi6#L);+OB52U9sA<(Lml
zg7kf~c)fBg>PXbF*yTYkbd{ZSCB+rr(EDWEajq&OF;d{Znn?5-d4?HbuvGx_W`;kQ
z)*p9hG&#nZkf|bOV^Rh%BU2I*M_e)pC9S^O at m;NW9u1W<=3Hv^V_c!b&7AkH<!p2M
zjGeqDMeq41ZNajA36J-uH4+AQ{)+LSNx;AF{@wsF@~F4^ykre%9e??c++#u(mtxYX
z52?F;^+OG~ga`U{o3taY%w`c*`ra}vwyWse58ik7-zbvDnRU;Lzt3R%a)!H3nDRd1
zCR(0CROU;VQj=jGM{QkB0TW4c^?Mxy<Ht|=1UKrs6!bRH-RI at x(mq|Sc#bODTa0lp
zc*|T5evDWGLoqtDd*N9 at A1meM8Lk5GkuJoKh<>ep%REQ%54K at Z@^&rkx at WCpU&E%f
zWie}BijLwFu25dz!nmi5N+9V%(v9latLPI#?zLl!aCyGt)#2sOs<8rjQTFFFOiSbY
z97}!R?NMpOYx(T|t_^BO3pB50E)<K6E3KVPI6bcFw$z+N7{wJ$ccYY{TEeiA?d($h
zW2tf#?y}@p3hi^LxX$lf<6&*hDu@!0+CCq5Yd2p0&QO`9w%oTpb?4e})G3j3w=rw7
zxAA|LKFhr{z|8Ha)r4??&}V~c5p!DZLXY3d?zn_~XEC^I#w7S6_8*M*koypFZs-^?
z#lyNm)FWR?JO>?4jO);Cw(^>>T{ZnDcj8IUtEv#&7-ReD-VmkkC=cvHA_;S7!?Uq;
zlY$b~dcu=tSFmf$^mXIe4;<7p0;9a(?|9qIq!IoKXcsUu)U-w><+XJE>5LG?R+Ebb
zzD*u#SGW;RGP77Z9OsvToZ!G8fEe%T_ayYyHR4aDB-3qN)#5DfZU6G0jIdb6jxb}{
z+g{2sX~%6HcruPR^;9yvpXm}(O05f@%_RW7HHp1c6YzZA`F&wwk1=`LJjm;ch_4pr
z5TOb=@9pu?zLCt^u`O_2#L6RH!^DXaW|mC3y8q1jsR_W-i)XgCKy%c~TJP7LpWv-W
zBNL<Zq6LS_nzFz3RSRXWCG=+vBD6mSAK^7sTA;P+F5-y9w<(A8T)gbzScD$^&?SUf
z3|XsIQl>nd0Ulg{-HUm+{LTrq!k{l`(lXXKKJ at Es{c`&6hORaAw8bNG)3IT3oK6F!
zvkltqX>LBy_2n$&aqHtN^_fpOKkWL96>9!UFY&@`!u9=g?xlVx)%E at L+bOPKMgEE%
zCGI5x$3R#EVs at IV5{#4ofnFjsJ>G5#jp_N+_h!#tzEJ8pQ}SH_(|e@?GF70`IY=@X
zdV>&~!MNcVo!q9NhIq9b?NuRsk&pbzvFY1uPLITRgt8H0EehH9QFnDrHJ(dZKzRbL
zc=fuJ`+k(q<mmc1WH!$SGaWLMhJ^;oH)zEXdgDB0JJ{o7H}80BIBoP>sUC%b<)upl
zN6-F;l8N$+AJ7y}w9%5XMmzc#r553oRjr9QJXq_c61lUx|5yOMz)Mm7Te%_irM<P5
zqQWnhq|#MjgNe_g=bijB-psGSbV4Ur9yLFSTX;|O_RS4O at __L>aILswK)id-AYwot
zi{KXf7ol|kf{VB(&{x1Gslv&(udTJRQojBMQBi%U5-kbM4#Y`(v<M9R5Bx#4xW5AO
zA$GnF$t{t8hEYBdt#>*H=Hcrtn-R!4+5))m at 2TlFB<p06wb$5qyW~lElE7DxKxvRl
zqMgbQ at x8_sD04b=%4_~{;+?Uumu`+$j%@B!#j$i`L}SAeioOo1{ECY_ZK8W}=zSLX
z9EZF(kR_zwB at c?_*b~nI+_yr8W>lm*`;#kGQk1^Q<x`<H*mRLM*SEgCxMrjxCjVgQ
z=Z0;p)()RfT+y$~&kXB+UpOydeVBk}+0HrmA&g9xZ?O)o at I~or83y;BUY?Hoja1&V
z6#Hh at 2@>_rp8An4xm5%|VXIh!rc>^uQ7ft0RT#`E-ycSILv;h2p}ES&Oz|&c*#h6s
z{jz7sr_3gL3_>wb5gk1vi?8}O<PPQKd4F=Oj~!)$;PmS&LF_k-<uM$>>);h_;aG`s
zp;agKx~uT58~kFx7;`-?Uxj3YW`{*M=F-uFQ0G)f5!)p~spZNelB;`~9|#{9$Idu^
z98e#O#`nKL at e2%?@c96r&9r6A%0NjS)LQ~h9B7p6K9%Z70AKe4Eg5AD%+yqAfet0}
z`!x+-GqtI13d_AsF4pm;JfZagYV6+ at 9xm=dx`YW4g2$8ZR~~am-1({A*YTlI-Bi*H
z*WtngIWHy$JO^Z(rkLOy#B0qKIinxOS6|Wf8kOqNjZ~x6Y`7!=)H7Ee(A0&R^&fgZ
z%T_z(SxHEO0&z%=Q>|Jm(-t$_F3G+rk62gD3pX4Z7K~L3d`x_EhZ<rV9Bw4;{R=pO
zIe4;k2uE#PU^ve=ko{q%#g|3)f5&#xLij51ziy1^QzI>I0iKN=;G%82<I=BBrsiL{
z^tSmGn3z?T<Kir~p)GW;<ZX9wM;=ImbOfOhvkirI`0hGYT`j!eNO2BVe at JX%ocG?c
zYX}_aY%+2eax#GqxdbUz9AvpL at EGON{f5jzPFo{sPDRrY*mcbA*Od3WEJ`<BFF;1w
z?VEZCeq$jvMf`%-;Ifv`9ipWT3L*&Hs^dF8r0!6lLbRFng_fV)@%vW_sj%=d;q$2A
z0?SSqW$sReifN+1KB`#|yH{RtH=%gB2)#9v>8PdPpYQeOO(kl$?SZIU9u46ytA!{7
zPQhFt2|cokbi at I?##FZ796<*R#vKC!ARt9+MF{QekU((wA{a{*&$h_~WN^pFAJc^a
z!8jO##2v~Zs!~Sa4tCBH6FPhZRtH1L@(F-?suu?=n<>LZ5KKa&zvI+(Jrx`_Xq@<{
z0Ywne9_b)W$AjZQ3?ldEOc+QO4M_x<3wsHeQb}AJE?_Bk?IS!11A(!UlU at S!I`|ZW
zIzE2=d#qaOVp5NhR?ur3?SW5P;#7LTz#DqrRp|ZZc5<IEOUraf?3JiQys3W05QZ}7
z$hGvc?itN$sv-qS6J*qo9|a){RhZdN;YmVrc^nv$SG*wb;sgeSxiZZ=Fyi=>tOlP_
zMyVjiU|iuK0yi8pp?=FXg{$y;LPCc}+Xu7WL at tr|eJwsuz?)ggwB&OM0IvnddzbE{
zFC=6ql10J2OMaRP28-Z^a+OlA8~4ERf-rB0wrp*mi?YANHpICTz#woEl?P!N;lL^W
zOUYwmcyGi`fK2TSm%`F@?r_QDl;`pPU5^cm)4b~VGwR+D$&MG><%t~aJHDFK at Lwlp
zBms6*_CC%lVdXmQ!8{RD{^eXpzY480^Hc7!eow|fR-^u&iQ$FdpN`TA6k0-U^`7Q&
zdgzG+KBRine}?XohQ9F?%`G$OInPl-oEPy`ISQTl9}h~(922 at V|EhpG66wBNBo8$7
zzR3J_!A9G~Wubt4p&+OePiwFa7a*`_nu5u at nxG!Z6z8){FDWjUJ9qqQCdVSo`M9OC
zv)lM-|F>GF1L7R8Y6{f=?vx^-Z?fZ|etcB3jokKO7e|@c5<feGa~hlwIJc}AtOPz9
z6ZlZ%bMwGJY~M$+I1{3)+EvbpO|gW0npZ-uMZ9~wg)0KAgdc`&zc|P$f7W1VQ6{q6
zT@)ZEC?bxIG3`0`fcA9-CKl-}2LU<qJf~S<xy9tvl9~5va2yB_OFP~RGhnaa;mq{@
zUUhgDaZBR<DvxR}Rlcc`QALx5K$1~pri+?@jas{%f&1(QWlxn=$+DP$5~InX^LNUI
zGueWzmSnWdd`waDgQ;v8AVERjr+v+UkCySy$y1u?Pw;{HVvyUyPG`_D1YT&a23s4@
zd1GE?b*uD@(-rutEc^*)lYq|51@$v8=Qwm#w`1cZXG(J{n~RFr&G>G?>!N9fDovrh
z#0;b{yvan&%@w+dShAq-?k<&P<%zQ5QK=sjI_*3^1cfrQ=j9$eeAcf#(f)PL9<S`e
z=J!>7>~~qVd`a$nKgW|hc03$lbl%eh>fu_4QRxsp?0pP_ZDhPAgeMexla<J>NEP^d
z$~m(=aXtK(wPu?EZhM$i9WSfF8BlQ|1`w@|Pzym#Qr$qR$69{CqM?a%VD#t_-$3ZM
zcYVL-W1gbP*K1Qw*ZSY(3112|`5qCFrr~KMt({8C227&AP}CqT;Sil2h1MFgKi+)X
zc_%Z2wH=p&T-Xxos5kPAGu^+Ia}lYOljir?{<UrAKW?J=E5FwS@>pB5TvP?0^g0nr
zlqCP$e$_|KBf0;pmCS#nHB9|O?@{h|_yvbsi>WcuQxC*}Zde%?b3DeSl#}Kr0)zM@
zmc7#RzaKxMSrKMiHag6qH#!qgC}#355aEaI+m$S$@qfVqPE7^vufKh3tRgfGG`dYJ
z<vq`gQhXil_wyc<D`ZM{B{xbYw{##|57vRJt0c9`<}Wy5<l0zz$(;IiBA7&rZ1TSS
zH)+YU<!~=P)z!)#@%l3-tff0U_Bul673LEszo*r!_;4syl;XOteFc3ssJ!j{=felb
z(_05YJ2K^7%)nnsEk!$x#o)}9`-4t-p3vbsfPXPM)YQmaeMmTS&F9DIc{p0^hs at Jl
zruR71GUKaf89eW*^(Q&3Df;KJ8YUVr5bmXy{}9F3wdlP<956T-f2f00MHO1Yd}D7(
z`~yKh!cFFRPbXH4qDTv}2m^b65Y8~3<L_9`@prlH#LfOUS-HVp#gwN~5Q{C0d5Ay?
zswdT^(J7T1Zr?QG+tZThufT0`iD2d4k}J=R^fyJGE4x!#I~Aqa5}finzNo%n^KqQ_
zN%jEQR{UZ?XN7XM%AE~z5rvd<ioO9D%;CEQeyi?kR*t><-XN06a^1)Ip;j8dbgdZH
zjpR9cD=po98nBrW#112|5<&79)6<F^#_2-Ej1|ES8LqN39*FNYD%OB7L00Hna;c0J
zz7y{m<sqTc*baCIM8Z=5{kJTwd)yj65nF7-<Lo0d2Qc?4IaSBAx(XF~A5jMkI0SX&
zRZ1&Lm6F9VFWtPwh)H+td2(+zj?o0oIj|B`(KivF6REr$ue}pc21D|8w6~f)X5-Y|
z9N^Th!}F>-n5EXqj0uM)F}Y~9T-!}%Pz0Yg;60``UoEL@`pR1+JJHG%H9T(pvT8p&
zAVU^s>V0BKg!eb|jk(;P;F5MB-bpS}?}yOCLl_e82F=~QsYhRPVE})e*wPg9UU0C}
z|G}F*7Q^eQT%lyGmQo^i*@UEx91tL3rKcNNXb}R*SE7o!{z{&%W6cXc&==q%sHfvD
zD(H(hzjx0ai;aRV#$or}+h68_azUTWULED?^VMZ|Nda0-mYTn~=VNp7)Dk+VLJwFu
zV5jy{-QgC?^~cNGq9v!`w6*#X*}%^E3FW1P-eFFGlmz|ox7S6V{I0W2g|?q(hEWqQ
zZ{D at w-~~W?9Ihk6q%kGFTQ%;`9_fohG$;=T+AJR3gAPN6nx4cNI(8tmC!lnGMLy13
zfT!4~X8AH+PK9I?2TQ&{>}q8$jEr<ds1}rb_Rzf(qK0*2qE<<EXs&OF->I~isPf*M
za<6Y*YyFQEdRaW{xJ`h@%nR<SUCqM)BaxWG1MFzc-Qf(&$E=&`$j7qDq|pNfq8NEa
zMeID`Bd_Oc)F%tR#1H1_WA2}ydiVb)_R~n`gnsVon>VSQQAvHQ=a-bD6 at mNG%eRds
zpQBxGe&unUd3v at 6Fd_@Cg0x1=7-pRyvO7{gzsN~e>qi~l0aP^fWd1xdfzU-sahW$o
z7H+U#8YQ8A at I@Hka{H`Qa543SkTvOzgQI{d*+E!9NQg0NpGb7lbW=6cz6o6j3aMCf
zS$jT*Lye*B(H~z6WCrCH^3mXhub%Ua?p-Q9 at Q$^#7>!aOM#(t;6%ryio|)r}D^}z0
zqKw_>d<crteRR#z9|N;0-JZc_a_m64B|O<*fdwc(KH8<n^VH1Kv0qrR{VCbzCIWiL
zk=h`+5yVp6HE at so7uJ_7zwAe`2^vBwj(-uKMw3s|<JV0~%N{_05{6+H?#uaD=g2zF
zdwIlS9rMWD`^M;=fxyyW_9=p4Fk~+B;aL3u2}l at OAVa(YIH$;k)RfHM)vvB07-uiG
z*^<_9880zAcHyNeDMPF>#byI6X9gm=CdlBa?)aX2h8jm!%}zpA&8QF;ljTB-xD5O!
zb&lJQi?^Q-E?wz}0lYmi;q!nD8iYjm{zTC6=qek{;!^SaUr!esJg4GDt24$JOP&W6
zC84Hu at U-Xe27^x?oq0 at ZLGX3YX?iHDh)YSO_jULnHo{K=ziJLp#z$TBr+(5`72wf>
zEdB7jN1>j!*R*T&bs#0UR5RI1?r|m=XjSU0hw2j59pXjk at f_)P0gp6+6U=t%ON(Vh
z#Y^|Y9~%>)yb^kokif<(4d=Ha-TB9V3O#=yF3<A1{RvVMB-LD=o*0z?cb``gOUqVn
zk>2(BLPd!F61%&LYL3}@u-y|67)g#abw(H?h|?>llvfK{l1_1`@WOr?H6CeQ=?=b@
z<>i+?@OaL9vchZ1wW%A at b>^9GRcV}jn8sgXeBx2jdC)+li*T at VOp7b8XpC>g^XX=K
zR=5Pgv-BI3s)@Yx)qCU*S9Nz1R^q~p9y2zhcyl_`kSD+_m1HJ0w at uB6;34^%qs|Po
zQkC_q;Ckv|d8QXl7UFT<(8hYvJ6H!tTHa at h=1^DOzL?^@5nk5Rz~Yy#Jcy2%HtnLy
z^}N9jLu4XIw(7s07YZolB{tEUj*z1dXFVTBRbMWH3bG1LT|1E4y35ZmSjsmYR>eI;
zdv96~kW#U>Ue5&{vt00Y9~A%%7*gMiHX+&oM&JZz4&8PV{FtLD;PbF1_O%EqddKb~
zkU-5_GhJke*@^}8nUlyIoUOve#Q{Kri}WsWvR!-1TxAC>!!qrQ)c_^S4@}C(nvW#K
zq$kOIxsH=>xQJnmq^5K!L$ig2a`J0<$8`0S_8p-cw``jeR!A%{oK-0<sHH%Tpc)}E
zq)M#_I=6~mU<4?kacu)6Ws-dEafP^GO%nBL&!B?jsMlx>R!IbJlgiml-f;SS7r15m
zo`A6y-~b|${1wuNg>lf7iB2C=nK39s-6;1*dR00J1$k-f2AF00R%--hkI%9f#`djz
z$CTnaL8xnPejKDCou=+-OL*A|)XLyI4U7nOv?|w4v<@$Wh|p;Topw{4pSk`XR at 5~f
z#%ZNeBQn0m>s&jt>F4vDzPk7L%d%~kSiL&Raw+QkcTe9*wm*Ep*4nw-b8YtJ+*OoQ
zo5O&c)OVpP&`b^^t%~}n9}$R`%-9<7QL&clFX^Slbff}GQr3pv^%fIR%C6lW49e9N
z=XRT`eJ)zi31QyLbLtfXnK7ZY>v-_pkTxBvWFTV~&N~Icx3F>5Kp4y2xr}w&cH$az
zzAGq(RTxtDEP;O6BfQSasYeFuqUd+wYy}E{#S(eJG?wG at fdD=6x7V^)O?^2MVO9a5
zrg{8k3&lnCfDuFu)03URCGeyz(BU6A;awqc!qB!5>Y))achin535%r at bIxxLMj0&*
zA;~+tIMk$c*LWGaT4*3Lv_)uF&PsJsRw|)^cQ;$hkA3{AQEMn~?oG=kA~Wbt9DON%
z3CB4kk}<G!&pSGe$9FLQcpG32JOs`7^KsZuQ4smw#{rLz)3E{<%)iE`jS3PY0GNDB
zfUM-n3CV|v at EKAdUy86j-XYk#$uma&BVZ9zVl1j?D5u2Y!nM?cL<L*kf<B|OC5vzK
z(K>WEiw3wSZ_`v<#zJ}mIo{x>HJjvrRpy>%XdhcUws>9b(&@(;^+L+$xPOEMAG_eG
zTa@)Ntyiy(8HC`zM0h-{*Eo}TO+>LqU_kpe;eb<%*X4+=h3Mp3YG{k6CVk<%@ALVe
zp!5<aC1W>&9)}gD<%ywv=o&VDTNnKPrYYt7h58!EJC(|Z)Q9cfHu^Mk2<I3U-&*{}
zQ`B`T<D17j4;L{{!7=@aA*_z1=}ErS2?G8us;JkOJ$J1^?{zO{W5#0EX5QFbn0L|P
zj_8*rb7ZNa{(X>2HdSFsm&3TDSp;wfjF#=gsmp2=?(JEZoz`6We(XTSnIi7-K>2Ii
z75%=j$>L;vu}W<{EgG$(R0m4}-F at Lx@M)**`*6V9^^ub%FT3wbR`_%_C3=yiLV!&`
zq0ymC!^v#T?-8*`E|K0I+Z0i;;=+_fppC;e_~wz%L<@N#p#ab#0Uo5`JDbCCB%=Gk
zCD&N~6JTy}_Y-Ktox5p?t7+Zkdom at Fkl)~lqz*rd26}_A(3}dMUujCUC at DH!;m9+{
zp>GM;1Q!wG6_kD{&ktEj-(bL^!kMQ4BT3HQeq8Me+xuc*G;s>8 at Hz0IwN~=9hm&V|
z7x`llA#<hqVQ`>~BFE^DvzVzZRH_Lg_1c)@n3imMkA~*C15R$nwn)UfYpynU-d}1)
z%=mG#HL`Q&iABh>TfQ(a)(Ni_yo#BXjeYpL1nC~M38LdJpRA%xvJ~UP at c8kaQ%r!k
zYPD{t=HhNt0=w9Z8YW#r7VnipYAWWQ(JG0g{Ph-ej)xhXM?@-0FT>HBb80(V+jJdU
zNe+dDxK^HLN*xhn)++95K;rgJ1W&TNzdyfvGep`GS~R2GdlhJ)-hRXX7(`Ycz_%qq
zQjm4*)iJF&Unc)9G80p~IKg>QzGb at 0v*jo4rwvlkLz0$oboL(#3qS#U1_lPMwv37(
zw^_O`h|RX04{!gvwOL{04dV<2s3O3>IfsO}FR#ns_a!9BPJaL4?dxP?-MJNhcrYmB
z(1y_rCi&}r>ecK9PwCDfZiG64s;j*;IDK0>`fx9GfKXh}$y*LnS&2)IeL8d9)0{h&
zI_Uk0>A^-&aF-Q2vk(KA&5F{-M79)sFp+5b7ea!orZS`~n=@WDJ$&QZK_Fq{zC<~9
ze1|>D#tj(H9f?%9Sc`ML-*XM0npVHB$9IOjDA1b}H9n;BCP at BHSY;-~+1Mo4X%c!S
zj(4Z1zh*8-l<~z#w2Bj0Q+;OKJg~`Kl^QQ5G_BHJ<J9rreWL7q4E%SP|FI|+5tB at b
z9Ii?gNSNvKizRvUq8-G8uLp-Nc)5Sc9t|`%?-wXS(-cP;F1w-*Dj~#oNDoBbD2FLi
ztCb`k_n^&@NH~``c6N5{>#xTG!*Nf;HRM16F9O%~-w2E_d!HqO3@?5xOQwpaobuWW
zXa80ZeQTC;cEv%OgWH!w$k;c>j^M5HwX8O0K|-OXgT?+~r1sP(htmWVrCifvEV5fv
z;NB&#f}>?wTC1S3KhCh;-W=X_NB+zaV!K}~|A{;_RU6LvKq?(Lq+b!lFYz%G-O3C~
zOrUd}hjR4p_Y|H+xQQ-r!0DSE&Mn_~VnobSg~DONO<IW at UWAKY3q(PalzdOzJ&z>w
zchOZg&i;}2FB51+psQ}6Zc(3kzfh8~P^U%wqvMylp5K|4h4KrRzt1p81cSPJ(0z)e
z+>K{$QlFsWrAorPk4zkSU@`VZb>8qCSDuL|hTdBf=_S)9{!DQ|tB`$4&kkYU#MOCM
zbiiI-4}IjR0VExm)VWrg)`j!4KsOYd<RZcBrWh*46sv{#ph1WT)Nhp7@}ySRu9moH
z+6W1GxDpZ<vdseZD&ukk`!mv>p7hG*{>j;#2Qk?1j84I`OiwO=s>?#b9jhaJpb)ec
zVh8w&%GU84k-et%FT!CGT%wWyaCAg)_XB$rz@<xOhq73?ZwT)TP5*uEIK_j+y%{|4
zfQfi;G%kxtgnt=(cH_RYQ(x8<-0UjhECwZc#BtT*`KE0Id|pSTWry!JVxvkV?Wf6}
zhJ15=o<MU}<`8cK5fa8BqJq!O%J)TsYZPuzv?B}lpQ_-OUFQ2H%|C%<yT&e0J273X
z8hnHPjEI>GHmt9xrHz9}*^5vhb$tK!J1UzU!awlc0+u at c#Ln$NbKu|%!b!z-uBf`&
zTXX!_lnXJ&LV`P@>l0zSekHtafz=(Y0l&=P-v6^KJ(NJ?68h5inL8u(cVcOuimk6Q
zb2)6Vh at Eh7DzeWt@U_wH6K2E3Y4b2EmCwe}m4Ckjw<*ex0Xb~pOY~fh#Es{W<JFq`
z7_q<XGJXGvAsYu1IJ$zeo$A#sLQhH6f!~>%yKpNWFS}#Zej{)-#dvh$S<yQW?8m{`
zuG!9_74=$q*9EPktHc%G#1qDvIsBHkX at cR8BY|T^&FNqu1_`V;^3>nk?dTkea382I
zd)0;2<sRJLTsRNrJX@@;7 at E!rlNuj{`SjhrUd-zJP{7gtZj{dzl;3u4*VkeH7%RhQ
zlwDfu!si!h%TE5vl2z0j6sxKSaFgir<7nmKdai|5H)XR##@*Fj6O8`x9zM1S+)>tC
z<)a=)lZduO#>(qO=MIC1`LJ6}L8BU4q%wr8L<f&ny8O89?%NVRmmj&FMOH7OmKLRZ
z{CNqZfwUF7&i8;w&bP6po2iO4*-b#b7YT7<L2PQ7qz}HLDYR7Q8Yd&j;5uvP*TZ)e
z!yoyr{Nm7}+0NtSwlf)g-jH}_>{&?k0zZYKVjw`xdT+)De$wY{A>XgKvK9eRyasnM
zJ at ZfP;2PMTafmqB?1Myi!6P_p1V9Pm!VBL>E}+ppFv~Q-(P$||kPB7)(IZ9CnRb1)
z1`h^?d_aL#!}Q|?$}<2Uf{_ at wNmxf-Tvhc-U^qvHRx;<Mmy37aMG8Gn5;!u<?otAg
zdgdG$y~PVS;328<cM-KAg%(4V=}>Fj5k>6TE0o2+8xW=@px+u+NpiC8CYl1!MG09U
z<-gYk#)W`LmB673lL)|M-Fdl29)Py=3q6~HA82KM7wKN(<YQu$KmR(&9Q%=LKcXdA
zE-<Q-rk;Vzk$^jL9#6urX_2!H|7#EOLHy*U*L94=_u<K+F1_s(aIHZ${m)(hE;9r6
z4{mN=6XmO1X{BNXtbc5sf#vadWT*5Cdb)XMmiK^OyXfFRgi4-f*l2|t70Z`VdA)6%
zQRJlvsnmR{eBq^JN5iROg72J51-;M=2vrMjw-FQ)g)r^m7ac#r-q%ri5{vo%$f6z}
z%{dGbw<z(RMh=prQHbpAOKn&0b#Mvk>PSdJOfq|{Y{$J7QtGVJ;wCiV(k6`gH7G4l
zQc#l_$Q_+35Rq(- at vULmr2k7Dh3Vb~`wR?zq6HD=?jgNO0S&uypoX!{BQAJpLy8`@
zycXry`MshG3Y-e()|9?TdwZ_hoFf~<#E6-PXxxP&U^)ib-_GBUOx~)L$|cvccOI&n
zI5PBsJB;UOB#6@=aw|IZ^d~AK1G55CDnv6o?nnf*8vT^ZQ9oI4xSv`e+%%rVcPXin
zD5q_;{2$YMU|eJJg2AwQQ0k}M34ctE_z&nOj?#2iM|gUU9A$H|kJn*tB{+DN@$Wn1
z4bOMFV%PM-`WkZ;9(o1E`*ibD46)1~%*h&ybIj3oKfI!%(I}Q(61ydVeI8;AySVI_
zFWzB7sP4-3z2yE)MMQ7EQeQNyQ8#{y%2;H72`14mFm4j4mxuajQ%(Rg3OPX)+WCWp
zquo~MpAAgAM-V>nu$DUXsKtgftxm+6L&cBbv$8LVr*Rx4#+ at MODAbj>i3sl$WLa=5
zyh(RCXWMx4{^$+0z4snE`d4i_XV^OL^B+{wo`p=hJ-kZ2RHu9LHh+Rx{=-ZGH2yCr
z^^a}Ox3$oU-w`J~l*xy11!`UsLJ_1vYe?BxT8-Xy1 at u$&w-n41OY+rt$}{ac0!4XD
zzty>e3QQ!w<k~Iej<^_&LKa?<O6!?dBjf1*_#2JkBHY&HBgTvmCr{g5I_2hd0}3^!
zPH_M0_3(<(B60+4T$SUfiJRWv(O*EuguZqRW_7BQ(j_>?f1>0igTb)V`id-6&cX>Q
zYtCM&>LeqFDQstf6^Z6!;oR<kDVq(wXXN(?ZuHc(E_ZUvj+RT<R!5AuJD=rhFvEUy
z0+|dYyi}}wg_TZ%EF|RS70khkyNQndJjH1fn at T)WL0ReaGxuVZ!l2LIa-$Xm&{gys
z&Du`VE&<LpLY+gsj(bm-Y?x5fT at -oU$3I+^O6s7q at Fk~`&dP-x1b^x52c4DE+khmC
z%#jyzE3YD620sa|lF!~+&{r9-os7#V_avV at +w37H-4-mQ;5<7wze^&Si{BS6+1#0m
z_`1FMSodqD98yn5m`5E^k_LgdGZB?`8lwE!D`0OX#HGeii-+wqR7F>_Rilzd)R1ix
zPP(XXE at t}g(rkyD1C0 at an(A(%fXaI61s7<*Zei_LczTnOito9Yw1PKKp@~8`bu`qO
zG6OfL?kQrFF=|%ylJbHauUUo+x1Ne^@6PgKt<<`!v~R9?=TnGF)P)mgy_Z)0Qw%dr
z&XK+T1V>zx2E|czU{6-AEb>51(*WnfbmQhoqjT$S)6vkSd_ at o0OyVFGJQOZr<T}&2
zvGXNTjU!j(U5444z2{Dx9A%4{svDsZj+hXbi&wDiu+ at Ahx#Pt7;1hx}O!2Y1giNyJ
zL%h2ws35KtPk#AO^qhDd*m<S&W?V)F%-i&aMY20LN0YoFVdZHUN{Ea83R-j+>>5gf
zL=4VH;+o4cUCx|t2{tIw!?RI9lPf4kUDFhyEQS9dAzs;@idb{j*q8ue+I!R<1Nu33
zR26?Ay$|y%tV<d4hklcpf%yJ2`WT8ocztEysl{wE at 5oUz*(~PK38v$bb|7U8$u$1F
ztLFaRkKvwMc5-9tzDe)+X3H0;I2*bkM{IK2JBx3ND)FDfdTEEET#pDr#zaadxlsgL
z^e$pE<Xi?BZb0-W9T>e at HZj|aBHPB~<2;dO6b(qqf7woX8}|ZEUssG9e5n+9hVff&
zegS38Rv_Mc_DzM)W0VFN>d06$SwmZM!95+R8y|>!3a^;aoUhAAElWy*@&WnK)%YdE
zSw8R(M_bZRN7|>&SCE&or-wTxU{AEpRV{g@!g^R}0v`Vm=K==Q;)lTLL!9yr)#X9u
z0e{TH6S_kVetjTn1C|n4vKI6n&<_>J+zl4%%(mscrZwWUUKP at C7F6t|?42^9AKQU-
z=pUO-<+e%YW+<t<dm}%bgMG3^ubBlSOpNdT1a3n<#Y;~!oy<VCKT#9v^T=&0C)VeG
zvLI~~d-`(eHQW^lR|Iyq5#z1kz2BlvRSsiwbO*}@CfRVC;zu9aIJ1>og at UJXi52T&
z);xU+o?2%XeDziNR?ZnBb4o05f8;7VdD#UKjkzd%_hfIAx(Y{Js1SR>97`z0wQ^w5
zl&j8}CSr+aE_h2XGbzeQEC6j5$KMr#|F8sY4AFF-;cGv<f8oAPu=qRA`{v8EUqMct
z+T#P%Q7OtziVIItgToSuRJpT%aqHB8J13PIl(^U%=n5Z`m5`SQ*WV<Ra8P!kG_$x}
zzCn&a6iPC3F;l#)XI^08#Xp!nf65kEiiBkNmxktkOlFQ|mQ6NF(MJ_1ev&2H_MrsP
zf3d_6yZfdfX!*wl)#>dW*$`=yUx|Gd3CtG&cU;>U>JIQX4RFe($l=I1%3k&KxgQz7
z>wl|c$jeU-$70(Nr^;-Uz at U_<sx at Jy(CA+^Ux*d+4Ui1vI7f_O&OAR+x9xIFvx;HS
z(#NREj6FV>r=Xp6)pzN$B#pJIvw*Gxn<1EqrlpFIG><aLuLTb1xOaP#fYkhYlLO$Y
z5@!mpi}UKj!N>oqj-FfLii6|^^<YGlZn~Aeeg^K`<btp$R+f^uCl7+iM_<oy&ah+3
zi(d-qy(+N%VTp~GQxkFS6lMMQR*gLO8ZhV5Ijo0$N(fihxYha=dVG%&g8pG#U94HR
z`Q!~+6$QCr^gT^4*Cbha0Aq;~ni at hWVB(`C^=_{eSqL9JO;PfUk4+fZU)Sh6m;O<O
ztKige+8eA(`A-HPUwB|^c~of+g>Uzi!e&9Q3bZ2x=%l6I;Rm9{Yxx6CSSQGJP%5Xu
zH5)Bep0yEDxh2H1r3=4fl_Dd~wv5UVZSjFpPGvn?3PWKg;JoW=Ny4MdR4NAo2CnJ6
z%6iZ_^4rk<<)6!kZuWVe-u26WLw+m0fs at 4hk6RXorgU2v=GSv5I3{!ANA9GIGJd{z
z^XG1LNdB9eSkK{^BFC;U;Y{}4n%~yFABW1m)&oWz&SF@^7(>4xFJ$Ue@^#anPGT~T
zrd-p7jc!>FeJg$O=!8S=_uY93tjynAf#)_I;~IyS_T%i{m_5J!?p6ik)5y~glQ)<C
z^!~}D_$^8P2|D>W^d&9KP#^k|*<(?05uj$5@@eF}^O?_I=0-eO+dL6hw13~cFPk`R
z at Uv<3WoX^!S1ljx(8q0>lzz5nwrl^{>A#t7KPuRB25fx%SMfr3l_fh^-c(`P)W(f=
z5nX$~dYdtO^Ka9p;wSWg<dnpm;@+uGv_GCz at f8cMQu~_0TI(6*)P#S^z#0wR0jzqa
zlQ`##(DJ!^6_W1-xDz}sN^g$xDt8`PNdwv7Ypz0Zv#?Rs^51$8Wr1B)wwQ{u<If#v
z4L5<Be2V@(x8#M^6Zsz8Lp&uR^@WfcF+-)`Lh}Siw|W;RYm1N2HVh`jMPLdXUAQuL
z*?)in?{T;6OdJ266$~34T`4qBB&Y~AqK>-Y|0$mR`gYCd^}{)4k;x{bay-5(G~r1Y
zUyd1Qp_9 at 9=pnm8ex84x;?ol at X0K(i#?8D&kH$O_U)_9Gvz+K8rtoPgJTcw~Cn4II
zZHE_7h$&Xa*MALX1M3l*5%5Aa9*FK(=!gmn-8)quy35n66R17x=PM-bH+B0GFtm4X
zD{*jYt4%bPr^tSZZ at trdYPv*<8Lx|y9UxzR;%008ysO9Hbn&4G5G{~V$2(0EYFuJi
zmE(Q!n-64r9p~K>7gt|xzyG8)uNmsja<cO9n)ZMAQp~1xH6&&6hW~e2!#u8?LRDa4
zcfYby?Fz+lb8AppubSG&*N;EscWUmu(Yw;h;3O{<s?s$V{8*Z<6HO+^JH7>btG;2C
zX2C2qycew12*2- at Eu0tB^Vc~}vIn5br{6_~gogdOnbDrAcRBtXuKQQCZy&BT$9rJa
zqWFfLg;rcSR}`|Y^eyE~9P5hu39x^Svas@*Bx=U9kQV~5OFu0zM=^ol-w^gAP#igG
z6pcvTn0%?USo%%i9NA3P$_#kiD1Oe#Qw;RVdN at D&#=G-}N++xHvq at Eb&DHV^M^XvH
z87mtolN<nVHuJ6t42u?z2MA6CQ@)<^zQOut@`<%#kb2D}3jP1!UuL0E(rcm-Ke5q1
z)xXwbyQ*qd&2kcw!<{K?Ep54=y6eY%U4$Wc?H8CFf2Cde%ah^buiIiWXm?Y;S(v%D
zS!7sg);r(k!rk`ER_j58qT@>NfvlU{5;7fx^}Zal176Pgr8XUy08Y9$Ybm>{`%Zwk
z`qO*+?%D<d!+rzA>^8w?{G5^^sU@|o_q|h^?u{DzBk2$rLN)|*`}7{tM7r(#0CWsf
zdE1lyfxYI6AwUiil>YDfNo%5xcKvV*;#2<1Peg_b6x46E4JUc;`gUaMq3u1JWP5Rf
zFB-CBaZK9lT8ZvCo>j-;4S|y%UmwFN1*ClJKHc0}=5h?!&dBu5z2HRrVEf7+iKXPL
zbzO~X_zpY4|ENlZCK4=<70e%DoZNT at j+fG2=Z$|eX<&&Omr3it&XVTi{QL=K3UEo5
zs6IVqs5He5<0i7i+Rc?n2 at s+_O@NX$5N4gw-rA}>(gp(3$|4mOMmMWkBh$~Fd;sm!
zc7Hh|-+9vLN3nIvYOq_6pe)ctk_J%LcIOROY8>iQc|k0U7P;r|rbukKgxJ7qivb%v
zv?rI1GqZjrfwqMf#nD$gYxO)AxX4EsR*OUzn{O>x at kH|-Ii%zr9^2p=vYSnLTS`J8
zBQmn*9+r6LH1vtxl=L=l^sge$ecoKhztJ0U^J|=)J@}^OcMIG at 3zEH{7*%yEVAs+m
z!D`J~3;%S!PCQ>fxmUXtY0|XRe|?;x>&>9LUq;LB4Td%l#8kw<-FipH7l+(ixpfP=
zAd`|8%XW1baxIST(xE1}IN^6=86!ARn+RT+u^ki#^DQ`KqTWx{n;Wr<)AX)G3q+)}
ze9GwB^tBcPvvf|<x$y5fK;F at 367QOiOO5e`s9IR8K0>_-dz`QE=E*mE#Ya;ACAuof
z3(N`HH7aDQ?WIZQX$xY2hl3P7*VF~GmB`B9h?EU+ at k*KnjaS<h{_XX$<F&<|Ffh%(
z>f%?Qd8d<={VxRO{yjG8zAoxjUOA<H5tmHFI)N-+J6gNC++8F3u+&lR2I~anKwliK
zZLMmHd|53|LP3=nxR|Xx>l#N}WOriRW>BwZ?i#D3Ui4l@;E(v{BDGl|a*s_Vzoe{g
zJWy}$`*0~@ikH-ub+2c=j{7VOXl;NR8GoPs-vj1nA1tiuY30pS#k*~Z>R|dBXI!#h
z{-brR!SHgq__40MLq6rVEicSJy(1g3)z+;<6*$aRKQ$e+v_0p1I7j#0DmED`8x6;4
zUtznSbpJA_O{GmI4Kf1 at p~g4KHyKpSjRThgV7^WKzx{|wG#w?#G{vpNObs`kqv)wt
zH+;2zrgoigcf&y5O*o#VNfyCrG!O$dCG4Hv*;EuDX at v^U4;|NF{{f^EIvRKt;|x{b
zndx(}S0rhjOyO5io9;vV4m15hexU>%+ad|mTKD8U^X-4Zr1ye=sY1n^NpMFm!XA1=
ztBQukxfz~4+zH`=5j7k%zw+q3JiQ*#as<)oWSQd2LGkp&l>JfpNp7grYjh6i6@`3n
zNWgTBO8n9d!oRt5!zJ(;uM2+BB3A$Y>}i?c at o|0mnaAdObu#32>j)`ATmeUxHpZK6
z1YF<(F@~^h*K82Ox$UCa9&c}Eg_TX8P&u08ZLqhz-_Z}}6sp|F&o!iNmTV_T--*EU
zCL|e(bgj0b%@QEy<M*RwPCJ~a2D&ROcfJ1TSKTq{{TV#1ThnZvjWC3kM5$$uSw5h4
zIaqmUnhvO$J9g)Wm-U_TC{Ies8sCp<YTWpw^Vs%sa(H9$K%AG|C1hGou9|^Z=zq+X
zM*!;1AC`tt!Yu=S)6Gy>MUIX3biduw%+=038+`}rtxKX^t~X at Yv&eBa9>2>EFCqUD
zml$r2)xz%=A|_hP4isfOBLj|FD at d6@Z+$<qso?y*jm9q#MoXx6|ImL6q at ew`4clID
zyF<SVW6_UFGdhmgH$)25)4zkXxx7hn9~?)cJ(+<zQ==nm(983g at vV3FUWY%qouAzh
zio^vD&h+F<rYmHI!Q)P35Cxrh1mYS3Y%Rcw&r?`>`+T$h9Hwp8DxVs)&vmk(rn7Y_
z^@iI!+2dc0Z-sQMq!;U_Eq#c&-kcc?yr$r3x<?XREa?yr)#Oa*aSF^*a>Yq^UAoxC
z3jJoBJGl?R%7*F5^D!bzf;`MV?Hevu<RfWRAJ(0vJ)<m>doSTSI96|?$=$HfPk;&)
zsbSF|$?20kXZy#h<}7)n1A<_aAQMr^+vM<QEMSLqp_Fd+GAb<x=Q(C?0y!fl^!<_k
zr2&0D<y}`n%?OF7uahWcM-p&pk6fkTOVu5$Igxblz<M;{c1B{isMWqiWgxWs62=fE
z#-ZjJeRj|;U at HVh4sh5Kav*Rk>$krf88Hl93ztw{yV5%#jTP{=DQ at 1kZIWKDPo1h3
z_~a)rgA6?{lvUy7v9#!QRmz&peeF<ljcBA+_(+u(pVG;R-y?Cf)XSj}GLFab1RHY|
z*+Z$#w~4-m$N^ImO^cKLAw9aHE(Hlc1?|Q{@u?ovliV8ar5j%T$h{?(NB9-}1Um4k
zXHRg^qlB^9NkUOcbl!DFgJUl2vB|p6!lFB;lDp<4{@WKGPNW34h_cbyi8)-WX~V~)
zrS0dN?;H-Ir4TEP?K4U`0U{F9vC5gQI>~$lEsJr?zY#9J*qE(Va7C~8KYg|FT$i?M
z1^g}1)!>4#y`ZfX6LytkcB1!H#S)4NaPIu13e;y=F7CxB3EYp(SM+&2!32&_sm7K?
zsTnu9Cayb%tqeadwQ at 5(IUmJ|U&7zuBVy14(!ZTo_RqWK at p09nQW8zRC10H5dwm{5
zi`Fn0vp=0|fo+h_^?m?;jT at i2Qi91JtDFEFRx-xdIEpJ27vgFHLQZPEqHh&x)46*N
zP at O<NH;{U;IR+GCa-!ux3O*WnPKk_qX*_nIUa-1Cfp)M1?KVi6DhVga=y6H*3AAg}
zXBo~RDXAgCg1(!d0`c3)5njiw1scE7xWPEj at 3;#)(+KCE16cgQfBz^*_Ui{+UtZia
zT7#-;bxOk_N_Iy-*-hu)N%n4 at dF$fN86va5zY;ET5L#RNf_43Q-zm#G!hb6Jkh at X&
zYqt<TcZz756AllW_U%7DJtn>WqoMlfbz~1}`|Xvd&)H^L(yve1>A%L%OU^wr)ti;X
z9BAm;g^fR$77nP2JEvfS>((mZz=j%|wJcuU(^?Dam_ao9$V?d)=?Ie3+$@FiSy0a)
zPnm}Iox^9^4H!2ewo1*Hp-Xc}ymtmj<1ElD_x{w!tdfg^4`U^TS>D3V7PIK+MWuyH
zF~vIXX6K8FG206ryJ9i>!XKl~JX4xX^Sk!6K<!I)d0fR}&Hnm+#C at jLEND5&f=i?(
z at uynL@I6xP&mpBG=MFS{kcZ%-CjsY3xMlp?embwPwKYOR at T|}L{D&r^bb-km9oP6X
za=`XqIWt+L2dpyb%TLc=x^1sm`E^`UIns4j&h~a_Y2QoJcakT2HdB4&sJub&Oie^=
z4_z`-@#e9;>}HnH>+ at XBWCK1NeB{I1$G4;vq<t!rlJXUNeQa#3Z9dq1ftfJuA53%c
zsatsOit_41q$OqxT&_#I`(>vz(x<+>p3Ru-2}j9t?6hyZsJ=GzY4rQ`F2$h!`(v+j
zI!0c`@Yei0t<HhpN){Cl_D at N>DM(uzSBYqMpMYPpc=qR!V6XTqR(!&}g{axk<W8AW
z%HP&;3%&vS(u~|@uRb!((xST0y-!8>duWHa^o)bm*E9WU2d9yNNxi=W-rDouTPR;M
z({(gdu9&NZK}O3aYbEb;INdhsuRyWBy=ZmV2#FL_4Y`(E8sGW)<;MEQkhNp&3FUJX
z11_)d(~&2*nhvDes!NP+ at NOl2yj;51Tqio%6C0&@!LI)@BwDEYBU(oGM~pR}=bWI^
z`AdxajI%e#p)Y?gVhht(J4U{#Dj#pU9y7~xc9baS`84>>;hUwC5qX9f57-s0QOoK_
z^&kX>zvV4M;f!{qR3b8bwa3RJ_UVgskE=x*F&Aaf5xkCw_=@L=d}etk+><jNRs!>E
ztDJn(j)~-jVufcDpG-cwRsKzebbXIRB8?bjHYG@*Zo3XWG(0=|0iRis{^RKq`R^$q
zz(`7A{CQu6GFjNj<5&;;%*7-)DV!mDZ*j@<-WE05SThN_=7ywfqyeuF>p!qN_*4kj
z)~9?dUFNp#$>(f!JC{=3?7PSB;E at Rwq}j-_3WY{WBg7KBL?*QB*ZBZ3w=;ioms!x4
z=cf8un1sXrF8jgN#gl5*DX8qhA}PbS4&Wv;jz-0TsytsM37&n<vDc;(i_a5{j91qm
zWtH|x)Wq0)Ag_NndNLf{UU`T+q-T(Dau94LVkG}h&#bzF(kZ1j)3DFEL3A at U#vM{{
zjSKk&wP_#h*`+MoWk}mN^9?PL^;GBa>A>45cfZiU4cE(%r0(#HM`718?!uVsS!+|L
zgj6|$PjH4s`QCwDDOENh$79AKen`N7q}q0*`XySYvjd2=E;K<VgCxD4PysI4Et+!u
z?A1$`e(<}Bmr-^bKru%W_#%j&Z+zDHo*6|Kn&uTc_ckr>@!wy^$BrF+vWMu^sWP$T
zF^_k3mbF at 3epNS<CSz`d-cwExbRKg!O_2f&V*O*D7|n>swl6O4813+uPcl3U<Ly3R
z6aSRHzIUh%>6AE)M*p5^ExOom{r=-}z_tvA`ElJ_|E?f}e$m<`^M3$RK&`(NYH`Nz
zxUU8D2JOcBS3 at R~fTmvL-fA_4XgMKk6l|~)Xunm-;Rs#~8Sa!6GiXJ<<c7tA!aVqc
zOqZ+geDaE at X^QfEclIMI<`798HMDw$c2j^t1S}bdazoR?dgKR!1&^%MH}^gcMI%oP
z0=`5}Ads5E78E$EuEa-tK#}l(U<VMOLMCQ~JXzQ-<dY6kz(Q_VTLCP4IUEQ(wUU%9
zgE0dKB$!^1HK%qQLfZr4RKX&hwgjW8F%=I2kO~XIq`^1vt1f_bYz;PlBy|}V3Zr9a
zXcrWNyfKdu$<ZVCkdqL+IE8C!50lPaHac^vGYBO at 5oGa2ELX~Ql;cFAuu$fgx`Sw<
zsyD88YNP~_LTmIH8vvn#zrMg8vf@$gheGN?0}>9zDw#n*@eL7GID`Y;>>Z|-28x;>
ze2Dd}j8X)OF)}gXi(J$YUN0cO6NxCgSCYfUI+Kt+p&sa!1Xh`b6dYS7n^F{_B<~*o
z`!MMSPCsnqVwPBHQ<k5k(I^$$|AsNCP?-O*+{gOkHb-teiIu6;K}8WSHcB5ePK|_6
zgaSi4s5|r^{2oDWlMfUdBSHNW`IMXzZU+VCw}OCj at 3G|rx+h<OS=x>8FpQ7HMUfg0
zx&k8zQewhhCbvwrvZ1YS4R7h at EDt|N?V7Kd>6DCELmQZ`LHT#7-eu4&iUJsb5EGz1
zzRCzRy(Yb?(=<kZkJ8!9wBHt3Q<TAy21(i`rxt03L}Ad^nxc{!&_pJONTI_7kY-F8
zrjpSwnfF&g at 6z{-ccj3F$qYfz8=2_{2FQuP&ksB{NwT~QKNbbp8YXx|Bq50;Al%<L
z#j4jv$?e5YIqW*@Clnd95!@fb0yHNfzditu_rb#;<p at Hg5r~s2Xmp^u9zDgEUaarJ
z*SOw!TiV`<;Sepjg&oEd!G)eac#;f0TD|aYLL?TU4;6qoUhr2S$mB at K3<3w0*XM(L
zQ(?HEPn}1Y#zv%n0~EL7;szD~m*vEU?>3-Nz=#AnjQh_F0p6K8(E&IVK5$Zj!BvPP
zCtxh4Bfb`gGWw~Zzpon5kLD?IUyQ2Ci`rgTMpX%o3N$W2#-PIc(~2E^sv`Oy=yVC#
zidPw6um}|uX at jg0y?#rN<n7+<pAn^?l3-#4_le~t3Kdk-6BJQ;bAv_(Q9pds^@nL9
zIcwGd|A?3AnheAwm7yx!6P^@rGG4O#(1m=W$Qm4mF#Hpni}Rx*4<I`HeT-k!{DaNZ
zon(Yb_b7lJnD}qko>Ifn0qlmLVJ4Y|vCU;v%|H}cB2X0opg6MkGDUkJid^1 at n2LX>
zplR2BY?cs#xYudlBz=T)8FB>GcxD0xVP=D$B+){=zl{lqzc9;^O;40RPu2Uq-`@{>
z6o3yN5Hx_wLbSa at -8l_IsY2jxP|~oVkfK9CKd8Dwp<*GADGr8s4Y`fMR$P9JywC0v
zS;4cQ!+g!7Wa7>Tg+xI>;3Rklhf5i*mk|&Yz>-->w3tZ3f(KHNq6w;D3TGm8N;6Zq
zDsUH)78^2yLC|cl#a#soIG7C1X-!i=oD)GpGawqmf?!d0sVMsWUoYfW at yFhFPy~Tt
zq$vgdXkX{_Mr1IRX-}|zzeTpl#-?~-R;(H{X*bhBfQoS(rJBhpsF)P__`_0BXjuZ-
zrJ!L6aZoSjzm_j_6a<AJ(vbtXa4HtXDY9#^WHo>73iVNmb0cm!F5B;!mq~n+9l~0g
zFQlb at hcgKy?6D77t6vUo3Ig*E9S})7j%8{aX^DFP$V;nY63vufZS(btm-ps$!l58w
z2iCLG(d|vJ`Urvce?QOaW#L!4hvq6shnBRtMH?`};HjYzkbO%6gU`5u^?%hDFAq?5
z1 at SkOHj3;+uN%n-Nc^E96)pyA+d-5>=oLT%V-vc_O&D`l!RkW5FhJmt0kvW1&zeV7
zbe1WT3)B#*5(I4Yg9<{<Q1;|-KCTB~N6;-VrcMg99oPq|r8Xc0fp5G6&gBI>etb;7
zNFnVLox^~}VQp7D!$gWe7*1iaEy;+)dhjej<a{~6dRMjoTP8!MX1CA=q5Xg8FZlg)
zTa%1tg#RyF&$OVU6g`x{FoWKF_FHXK57Uvc%@522v+XES&8MeBq)<KJpl=Y_P>}=o
zh8N;UoaZ+x8V|sZk%$P8i3oux2_&SEBmxNpXm=5@`R)PM)5i^${Go&Q&IET2ev*?t
zh6&(2mXGQt>5Z}2Nlw$Q4LXm?enCIibuBYq?H6ZI`m*6sjF!a-Ww{*-D at 3Qj^Z|ac
z!sPgY(w}yH!mx8soahT8{LKC+;QADq6jS<|hN=wiRFIqV^5ObTZ7AyACJcm()d&Lw
za1;Q6Py;R?W#|@6-?cXQF0#hwS1O28_)p3B<E(lM9g1qLEH5Ng0Thg^2LZ9hfi~^7
z+P2%s+?a|WU}1t|k@`g#h%A&vow{%su;S=C0mlSB*|lf#+B`Vtjr2VG!pLClFx}2T
zMBKtMNg}Kf6f_<sXA&MdI1|Y31EGeKQHB{I)<a?>#j8}wT^|2|O=wog_z_26##Wz2
z0iYit`LX?kgwg`dN<4}g1~R;qA0 at ao!7h+l#Muewi`U5m(;FW-5*MKDIfRDc<_bO$
z&LIe%h9)X|7(J025FqdTQ4Wv}J^F;BneGG)VALs=iV6jCLS|9-Km{CRxUnvD)r<+W
zTZYBM7IC5=6GU8`L&S$h2^OZvY$9l4p#s66gad>kksuKY*xz(cv61UQmnH=pa at SEV
zIYmh#$WW03r^Yl;1e6jWOcDfuWUHY$0`eXKtp^_#v3f6hxq2xCtbY!^DC3$L5j{jO
z?k0wqOT-}{RW>6R5`+bUf^0X2;y}K|jp`R!1!*B9{Gd`AA)rx at b_D_3;0nMHni2=S
zC=7w}1mv>f;4XKb0r45L$snXqS{V(Cj4=M>cVPTLvthx&B(@Pq4|S|CbpfK4C=N#_
zfbhe*Gf*c21<6Xo4c12!x3n3o)R96CaWZU$;Km6M;B!6Bem}V+j1VwI4x<v)7j2W>
z6V^beNbfN11I at pu>B-bN8YfW}IWO=hu%Ig<9&9VfA1On?K5f}GAQ=(uL--W|`9h35
zNt8}M&?KUnn2L#ruRophJEh{W at 9OxjG*Q?(JTvfa1A1eoKgOPc$Q)TVTrx=#A?cgo
ze;IwNQ<s$P9`N26g`X%N0AkG{0R!Tp*ZZidqKYZ0qXJwDgIr39dnib6{+6XIB`&}M
z9|#kQ60lgY-TQ|T`=cjDagu&0u$$eIY9EL<fyE>x;Wp0^_IAFenTl+=J-gPu4g=*%
zjP&e039IJ;D0PA?U(onJe6L)-*Z4&qs>{U^fce-?A-!D>mZ9p{Y}_mmC~pcOL^4Pl
z%?|+}a0LNEdq8}Glf9v>O8o216e2X+JEtCxKnK?(5-+KP7QilG5S^6`AO$5T5hAew
z5CoKv1`U8PzJPGq{E&opH!Zv=abrOQ)(N4h2B at RFkR&2ik|TVa>Ln37{Vue;Urf{J
zb%X<GZdF2ilHW9BJx(d*1>y}}=thdKct5l>XO_vbFnD1|-&EO5DUN0cak9^h*{d}J
zO0yJW{MiO?K<bp#$n$hjAq)eH at Pt5YwFy!sIM5^_+(pbmAa{SaCem_*Hh>k$H)+|X
z&0}zIEeH2W+Fu#&q!(<a*hX09*KuqF1#Jpq(sgdyYjnDO*3E0JAxT;oaiG?6G<b}#
z76OdofN7Iq)z2juM$u0(vaZHLq$y0{aD-Nd$d$SsBrcc^%+Bbwi^;kZVbaN-*u9%J
zF at -CrF)D=Y2|?hx(UyjD&U1noCF%$}fjLh70={V{ssuR$;R8k>&a`0EuJ4q_^zMVa
z3yMTYu`NDjME}Y9V~ys at qh+jQx`;8sVN!z4PLSkT94JLo1G at A=ag3!ADQ$E!b!wHk
zT?oVr5DYvJ;4vjD3wRxEsYysCs(F_%l7v{QD at g*(8Nhm-hoC1H?=dDmRC|z<ekcz(
zZ@^?tDD*}Mf|HPi9G8TSC5`!%J|p%e8z2S|F*}MO+ at 4)185mUs!OHNUBPLb)q{><n
zuy`PPRDG%JCG2irv+~HH9Qo5>kdTr{23jsff}XKOPbPB!fk+W3)Jg6U`KQHDg at 8dI
zeI=ziB`8EDL4ZiSdye+p^9XKKG_hvGwglP!CL*koh>PF;`s;b at MEtOG(nK)NLx2y=
z0SUng!lFky#bMf}P*+OKm;igpR=B_e_mMi82|6HsP*F3h>~bK7Qyhj!5Qss5A0>hm
z4T3g9<h<PYDD3U;$oU2zSxDwcFk=>KdEjxXy#)~phLRUKDUo5O2Am!E0d{H at Nfj-@
z7%}01heO=!)WDr9O~N7`K^&Y>!;;kn%!Uj;=$KEej>yk+Kl5)iIL^61=vyqxOb)DQ
zAQ*EV$T;^;EEw!Qn9vZ!3lP$!ybdo=yz2x}5`{4$ACxUDp4?}tN?OF8e0zl_L=#aE
zOpr@~qyuTvE?72}Ie%p-xdaV_{&WB)NDN>^0ud107_H&x2L%pu+5`wBAn`ia&aEAF
zma-~``zWO)(JcPonso9OXycklun&p@&@Dp38=yfV!$VddgPs2Aff&M<Z;1#=B6^IU
z5@&eGT+1z{0CfTD@$Y5%{AN8DcNKH&K4CNoQ4`)ortE>=4sftQyNQ6eN&{o4da~ut
zv>71>;)Dkyv at 5B&H)G}%Q-FEBpGrdHq5z7O^kFL`q>3J}0rtQqgT6YUPf^kwaH4w_
zyt)nNfngVjchowd!y1{f1fU|e;<34+I*12V(Mv6a`BU;9qzo(X|10_FyCorz4GCdN
z&_rpl`Pf)+=jIQtI=>f;fEn_gz!ZVq)-ptIYy&B|z{OWS&0IZW057A*2V_+w6WZCJ
zT(^D3_Cykb&{&fW*nj81V}ULMD_GPB<&U|5)bW5NcJ19^+#yFuwia$!NW%bYd4-0?
zLo7-Y1Ex9#2h)<HBquSjs)frwE^Ru(V%x`UcF9BT95QInM(0|-S`+{&M(sq9=>sqv
zqmFU9c*RwS^OLopy-O{L0W2T@%Hu^NzBnPyj|+z$Bb#kS>J>H4dISocAvxnE2PcR`
zgi=_VjB8_`PHCmB4Gi&`b8r$Ah6`k&u%1YE+c?3Ur_w@&Yd2ENfdE)MLaUa>daS{r
z9TJV~t|hdf$r72FlNrG at 4KW?z3str)F*$^e8HfOrGW;Q=fN@<qL&3yQN}+esLZQff
zD?sBlZ#scJ+8WE*N&FSpH^t{2+4oV^<eA?u9(UP6;{?X7Ypghm*Cs)W at WH;z9yryD
zePC>|#7<MCvY^dpI#CE8t28hK#75t#GX}X!F+4uC%1*3#PD|ZG0(fQ*BS9pf*6<bn
zdw|0dG7~Y|4s8>f)8KJ~FgWpsMF`FHOS^9GFQJ=FV|mAIc-4sVHnFiF-THShkjHVC
zT=wmov15&<o at 8K?j%yTGqsjufqeiH1_Vlm>!N*I2g&TK=qSR2aD7o8A#>VVw2EBCf
zGe>ymQa?6V7YKFVz at c!MRNaJkeY?BPt%q*#LZ1Ah6qp^b{g4}t&Kf$0GBG{0`OZdU
zg3}?`24OR0#hXYXy#zHI5XWq4o%)KXcY1h>F)?j%zV)9wd2E+?ml>iG8Ul&%*p<(E
zG1!n>b0|zXrxmU<YV+rB;<c%cj`7x2Z7n3Q%x?w5>!^XedD-bMc}>Rpt-K1o1kA!+
z#bCP{7#u=HpyW|-;UJB5ZCE3 at YqTv4i;0ge^C3>X3UFlNm~>Ek&JOEUTdurg1Evan
za?G0=hb5V(dU?xo*_JZzs5u5R-NDy~nTt7e8?Y$e4oisJb#O4cyy%*eDW#?6vrjUP
zbm0w-9}Yy4tRC>}Q($<$1B`nH4tp3up1el{40g};Y0)jr*^MN$&xK_^cDK>m<ZNX?
z!2=|gy}aLsq|J;xKTPbCPOkXtUhwHT1K|YbbSY$GY9bN=7M6W-Grw9!+vmdia1s9)
zy1%vxI1PiWHL=){{W_I0n-JqMhHg2Pq)|~hoYgip5f6;*0q8(w3x%cgKK9TCLxdUI
zia|U3miD+5mx<*r97J?30T%4$7cP!?Fg8YtIN4`$$+5t!z?KStu4 at gJ;imF}D10DN
z1cb+|RK!5C1<)iWNEw$9xxh=<?H5#vn~BgM`GtQ|d2^Bj#!YI*6?|9JL(#;3MnWW+
zXslFzlmq}$VQ52#>In75R-M6p;dr#7L3kn;iJIzH4wN$_$Dg(B?*|x*63<B_5Rv&k
zd51awLu3x%KlQx14^Z18h@=DA37j+(2%*;6T3CcPqU6(R2#;$FUvC<iXqz%}8kD5N
zNAkkphL6LI;fyu-BjxVbQnH)pR2 at 2|7o$2NO`pLMn*t+@*+{<vKBPKYNi6- at uC(IQ
zJ+sg^8+{EpaU4j6kF)6j0ZDPh20~l3>WXAB&UnI%oI$p%C&bSjEN at UF@x8KY5=Gp?
zIeKmwZN5JKZM^p1oh at lCinS8#$25}iiV;WK1l?O|f#|=x8v@^e5fAzxF5 at 8tIzfo1
zAm0*5Fz*<wDNF+9_ at _1~?di<7DiuD6S%RTg04NXx{}={o;~~*@61M^iAXy`b4x|DD
zAi at k)WLxMQi#{%e0Oj4{6!t7Y_rqut)_niN?fw_fO*2}{ms+~j)qWGGkVK*+{TJF2
zV!&j at N*ORXP61-ps%of!!ihN={Qc2_nUUm%@HwJcuzHXP;kE9DQF2C85s+<Fadadf
zjt8;x)S>Z5;t)hFBTNk<FlN7U5F|)KT^o=0hFO~!<O!q8;-mHq`wtJ7&{V8}9{Izw
zQ3^x_6mj%<2fN(qC5SlKfcXgzJA(tqODI@}h at 2JXj%CygVsgF<ta(t%YrC?a^R9^`
zfdetpEBsKx|0sZckifYG$K@%|KbS3v1MyBc0S*krA0<%QYVlnV%$dRn5fT^?3dsV%
z<Pn&0e`TUPP(UOMGbM*%T*Sj7U_OF$B!kgK50EMdhwf}!)%Mu|@}I?2 at +lHUh&;#f
z`>Fqg85g8xy~sP_FR!&jZ%5b6N{=Fn0zr%GYEscdDo^+C?mu1=Hu%=6Y+QXLK!24A
zKS&P3;g9k|08I_9nU(Sa9ic>lBe0~9?z$=01VWL<WQ$U$#TLXbQABph{jTs#!$Yv!
zLHUxE6O3y0xhB74AkEmf)M1!|-5j_V?j7bbZfx-5#n*Jpz`_Rrl!n%YCxo910&&!r
z{#}}kYrzD~Q_DGJJA#K2cRb;EvpKwm2phD?&S0tAi9_Kd7%sU3F2z1>F*&4A at Kp~I
zG8vp at FzjPU2%*@zw37f<GUQBLtOOegJqUN4N!utWpzv~V;HIb<BXRH!ZxX7L)Del6
zVp(VmjFAh5=_+|l&N|v!9TK>pcoEHv%+0z*oX8U+1(}ux!@XH7Y^YE`DtdVMWfl`r
ziKm?xi4gwTw)fzdSqt0*_YJJ_{3`|l6m}pUH~y0oJqR?WganL)rRdRdu%Yfl$rd3X
zNG4#1n}5ypJxRd!b*21h`JkAoIBrxphXcMAk9VGyM~nn+!GRKJiJ=XV12U4H`(4aO
zrLa_ej-x6TVoc_f0-#;3dM(q|0~iaU6X3}=f?31Z1Mx+MClq8Wv^*SoiL9heUjZm4
zgH;e2xKd(Zfx`lfG2Rw at 7-!hSh#k5BJDDCqRHGn1(voHX+|+S%Ic>u{=BxVVn$N>O
z!;1W^sC>I?6V33sWrPH#1}WYdI5wOD3#SCS)(rb+U>=9mR*~I!)RIVq4eh#gfgpQ(
zo{3^g_3SiV2uOW**(6G|8=r0fK!YS$fwN?-=>vg-N{omcUm)*-lo1S3DUw>;p)p~W
z1g%x9Cn6SEAS^SEy~j&REPnX66IEYA3MuC(im3rh_%=vlPKpq~ET{|={HgjSEbS;>
z61-&Iu7+x?X-(>r9pwxyfv1*o;K5|&3|NYscLC@)olz}I+>;1$OQb?^46_2n(A6;k
zGZG6GQA_4xD478TQ3NPYvW3OX9#{m7YH&PHI=|G45fnWTI&7%-!8c<-?V4W4b?1w-
z7lCrj4DycSP(g+{M_IuXft5RW00|JZcJ~3^ie*eMz?uSjBbgKxA}~aZ1mWplezfO8
zcDz{bfz%XCh%$i+5dwhF(!|irlnls=_V)D;rvQXH8wMDbaz1eR(Ljjj2h>{$<rle%
zA5(G at 6UoGUJ)*;y5G&FoqKLmStf;Pl;ir;{aN=$}IuSZ8lQ;Hkrxj{BbD9Q0dq!iZ
zlM5J5q56gnSp|q8mE0N?KgOy-GE0vd)1XR)0CZs4W5Mc>Hz#z+Y8YR)Pza$If}lwq
zR*k8aw&xEak at 3g%o3_Sd+Nf_2Pvs{da}DokTTDq1&>)jo7`F}x7AS*5Ysdusapig2
zr~%|e&j;<1keHGrppuFvVp*7&i7F6|q|bpSB%>H!-xua^Drfr~8ZCPT>A2v%b`dd1
z*j!O8AGF06`H=!a195RU!7>j*sD{uT$Ur|N at v-8O9ZynrlORM3rd;>7Z0M_kUPDKW
zmI!Rn=?WX!nkx at cY@-=JVndHGedu_?kQ~klOr77S at WfF>N!jYC4rW;hKmnkKB<C?l
z=t&6?0J&s0lsCE0V9ARTCS>=7MD;6n77mWsjMG6O!R-~W{yG`Z4#7^dMDODr!yYq%
zU{J~~M~(wZOvD%_VdD$9L|+&L?U&ICa1!AldMy(iP_$u~@g1{+6A=kPF%<$y(;~PM
zP)n>i<dSc3)7Q(oLJk>)#28~>oG$W60|_Juq=)zoQr?0DJ}Uv<g_EE*6|37u?b<1d
zni1O)puP}l0+Z;fA|%KiVdg~D!IKG;O3ou_2P--qnhvxih)8<gQ)VF{!}eg)L^nK8
z$SRo#T{n6lt=X?VOa~$>fS>Q9F%%;=$kujnCp9n4G55!}Az7W4*a}$%ED#FW1<tyu
z)b0`<BOowD^U0Gaq!7cz0MwL7BL&hzQe-|92>hY;$FEWiNe)3S$#$ko9PQU!I%(lb
zPd3EGvPug8Wd~$4HEX3M70U^RI+6nd`?Rtus<+%hRGI?Ry1Q`TbX<giF+l|bD$)cA
z+J>|vxDXOh;UVCg2CAylq9VvaR4hv=1cWIu1X2XcBqI!i70Z~o*=!&`f<^N3xQ56F
zItH(%$b5v^tPhkH7fw(^knKZ7#1RkTkR}RR0H8*YikeDMpcV~@k5fe*ja9%nj59!p
zWOg9`40*?1C at LUH<pB&><yPMq6p%Fac^Oxr7;L~X<lWVLam at o-0!~8{LPlf>bf!s4
zP|z;}(KSpGF-a37qX{t+L*c{c^#@M}r^V~yOejCl!Cwj at Rkr#I%0tNTA>B9h^z&eB
zhC&%5p}xhUg}R3 at 1c{uaz>WPxWtdU|a<pGt7$6YIF6J4|AX)tJqo9Zt2rgZSQP14Y
z at S4RPcv1Xjm^LYp=gRF(fAwL!l6UOTV-ysVfZuRoJXjZokvidM0q&WVKpau&3&0~v
zYP!ka+hj5O`-{QqV*hLj6M`S&B2Ez%iYL9o>Y|{EqEURARQx0yN`N1Phqgn4z?a(n
zs?R`gh^e3-6iP#$pn5na1Fid43h=l?kqlPBt&t=I4tMBbNC-rN3+`Ns_oeAHL5L=M
z(&8yb47eYx83YjH5DUQs9iog86Jwe3nVaD6cpr!bM3^DDGXlF;swC||j1SBU@%1U!
zPS|;E)Vp<5gaGqJD|iALkrzAdj9JgA9=A$(FaeQUDteVS$p<Ar0qLw{VLOkoxEF#b
zdlUoI$k3$(NV3qx5)~3q6je-#1gk|qqm)uWArhS8E*XJw6AV;R5kA1|2S^<bFGg#U
zIK+^os at RGR3Mnt_$aX&Lr=Z}c=YtQ>Y#6vm7Jxv6Tv|Q`KnPIq(M2- at cc+!7IGH5g
zeIX<v`~nXTuUZWY2mD^z64o10WwgUo5+MYMIwwm%-}=ApIIF~uWAl$q6M#JE<M-ot
z at B6)|B3MuDU?I5_DiDk6+KYqVxu~9ie;CCogbJcGog|qayf6&=y?%N4Q=$XHQ5h<X
z;Rs at 4!<9n^l%T{+1%`a`55lOWzpx|(iGS<uVfi6S0nuUs=s{HT0;2eoLe&M+f#2dx
z-hd^^GD-o at ne@MneRP1J4t)FiFV6)DP{DO5W+B-!Eg5$pRP$3<Rv$pRpVx3R_po#J
zJxQ&y%)nDFh7Os5;8RTGSqS7rM>ex9TAW at 4QW@FvEk_Mm{Y6mB#4>hlsK2DkAmjCY
z`e0@)DkyB1%$wgJK4bgE%2uJrIvWoAKf|4wa@#N*bkZ!e)rSGj=jRB2lQ9jA3&MsU
zYI#-h0Y|(8$w+zDAVrB#K`uq~*LVk27?>D%|FIzekS at K?H2ptjgKi~N0iJ2f`SUzn
zwk;}=XWyA72_TF=Xu~^`3 at NIi<0ZSYO&CDv=2Dxv88(ijqJZQYFAOfJMNS#@^7_q5
zt<D={=*pSWDME26DGb3%e4)`!V5+jsb4-Qz^4|8BTDc=jY;Y-Eh(ZgT$^Ez!CGx_O
z!IA^%=aK40AB*cqX#}7si3k{>pd_GxpeP8arB8wqx(%?EAu&Y62qaXfpp?kP7l_@)
znejs3qJy>|nLvJG9^4du?O<G6D4v6;Iq#5v))D at pci_4(x%bd}0qyM256l9N#nbT?
zYlJ4z5*sQ~+w&bf1b(<f%YkAfikcdTNr{jlN(e+mSyZBGL(#v{;wgj74cAAt{sst$
zqQyG?ht7}^J$(H5AXpv1P~;|S^7iRSM<*DOBFH74d4LbXpO4WLcPz6s4G1U3#@hck
zdrX$gXu=kh$q%W@=nw<*B8aH4o60ee6f|c#)Y>RC*^ryn6w$;itY8Zy+h&wSTJN!-
zbtDw at y>WQF>n;PU09G<61jrx{7REoiBHyUGk`Sd=n07(}0DE0W at FB>nu^feW()IxC
zBa}%1V-gSn;q!4g5$2FioW}J4F*Jj#pOwN==HBdy3kg=EZ}`hxO~gVNA*7OpPgxWM
ze4inLd`xJxZd&P)urjn0B`VN|lmkQtqJRdMnTL at hWAy;+CPV?D4xSF15(g1q<pK~I
z2^1gzNQ0oWNdfxm9e>Hlu!|*yD?0n2Fg~K#1R&@bV8bEQ6KABzM6U@=1Tu9d3qwqB
zc)SjG!uBWJ39 at BQw4(<h##t63AdG3wikcc1MI{b-I3`<Kf+V!0y9HTRoMi=0wXB8Z
z%>Jz3-zOb9LMTQtRabE`dMSnKOy0=ko6sqW+4=@tNU9Z<PL|R%G=UJ56ce0ks;a80
zmL=d$s|PR3eJ6mgv-W-mxPI=Z)(`9UQtRl{`uDiw7N8q4 at DFtPBqC2!xK5gofI=Qr
zvG1?}(49_#aZP^s*fSK&687y+G)NpTlKcQw0Fhm(Ml-TZox#}wpm~fth9Lw!4kR%x
zs!1)Vz*Y3MRZ!8%511!kKJV!FnkO#mqQ_}RE84Ae4ob8bMX?YnA$xQjc?@>YoigLU
zeE`b|7{*BprZPe%3B)u95ygbCWaCr|n`oC*)O8BMEe&R13L+$=E?b)jTaaIwOq5B8
z+48`&mzmAeNfubj6DD^H8WUxL3}{6GG>0l3kL1W?Ct-<z!%8H7x96kg7|SgfsLF;_
zC6VdH-Qd8(sW>7UNv%j&k{MBDt8jxvSX|J}{LthcloQdnQr$KJYXec#aPHoh3}2ks
z5M+=^1R)6kk&GfDd=s!cwRwIUji~|`5UxZK0?W>^I2L at t3^JB6CPA_Fk@@W2CCI!W
z1rQI6?+-6<IKI#s1Izz4_ZUVHR{$Qgm4X6$KRd*avt&43ByvoGO%4xBNt)RVKL(2@
zL^Fb*GIH>l!9e7XK{$@ckvZNR#0~R!&|n!Dz~t3lDbTkQn`{E?c?B{~QenGd7f)QF
zCvYAs5L3QDPOvzeTEQ<P`>t6BIC at q51f$vRnx?%_)J%x*_B{gCD8kZ=X-hEF>AgRc
zLyV@}bM>6&o4R97;-)!GW-c1cKFJ`SBfBM9cazYtJz*lPMDzk4P$_yLRI_A%f#p|j
z&#XuAS)@1)V;%pK0)fZxUMhzJNNzZTU~~>o#17c2fv|P<5DpS2E}E+VWx?g*{Ub>p
zQ4v${Tp%b&2<7F|L=6I}l*_|ML}JGQqVO_M7>hv|MdLC{>?T0XOv<35!Bt|4EI17A
ztoR3w at F~=xUtmz^TGv*2sv#tY#YmXJO$pZlIN~%e=s~{#VcZn%6iJh at N7r2hu!e7s
z$3y8qC+fHq)IuT6KP+Jb1du0zkKbe5nZ+D{=!3lsjM`7ZW*F@>Et#|pgBDDOcv?VL
z2w)6tB`O9NLY-pV9Xr>I at u36Rkpc-fkip1D?RAAAxc at t}8UKA=^snKpLexn!!Lh?8
zvUO?Z%;cMK+;~{VQU#`Fef3W51&colNnZeg08;c)z%Ez|HbA at qs%%(C<%qvl^c4Z?
zr3nbf-1*bjtW5fyp|3yq_YRrSuD45h=?il&ov#}cGZs(9g(2Vv*(WIp1n>~XU!3qV
zVP?NYH#JIbL`q>rb7XzDCgdYytZu={XjcVr!2>D at m^p4sj7kY(>s<wbF9iTo01h~l
zh(U^tW1r1Pp0o at _N>oqOL<Q2%4ec%^JobbnWe at p-PFkRiqCW7ug*o9e5(R*zA%%w8
z<-mKoG!TeDf`lN1NTGmw-#SIb%t{l*MIRJkffyxH356koa`x~%f&V&udL0mmbe+KD
zHV0 at TdeVy4)?KnNB3?~75to2bOwDr_BO<7S32Yyq=gioFKgc<NYZK??k((yBm0Idp
zx%%Kek8UailEA?O!c*r(5fMsGv#13?WcdGQk9YcwNK>~9zcBSl at +heTz+qU@f{9T9
zK8E66qvr#W%T5o?wZ#F&z^#vQzJ+2 at z)ar6xx<`Fc{tjr8WPGDq>dB`Cq32gL<}4V
z!25R|lH8QA5W<1P;^0U$zk|gKxdZLa!W^`fwX9%Z<lEW at Fh22{@ghiHSF|^(_8_tm
z%Ak_dP+6a<r&D1-f^Zm-GesUHKtBfP8-gZ{&QvTY3i+Lcz;{xSY<{Ve7pXhQY^NZB
zNNbFO0!)NqNHJg!9f%)Lv3Z<EU}6jb)~UkJcZ+ev7D8}SB<V+22u1zl;uip*ZnWJW
zNK1o5LeL-6eE^^LHhjjFJ)y8HJGz?z%kGH2g|{;?PP##}m+pL*##zSJ(1EZzB at XpS
zcOaCo?wso5Vg^x+EKv~zzy%SmW8ciN2uD+u$#&#*jB!{b={m-W>4usLlo2!pnQVkI
zVeHA0O}e|4h9t#FNd{2S{XEZjIw2 at I6<yQk7+ndV<g!Yv;hHyLp(YF^WW)x+mfe#m
zGgCd=&6e-<2OGq2+SwVsOvs6DWy5mgF87(D!FJrR8E#ZM?{E!j3QgvdE<(plaa>A}
zNHDIR4eUZ?HL_|?`p61M8Q0;ZlOM;{^wl~u7$KcuNszYG0i|m!7!Yg{wgiK*4oA#>
zysOlAJ1O0GuY<&;<)R?qXPI6e9=tCC4y2{98XQC?2~3{yXGu11Vt!wzq(u?}rUF_j
z{?fxru`gik0qze4)L~GR_z{19pIQolb0PB|aJTwL00G*Ebr;JLq4w!)02skyNDOKU
z8^+JY+?K_-ZofiUDGc7xu=b@;9{Heqe6j}F18jk}bbJ)N2{2$JBu~P&h=F_!?&2}n
z$h;v67L$ZJ7t1|d5G)x%-+KzUW2gY+0&+T0u<E|d#G&)|4_h6S6UKwU4Dg4{4_;9^
z?Dj<*mXQX4mPx5#`>s7l=tJUhNmhjhRU$&l7(@7p at P>f^b5<n!C^j%oet&HhVOQNx
zlo^PzT(Z)Ydx9PNF7t at lcMuybDslTBN<ZHK;se1DegK{r7&0lcNK=fU%;%%w4t6(R
z%pP#(V3JQj(F2O8h7|$%f^)_FE+|wakQ2&INx-OpWJrx_0tO`rn2>0MmO~p1nI<L!
z+q6<6B1H>DY$0X(x?#BXGFj?TBf>>M^IB4*9|0tI_;%+B3L#?-mqq}N$t3__WCI-O
zVea2>5)@8plOlKcg~~Yeg-b&%xsZe+qKK7tSdSEjiuHym1>lOnj`mxc=j?%ruukBc
zWDULO`awhHllu=zzDetuPC#f9gf$-`qu>V)0Ed7m5xPXkN&tIdN)aOihs?Mj88ye{
zO##VE2F at I=Euw`ARF`B!Kxr_;R47rqmlJ|QY{r8 at t+5+vU<_RDJXqlPa8e~|sRJ&}
zEJ8ePbV=DbqGkrTfJ?(F2AG{tt{(z&61WMIv9JgMp6wD%&9#I;*IGcT%T-N(TQU*^
zjAHCiIiMBYrC;NUv`HhrLN_eXorB>KgytpgPvnGeAUgc)wve*n0%PmL+qV<sLqFGL
z6G^ssNRYa{6T)~E6OD-VbMKS#5aEH5M at Vq#fYTsaV6L1EYi3RkJU>@p$;XVCOtAq}
zf{|w|ERBg#Z6=fm*@_?Sy`mj3STrE6YLYCOp`D<@W%wW5FN2*aj255{F-vR%Bk%pM
zyfXjVe!yy^Kyn;J_z%bPeyz1tRwkj_F)US66qK7_>&v<W&I0<*Bj+N-F;a~p5e2Bo
zgT-!jRC7aO1&`pX+>0Qeo7~|JTaNvwMT9zHAr49hcpjiJ-8sOZ0$FczdeQSBRE0gc
zxO21&5y%pLe*Yg)<e1M?2#{1Kv$kVIjR6pZrdYTg9E=Cpp3p)PAap~=qwIU?DASl_
zpe>~Z!R9_l5S6{WJ)$`muEER*Cjev6uuPE_l0&!b4 at 2)_DMy^{AmWCB0|2p66FAT^
zfU4(9lC%D=plU!j#^<}-WPt at fFl>r|DCuENP9PtA0q74CB4R)?BuUvZh>wC#hDcJG
zOc at a6Lcp?mkTWWsSuX6Ahf82REGYpHePDiTov0M0v0UKMVwA}ba$N8On3xFcm#t-#
z3uY7zh$QnF7ls$CKBHqaEA`0{UgUy6fh15eKH>;;^-kmDItJ1upofTg1;fC70qj~-
zXrh#u2!?`$C|=!`0ubx4ITwK}6vPGuV+kOzz&m^cpz8d44ik_DVsZ|nudM7sdov8N
zC3ilOqPdJ|d%eWp>)dVwnTCC6Zld&E*#p}d4Td69$+XEu+HL{dQvvgO4QUVDkg>IY
zyA+XG4m|`!Nx?aSL%w%23Ant|DH6G3hc=CAd5r$Q0NgtcZUc}pIDBn4tjP`#(a49S
zNkJ_p6f^M5aX&##IH$)fP_hgqw68Q-wd at zVqw<FN+X3?9fbODds3vA>=R=&483;3(
zlN5M}A^VAXp at K>VrWNdvVrroSayb#(MKT4AB#zkMk7l-(^C0jWkQfHo7V;sH$TE!+
z!i1qw5nw?e*o$L=dxr%sbUf(}h+QD(5&^+Bxu0{c-`Jpk#7OZ{$Z_9wbdIC>8 at _?=
zqelcY0Pev{91gKrGX)I3#Qv~Ie+|24L=v;FL48VHEGZtI5R8cK14x0(3FL7SX+)02
zt4h6wL?Fff1$?Jy1?fl-xM1f}DT&~|5xJ4IG0f%35x(VxiTwfKht0<zVZ+`sLxRe=
z1Ff97_3Kkad9nuhgt9qsmkbA`hEolhV6w4U;Mhk!W>BnIEI8}?@AQ2a?bu{M2r!TW
zK~$LPr42gcb%J3N==6Qj62+1Q&?3y*rDI9v29oI#0c!2A+ at A_F2N7t_jo=#1z(MGc
z;<*+>mvx((_2IqK)|cNa08>(!BE}*0GIU5pj4Yp>-`kBcs+CVLw#JSNFA`<-E at uqp
z1#k>dD{_^w3qg<wx%Dh3S}d5}0m~%H<MrH;8rEtDfFzUTAz2WEW0(oV?k6c_u*bkX
z$RXeCEo3AB$^TIRp&uLb8c{U(^R`O^AT)J_^B@<EAp- at 0oY=Vnl342+ft&1aj)4bo
zLB!`r6E*1RLmshkEHX0!<rIz9-!9azpcPY};lMu=!4&L;K~n)r98NuA(RA<t7y+np
zHA_T>xN`(59zgjf>@ZiY at kf*#MezWS6-Y>AZc@>*4m)~*&7_D(GN?z at 4rM9f3ObP(
z;9M3KV{qwP<d7>0yM`5jltGXpdr~{0lf8pVfPnQw5Q{$oYtsjauppLmp5%;^Y?A at 1
z!}7hJUDB4K)Pf3EnTH-*`0F(X3{WZo-2f|Ug=&2t at 7MVp@8g*k1!bhbnDXum%XQot
zSVUgs at L&_h?j)7#L)d(CK|;!Z5_KHd^2rAICJIBk0B0Wvz={xo5({OyaT56p?tp3o
z!=O~?3KjAv@={m`rHD9M3NUPIP(Hl$bnO$!XtWFD7l9)mvLY1_9VqV$Bjn<qeqjcD
zy*}?pO3*|GV-i71%EXakF at 2f`@HaUSBvf56W^^tjszw<Oa84K1=;`*iXTHjH+7 at u;
z1{tVqJGEdLM1yi=)v~5DHkL+^PW}8|p!b+FEYuZ3K$K8SNdyHUAD(hUEQu6(V at Af=
z>Uqo=Z<}a~n0^+HLef+f0CtBIP*Ed5(+bfEMp(txQ&<Ux2!OC#Y?DnOti(eyQ%D4R
z4_6LN6Hp!G14wogv at JPgPp-}C&bi^C;Ft(QCeiVyPBhG+zZU5`8=z*0XAPa(k<P9n
zy*GlH!J5G47(&xz$w_l3eyjk%<%*0gX*QUcD99Y82{O;#B_k%c4Vl{Er<;y-r);l1
z@)8z6!zRW~tcrVBWEr8*!)$?!npnU(1F_jOB`9W03*^iEH*gB!e}f3C_XdWjPS2<$
zVF;;m!57Q?IrJ3z<btGu7BG?{2Z%NNGk*X&_;oK22)a7jd#UtR!o?PzfQ@&CD=?!`
z)(sFM{M_0i>ogAxh0TG8LHUtI@{d&g`9nx{NRj~qs7HkGBmx5a${uotbI;v7oGu4I
zq3jdOBh=SYat$hJHUn~NpObmL80-NjVPv>u!$#U-6mpSQGCItGwi*=|Hy~^sYM&25
z&i80dE!~A2frGh(@$R2od4MuP$QHK}=p{gY6}>t|p!>oA-REbGs at r5Oo~qZgdx?A)
zA?G&3(HM&aBn3OVfq at k*>~*Jx^TgEx6)1u2*l+`t%8EZC5kOQ$M&2z&a3un;#PTEv
zRM2c{h9ugptYHNB*HH3DqSkd3_91ws;=M_anebvsehxOmVqMYFd=sFyMgLI~wLXLA
zk&;oq18Z+^D&IgC&L#A|eD&6;#p$L2kQsflx at cTu6<Ds}Wg%)OUsHZ#+bqIl1QwCV
zA}w}5psDAG#=-n%Mm?6Nd9fM747%D6HC&u-M4$mG2{k2Vg)nxl!1v~gdcH`ZpPZ2B
zWLT7#n0|~akPp6I at j#3h^%4>w9w^!*UKe+42C)#jvlimSPA^d6;K2ObF;d9QDMzA-
zbt!+yKh2UcfS^QRs%jG;*a at N{d2 at n)SSc7_nV?vyRv?B3At+!aW(a~Hn3;-bs09rS
z&=`y0KvI8Fk%D5h(n|FhDda?B7)4)i^pqlSQ4g37?vN)f$e>t&F*2lS1u3Gx5Z<3C
z0Tqb%BT<4y7%)g4UP1xoN7KGRl53ZpM{PRD_=o3nctJjacu>TX`eb#7i5 at TyPrAGh
zT=kncn!66Z#6_K97?6yE3Fsfv$7H%u#vYL9iU%CZDnSHLM5PTtF)XzrAr^=Q;sJp7
z`@69mkU)VK8d9Sq2vrg+RE!XmFacBv-gza>&J=$hy)JtId>IAf4L1@%*p*1YQNsiw
zL=ep(={pE|K|1a9r~vZ9DjlL1AVWs^kYz|lL}WeT$EQ-EvYQM^g)$kqMjn<EOo~B@
zdc7x+4X{Hx%d?=p0f*`Q(=zoNJW&Qo`h*caL77D4;zRK7k%riQhV+x63Vc31uNwPl
z$>7S?dphe>tu+>6nEuUj?%&}l(G2*uc^y1Ht}q!l2Ei|AGa;MS8xwVnvPsfmG at T?5
zLD3ABUrXj0CLTVg3#JH<A`bnNCx;GzajRv634<n()&{IHoj5XYLIWpCOmVgDOVu=;
z5Z4stn02~#nrDb~@;pAx8i1XdSaZmEQj at jsW<x;Ue4y)hRDqOnEejg->NZwO{x~0V
z3xv)w#%)-K7*ZyNX#7TZ8pfq>?T<mPJ&ZClQNK7pStXFzvY=?S>%!M(zIM}j<b+ep
z1{xNy?I4SVsL>(1r9ex7_cgaJg=SVZFv+kni!?Bd_YT92sq#3UIR2sH5ZZ$YWTTPZ
z#$jWGJ_$#*@lEAhL^104^+d-yG at j)BUMtga?>y6dydz!LHyxRD!#U!t)4U%R#WKe+
z9-4Fpt$~raTVe%?r%9sUy)~dAqtnx`Ut0yPHQ!{@bo~MEbi8wj<jDDBk_R+<`io>B
zLK3DUJX6gYa5<o9#S-y4KnqJ7I!*dzb{k;4L@=%QF`;t at PL$;w`0L7CzXQ1$1_Yb&
zqq?!NB=vUx-E?5C7=UIQmYyFiEzVKLsoNZ8_uy~Nj<Z($xYsJFTd at ljzUhL)5~rpW
z%LFlkl$CyzV+`g)5Qq;~C^RyjOe}Mu*^GoFiQFS{2BbP?ewl7-ep>L%ywVsxKF<Az
ziEGe%&a%vmzRZRy8ZQ(n<U#~eO^!p$V)mKUR}-CTUIq?5&RANK<BAy!z%wwijBMzx
zDV{qBiz*Bmjw2<R)-&aNuvPZC9 at rTML6B!nO1;h#fd%OgWib3<!Ad0ub^;PdARGd4
za0dbbf&e+ph9Gzv4?Z9su|x2a@*jp4&_63AK|htBJB-<|wb=bA3smxT+zdo;4W${0
zY5+lgPQbEl+RSouH~IT at uarbf9Mhimau|jhH>W30sCHxG^%L`QnIsN`D2~J&LC}QL
zn=O)>Ap4sM&Vx*MWyz*PIW(1Ajz|=P0N^@0O at uTkV89tVm9>JJ5Y0m{S1?!1ULK<$
z0~q10w!`TALIx00f*?SO5hApD3GxAC3kdumMz9bVlnzF|zV}U#IRLY$L|zHhKfKl1
zu}K3>XV+oRV!;=zecL?<Thj)?&)SfCAfap$CtK(Q4Sh0zWZ}G8WEA`_c#TRRrV>sZ
zVwu4Uj&#(9jyWU_4lJcyyblK)NrwxAa2bgQ7MhY<M8U^EfCtnv>URmaXlexs3dtvW
zN-9f%sS63TA2(IVtfP`sW;R$d<!Zzz`gkpXlFH#viIfXraFBVN0^Dk%lzjr<xQdC_
zGKi|2PoIF8Iip3H48#RrbKRtlj#!_5$R2?Z`4&D93lGt-p;8 at 9w1|WOfH3lahG*}r
z`~XA1J&8(tSx4h4P=Se|LrA7nw?N13<hc0=3-B5rizeWpM*@1cPlPTuyuFGg_9s^Q
ziV$*5==dSIINY$0ZbIU&dG7)mU?kKbgX)1qA-<LB&t8k*HORyBp|K`r7%<kuCS<D+
zp@{NQc&Z4BgY5Lkcaa1`G$$1BurWGbU at 0D5Qn+@qq}G`1mKI26noPD73cqEc05Um{
zl0r=cIT;>xk~$;2te_?;z1anud6Q%_%mPUix^fJ_&I1A~B7}<A?uEY`8X5ux#zDhj
zXpr2mK#VO5MDwvB!{uaq<WwXne5HiUi^*8%QZ0)tkn#*QJcAD&_gI=33ojOxx95<z
zA<`|w{pv|GSLhMVoEp-q=@M=v*2OomCbS6aG`iM{GzM9hy5LO!u#;Ai5 at kgOvq^;7
zc|o^BsNUbeaYwi5n5{%%7(_uC08$Dar8j_j;9BAH9G}&j2{U>%qokU at 4H-c#s(gBu
zV#%#GHU^+q5bzebNH;KCFgTgkZAHWvIE at WSNF^j1ZntU{%(vR+Z{xqXp1?1mPR9^#
z2(clgT1_Wu47doQr|?jvBQOC-L at PlN5EM{^$w%FRrO+h+QA;gBLlUJ3P*M+;D5dF$
z?1-*nyxZ)-VoWq26_}by<enYj<0J#a{2d<Cw at Mg-NeG6KX&@>Hk`Wlee&CsxTfO*<
zLz!5M+Ki^EAHSc2bX;~N*=<sbk&#Q44)y at BM6hDkbIcqF<}qX_f-Gn?lVdDGPdH%G
z84H-nhd|M at CXp)`*vwd10?CxQ!-3aE4y`o+#%2`~QWUvkg-0C7Vus$6BEsC?!*7bf
zv<P8hDhb1VN~W8f=IfE;O%63d3A`$*bmA5A_mPB at f*z2_B-*mGD!@oEAd@|fmB^=J
z@$O6#0X at b6e)oZq;|PgaAkwG=YURKbP1iZlWS6`k98o|*dnBEFI#2{SfeMdAfxBZt
zRaBLVN=5kt-A0|WZJK1G93c!152B!3XR-N6f{nKIO^tiC&epcH>CmT5kD6)@t%q=l
zu?;MIT&0Zh23wJUIL4C}&;CH|+a?1y)aig;FnQxhU5Tw2wF2=~5)E`dWOxQRFqKH;
zAi^cmYzq~$BsW at fcD`g8!{~yIlu%;gBt~H%>T`E|Ml`=;m at hD6i~X4Gji4iYgp?t+
z!$U#_24rnTG&E9_bcHK87&p4<T5A at n{2{e5+Pvq3Ow(opR#Jnz5x`@@?5HUWu#vT{
zSyW3VM`X4TrKz0Hb5NwV=x~}!k_SpT&R at S4?k)spBmzYV#^Iwi5Dn6z@>-<Dr$~#n
zO-h`H8m#74q(uZU$ihtQGSiR<fy3`bQKERqdEC*W`WeS`3NMsqRig|8p$9tFkvga|
zq55TkHqgjqUMDAZGlWY$OB>VF$nGF4nB%-u<%;-kJairyNzP9kB{@n78`j9oq=heV
zTNwsof+FNrNr#k5iolBqByv(8frio;4DUm<12YJj)IN~A;tgev9-Q?NJCn%~;o at sy
zg<`KE&fpIE?RSSn at W$PYK#uHWo|7cA!GLmtR3&?FK;wkwnc0FQ>;a>DFi61cXyIv+
z8>H;Y1#c8H-C{iu$Q_UsjE&h!&TO`o)2Cwzkj;joFhmYSMq+|V47Ige;h0`!(uVHh
ziY~IiQx(YW!`z;C3xdbMNX`W2A-o8J8VrD24#{#bAnI>dhghMwAWOAX0N|6jXet1p
z$ArH21PV!k1E6*f0;4A$UKtm$rsIM-<Bjdu;RQ_g7NjjKr>GEfD$Nt?+4h1*6bc9$
zF947sYZFDWg6Ny<&>?aRgFrWei%A(aS>72nvcpn$9TZ%fIW&e7TM8YdNN}taIPEM9
zrssBn(#Ew|rW)ZiLjo7g0LmbuXU>!Zh;%^E9I;ng+eXD%F&~lUvJdTqkc|KyWC&su
zM4ulP;-SQdl!7oK!Xs?%tEvs)B?@GR9#`G}U}k at 6py;aUMg{vo{BP_T=FiNO3`RVe
zVQdV-qRPakIhCPVG1LJk8A%?Dk=F!QffF&pPCUuSmhxWBkO~ljBsQV&m at ycqu;bgC
zrQYJ12V-<}3$2jUn6BeqFvC4P#3SBqsDZdbDP^StU5?qPU2h=-eMp3qa9ZOV!nl;%
zinJnU9L;W7N7`Xj)p+nw!rloL4f0??aBHVCYDz)`BO%UghM}eOFp35_p2~ku;6#9C
zh2z%L7K&(%h(`((i9`@g(Lx>j`*qGPUhI-;0B{uh at q}3sSd5stepG<`#>`?f0(9_&
z#dBE=KtOCKS3aV2%+w5*Auv<a%}60i`mHHq5PO|e<Cv3z5eNym1VSVsqqbm^*-bDj
zkcinV1(l3BZt_WigbL>L86-e8Wt%X>lEDa~nhnI!$X0|eKpv!X0*_$OM=4bi#5kyt
z-}r3^5RoAa-f71pHhB}gR~17$6Hiag&u(u}(eH$k<s>0eZ6{FkeLIKePHm`+koGL}
zm(rDDC<4Yc5J^-9{t)TQ3xhVtra(pHgbG3cU^t0$_co+6E0}o*SPB!wVA7P4ag-qp
z1&hUl78o_pi2pR>Y6F0lOaV`Wz>wKg6(F at 8{s9gL@%RpdL`EYYJ>`|N7!V)@@z9V9
zK|A%xa6yQ?cg5WB9;$Ua3MGRv0EhrMeFqURzzl{Nh}-<!@;w|-bd|b=yC%xtzt=?R
zyBR@|!h<$n4Ibxy44jRoKxuI61yuonDcG#84x`BO6TgaTieUn%qOb;TkawzrYsp8T
zp8Qv3Kim--`gaqd1c^38THr8Xg$S-u1*I2qzbFjT9Q{74`%8aY4UCaJbM)0v`7jdl
zFcLG&C}EJUVTMO7?qslB7<51}l0_jSfR_qG<b4)Fb`mT*QXfGE;08Q%4Kz^I<tqDx
z?HQKW>+G^EMDB`IXieRxCsIhV1Vf*@rmkNin_9q|Pf^pt$RE6b7CS0=pImza(&&1s
z8=!Nr5^Fh9dqR{u6cH~JNHFd;2QF at 4E9#}dItYN-f#*M^`Y%vF)>k`lh*%)e7T;aM
zHi&(&52P2&kUr)xj35MH888;i2hc_H!jyL)^Ph at 8?so{}2Jlv-J^^3J>Hbms2*FVN
z5D$?(;I6;m5F|nhKqz$U0|^FP)k2qt;Q+v195dqD%>kI3CP;Az{nSt$V{m2M$4Jvb
z at puQK1MdeSuf&U-Mu!sS(fcu!X&Z{*%o#J_0sc}!!S>yKzf<W^`o=;Y<e#ITGheGF
zwYYE&OGSj$3E`VVm0BBMIi(f-El0!jzw0f4x$zJJMM)M!WDt>LL^~c;2y}uUr$rR(
zA;3`fV1_{Ofi?&e($9iGihkx0KajckLQ)#N)`UEU2|mi at V4;B6=N<#G5kS}Nc=Lov
zK*2-LZb*B9=FpJ_bz(u1iVQ(45o|^FyBY-V4o^f$05yTX*e9rq&|9ENQ2l+x<Hdx;
zMP&mMe&z-XBLBd(e_ScZJ&wV65D2jJ!?Hpw0ff!X9-)9?(5J+Js<k(sggj7V2BKm;
zSTMoX!APYgB?y#(K#D?=vdRbg5S$Q8Q5Z;wUIc=M>K^Giy8WK#>O*yzx>w^6$p>xA
z{!>41>(&=7Zg7eR0b at nKvePT|=1gv_aVI34h4J$w`eC&@{+KK$;_jXO)h>k0O%-3W
z8RQRqayg3baWF|=dmT&3Nw;Cl42W`6BvdJzS)0|A04$-g0DC{8IhHWcR}d*QLdQ7S
zQB>H-FkN6gfd3W)2$UC7Y_sGVWQ2nwmDc5KLjl4QB8oe_Csz1e$08TLL_#0brB+3#
zC{&Q40hT<~ft65kMu?shXpxT6T39X0kU!Wrh3u`>!G$Sb*qNsLC#_qagANz$jD3Gf
z9~x4m2}%Zv0z*h4NEmz^Rl*%ltjTPtVMB+x)M~PDfgmm<BD<LogMYA!g&X&#^$&9V
z9_&uYE)2vnY+Gn<kzi5 at V=6lXa<AA)>h;~cBp__GG$jCDe1DH_A5Y&x*gy-QUfhD<
zBrDHkc-=0zLs{kn063(*KWm;a+&GVFRZIxCCtZLX-&JHHqPsRTG-6h5XLq8Qe}BIE
zaHeOau&D>O$ff<|0ZOZ at W`WO~gpzw+a!q{_##v*7&9&q;1r*$MB0XXm7XU+a97O;l
z1VRxxQAz)l|E#DJv>xdP-vbbpN*x#Vz!o46H1>F&J_e-j)SyR86jCaK1yxi;=gd7_
z77vcj1DJaA6o`tXN1?!AVj^Jw0B2S`CPT8nmoJL3-5(>k?o~upQxMb?R8)l5jlsst
zf1~jz7w3VdV20ZgLJ~;`s;|u{L_vtEi1hJJkAF}<tFH)FhX9gBNi#sQiFmPN*U`2o
z$A!9UtlSs|tntq!{bkIcd-5Ik{px^10*BpW_Nm+Vp at 1R*YVuf7RL>u*nrC|x*0JoC
zHc%hXNz!ALV~-=JP>glc!ckuNc9tJY1IjT&rI&eD!hkTwQG}H$k;Hzn5J3nqiY84x
zFc6xP*wA9oJQs&B&h|wSeW0M|DJ+JCVrL?145fz-4B`~37>0}sS_;7>#LG$+&%kOV
zG`cXtO+*jGij<~%|7iUnA6J>zIphIzZMgR+Ku{v2NFIPNoC2d1U7jR|kx;%<Awf%e
z07C)bxIGIaElM<%N5|!mAc8>oy&ekxT2xE;3DOx9eBtdXKc-)kLr at Si6pKYtgn&#-
zLPUtc3VyVKLQtV;h7h2DiWH<;K%k)tq7n*#rkJTe;XILOf+0j?KSZD1Gyx?`42R(e
zCSId3ngA#Y0)U_`HLw5qo^0&MLqvv<azKB*VLK8ZyD5YquG2~TWDZaSM2PZ0B3HRN
z`#(-Nq)8AT at yd^>2~HBBfC>ak73Lw at BwWU$f)hWy{s-p|)_=791`!kFKQTk^3=a^@
zf<gt%$}nzva&{~$j6p^agdv#VXxQSBgJUl25=i3=F=K&a6iI`*4}hLTEeDb4Hy>oF
X8U at k{NPeOd{-W+krwS4imrxHN!XEAF

diff --git a/target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-exp.patch.bz2 b/target/device/Atmel/arch-arm/kernel-patches-2.6.28/linux-2.6.28-exp.patch.bz2
deleted file mode 100644
index 9417b3aab6978d0aa82e293750cc2642bd3f292b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 56841
zcmV)gK%~DyT4*^jL0KkKS-+1mF#$~fUx0u1|NsC0|NsC0zyJULVMY8MQzG8rWCz*q
z7)RUdTmS$79_sF0_fP at QBW&-m1~|$IDk1C*FRgjkPWJ!+ZtcJVf_4q<+0yfcXrE_&
z?q7SnE~LBfUJs9!_rm$Tz0aO^aL693U5)79Uf+Ga(SQH|-tL1}*gXcP-#z2%oqa3M
zyUzdvpgx1p4_$k2r4#@Z6YNl@&#~UH0;oLfeI6-Db>sk#AOHXW0000Z?tR|$-rKkj
zPql`gnxon7Xay(%@BsRuv;a}i2_ON_dF#8|X3s0Hmb(jITi}*W+qZ4?UH80wncJ_u
z#*p*P>U`;4hud}Uoytj1Rm+7H+|JptqX{g-xy9Xj?s>^>XV<;3dwYP;q3pr;Oz;{G
zI1ftt45{Mxx1K;RV`dl>rCQtEZq2lAbiIA;^;*StWdHyG00Kw{RbKg&==Arw-(ORs
z?)tB{oCyJ-YQBM>466H$R|W#xTW5X8kf1%V1#ZTTWK)T&V0^Nxp|bQk*_SdKYb0%v
zkkKmicUG-X!uP%0_E0Hw+LJG at eS6*weAosj*5&|jZ#>%1Z3Psq0MHawSc>;IV?*zu
z_q%UNL6x-t6t6+2riCa1_6-$4qJRR2*-vujwp&r_>(yzzW{-X6c#ZT2w|&|-bJaaF
zSZ-X~8zoun2cEaB-pwBOMcgMHtmhd^j=MWMmWSKg)O$$wR->$Uz2IZEdT(F=0B(nS
z-DREcCULNF<?cM~=eMcuXv=Xi4#PM~qwae9?z`W0PFuG5?Q~o0Zp&5N19KfOZ?B(k
zuG at Olduw&?6CK`8#e2JG8!Z?p?Y2ugYkl7JWk%CSvhBuo+uPmljk&JvTKl?k4}F8X
zo7C*{8=T6b8}8vb=hXV>dI~LkE%$ZbbGtIzcaFOIl;_xc8lLp?vGnxyR?~fp<J>uY
z_s6|TZP$72n9)io*Ik!&wBLNbd;$_g2mt^D$OzETO)wx65rGDYkuyo627o0r2q6ig
zYBV)8(@di&=}*+#NvdyD{UM5aYA`eaOaPbxAdwOQ0%?eiH1$0uN`8srH1!H+s&7qA
zG at 5ND(K2c3Z6=KdOd%;E1O#XRN$4g_hLMPAnj&lz@(HwPM$%+t$k0TPfSLjU0%<g<
z{!`LVMyINu<x@}9H-c03Pt`o9l=VGEo~Nnm4H{{n(+H6eQK{rKOh$l4k(wr&WYbjf
z6n<$_^+&0+^&r|to}sk>8|@!30{+k5ImT1oi~-Q+Y at 7}WqUpwjp-PepsuKjb72snq
z)g>9&fXPvFa2Zl0`(vZAkisDY(g?5Esfg`liUa*{=zm0y+CcI<U-XbU147b0L8T#j
z&!_76i~wDq*UepRzwBS&Ki?Pcf8<~zxtlo|{r`V%BkLv5WQEY4`NZY`)EI*O+ku1I
zNomSK70U!xlG`zsKyqmjJ`9jUG!!8(At|AxpfpKXgHaVV9xMDi=Dttr?fy<5&-2Up
zen;ZNSMasI at 6unK+wj(2`5#eMveJeUW at +^&(}(T+jHcIrIA()ag_u=u*@3FWMT~7X
zZ=1oF`wRZNKkws2f9h}}+I~I5#JdUP41)}_3HX8!QbdqY9ASn at 2sptOV3{6C`D55j
z5hq*&IvyMwb6H#&<FprTKHgj#`)KmFiX2&+cMsvi at a+6;vdZhP`{Ui&4xKskcK>;Q
zUDMmmFm#~A#qj;jNuhkOSZw*0f0^vL51c>uSw;->{Q+>}{@@^QXOm-HDUyD#{o!TE
zU_pSwiY6se{<97wPn`IC*g7M%zb%F!qw~hwgmTil0)QifsL?DdKpxB23DG?st*WZ1
zC4LqwVCqkQPAzV26j2aC@%HBqrh^hhG*hH#$2)b#j)woFWSW%ai%S=71}Z3#pEGsJ
zauZbOaY5s7*+|0}+-PeDO=48g%~%>dlG(Q`wkKm_azqUXY*B)PdNHD at 2#})^Xed5B
zb#jE#rh$l{)(fMCBbp_74kD={mIaw83FXN+9jdCJ*HXA5mI#po4U8mAL9vF3A`vc6
zxq8oE*baFG6i^gb5<6!cmq{_Po<}9)Cb=An15T);n at oifv$UB2xx*ptl|LgXL||c)
zEq$;*Q6V^k0Q<d#KL4}ZAH$tshK=+PYn|z9;f6?#Pit^Jp7d2V(b$io8)IYnA|`u&
ze)C^W`_ud#+~nFWi5p`chPkt}Uz8B%%HS4^oBEN at 2!`hb;_DE{fDnDmeu$=RA^7b-
ze#heco5_64KCGFDVi|%Ga7&OSCP!t=1jsu$U4bxv;gHBkPv4YsLk%#?7xrf~F#<qA
zNizchf&Noq(LfDduWq#il>==@gC-z$zsdOjzuR at ZaqVw4DTeGu*7Zp3Y3kI*ZS_(O
zLUMz3Jk3)5*0QI!6k!;3Jgp|j6dYW2VSwKC5n-W<*VWUh;G;Zl-O{!^InERWPOxni
zc&2*BQn_-~z{8vtxtvHuTN#c=0WJsC`upzt{}0vo{yV??b(}}O{82?!RX%sR{{-CN
z{#Y$a<{bL_%pW#<-~7bCLG{EWjBmTY@^hTv%t<S5fn-EzWU^M^?Uuz|mhrYYM~{wQ
zm*tRX5s1VjAG-kQa*;7V(tj8Bg+DMc8X7hEm1R1CguvsBak0cL3=o6&$_WSw3qJzd
z0FYnS|F+^$r{Q*&=IG2Embomo<f1!(NMa&l7{G0rN?;%*CSqo(Ng{xTW+rJ_AcCNx
zCYrwqqV*DLPRB>+9)qBWKPGYE7Ie?$gAl=ZS-*Zn>@-&+cH at zT)^2RGNibDJQdChg
z69q#<uv(%qZ8>68a(V2 at 5k$0<6cH%VO!<27JA+E%3${#2XfjGf(LppwM4uMWG#rB^
z4Kx%pX4N}pA_ at wjfu=D7qo_4A4Mge8PJ<m-rluwyye+|jm}uK;K{0PFsuAKD#U>&H
zS{*%HN at Ss@V9H4^2-HhSz}VU|$O;3RF;Qzt6#+{dCMBYfh=8$+1uAJmiXv(&LKul@
zYD;QB#9YS)Ijm?0_#?dZqX+5CV0&>I(+<ae7y>F{poJ at v7;1tVPTRsb6wwfsJ+@*(
zn4wt^?HP at -69GU-$W$c-Om at q_<raF3#{x=xWHBibLrF4Ha?F$(41{=7oJB=RAqh}K
zQvm at 4NktS?5hz7U6d}k^seqs$qGD0dp-Dhp at q%Ec4n}<PnIIXUydx!A3QmfUxt4~g
z8*IYtV1bG$A}h8h4+ao|1BnEHnYLUmP?|{U5Olnn5Vts0aNuQOnTHbsU+4X-f87K6
z`aOR%bP+QDFs>%J7uT-3>gNrWf4ri8v6B-Emt2(ara4=TQ0m{DW(=0-{)>z$MMK6f
zQ?4HSVR&s^VP%c~mJ{J_*524ADrpdO)kch<be>)REdS=8UY at Y0KO3V-O)p7nRW4|O
z`B-kwByP6b=Z7mXkk!K at H#KO(>Smq2so#Nce62ngWagRIQOSt0y(5nGd&K{92%m-o
zrIH9Bf&zkxuoyNb+d=E^*AJiGSDlNj at oUd`{)rz16qrI4)<EEWjcgLDx!tl%*koAL
zMCUdk`@T7k9h{UA=HHPmDK`uIPih4Z7x&bf0Dp8^iy#pt0+1$F$=OW(xH3=PNr^*U
zJ%8tfz(h<T0stPTMoOVD77|G*B$7(PO34Bg0VG6B!65+x{|Z3lfUX2NB!UE?iV2uv
zLWCfdXexgrmkj at qATbPtB*{tHBybQ(BoPS-1cP==nSg+TLQ1J5CB{rL5_Fh2kPi|Q
z^My!ZWF&x?mQDt6`;rr2;AG=41pr`!2>}N|I+B4-1RM?q1mI-I6C at TAFp@zg2zoif
zf?!A`k`<(2g-I`e(eh~3L!hOmXzOlH=-id%xg7WBZu)#%*Sry;8j7;Y({BEVcqQsR
zNd(K1NHSzGLF^Cd44sk{=~<Ew^d?LNOpo=x4;~`ILKRX;6fgyyuN{JxA(DAG7#=1=
z5E78EL_F9?hiK;qi6op%nIs(;2~O!QNg_<t1{rwZNSuKX(S$0fXzuJf!`IsHgO at s&
z!8f;BDDJHBg=TB+vmZ}nbLg4K5iihwfc`@Ns!y}=&h-As&*rD%8L}Pc at cntz8x&01
zHebDbrADExLY)5dHYW(1T|4Vr)czzbPjpT}0D2%(8_#35f4W~mktSi~=yA=BFF2XR
zzJmnIaw8FAp;iOyV)HU<W{ft&+6@%k?<Tkz#)#Hoh2D!;7@(Ul`uyzELINOp=S71F
z*f8`5r=gvVY>obJcVD73l^q)iw2wni at VHruJVYQz$$>)_5mAYVe&X{;Gs$Bco3g;s
zxp8~P at nstWhW1ALa^VRKW#GKH<II at F&@5xxV at JCLNfrzPPjrlgH=Dc(m>WTMh*gR1
zCNgl;X|;5 at 2b>Q~H2K3u-uX8d5XKFFz;&uVV{|d|qBLamT^SL&qO8*v*~|6h#11}!
z;Jj$mplPmHqRy?&=1{mf#<o^BhKiOmNwK!lkd3C3L$emh&8X?1j7 at KMEFSRIEj0Cx
z+=z{tC^uAVg$lMt^u|+Tj6kG9O}zZ#i3q8X%uQ$OB)fIvg3J(M#;RLAkT+H1D|?6G
z*vMR9=?2NflZ{*~{BpW2LSI%E_ at _Ai?qytj at yyK@W(VnalRL2ENx$PKDLnal{q}t4
zU!Uy!ey8<_MhIGnCPJ8&5Q-9I0)~)?DH!_{Vt(nq%$$&*<X2T3xKtDvkHaUG)C5Xx
zuq#1~vsrP*j4)$526WcNQ;vSafUg*bk(6LUk6A`zAFOoH at wOK=G;O^<hy0)O>$z1#
z#aDA^E5O*0ku*L_6(wQ!?^f~9jqHSJux;16S9IcXZI>YiakUE}2l5NX?@SITs~br1
zV$T$r2K3#ERR%j{6^cS76JRnWl2Q))e4oU9J>LHv8|X$2jg56eraDHttf+n74>Zu;
z8EdAE%2={xtyC|5-Wb<%PY6!s+p(gaL87ESSt#+Mpz5)J<n;E6b2Zr2-v@^=v4U+0
zw_yW=+?R+=Fn|r5J5A7ygKnFbaZKyCj0a;}GX|S&wwUB-h={>Dq{R_Oc&NJT9ljr}
z_xU_?lgZCUG*=?(f~;tgm9eQBBLmLmZ0}2=<8`9v3Ny2;K at q2295JG(38IN5rH*49
z<_D3d1jG?e!J}B_&{EJ>wg2ah2ADf$u^1Ey=3>Sfv{9z4Y4v_~yD$w6u2})dgKauQ
zqeY<PWRS86u{6gC<6%L%Gsi-Vqu1=}jL92E;iOk3Y-Zfdwe2A;=8!hnD2BBF#7!`n
zfRY6D;F2E<^1SQ#)%-t{xvm|+=!er_4;TYf4}aA=o*1GDf^^ZX28Nv`yGg<iRGo7p
za|cnzD6a at IR3u(7Zukz<+pN(?Eh<vbP&5HUKz4&bwzUY;*qu7nAXbebRZF*Hn(a7*
zi47uYJMX{W*N<2`?;D2I%Zo`E-nW<C*ABKeTbPl(Nw2dMc=>IX)yXlRbN3&p+Cpc)
zG0l?+L?#&xI?{h7hze-~m+T*-zrWY(r`5LK4sTYz7;68 at i(k(?H4WP4l#y}=^tS#f
zQ0fdc_s(2~l~L^ms$)izJ*RA=;rO))+{t$wZV&2ABTP-HHx9{C3j at GD4wTbb=J|Ro
z^CvdsFHyK0iM2_f!6Bi%_BjKHB1YU~iN-_1<wVZwz2ZAM`g*#Jbv5_ at XL<O41+~5h
zud4of*U{$Az04AU)Rf4K#J)EBczG<!o7n4ZF4?XD+W&Jn at F4I@``x=N(4lYNS~5ex
zMosF!R6Le7($rM){%Z>lQ=6h)UA#=8|I08{{fmC)wPe)B9m^gV>iHZ4R)NJP0%HVs
zNqz*1O_+4FlUaE65j_{VW0z1m70dhapLBd64?6?zNwBI7?x(9==@PGIp}>fZcT|*g
zlb*LZ#Qpwy_eN~Y4ZYtkFi=s~MD3F_wM3kLO6Etu%;`}O=2p+wa9?qTc75m^4Iuj*
zjwB6#Ho*wth~w^$pMC7>#`cb2H42YRJ-=s1>n92-0kVB5vRgEjK}wFCl8sP6Nd%NZ
z3HZ;VERS5zQiTD+0})o*=j at MNbTJJRQU;exB#;pdj4-7LW*FHBWoZcJF$E9zrOOG_
zh5)K%b{rKDK>-0Dx3ED0UE%1MWF8s%BOC%)A_GKY7{p=35i&z81VTg at oIu+d2@0eN
zS{t>1i;+WyEs)lR8AEr-V1urVG=UJWC8P~z17i^s1j(?NNhP3yLP<(C91kNH=HU>o
zmsnsjM(h~j5mg9~M*>EUL&y$nvjEUA#t2MJ4vx3J9!)<`N}mUjl;i+%q&-(9P3-vS
zs;DWJA|?VVC5VZ=HUjY2n4XQ6(V{{mB10q){Sqq at 5HG^QpKHH~;cIr=X{`- at d%l|2
zM*QzFy^iiXvwSr|5v}l?{nMQ at TXJJ<&RjD#Er3C}{<#{M;e;&+Ll<Sp!<0AqJ8WaK
zG~2#wZSbjuKA$Yj$Y^cSiWM;)ggX9VriRvrfvA>(ieQSFL-zc~<3u{`QTFU&Q^pFz
zUR!`N#Yj@!V-XV<P>JikSIzYgm)K+Lz~I%y#<)`fScmB6)OEgC_<-=RJwo^e1Vn#M
z6F^ZMCHl7x4GbD`5=$jRP(uR at Fu=gWMI`9SF3BGwyaMa2Vi-6X9Rv_uB_f7X$S+QV
z4RvA0dvG)mL|i3^!2=M`5JXaWZ6PJd4U;A`xGmCTH!)i_U0WlPMr4vfqG=@ISTvl*
zOI<=7hKPXX(FVue1ErZlJxCS5Aa_3;aYma<;193ihu`}rKDqLqmDE?$K9lsAw*B67
zkVdhrU$o8b*z}<D_yrGL<GjJ=VG1wBjWmCL(L1)_6todL8i>*N95nt3O$q)e>z2?&
zcpSGWDVmCobBJ(j-FLdKyC5%sKFC at KsR8W*{uTZ0inR5|Wg}@+FifzIGp4xKc)sXV
zT<V+Ep%#8FPCt$E&ja*3+WLy%+=-1wzAgEY at 3ssE9GwopIvFr?f>=Z?44rhadXeDa
zBY--JPqZgb0T?h|hoEr{=;eX}QU!umut|a$2q1xi0D at 348JGxJu@(#j!=ZyFM+6H5
zfs$}QwlHF1Br}2_%o|P&G8AksNm1+%jsUxSOUKn`)-RL~Z-<W7S0seC(zj|zu0y1L
z_<m^Z;HW?{1jrC~2LS?gJu{9$P9TFAtwAtE5`Hg>@n9;9m=gmuP5bN8(M3+y6yqGU
zT>-)BAk?#zMlk(YLU*J*JHA~XPW(l!fp+I)&?4hsqcVJ!A<m);f-_vGnMG;EE<^WG
z6ss&{MJo3Q81G4qR&?SKnK_hiniyK`y^*HGPuDln;6yq*=6?<L>Uf;IIJTRms&X^L
z&dt7(j6al0hsr#x?ZXL<rSLmAIN`M&ckH_6&zZ*l>;FHa(|sHAx_EmlEP8rE5?{DW
z($Ly~NFaQ_aR5JVLjb)%on73(QvxWNLZ}s_01xdE75x9d`WAwi`%mC{j>E)B4v)J=
zU)EnRGS45pSO at bBNiraYOyTu>hthv@(tU?v(a2kVo>|K@%lU`$bMNexUKR5Xtkidw
zDsg}@LB{PJ2O)+1xqSD`3D^kKApRl_p#zRNXjjZuz+Hwr*z7+|V@(2f&;uSYgC*n=
zyZs^~7=`}#_<6klU-;F0Cg+`Dy96O5NBn`0z!+ZeE^tnQSEl#4KE3b%+ZaiGyqMXu
zIMh7>0Q$Dy0vj5Nr){I*CV+{5K3daE!!vr4oFVuPrlj}r`KFkN<G(CE!&I=C@=n4l
zWR}=C!DAM{2{Cu=tEiP{N5muak%_nJ=VowYP<64*ysY<qf0RfOXbjFLZd}s-qyl=v
zbBGfdLqcv5K~;a33_}JpBjEXZVXa1nq*^}VP8!W9q)<%ihpFv`$FZpp8(S_`W+&>Z
zAUVZD-w^YlDAS90HtpMk1cewkyx?v9SZat}DUNaL|I{f)8s-)vNAUl#_9i~xfz>7E
zI-B(}9!x9*!x{)vTb}2c4{?o0_L6Y=E!NzAzvI8rKR=d$>K-KN at DEf-tRWc~eV<JU
z#yzIPF%3i((JE-2p8?;0kM9v6S^b_<`lWbsyMKnO*@dD<{Cc*=W>r^*O?#@bQmT^=
z{lt%uc(hK~8_ez`BvNJ%12BSI{*jve5g5j^lMP#*==ve1s?W`lZrxC*Ljk#%N45u>
zI_`ovj>YakNwv#A(TB?Q*!ii at o_2x#{Yo`K++kH5i$0yMm+~BO80Fg>Ic_|NxV5J)
zW)(0)XoW at BLdza7I#bP_{8nr8vn510FL0Rx3r~_A5kNaR#l(J*9wQO_W&Irgar=1g
zfF3dYc*vFI0fIoHimhaXVrV8pf~WYio?-l9{ark7$^E`h5a^&t31|q4e4!tsm<alF
zum7-VVu6T@>@NHbG4D3J<j{sp!nujJey!&iKUcEn$BlkFeK#{>Oa9nZeP6ry?46(B
z`^QJ%jJWOaL at 8^JDG+@=E9yy$zuF&#XVjWg=zqSAGyLJ3k_lVJxS-qk-B|(<c4%kB
zxQ=PfhWw)scOS3Q`A?kR)t|8(p(%CknRGesQ3<8qm%+o<4?Fk~m(4nKW`jNV3*h>u
z&XQ8fCG;;c`(HXR$o5G48%q+Ef#ls7U!s`6#L9+6AbkbaTy|XyC)GpBzm)Co_paX&
z0e&oIrIW+YvOaQmSAUaJH%r at FvpU?>+LbJeQY+CR0a(R-^c}yY|GcQ*g!^2j{k{J_
z_0ErnT$R-c>mL#i^C11iAEblykbcq+;6eKcKY<7S2IKZP9^?aP|5d>GWKp2{kQxib
zA@*Q2LjeptgX;3scz&PT-+a^hdg1kcb2>u$ZOoz&&bryp750#`#5MX`?pfy%H`JsJ
z3|!RZZ?`O4!Kd<J-45&QG9 at MU|Bl8jV?Wd at PLQ$d`GW+5Q~p^QwhCZKxg=KRv?^A8
zWi6PiS0nh_T~mP~C6 at nKA2B2-;EV`fg$9g7Ukg}BwS-s!K><7?J607MPcX}R`FWnt
zBR7}j5j^%V+D_q!FoIrPA2wn{9IHG3$b=cgpcx*99fQ-6ZT=4{@^5eW9%nl^I5sUj
zzIJA2q&OljIVO>LM2(`=5o4HEMNq;>RNK(gZj$A#%Wq3x8Z_QW+HB?PooSeKfx6Cw
zr3)8&CG{pSgy_P9NP07tBI?Sjc$`E`X(eVNUr$b>H*)1#d)98}Dc>50c%#RT%gn`N
zCUWiLer4tKlhfY3JeVFg=sTVQ^k$I=n|?!n+y7$<x>`SXnc<Y`&!CI{I(qrloVKlP
zWt8xTtsl$@3?%{l3jTlDoB)=>g8WC9R6vAD1c4+DXou>?8V+IA<=gysq5Hj`=V`BB
z{fWi*ew^E+Ydb=Icw_WsL^U9W#1QzARMdc<AKTg2J^$78kUa<x9_pl60)IFsh%rbL
z(F at f1Bi1hKmsNC$Aco`-K|?|^KV)@R;r(p?h$8L%8 at c@$B4bE#AIive;Fr+T{k3pw
zT4`lQo5tc)ObKErP*o=*@2_+8)zkg3>#GXlCdN&D%_}t0{h+_xYIN+HMRe8$u{BWj
zS@~!bgBKM`0d8&kc4!0pnnQWdVJVs-6lDH*J9!zBFOfM>)5c2mcZ55 at VJ9ye3$+Wr
z3xY#rRE0*N)?Udo47GL|+mq^U?&^?ixWMe<i&#Ezvf!k7d#Ei2IVDH7R%nsyJ!gM@
zi3Sk2CYbe*w|GU1_U>=KgknBncKn$?61BC+Cmqng2p(VRfT96Ab<unc!Dbc{DshV)
zn6U`4QAiLbD50pPMrhIdO^Dh)wzzGy+kb174usol!6B(+IuRp*jf*lbm|eN&J--Gs
z at w3oyX7lW@4{Jv2Fz{q8pHJ2V8?;^~M_J-Kh-5ILM2Q3PZ<T`MlO>jkkGmI`R%soK
z|6)Sb-I0Q3B-k)ul0=v!l1VG$7o{ia&(W=Zd}>aSf=d>Y5J_bcaGea?ON)$goN<Fo
zGWpHo^I=4iV4SB+JUvX&xT-=VvPmS8Nj6lKDefdw>kME`gw%jDBfcFx<dHsVT2mkf
zRj%Y`Hjql at KqKWpkPabq0_C&E_hT`B_FTV&e(tzHW|vk^L5~w#rauEBCY+-yC0Sgl
zODt6ttxifNTl+wK3(-UTce#^q)cHN}&wKtzZ at M-kfe6PALBgt`1EZxZc&vI?+{liQ
z;J-r4ZG3nboou5LLC9=tG~1)d*cv(h!vo5zXQ$zp17xfR?04^?@kE*-Hg6X9&67Vj
zwzaEQBGFFmQB#-hP=nQz9gp1~R0cu6I|Y}s;8N+Nhm}7!+9ThW at USO($HtDPQ5cQr
zmxH!6TUG}LilO8`Cot?2Z(lvw-GPyhO2xUGz<2f1^|@k`!23{3INY>0+ilBx?8Diu
z at qW4F^{qJG#DvJ5PdCcJ(c>oV-n||7AWEC+N}T&|24~uQ^~QX%HPCvuVBbXZgXrq1
zcD`*K8xv_%t;br?ZP${jva%s@(lstAOVg!FoPiOB;Gu^RC^$MR9 at gL9P>1;DFK*Br
zjF2c{qulYMn;XLJ7IVtjNSq!(aYM54uRU|x5zBBE#2x`*<M*BN%xEb@#tduMdrGBw
z5%ZD26Eu`gExYbn`!)U8>>62x)zbjCa5nr$Gtdq!RPP8nC3xrF&?j}VPv6(``FdgI
zBJBbV4xXq at L}|4f!fxsAZq-`EQ23JooIiou)!LPE)e$d>H4mK2dE<=SHbNpI9KL#I
zEJq;MEfowhQg}@)TUC}738^?cCz{T1vKNYa%gSod>sh5Voue>IQ^v9ph at ee)Vl0}>
zwkn;H&|!?Sby!AjUDg_B0Ygxs#AEh at G3I202J$Zim<5Y3f?3HK<0IPd`Z3rstlh$D
zv&Xah9Q{X+RaI40RaI40RaYO;>?j`SPE&8H#Gu4E`BVD8wKTI?_@!a>*nMp0zv!uq
z<2Pg7$^2 at KJk`&uh;DPVHij&mbHKFYWi60MBic&xI*W!4bV_OA0%BegN%Wh*$hc}k
zOPmy&a_9d4t;{d@!_VC7!*Zft552b#Qe-=JVFz?lCer>kvDmw3KZ~4qVGidHB(zaP
zl at w7Y$JbH8W)lOlrHm(2B2rEEdMB$(GydXo_##VMo(;1wbfY8KabB at KNsE4`^rl<I
z#4OFoe6iPF5($N3xdN(%^FYc2m$+l{>_O~W=>XVfMllgVLbU`QfcZUtvd)!>bW<bU
zWY|BM at il@g5&W8Xl!6NueGdf}{@e^0 at sfJyNZ60bkT8CuA<}asrWy?eAxI)gA>=~1
zIBdxTAu_26BL>NqMo3)2k%Y-1f>4qfAwwotLSW7k86W~lP{Ar0lO(ca!-E78U<_=z
zguw_&Ni!)VNs}RvhF~)jDw1I`V1cq^NhBnLK;dLb7y!;pB$8|xLncf{lK?F=g(ynr
z4X`A^rKy2w+QX$=WTY`Jh6!CLF|k7oFc1<*XBpa~0)}NIpus7Hc0(g1BoHRpqe+4V
z$%6s-N5H_G2@>kC4o!yyCM7aU1S3F18)_9YNH~xvT2nHZIyyKUmW3fD5r`QgSpf+;
z6Ja390J1=2l?X^-BnT2fDeN6MK;$9T$b|wy4hV2UNo9--Q-cN>GGKB_*~*g>tg2+0
zA%Yk&R#+q*mdG}6rU(oWB2KcwA_f9bz+(syV*p^3b0U&Nz%W58DljS|pY#Mx&*RC~
zNp;_2rv<LmZU>?CZ|gckq!VMHu&@(kfROn|<2uKOu`S-%Qi81O`?}s>+uPgryt%W=
zsj}u}Y(JdZ2*^xp&a#c~_W3Wa3&Z?j`g~1PTRx!c%_1UYGG)9>Q1R|t6aM$=rrMo{
zCfdKF+qo>whZ{Y#GV_&uV`YbQ8tOweZ<n5^+}(lWFscXTvK)h<+6utCMfuDA&%K+h
z3R=s4RlrxZ-+LlPKS2IKi-gaY7!WOLk{Vx4vWY~m7-kq|&O3w=pbzpw8XXy=zFKee
z*-uX0bhug^Z1DH5BugV>YGS0IR+OjF9gRwD*$!duM^I at z`FM}<ez|F;I&bKJP&Y$D
z6dfKTXc0-6cdrD01RhihrB}SHwW45nuX`4jIN*q`b!o6~w0%siy!{(V4%Yz~9~;1G
zZXD7n*LgcXw{$jtS&_SPBvD=ZiP*U07`H*{yZ0&?l9DgINIqA}SO!#p#`|*YqCM2H
zBLzrFL=&$)97Iah&ZVFU6crFD2+>qh8eH>POS;MYTB*&0N?SHwj-J|Tv#ExIvtV|>
z+}AXc#eK(%Hlj=hA at kONl7M7W3WD3wVGMA0Z5;#X6IAZ2-t-px1Z`;GdWH<gr-eD;
z%Cj)7`$hpm?7B7uU2 at D}_xc$Kd?-L1h{%kDAzUB9%c at ofq!DBJ0?1Cf9-Hd>?hS^P
zEjdqL)wL{keI=&`MY7%1*;&&lN>GF-h%+|^a2?LRf;&WYj&*qIh(qGiW;%H~{s*AE
zx3PT*LVOOF{|Pb-uiIr@^Ny8*)zj`RGnGX46-(FV!YnnZOSOT-!Q<X3sPjOioTg<9
zn9l{4)O?|8ACtkt%2!>R`rM3sxpp}MX6zp@?vVbnpEZ>Udp%hANyIu*|HjM-_(s<s
zvFxAEM~YlqTP)_)Arq_2mZYNCijve7H>o#M<ODh)4ml`gEy8B at -hF|6?(*rE-AVJl
z0V77Zq6wl~Mmghwn=6#WeS9;0dKI1W|A2 at Mom+*2E59F#dA(k~nZr8=6ByHde<zg(
zl|alPFoetS{=3Ds#(rAQk79y~2&gLRsf;reQA6%MoGZhl1R=bj|5cMPDpRt2hnJ}A
zmtQTuu`uX<0Pc~Q9`4ETZbF}puH0EBgN)m_>?=y9NMf?8m`9E_u(W4M!@r5D9xZR1
zKD|Dv&Y`#^S8kI8XrRW7 at veHLmd%m5F|Q~m_}2)@juA$T+OKkSnAIVZarG9MeCM~x
z{;Pw}21ZFId at 4^|0sW2Fr^X#D*%^hSkDSzb{vx-aO;<Y|(BaIHBIcGUJVBWu0IJ2M
zF-<Chs4G&w31DUBI9|=X<a9!SQyWiS=#m%sN~ETEc=_`aFq<f8oNv&r3LF{H=YL_$
zG`NT*Gm&d5+AuE91?P;K^nNvHrC+tSt?|86{C(YW&_qnMexF!p$Kbcy*OPLziA1MZ
z(- at kAGMi!0Df|^4^{?YpBrs=Wocw0aNY|qA^GBac+(u|BApEgN(2l=>t9(^t_Wqs;
zON8Ocu-Td$DIwlek at wwI>2%7i28_zh25QZ5z>OD&iorta{z`lQc_C_bck$Y!Q7tag
z%>y4k1ocR)7 at bfdpTL#)dG at wr)f)B~$#wW|e&c>ykd!5t+33-gJGyR}?61P18#$HX
zyARa#7FT{o57o0|56(eR-N1G)eR8AmxBU8Cb*Z@$4Wd+pYJ+CD{C`e7W@(#KeXXtQ
z;;UQPMcyD49&y(CSuG6hDF>Zo;}#loBO7FOw^M^_YP)QXIU-5OPZB?Rb})Ohez|2%
z4ujc$4i2L~Z*FgVvtnkwc31W}&u!IJRqxr0n{BE9`41DHoa-{axijBpntW$Wa?E3Y
z1Rl#7uJI|iT$#-|QG11;(}^Rxs&2{Qnt@!pb_@<Q+f;{AlehvM;RK$ek#<)6lb+iT
z#&Kk|FL%S{{q6J2uZ4fW{pWyo>y`s<DzNEX3yB<t-NSDC&l2NES<?dL=y*VOu?|Fw
z%d6j0X!RMM9~WlT(){pCE6%>+qiBfg9I=A=IP6-?#f((7jgi|EGVi?S>o+T-bx^&y
zZ+=RJV>~9=xL3QmBW!dX)cyOf&vtJeam_#LbH|xDc{?Coa>GW*R%%vSnaG;BR`6pF
zJPho16UJ&ZV*QUnhGrDST&PO0p#2{T at G8t4@-LBU+3ve`voV^btCJ at L#n(w?D-BO5
z9=zkRSE9(k6kspu(DKVJ=J at yYI}rWl-4yj4P0H!X-m at X>8Vh=2RdRAs3|(!W$Stha
z`YR*)9e2*cHehQhU9>EIcgfeEzE%>+>g00#l*Q at jYn-dUNoC3`%=$L at 5#kjwHL&%$
z9`hZKKVipus`;OeF>f9O3$8+U!da=na{HqiSeYJn at 2q45zHWLpD$<2mU|lsSke~GI
zgc-W_+r-#*jyU6vIOHJ+LJ))@2tp8qAqaVa8}=QPYV!6Ph#ZiembPXX*e7;oj$W;B
z+}@Z$q<Nv20W4MQ2N(#Yl&5BH1eZC|V-echx(U at p_d}a)iIx^>Xr7ZO#*$a}$=LQs
zj{R+>21TiKv}O?GLAk)vjz4(rOUjP=nHo`WwZDID^D~XNU5n#iY&3N_ljp4LVYr at V
zqe?=S*LRKraX~N2mZrY$KTw^9>vpe2E{|_dWgiXkG?=F|xoQXzX9WA1j&K#7gV2P>
zAi&B*b(Xwy5U^3~V!m(MG`1ZD&PDZewj{jS;d=Crw{-9l{8Mm_sScp33Gek&?-{PN
z`id^tmDY)pM3k;KlFun^RpCeE0FFekH|u(fs;`TRUucaG6B8^fA#(;beMl88*&2)t
zuA at 1_Jg=0dGfU|e<OmW~`lBwj>6u-(*>th^YdJ)A#gj82y(MfIZzq3T^GfG at NBKx4
zU9mMn>Ze)t)7d<97w at cJmae&&R=f_|?Z-}qTq`;^5(Al%aphwbF~?m}v0e9e+KgNh
zk(KxIPx5|!U(NSil44>uo!Pxwd5mHdi56G0m_|T|P_JAZkotSd4OrQG%<Y7YA+oq-
zdPja}9t=H8ZtH744W5r~c7xvs_ZIe%s&;DC5?0fL)lj at 2OdX?WcwL`&reskQOgagR
zZFIWc*acS^$yuIQMLB%n4EZjZV9=Gi(y{ZtXhZ4GS|j&#fnT$$y7#Fox9$mQZiCH5
z>OqUp2nb^(?2%JPUfVUPH1t{orP~R at a41}rn{!J}ftcK2MJnn%|1R3PK5W7(^gk#q
z1630DcqZmQRCO>7A0_HJP at bmME2Vm65sZuB3<8X(`(pJyBP%N*=?4Mk2$dCB-Sof%
z#ecmAj5MLbJ-b0wqYy~O;WqyQ9wIpCAKK6=Z#*-34Bl>KDGkt*YO>iD?u(N#?YxcO
z!W{vL%eD0Hi6J~Fe%zE?!FA^7Srp9#i1Zl!T at H`jwFl6THiO2G+t1}(z19Q*q*Wk?
z+K-$+P=16>uCQUSAM_nand6?4$h#NPHY#0*^gruAz&q2iI+Bu-CaFnDY3EB$#P3ZX
z=!%hkff|pPb&!5Y`PB{KMph!!NfjHBSek{C`~T#fT|@ps?wLPG)915yhI4Wg{vTrL
z0TB&Gz&3;xX>l~-xCVvL8p8B71)I*QMbr%Fy+sfW$lO2}Q_flvy%P(Ao<txMht=%Z
zHBTJ=$>1)X1L(d+6YQN5C4-V~iiBbt(STGLrOg~&8<AQxt^)hiMWEZrrAX$DxC8>Q
zy>MJYu>3)SK*3;i0|mjP7%K>vw*X)rT1<(xa|`gaGwClyyaQ(>SH1$_=JQO=)1ljv
zT{lmJ^5z*voF~yNs|<*TE*xy0>rJTGi$j8nE(!%f0CZ3#z<8STqO at X+Ea0kD3Xv=h
zkhm)eg<+DhMH;U*aK_1veWWe38(&N^rrKIo71}Xyr%WZz{)j8>Yjs#zu1;6KQ(3`{
zdYn`1%>{ty<ydm*k1?3!&d6l3d>B`Ypi<SY847zgZK_R<s|+HH$aH2$G;dq5(RQ;9
z^)XaUoqPpe$iFI>&u>7fO103mDuP)#eGB=bl?@Q#)l)}DGQ|mPH?geg%RMI7&r9oI
zwYg31wvodz5V^u98ii^hJmPegw-5ay9Rkf|`|;mRQNg$KBUx<dOwK^LCQdnSQ^s+C
zvN=TBR#ibl)G$?MflV;AxNZ)B%pI5AoPK*Irp9!kGMfd!RSO|lDu>5tIGDV+&}}+S
zWXiaU6OhDA<OeP)9JGPD_%0RQx?tPbSzA`l93B#myXS9J8gO~Rr#U at V>_$m(*iHhz
zJB1Dgsk$o#q;cTZhnQwOSZ{8gy{pJO%WB?-G4d#P^3R&US1sV$nb^&Zx97F at 8#QJ#
z*j8J$8WFV|QPLR0peTyb#TuJilISxEn<oQ~Zq8v@#z9ffLbB3g&u<h{3JJDVRj+1g
z?B&#F7?7(RR2*6i!DAg@*fqkg8t}7&Y<eP%vvBy|c4TU{%DOC=Q<SR=uCdVoTQWt=
zW*T-FDeF2kP~r_#(AH0WAyui`|5IHh^Ur|!XG4I{c^!*yrUMLnLC4yc+FlPqgMovT
z(8cneH~Jq}gX6xZQ;=pFr38AoWH<5dd$iLdYw8{j=1k<1laZX{ZN3r0W;t;UQR!Up
zyj$_L6$Xp8?5e!nR0`H~UDT{ZO#xx2a?(Z&n@#m~W22R|%$7>@M!VjVs54WgEjhAP
zTDe#ju7pT2=vu8ffe_>u1BT$3S`Z0?gY at 4(d?G`L2x86sfgzBf_yP at vg8_g+aI`u?
zy`@!FQ(z8=;R4<Yvm|sb6{2BaIyVHvq&h)^m^f($M at UdNDuRK`D-8kE7KH-b+Oy*c
ztHYou9D)d*y<xQB&=W^6=|o5+oH{Q~w2=&86^BSfTWd!IU7MD`kdEAUIDRwbPsu1f
zRKK$A at RiHS+jJ^OK?So96_=al@%)}&Uxec$+Dblnq<yviQ%I6t=+~NF-=!ipdx!;9
zUm?e#HXG>?Z~83XnKlOYw5Y!SnEqe9#}BLDo66pV{;$bZRaI40RaI40RaI40RaI40
zRs7$_RaI42%XvM#c;jyzb=O^O*N+}NZR3tSc;k%h(6N=txSwW4!K#yo(w|b?afFT_
zm*@Mjm6Mx#j3c33sX;eqy at h@UL5Y5RvHpu0dhhSEBwh}GQibDs&YU-o8k;KYX8mF1
zGHi6_21s(l3`d6>@SuwzPTU`kJ1qO+TlRVo&0O`J at L}=$+Xrc62B|v6i0YhMU9Fe1
zwye)dJg;nzFM}f=x2BxYMHI%1t!I-T&@{d;+5K6*MBZ6nlk<)fqR3iF#A57qCo4)x
z4&PXbP-xusjSWA*nYXyPjkWPv8Jifg+T9F2Zj3kNj|L*xiJgSm=+tP&CsH*|8)bJA
za<acwGGi9{&Hawe76xJ3G_dF~7(O+1$H!IJ2*=L1IxcsEKp77C#8-FG at CB#W?WHVg
z+U_px7BeoALNiITX0I-&+0HjHUuS?~%*W^H9C#rgpm>5TTgNpc>-+H6%DmdlAy~2Y
zk9p?M%7j9_gbjAm){j?zjs!+`9leKb6<NQLg)OxAJx7+O*8hD#ab%7*gPF$yq<(LV
zlk;y&5N2)Brl~UK8yr;ZsGYr+XW at G{l at G7p6`9S&%ydTL<3zIPhwJH;h!v_>Mw}B{
zU at bws2M1VMBCR<1j0%|1o_1x!8Qw*%feRidz27{KsT=;8sZt|Hjg{%z>2V&>1FL3*
zp7BF3Mq|^G49u=K+x7WqT)S<+%QT at 7%E!T(rp53Tg?X}S;ZYWPWr&UVcUae7(Z+Mz
z|J^axc*aPe__J^Wi6CK+Mz(vuiuM}Se<G{c7JG6%P4;21R(%(5ux+V8Z9VdUqINqu
z>|y{h;gEDM7l_K3hNurVyNt28c%3oxdZ+U(b<J7h>0;dYN(e|uNSLu<j+R>3lOiy_
z8{=)!&h<B3V^O4Qm~piY5LJ0nn_=Nx{XqWj(#rQ^mF1F*JwQ9=s8cgKYn}`cI;U4n
zvpu=M5$hD_@;`=eO!SozdD^P_D{Z#7THaSGyIQL4TWz-0cGZR at rj{6pzz^5*ETLp#
z<V17ZwRg+kYkajwGnn2Dr=DQeY9edVe2n?CLp)>d`t_6~9gKnJNb7=#Fv4V+jnU^6
zwXk{^k7H4ZdtF8amKhW-zkX`9fJ*vP#8<grS?kc|67lZ6+tJh0Q-&c%P<MBBgdW>^
z;K-rrh+LacRr_qi2B3Yt<?;6P@{L--4-J~DD{XQKpo4RFXgOQ;Nt_vbf(rTt5Y8(G
z81?YyTnTX%^_7>}`I{nc+9}e)$ImllBKfc(rwJy2E^>^rbEay|Oq~N}qkCl*YUWzW
zM-}qHRrIT`h+`@8{owp`dK%)TPdWTtLpNv`frCw|XgWg?x>zX*JfUbt`&#?2i=q{-
zb5(R-7<sSJO?-Cv_yxW<yNBm{hTFb;CkPprK#5VNMN4~Iew%F9U79U0Z8uIAN?DAp
zNV---F3iuB8;qTnds|d?#rdc1%~AlzZ0nv^hl2)>5)p65;vyONpzn@*?mi}b_Tu*%
zF0{4rtjFiCRp)m7ydE(ZUxil<=eh1<2bm4=kd5+rITF{^2&HnrIUQB?07ua9c+P~Y
z=j~H=eR06Cz93iaf%5(DpYGfMF}c at meO?<rOdpS#MHvzw$rRB3jt$f}k7ZxYvw2(L
zasBd#3yp1Zdi9ZxHV*ru<BXIB*{k_#!m2YZet%y-<4REVns_j|eOfBd__c&+LBSMA
zga*VVX`i9f0H(t*1N&ewGaB8-sVF|~ivIZaWcFc&9S}HJTFw0Hzl|qQ&HV!Jw>^Co
zOG52BKoOV=hW=h}F5iyyyiFitSDODNt+$Un6HP?<T>Ur7h#L1OmfHu`lhqwPvr=mD
zNaF#KYbV0W2$ANgm7c)u7<xKfhx{4m1fjxMf|80tl%@Mv+QJbC at lg1C_Y3!+@!+0y
zKj~G?XLCI(6$W9L8H-&GFMsOaLHHg+?L81XJ)d81&Qu-tUaO_Yr}upRT79^cFsr`N
zpV>%iI%%N(o4U`$apoj3=K+YtbVJH=JUU~eEmdN4bV5l6!vBYGzCoB8E)JJrHV#F<
z;9v00!va4e$aHte0!#w~AZ9{l7XBXH-eyOys6UDrKHnUDh>|9WgD$InrocLe7p<d@
z)y|%cmQNI1Fx2bEt=}U>5e(viI)O1Jf3+FD&CKVD7m_3Pn<>(T6Nr at j{$-}r12SIL
z^J^KN at 0VdIyp>XLl=m_G49y1Bp!z0MGh6AXAag?jCP5Yf&5pA$yBiNro!buWPV5B5
z(#_UFS#^x?r+rHGDNY(kx~WmsM(L9*8)@%yp-GPO at reocpKv$Z+dp+z4frJF&m4xS
zkMOv1$q*TcopmeJj~GAYE6DIutUR48kW+uRzYYYQg^tiMinM_fG{P9ck!&t5VA~KR
z2K?MPKhLWF!PHm~7xM^|kO3&DQlLl<2_ziDl9*D8bl{v5q)HVi0nz~kteGNK2_}J{
znTZJ at A__zxpaUAzGFxeqB%Bgpl9p+PXd)8HlSxTQ5=4;65=$i|B%vfpNi39;Bn5*i
z(qyVifX!smQcy%ogF0v;LLw<-v7AJ(ST>lFl36B5Vn`|y3JO|C2qy!RW!W$(5?LZi
z!5L&QV8ql-G)|P#WGiWq*~HZ}(-6$l0hkPvOD0L!AY>uQAk+{+AtZzt%@7n66chyk
z5KvH4jRh1m$Vp@(jTBK-l+Z<EYD*Y2#KhQu#SsLML`x*OmqCaz0ZnY11`QC60N{Yk
z;II<XQd9+k10+ncNH}m{D3}N#l4QY*5Jb8HiHtx{l|s=3Fhs=#1q2XK!&ornprnc@
zsA5Y5Mlq9QB2<{1<;?{Y=O##kB$rx=FvAAPvS=wNDWV((Oc0SJf)&Y036mIN2_P^~
zOOnBpI4B{>Nf<Vm!9fEB1td8lO9cjWV9Nx!A)-mBC?LR4P*6}%P+2J_L^eW_h=!OA
zCWk^&P?VH37Rf?nBS9r4qXb~5X at e3ODI!W3f*`PD$uTlbG|4p8G({3iC1wmk43-I7
z2B3n1f?%CyV6%fH5d=XHLO~Ef;E<UN5Wy~N5d{SVK}}~43JM6;3JM5<f`S;5B1#A-
zm}&wSB#x>G*)SBtNl8Ic!9iARw3Noq2qlsOSS%D25tbmLnIcInkeDRFokWt!EkR`1
z(S{_LA(HVU1W9mgGp7bjWZFoB2Ebs%%o!lr*q96!XrR7R{tLg<bZYGxq9RR`ZKG^b
zQvfnTkx908&;pbQHA;~s{V-&tUjwM-&s{H2(M!lf5D^*_&;g|bG)U4=#8M<v4GfVL
z3g7;BUT*659^Tph8#!9Qo7}(6aQ(^Z{@D%O%c}d)icgMs6vSOn&{Prrd?{YpC_^$O
zEi|+e$s~q>@{y05XyjocDJdAFsvt^OnF=H#R%HK=HxfXaCOCDTF!V}dmtZZ8mncaM
z1cXYG6dv*XXnT);d5_)gN8j(*>5PmbAGQO+NpVY_s7Nv=-YqBjSH}MX>>TkRY1b6~
zP(CpZ!gPW5^(M24A^kk%Ub5jKOQtigXxj3$4-CaQCnioo;~o?jIf#PzBvmNUyeckb
z_M3IWcSyA>eaLA*knmX>L6<`iObr~mB7i=Tq#ox=rS9$dr96F}=7;S{LULw#X3>*8
zRUfeI?ZKA&&dDxcRSunX+GI_Xl59R;bm*f;z~jB&r}PJZ6y_oQBe-gR at D~C?e=>?8
zFi1c42_jJX2mC?4u=5?!_>6ZWhYD56!A%IkQjoktgH#$Alo2#z5fDlF at SCyG!-PZ=
z(FxjuA`b$CF7dGtT|)3634)n|EMh_gAw+n5!+($XxlIqeLhOa59+S`!As2Lzk^l2E
zXYXG(jUA&l!Mq0<IKg0!jx!!Siikr81^>K63=u at W0%1O5XjaqhiR(n^#)-o(a3Q!-
z5MfCmig|m8P<_Ari{|K|A at k7njS82i*i-ghB2hf{KcS5?UeZCam}0oiYOa4K9zo>(
zk_1o^qGn)W%C~2ch;1c)c{5Z9py;e at Je_dgr2C7m^9}{V`y8!`a(Dc%dxl at 8$W@)M
zRjUB5aLY(IO{l%E4ueX}2rDhM&J(M15TN;{Y&)Z~;OlXQ0<%%A;^#x$K at L<Ty4h(M
zP&STL3L;S})GKqsmP|f|D9~c2Qe$^eRCC`U8q*3?FfWN-DB4OTqX_L<-u4y5zx+|c
zPW&^85!z8H5XoVqKCTGABJj&61GmSZadLmO_Ay7PXQX#b8d$<h&>B5R&N4!uTVFD+
zWh)>{q)^cnpdj at U3fFHUhCK$#&9x8Fm9a8w*m04tWRYktie!|<Ah$#=b}}*V#Ml1v
z`W=1CC%|+H`7yllF8Q5>57J9{w`;BlLc#RczqYgHC1S}w{r?!ZC${zQT<_(7U7vhy
z8|7Ujh3c(7yKQ0_l#|v~RTpl?^)AN%fm<nPO6E2nRfeNI^ynkwtTbdD5JNG&jsbK>
zgp8H$zGg<~jTtG&kNG-Jug&|9LkxIB$=uWR*js(zGD)=@_ISIb59IQ~1R?Z(+s6AL
z_C$C%?H{t!&fl>~zv$IHP=mt61-CjpV`1hNVQpEm9~*LK!QmaEap0SpgoNo6ZQ(IA
zYXJxQZ_Sewg^A!|#%S68%>U}y+xcvN)rA7S7kJ at uXxfW>WA<8C<K{z)4m7$BxM%i%
zPc at mx{C*gb@(uGJ<!xS#Ekj~5X$pZ;RQ*Oa-fnHH19_mprb+Yt9JR^lvWX8vtyG`H
z9F^YrwAo}&pBGjef73_k(#BjGfg4N37<I~-!u&rdYK>XnR0m+X5R6Y8yCA#a*zcb-
zl~H)LUC$iV-?D5^U!qKQU62voF+8(Z=S|SlI4*AS8?)EjqK at 6IMIerR4-ZD0PY{@4
zj5(e!BfML9+jEZ^n0BAfTp&hd)P9{<MR17tB5BBX&2SX<+7{!OlJv=$3{lByvzHBh
z3 at q7H()&F#<Gu|DLJ)(y!QK$jqO9>rC5jET^2~Lw1>%;BBD}q^6C-{H-_^>?&C74q
z%hB~{_VzMjY^STu&~M;Xwa<RpPPvfU+A~wh!>6E-L?%pMkl03ORNxE~2wcV)#VG)K
zK!v~e&P+c6!O5d0Oqnud$&(?ICJY!bV9A36nlfa`lO~IxG-%PHO&T<4tuZ?A41S}0
zpHSb|rif)P#@lk=BK#7E_(#$w^O2MKXZ;)8?4ZA^2Cb(OxOIqb)X<lF7mhnPA73f$
z_0uE9Xn_OTN!n4mH2(wnin7MpbKdtcy^I*Ez#NDE9UElvZ4I6){;J)h?L%DQ at gF2f
zjek>#^K5vZ*tc!T`*uY9dF)Iw68UsGwy7^`Roq?2ZQPKf)&EC-EPFR<in-fCG1}E8
zUw-#rD|d|Y6Pa$=PdW7y4^14kk#ZPrHp9gcnUh})lHH%r*SF8<*i!wlbGkdNxCevY
z&1II|=`k~5?(6Z$wAsRD8FnIEr%xFw*D;SXD*?8HGUJzw+py|hwvEqXzcv9U%@1)5
z)l|<qK(DrHE4`&gux+fc#Eh_)%Gqsu)Z+;^#khG}deIZ;@hEdWW}~Dtqts2f9*ps0
zQMah3@~Ha?$SA|Btkr5c1B^MsUduW(byE2b)`#0YRG%8~3m#t#x*@M^o~N$Hf#Uh6
zIz3hP=bJwqNy>gj-^PV0r-|qA6>EQ&OW=*4yWGhhLzmQ|oihAc;Qb~!hr{L{RhePe
z-6IPg%Wt+}+;<Qr*lcobV+Tx<eUF*1Mv+ysP+~1*I<n!2&2va&muX9iOwm??wlM~d
zc$|noa`~%{c53>Mg#9PRpSGvB3SE)7 at 2-72eI)xnrB6`oRN-}`nkFPl?Vfz{s(z0K
zZ%j3Oos*k9K1f0hNmu5_Ufo-A=CaMBeCoQ{F$s{iw%t_GQOqX8Bc{bIj+uFza^A^3
zlB)?2F0 at j@3{FsD_Jc>^<+HYjmTLO)<ev&x3$M$%UP at a<=iBpnTBtBTYi2KwEyE&K
z=V7db=w`;lWAS;=oqk5o%Dz|O4OiWL&23OByNTtF26)cR7)hFJ&m4DGpT6u%vbdb|
ztGK?r9I98g7g|QDIdSWQGqr5xxl_LCXrgA at RuZc<R^?lFy4`+k?YA at BUsINsQM+bL
z!>=~p&y%MPO|_3hXv>2$Yt{5ap9gt2hh$~)S7H|xzFTloG5y|ZPS at X@-Cmv-S2 at Y0
z9Ch?}S#dX^OJZNt<eT9LGL)Oj)z>>VLQIOYcHq230R5P3%b>}aWPap+U^4?IR+OcH
zssN#hVv>T2QUstUnn1y<I5iVW5JJinEEEMO1hg>}(?cmE2 at 4Vs5|ot$$`nM%QqYvp
zK_mqW5llf8l|aQ2P!P1yOv*$nB@;4GRTR|`GD#9qNkUOZgC!IMRYDX<L=y=#ve7I-
zMFc>wNJL9a(?rZP%vCG_QcS^AkdYAu5J=GwLKRg(L_vKhWHJK3_DLa^2m$@jdm^VY
z2)$%+1XKPH6T*MZj*o6XhfYfc5d2WIv?>32b^YiVk<e%wQbhytHaA180UYTP28tgv
zfI$c?1f>lH0MMkt6+tofVbc{1U%_cVqDNE-K at yY$MJlv^UU5hI)D%D=2n7~JJ>w*Z
zL5e^TLn-~TiS(iJ{=AYA4u2wkWbmqhk_!YN`ZRgIlgSN)(11liPO=Px7)b7bDBJ)L
zKUdfGeScSPZ3`AVNXwUoUf=SMS}O5EtT?Zoi;oPeJxAH`RhicYdusN4dhz<cdnmp#
z&5h&_5Z)u at j-n@pm1s(I0g{U{Q+4YXP at uIgfn2@H+sfP-V#v9M7=X;5KYU8QkGmf=
zDV*-^rbVkt!Te2K96Hte#&za$*L!}`=^#6~P?Z+s$_e?0B)n+4RxoarW at I&0 at r)xj
zmj1YO_t%YzO0S;-MlX?C?IRA7uz>==`gqy9bdKFiI_$FG(swN at 7_T6<*iew>!0taN
zRF{E~pxnlHuz>$(h6^Q}@|F<D=J3UZi2V^>F;M%cIm=rG_4k)XVhfE2d6_XD<E~`L
z1lEE>OZXfrS~2F6z*+M?4~D*b_V`u0$N5@#O1jAuIMSRizGgjIkomT2t&~|xtGe&=
zcK3Pes;a7|p0Bg5Ub^4Gq2NdDbIzM;oD(?+4jDe_5MVAJrIf)v8~iiUbbGflViN>C
z|3unfwk4XHmee7(SjKh1%a at c7SURwYn7*`hcJ=+L(f)+!xYU<C{JFWS_1 at -K0qbjj
zccT3DLTeh_;b%qivu~x2jaRqd`Q`jB`FQf!y9-LpT-=#zgbiAB!fVLS(b47d`Fyoi
zPO7S^s;T5g^{s1H^x?|=5t(<*XE-;`wXJJB|2sCTTGqZg^3AizX6Y={E|H{&{5uNF
z655q~AC1SQD^>CrC<;RIvQq at bJke@RhF2X^C?$l^Vq_hGM8JHozX9zLMoP8kUv82p
znNg{K;9r=%qTnVK1?vv*(v$`8+)--4GiOH+9hv at PFu0N8{7>WF!#6^9Q7)6-8>`%@
zn$te9zQ?x8d-VNR$94v`eWt(F^L>*JohGSX-=*25d>;()f#g>^r*`$)@Pw|Yv6wri
zXg9D7JV<iUZDUp<P#$<i$nj3b!<l9I&Vw5 at 1%>8spQ<q7rr7GXmcql?s2g1x&!Ilb
zwQbp=80}3{HZgMqi5d{c!`6Gue;LQu7(KZ17ooPRhtI~6CQFWxgnmIB@$@&u^sPCj
zTw)d<S;_9byY3}+ at +M?I+*iOM^W7MXap;xSX9oT-`(;wY<K3T at iZ*SP`n==)Timly
z!_~(Xq~}xBqfowqiqi4(J2clWxPJ?PJ^tqTz3lxvr9X$vPI*RgKi1QcnW@!HPK at U<
zoo5inDAcRWV@^fF&Kc?6v8^=2iZo at 6lXs;>52uY8w^(?JoZgl(IC;g+G(#%3%RYh)
zAad?Ah}A#&W-??qs2>xjV-It01gM;A8-!ZADsMAbAkx(03#p2bxz*z;a6U4y^0OOg
zna-4EF`RAlIL6+f&Xy??51Wvcddx<aigM}oZwlZqR~8tJNMVW2s~DGj%i|bxSW$B8
zGn#`BcZtMiYVGqFoYXk+I?&UEu2yjuP_HA_E%R|zh7yNkI>s|v&WooptmIcj(tTy#
z>rXn2PO0#!u(24X6Ar3f*w(U&h{H}XFP&6YGO+VAh{kA$e45gUgz9S5MzFP)ij7!P
z++$hAJBV<r%jX76RK{&%RZ43tSffh*@7UiKpVxiA$^rb)BcN6XBFYgAtcXGx0R;cb
zybeFq(^&vN9~3(%mMBK*lq!FmRX^CwOe?^>#pog&lLlZZV60rM5HHdIB?$GS5-O1m
zU?GJdi2Tq&>*A+jgnsqhFr5x`2WseJSqYIP<qE48TCb$HGN^C^29;*fBLjvV+A=)^
zEe&C=6wp6oVE11Hf at r;a0Wlrsm_2)wxx9{(#3&oWaU%wq4bXRDQOq<m9J1MLBYu--
zC7L0aMgH-SInZr2JGrM(2WS%6Bhv?(o$8{1qM+)->QL$M{9N+yU(29((;F!=MCOHx
z0u7NMheARyJHU1&()8x`nv+1V&G_0Pd;sCW;5Hf%0y_hVA$9?RM}SIOKpY5>hn>aw
zHxFk)NhFL)5W^xv<|F~!ZALW$#@w6+77mxCUO{psB!LMa!rO)$qIse60Ru!RPe317
zjRNxq3Nplk9QB+H?2y9+$kZ=@AYou0)+K9Px;$IAVYuF`N++VhLro-TD7Gz~`OB~L
zUuLBxrX&wS1w}kVvyuG)`{)}G6Pfs%8k!-$lO4k_&B=5j1)K{Tvc9ftncb8ARF4*^
z{@6y`pgUJz!<m&!__Oigy8Wjw{Kh2tiUAQ!&t90ZT>a$rnUKOXlu9()$3KcuKIZ?J
znQGIfem?Aa2&wTnIaR$4unggcNy7X<pR~{~*XbY!(u41mWEe&<w!ruy^Ekxk%aNw@
z=Y`vb<dRQ~t`b9FgbpNxd`iYguwKlV(8r1)7Bq%CJs4pqc|POu4e>)cQ98V9QHhM2
z8cNo+sm`Wn1CKg1DG{!^s*QEf?MEw<h+qrub#fR->T?6uF``H0IXaLg&W8cuA~Xr6
zC-R{J&g3G7aBEHKgG4(AYGCvr3**exdZLi^H8iPI)4>q*sZ~@86e at pTS8FHi{pkJ;
zzPUR`<;%>PkKy^IiAgR{xTusYKhL%Q!STj9J3Zp;l68o$q~Fd>2<)AfPR8Kx#-aFd
zwk4)e_Ai4m7$%WQVfh4oSV#quDwjIS+78_}?b+*n&i2P`O&79V?`jYELjsYsAK!}T
zOrV9hATVL|A$B)XJA at yI?*qOW<WLk87LJB#Nz at dBebnH9N2Q8TTmldeYk@CY-P+|N
z_U5AP6hKJ;6XyWjfU~lYhfDJ0bdU$(q>&Qxp?DzskXnf!c0?@#A4d%^0mC?y)JhQ;
z4LdE#4IGz}Kf^ss{|GxoL)D;Y9-yQ#08mrZxRK_<)fTb=Yz~$ra|V>ew7<8^J;;du
zcmrIOC{Ec11ycfL14~Dj)+sL$Mf!bU$J4J at XLn~@S}~NRDM~Vwr720<bop-O#N|$0
z>#eBPgyU=-;Rr$D2tprlegX66J|Z)h{$EO}s{G%&L_|bHL_|bHU4za8kfXypbOO!-
z>Eu2^8Y4jmVD2zGfkT=B{d<9C;Ccof0X28XY!~_+2zaMEAD91x!Rr8 at cf5#*h=_=Y
zh=_=Yh_{{L=oym-sCnDDcL*y6Dh31KE5TeDfWZhH8u|qQ&??-pVe+wU9#koX>pc+L
zCZX3x1BlkU3J1I1L_|bHL_|bHL_|bF5QHH-`(f-Gflo8+0zN;K{{Q1w at m2pk2k5^Q
z=rlE!Iv2J-Eth2zZ3AH~xR8j1&ydzn;){HLB?uqYB;vuRd2s at GSrop6!Woib#}Y{i
zo2<%BifW2#8rp-{{e at -y*_L70F%r at z^-E1{3r)he&mD&wKsA;6QiEIAG*h6~S1d$Z
zq*sa4S`7vRfjE#Nd;=NI)$HZURmr|#6MB*mles4t;$Mk^D*^L2tyL0+<?WZA%@An^
zOn`D`FH7H~!Ql;}xG+#XBy}R2$1>sdYgsp>;{k`%<zUlgCLIm&AxK$c%*PyHl;kGd
z>sRV#ZC*3_SeIgXf7~bQtk;ZQE79{|Sql=kE;GiGV;0h4_!o_&ahEcM$u2;;|H!xq
z{E7(>8U$!Mkx{rEfs+U=L>;?Y-pmFIOBy%XZ8fcD?-F1ka2S?>n_bv0Z+Fr!vVzgc
zIb31v5QDp_k5WA~!r+k6+=vJ|!H|MY;ekDa>cFpCY!W;R*&5zSCCHya*LKa5L^^p3
z%y3wF4!7sp+GsB{*ZBy9$5{0i#-naiUcD{IbEsUT&f#cF7z6B1ZyyvUM%mynm!)ox
zqLPiY8_+gXV|?nBN7%^m5K`$a!x#ozo>bl|m*hhYY%JCmVMsGJ*s%ZhLHbtv>Sw1d
zw;&oxSPsx6exDcy!s?Pe-+8X`;f3#9z;Y=c7~~yFrTIy%A-_{`*vXg-gWGX04`D5j
zr|}I}G692l5F|evQqZ)*SR@{jCCMXf2HR`^_e3Cl-sj4EWchJ<NAZvK5^={4cY3SW
z+<&<IU<d3FBnS5xPz)Xf(?k~z0^^;7297-tu6b57utp%v&Lmig*eEoIL!a4CyW{9R
zUQ=N#!Ls1Zn-~tu2{rCK!rpEyB0{L4m;xx2f>MemA}FGeh$NJzhMJ@)3KD`Tp)YSQ
zJhyYosw`uY8LBbTg~CsfR1+umO%S8&PcYcSqZz at 0))I;ePi*s?dEcctczm=1>Q at 3i
zcMy~sYEuU3I2oaeM&O;3;s!H!6g9?MBqU|f=i9BEA~dNX0ru_xx$rDVk36~W at bTM%
z7Hh*sdI;JMpKlCGX~g}@Mu*#HjBv(b_n2Y~KNXG%b%`DArSL8nWDUqNCo7~&Az%~R
z<qk~hWPeckQAik~Y&<rzy%|ej+ppzy`e=wjA|a-{>$&TTLF&z!Gv+#s>w_iTZY_uL
z2w|FTz=UL$o?MOOjgZJ$K0JqLFSapw9ivMKDcwega(p0nL3B>#Br@=~+|lFn?^u`M
z7ZP{qJVu9MA}UTfZGj=xYAmR-ko^d}HuE4Q)-K_CP|pk?&WJ8#4=}C7jqin=9_$E$
zN{e)C at I$XkAt(&)=$O_)5Y{|ci@^IU`r$yDe5fGW$j%0ffO-aDFdA2sdt0IW2Zf1N
zpv?>2EQR8x8tw-Rxg3PpA!5L*WLJnwoEF<@yF-T!8}x@*G at _Z`8%)_DWS|QSE4Mwm
zvqM}3Ua?e<v8Z-646=C-uJI`K1Kvn<>Y3t(ia%mPP$cZFziwRgVJbE*W&e>xiXogv
zv=`9eum)&Ungs-2p-l{M-<9;<kf`c2wJyHZI66Jh4a<C#p?3D~$Hj}^%a;&=1He7b
z1l`l;wDCtRHS}ETcCB57+2$@3dhN>C4rD`U`*o;viWquORR02tTfjvHeFy&R_RMk6
z=6YBKdZ`1Xi4*vTLQ)@T`VqjuMkHT$GJqOX0*QqQm6=EN9``RLf~)?=k)V^_ZT;9^
z_Qmn}sLi#xMcsuS_JtI8Xn8}*^k>ZYgQOIfa-U-qST(2UHNBmqKxGARYX}_t$fdKE
ztIh(vR^TdJXBB3Ea2&+2bc$>JNA(yB;Ak-<hViITA{2rrdkJQXA>%>znhBrRpge3b
z_deP2dgqJv>(&O|yps4yako^Fo#SI^^_p7D&WBf8S=8q#RV<eyv4;j`-JzSf0K#zh
z{~B<A7mOr)Ok|0Jq5woFz)CK(*_$bq7MFyuJ?aoG6ZHOs`ABT^px{vY0={}7<6S0R
zR#;w(#JT)BQQ7P4Qg>MZ8~O&3pc=l^RdD){uhtHg(K!Zr at lFM>Bs;!U7+S#N%`?Bh
z$ERD?>6;AqG=-$MF^&Uw+7<qpee}?h1^xVV5>HtCjlkosfZ_=W7nJRCOMA6p=MVK3
zwZJn)vkkCC{s!R86GCIwXBLcew!H(3i#5(+>qkP&5*;xXb%YpggnY~87G=BCi at IB`
z|6T5(lt2zuF+EYZC&+hjszBx at kBxQ8X`nRNs^&O;azkaGg>-rFuNnGqWtO3EAqE1!
z{Sk=;C6({cj82m4E9%lc<s7iFhzBU7W_{YfO7Uukth5hGPt_pNRdNTVz-f${K@|QU
z=5yuo`^h-}Noz?af`7zj{zK|d*thz+2jZ4Qeq at pYND_(*J4y!8gZZpV2h04Dmv8m2
zv+dh|-*@-5v;0e#AE&t}JbR2<YI?Fz{R9Dy9ewjlN|UdDY%sn-N3u`IW&CUU-!gny
zC@!CB-?>x$G_|ozDPGY}1iSsKmA}pNV;>H&bGM!}I?oMuDYz?B>|(<Rm<8<l!rDb{
zF^ajo?Y;-N&(~djE}5XiH{X{WSFwLFg;_#_^h|@0Mbw7U2D=sqT8)oVs>n=B*aoqL
zy_~rCS7L&jZuf1ll1f^UR5k6V??u4jJsGfp%@?7YfH-`x#O at gi;SAqAMO%7y-_yGs
zQerJ2XgUk(>FPBa7cD%kxw36SA#JtQ!o#R2Y_q7HS|VYls5ITiW*ruWB?<<KvN!3v
zH|&<e5cB0&%YNK~c;7t8XgZmvG{z!dbYmVucVa5-6tc}M`b9v;9OyKyBBX;f3s6Cv
zRb0X4{Rw%m7SSCHTvQB;a9zO!p`3BG&r4_<D7qaG7$2MCIKyvv<k?_sJH|JNiBb=0
zYi6nt)^&Q~!O92ANkOC;gug>G6X--_GBqL|Fz_put%LCs-wSsHL5EHS55j+zvZREN
z+gq|RG at QBTDF~Pou-e>18oqlch1%FSJ-ht>3|Yr#-+P%J<cO`h)@O5dh^wfWS;bvQ
zL_N8TXnK5wG%N?dP7dh%JwJ(#)T#?^y7#RFf}wc at aJw`x&38bXJ8lJ#@W$M8=DAF^
z?Fkuqk}nFyeYGNwR<^E{IaZoma8+(#w!brUKJQ(gHQ#&Qp)lg4GrvrB=WdS*YpzcE
z=QQKr(f6YbSl)=E*9;WJ_)TLSob6m!ZkIc3o<V at T%6CN23X)j)Wo9 at _66Dt1Mq~|z
zT5KfQa3U~BRdU=YB22*`ULijKJVLZ`&5#bvTdc_F`e2zAC!DCnbYXtpcuGUKd?nJ^
ze98~0uA-;g&H|g<rMAH#0O9fO)RIFM;PbhTa`oNc)}yH6@}DqcFNIMhiC$owm1?AH
zOzMcMrei)niqg}uq{Lq_EPQ$E=$^xVut`K&4kD`3yn|6o?v#nR09Y$cG<A_=`{iy~
ztVK1ojm`#+wa)Xn!xG0{cU!+$T099K7W7`3 at 7GW3-^4J1Z;2b{Vj%Or{Agy4&u<mM
z3~N#zk2>8f2D*Mto{gcQ(dQfL_*o9tp@`3HvwY(&v?-XBIcFs&7XUD9oAxnM{Q6lx
zu_T%Nm8|o8572G>iExm(;UNp2$F*2DNE||^(iaa)=v&CgqLK;{0Lcgp^<h$Ysu{yo
z85goqo$Ibiuv|XQ0LPzB+G*#my6O%;U`Y%J1OhhWt{K4&>1$lhw~Qz8jacu6PkNiy
zBd2${s538&+Ojc%X<UtqGp<^HH4!%4CrE$bA4;fHHjCaLNu24w%DY>k2;b${l;)lL
zr6bgV&K$G0bVywceqo80#(ir>keBv`(Xp$a%!9`?G3n_$4EBiTHa4^YwR)71-isae
zP^HbMRu|yR%JjTwYxL at z*lL8%R*^jNw77XPA(dMN-iNa<h^o1f6)9>)0erLiUqsNu
z^GQdx`gYQc)XxK(U3(+48|_|F&^(wtXT`AC(0E8{I7%QNQHu}A3kmnh&9MFL{ehX`
za`PZ;9M_0}Obw_hq6kG(0e{oxql7nz=h~K_k%Gnr#Wo1r9l<-pCj9thAYd|D93dv+
zIO|C!bKi%}ZW^SV7hca%Zerm+J=5lW=HYW;xtWGcY1MnBIK^=D8^tj|$e?VpLpn+k
zW*kfO7*||bRnH#~y`eZWXDN#V1 at DEI(p4M<@r(u}o#}ZBfJ9%zR}>!AI`2Tiy9;j6
zJjgj4+*zLumRnN>vJX>JP^oMcbkbCaonb}ID&~(o_QyuApwr{?4Y=#Y=Myqg(A+*~
z&lOPf1}X#p#t49X;pjgqJE;zX`v+v=IA2)AA?_Lw2cg%$;&+y5IB=7ulKZ{ohIjMN
zBR84tZUfIKg`(7upos`ogNy5}HXbafFvTT{u?Jev(GlwrCnw(>48Q!C9rX at OU1{DW
zqZY|fbhZ0ulYD`x21(I<dtJ^xO5Z9+x0{6*5pYA+FBTK8CbS`o*I9!&*KO#VVr&}0
z5W=gg3K0rE*TTpUJO9H?zA3OAh(bv%<{rPOG_<eb9Gsg)D<7u)FXBTrU4pK?D0Z(C
zUa8rGYeja>%439XYRYiF%VjWvL#x9iLaQ&nbroRUAby~R0DzV?`6WTY6GVvs4xZ!2
z*>mHr#`6-RQ|dZ*@1}X}M^mX85<&?A3ARa-j)SPN-8r=JeG!6=1P`emzyr=G?44UG
z`6Bi$df!kcGz#6Q<PF at 5=8N#ONt{+4piLdA5<px8U-p6R&T`PP?1s@!D!EJXSJH};
z*XM@@4It>2Qe}Pt#iXrv#x&ytPf;LAAF+4~z+ATr<?FfQX9dyKJ=XO-?4aDnAl3-h
zv8kBE)9K^p%tdeKio at rD_G;4CJ7PNPpvxU#ITICOy*zz{HjpBk>(7 at if6@pW_?)&?
z0MY=j?MNt&K%f#RhJ(mwE-QnMEz8<|w8<gA70w^7AB@}>Szw5kPGzNl#AF`NEgu`4
zci*LZTjmhhvihFm<~&!Su&TDL>%di2DdrP34XH?7w&vGu*4>$2T at 2#v!!NA#2kHoc
z|Ku8sNJ$N&r!9Bt$R&&IA2G+49nevI$On=^EC><;FCJW`y2lR^CiAwMsTzm1-w79>
zSyuLHa7S>rmVg~%hzvk+GGQGE0d$|#{6;xw$D(&u&UL7}+H{!#j7bn6$-*qXSstn_
zM2Nz_>wyd{`!qZJ=AKtGO{4vV9^B}WTEFYE8 at felpX>Z8%3&0S_a4|1uo}HODH6}V
zko9 at pWPbDE=~oJ at vt?X8qO<M(Q8w(?Wr8Dbkb#N$e3-<Hy~ghro7dueV?|1_{kSCH
zo}*jwY5L>_=4N|)K;BGthNhM|3-=Z$;P;97C#(9}Bs-~fMC3c8`<Z_-J#OfJ(a+7G
zdm#lXRP$)dsJ$~6pW`gnw<N<GGk;C;Bwsqi9Ro);m}ZWdVA^8wuKQdr at bBL#9ySPR
zwgKtGkD at DAcPI#aKTEr7pZ058>x-DjU-68YABL08#4Xj+KOfFrnx|+tHsHwF^*Wne
z-}W><Yh3clKK3NR2Iyhgc`mGi8%zi;mM>-F!~F(+&fe=N8Sg*5G8iuQZBEQU3`0oh
z_G=<R4#DCEn|qkLr!;WBMvVSCT1(tgpPA$zI-#*0MS$$=Z8$hSl<0)9uIne5V+eTJ
z$T;uR#~Vt0iYxd;liYsys|o$kAL)P||3aQ1xz6+GLnsG9vBqZZgkgSLTKcMF88(I_
zwN);1 at L@%Q+4h*la?$g0l!}B7=;5dQLT!H%FiH)9)0)&_bk6N9nhea=H+H98<6gfP
zvK$Bqy^T$eiZDV7b~x?keVN^vW?3<>!pg|49Qb!@(|^lD3l$n)vxygJFlZx`-Ik}M
zf9Q``o5hun!?u}ZRe8Ym<HeBi1mag_aI(fGpuY`~hL)dEwM5K at A|{fyS5jAPrSYuM
zn(QyH*`iQY+9%HOC^gKBn8sLadQU&2U1X<9ECR+%XqEpf_r#^j?N#B1S?`f>&~il~
zZ1c6+Y6C_)rePTnwMsnkIMhNF5VwRNtQM(wz7U+w_qrHC`P}+g*CMlA<1blsRIaKl
zE=S$lN#V}FOp)rE_nk+?@F>S)r9W7G=eKH_``F;hjUahxL9}vU?G2+LJn?McR6cMj
z2hJ|=?XE1Ez}H+ at leBb{@3KZ0Im6`5PVODFHnwBeiF!m`gGR at Si=`2njalCcY=x<a
zcyr+p-o>ozcNkX1eY53}C3_<;`Jc_oMH>yLOf}T{*;+GieoTxQ&9&EkaZnmgJGeVp
zWC_IIK9UC}TbRLtm at 6C1%8Zw_mW!fy at WbcLQl%W-%2Fa1xxXm)G&om{TIRj9e at N1k
z;Rm^wMY7MXRAA%SDF5G+#gH`4S$pA~*-*wX!#K~mU~v7=)+6kLQP!x^m#^`p`J?-L
zH`@cZ#>-Ibsz=xPX5VXp`CJYejbqCoG<olf$(GIz*uCb)a`z9s(Tr`ikjZq&SZ-gb
zm at z(%9o8AFp58R29NqqxIRMw^bEnxT6&G~FKKgksmS&qRO{InPR`DCFK#8D%-DPgj
zYEdcCuubdvQp}P1hyNl#g%pMMfdIfj1p=u`jv&qkC5pvViS>|D6ar8Rhr^gr5Bne6
zoFDoIibRtCZp^^Qu at tpT%ra60GV+BZ{gI9aKh-P$J~$ZvZpADDANh|6?+-*WGRzu4
z&?J(PCn4iJBqCnsGQmU<|62qR;xRBW1CcNNZQx*HQMQKIkiujsyC^etiK~Ik^acoW
zi9!D;Iu4gO2!@hIeO726OF|R;SQEnPPO63=*ayZ0I}!n<4bg<sYeGaNGz}<qCpyoG
zFJ|o~k>TV1qlO4OL)w6!3K%LM@!Eo50}wzz(hg!^ioyT~0rm;|q5Q}FqxUKN1+>8Z
z>GAb`kGdZVuZ#?)|3Y+bHWz7ZKPe5vq;wziQ<7Lo_`0BcLg_3zD{;UcR7 at ONQWyRO
zz(M5EawZmo`2P*EC48ulHadUd7J&#?>j(rB1Ae at 9Y@;%>_WUu5G*qK%iY_fsy3Ci@
z$h8wgh{I|y|5>lVFfXkcA~HwpA3ot`TS~Nrg{o<k;iDZT$o&<c;53EEkTJonAO at y2
z&3|NYMu4V)RvZ>&OJX#mIAn;Ua2v4JiY^(^tiH;TSV|#)WWeElY|ajeBj3fUvfax_
zX$?GFE;A_x)M?&~gHfy?jY!&!sKG3q!0sN2>K>^QJ=1i}DI#|Wg at KV11Wt^NA~(vg
z;d~KVDZFsJGX#QdFp+XTvL#W93(=A`f29$6Fhvn+9T7!nx;w<WcQg1838H&!7z;WF
z{1aB;no?mcHn3iZqaqvOi{R+!zl8PC4r~~~Gnh9Wc`W=h8SCqJtprxs=s?glCmYWT
z)#eUZ@*hxaG83&hq*&pVwhLuyW#)p>TE=0{Clfj?M9B<tH at I_0?Y{1w8f_UDU9T*`
zyN~wVM!OA;vxu=A;tY;B7b`l7i|JGY65~EFMJg+W1nmsk>lZ+zO>oa%P>86Oty*E8
zKjc~{HnV1YaKKM+pB`am846WGDATA>=OC_PuvUsGLRdD|!B at Lj+=~MnLX_a)DQ%*9
zS7PP}d<U_Ex708`Q&hRvVZX29lzGoA^zBPyt+B<EshjnCn<j~b&`YBuKO(eOa}O-R
zsSp&pZGf(|#a0w(UAwMxqqt|Ez*#*Th8hmR$S}b1pjDbn24Mo~f(r5q!ZR~0O;A*+
zt+Xx*1;J%pG*}VhKqhN>D@;S2G0loI1<9DC3 at a5`qU^z at LpStDe)OsNfd08~h<}6g
z$q)p=&ZDlCdjJXr{=d#SKQxv9fd{c55i0}&AYlRhlt4*9UlJGn-_cV3-vAHph6H-e
zo<=wJZU1K4mua+22!d3wVgw#e4PXl)7+3 at ZmjdjlU%@@8<esN={9zUN#=4t0`=(51
zh9E7Pm~suKT)9U?#JbF&h>q#yG9J2;z(G<MoIJq0(RxLQu`TW777KFe21721%##9F
zaX8s-KcMy=#6sb)(z_001I>2BB}KI_{cu_c!6nD{3Ms(j0RaRAg0K>>GNBL+BUMEV
zNAu+Dc_gWDbnF1Zfc8 at 0orJo<9EUv7+=-GOs<CYZJ9P#r2V<(b7D=YMWipaWiz>2H
zG0<(ODDoc83!whFY`eRTC<rgcg8<bIm>3j}fKsgr5MYum4gtH74r&$5O_MqS&&eP6
zjfWr4lw%~3D{q>&OWG#LW*(#bQpz3!QPsfRb2KP1ISnTzuzf|a at I3?GNvY<TCsZ2@
z0qi1N@&E#tO_QB~J;8 at 8FoXdQVeW^#c%Ebg1iaj==yXnDcXwe!Ys at wws&;e<%p8Gm
zEQp?}7EWqi8eCH32W8!N+)7SGAZD7Wm^Xvc8oc!op|VL at n}+71b%4Ogtdf9XA2)=E
zXu3lo^G;FM1IdsNq5#nl(keb_=U+K9szibm6r;#~^v3p$boGY&8gWe`oyrDyK at SAc
zu7Mu3rogq&=LDp*cMZ>Bi{vXE$56>ovIGbmm$3)P%w|ixqtP{3g+&g>C_)C~s0QNz
z?A$IAMRsDgVd!8_O68~_z`@Y>fzY05&yifiaM^MgjAD^ZAXFfUf5<<L$e%z)0w5v+
zA_!t47=VZffQSfyfc*rdLKq?m7x{^44(E5S6i{&v^{WjbvUMF#LdRP*1rQMMWE}I5
z#lYbx5Ey7836bN8DrMG4i7^I-jPY}x8Mrqi099^zkC4&Oav2gS0IyISjRQ^SUQtX$
zwGl%RR8dq?6s;{pP{dUigY<hyepEbxAaDdzaj|joiE)fb5q!gkL59!&<G&#2R_Mr-
zHubV60J)q<NQ9w4OiKSOQK%UiA0ZDB_9hwx_T(%d+BpJsA3!xX4qfPwBu2>%CXnb2
z+?$y3JjMe#4wdYp9xWnv3LAk$JfCnx=mwn=&H7OCP`>F#=8P4A0mv~6Q`;3h>jf|{
z4M>JO4btbX5OocJeF7+D0I32rQ$R!!0Q1%5?T-*mZ^0hkr65A4v2Kb9nOKbiLlC*{
z??@i7J&CYD<vYDod-wMsk-ovPtm#~*)Pu?sAZ?8pe^;MDwfTf+4&f{??D!iw7&lHE
zg}qbFy2GUf+_Frv#pT!V6JZ}!h^4*3^h7MV2Um&eu5X!;O-I(kSVN#tC}d!9PdIW;
zsF66Ca4}2)wWO8<V<+$=w4>5U2cjJh0zmetNIg)vVL^E&1UYs~q(I&w%?l at hfzV)o
zXxI{w&4c0d9hBU^DG~$B9e9p|fx!ntF*9ih7Cdm&3K|a(F91nTjWGR0jUv*0M2ATf
zkikLuj07kiQC+zuHv%Kc5cdcq7p)`=zUKz?9O)tOOrm7?$0#ot7lDE at 2?PN`KR|q0
zMxUNX>65fDz=;A$N#+gMcoe-n)2<4UAUz}+AbyX>>HLYuhnG3Pow2Xr{Sb==C8Lhf
z?k|+PwkTn1IAFaQ2XMG!VXDNjS7l2T5XKfPY%09Hh6M at 2aoiH-(LIGG%rOGQD#aP*
z!1?WR73`U}4u+>L{-Kct at FTk#d=1U<$AntV2O+o)7(5k*@reGD5u6kyfgvQ5Ao0tW
zTwI`|Z8{d`i3n~U55sRi?)U1d at M*X01iGT%kH*Zi99+x=<A$ZMPD at qd$QHz2DhSMy
z#bKm=X at T`jbx4W;K&16G3kO2%3Oa?u#oxAg8(137utb;zEvZyqB2EztTA`qFP<j>(
zuY!N)69h~F!UKA}gKj{O-U4%9utB64fqDdqz(9v>(Dv*-hlA6J29V&+BuF4?K4;h&
z6 at jxtV!;L)P#y-zx^Dr1_{Q}CaA3sY$%BD|CkMEDy)eS#aSNDEaW12Ai)HLI=rAyl
z3UV<^Nka#v2XsDuDMr#UQ?#L`3<sF at 4kFn#SSAAiHJP;tW+2?)m_%<t(FceSNG;G<
zJXB81Gz9 at eNfHGj0ZOrOfW$2ifaiOUGsQ3zCv)^Z!HgTzXdMR#=D=gp5_6l>^t6I_
z)xcF%3=ng68tyo at Q0QbFvc8IYp@1+bg{-MB1BZa&o6wksgJOmzi6TuBk+8QAI*G+V
zOo){8lq4Hg(y9#&=`}Db&|p3FCV~`@L)JYh*FlH5 at AR=_7BBW}%*`{`Q at K?{RaI0+
ziU at l=y!(OR3}0AaLhKVJ2pgtkp}F~uf0>}fipY{*5Frf?Y)E1nP;kgA4Gc7=<_wq+
zsDYpjjAC>r7)LP#gc4Fvg$YFnQUt(P5)5K6QnZaNAW+aOIx7&%45cL{B at HA&Ot6%t
zDpKjvE`|sgATY|b=uIF{gh^nB3=%ZCCk!UW6Osmont1?eVoC^Pz)mKRr3}fWLKsMd
zpn$=XK?EfPJi<CiWGEym29TCWf=L3BAgW=87-5DGh5?nJ3KD^6iK-IdP+&F+3<<DU
zDMTU(keCfL6ec93rj{yFU}!Ud*?`bs*rgbPD1gubf`S+&AeKT}P~m4714_XHNyyNY
zkVy>DLj;&GegU~KNm5AAwDbgNK`9yrI>w?1f+YfygeeIoB}$2iiX at mK2q};th=7P9
zMc8mLAjApGI7%7-;7I8jQIb*#AekX)qJStFsi7Dl2r5=48Az3&B!H4sp(tP^L5PV0
zmI^5(1Su#=i76=x69hU^k- at bBQZx!uODRD at MlfR;4J9Qd2olVk%V(2tIB=RO%Os?b
zFq9^Q$QUuCq@<vMVgg7~Bw`v03FKuc3R+1dl*yMtLrDQ808k`KLn}%x`sM>dP?Qu6
zBGODFKyiRHks%OJ(omEj5d%yRfI))+rAitUC{qxwg(w!1fN2^^N)^CJ&^ii&X(%hY
zFRUP?Q23TnJ`gfM^pP<i7c7Hk+uVk22V4(|PNlOsBuYdNM at 1hXgA9lpvs=>;sYO*8
zt?XtY>JSHjAzuh_=#pXhgz)Fc4?sQYs;a7_S97Tf3y-7hNNF6Y1JP*485j~qTwVr;
zWwB)SO<%CqGVvFvHy4*v;IEh}Ih(FNsQE9wvg`^MdK4+Gfz2`vfaWl}1U4Cw1jb21
zBbbecs(962Fc}5L0kS!`0mBxMu*hf$KwMZrGR$luCd5(Oo3J(jz&WnO1f|vl4Z+Vj
zB-Ow=E?R+MfEYK1yg8S-auydY28RI?K6U_!fi|{g5au*)niz00>rVrO$nXkH5YgaJ
zYH;8*7)#wuxImIfa|f0}Q^4xo(j~#N5IJg^6ou$@vC^0Z-NzOdhDQU31 at vYH5Oqtj
zb4~{O4&%CEG7a6$$22e(2N(dLz^1k|2?m6^4W5c)x^@BaBBJ-OWI-w at j$O4Rlf78x
zP-%NS8y}qxL!9TCL{Te4x+smMh|18hFm4G|aYRrYfYuxwLea+?Ikp at djCz}-4W-l+
zau|+htb~R|!*J8WraI-U#*PNUXk=T70s{tcE9MkJQcfBxLWQUgB_IQtb4`ehy6l`5
z<QNV?1I;aT`RW%*gvdCpvu*6byDT#NZm(Q1FfnLkGmVIVwh%iSn%hMB$Ok`QJTmmu
z5(?-)7O+?j{`_~);LSkncRs^p=seKq{CFs^2bx6TnVN>>3`W>Un6WCB)Tk&`<CtW!
zcOdjgf$Cs+kaA3<h#=WnnF>xk4_4|4lu3c5c61iPHU#t?&@3f{G=SswZ2H{bz8q0=
zGZe>$lO`ptxcn1($XC#PnW6|FggtHtBlx9V0tm%myC at lWzQ94UR8$%h1Jq-2u+kk-
zEAvYegt#~ivmF!3AO%GP3?htp!tihlSp`DW{2Tt8F!8u4P*8=_Jk?V>x=A53Yp~bI
z87-KBsDCnHJ~}?gPrd{0f#f_6gGh1KfP^qe5i3CceTSw(Cr!!6r<DunFmnOm3UUkq
zL);EQSC601Z;(!>8xt7_N-*HK3t${|a4L{MVrdXk3NS&7ng^hnk=K?$k8r@{O~V7Q
z(o<msb!k+}fo at hBqA>?GApg5zxbJx9sD*$xITuZnaj`u^2G-!M1Wj0|=D?_?Aan#5
z)-W$LWMM&JV?~WBP(W~K1|H$uPUlYpE7Fkx3^0gs!;KWeT0w#lw4}&OGlIeD8Gs=R
zDH5GVgk5wUQicVNgOF%o(CAnt51eRRgaXG`s6jhmjj`=wQ)9yW2IYemv<DoUE6ODR
zM%Rj?qP{vhM0id8kkQR7n}-3<c57hZY!sW=-x?d%Mz1%- at XZoIcpHffN7IHTG+<>1
z)I&FOElg&YtkMTr&s-cD4<u|(9myFIRisHm*C#ofbcg#!BT5>Bp{2HPR50A&YzML^
zHZi%*`mJhK9(r7fqDf?z8;>B!C}6o`1<A0bM|d$C4pGq+8xI at Z2sXy(ZG?>@EvIaa
zWK$9|o8K at t7b@%>He)w3m!f(^oX|KF0pg%o<$6Xp+({uLxEEv6oK at Xa9$-N)t$|M{
zas=2-BtZ^B9LF8olo>zz0vs$TJCBguc>$@KKzL>fFb?@d at dnl{XlKhmcU0x8qMCuC
zM at pfv69cGt;M7p&cNw}4p%qSpOQ32s(JUGbhjF;(@tfv+QYc+I!Q`hzxb+lE4D%SA
z(*bbEyjNa<Ny6%jkmx^Auw;4wR*7EIZ<?QuQoCKdkcge*2A~y7$sjg0R1(6gjyMb!
zE{Mw-2s#iv;_7;6q8SlI$|{sZ6R8JyB at sZ;6H%1m8WI$^fcho$8;xNgI2ss$dTG}9
zvu`of;^VOTd-5~~tM1t2W0C>ciSrT<wm|1e(shFp<5)zH#2EsRFbI^;dZS%OFca<M
zK1g|@UI<EFgP%no5d`blT}uuI4TNZO3Iwu{ZZ|YngI}cudRmM33<T($)9LaLa}+g@
zyNwLbj5yd#cFth1kZ^)fXx{{OIZ<`XG~YWVxf1DcqWUJol3a;!pyV8ZF1w5zBE3Np
z>%EpJKp<x2*#-<0<X|`F&>mw0=M2Mb_(~fOp9zGdszAS}b{-J2n2ze^HJH%qn6^rA
zp6Qt8N!-9{m$+&Xz{T?0Qi^GJdWA2QyA2rz0|O2MSSTvi&Ot3Onx$kl9V~NzGm)gA
zGZ2H?o3t-;klk_}X2wEL!L^igfN6EO;i3r>l41_9?kXBq!ya{V889peIK?I*V#P)R
z<OCWwPLsTmc}w9<#sFa%Ab^2^h6sFELn#PCECKK)=E9kbL?WDlgPO2(9EJ}GkbqGJ
z=@-yF!>~rkE+UKLkRi->V6+<h{$(k4AY5p9kTOs_4&K4sfRZqVDFeF`KLEkzkaHQ_
z3ylqjGaxgJgPCE#o~OCM>M(Pm)(>pgJwk!xIlGQy1`Hff!O&=UA&_W8QL&)Z(2b=I
zM<XpZ8cc at n!>LEA;c~h*8SXbQ98z)_wnMH`17WahfygjBp^(tuLD*~sXW$RQ0!5sZ
z>ALz@^$7n*>E+op2{0W)UgogDvWQ0IFpgF92hp*!sw5q3_6=cQ54a`9e!zfx1Py^;
zMG^>Y7C?a(MPIdsk>NQcn~zh}Za^QPbGs8kfSkq&(+A*9!cpep!Z1oxG2ih~bXQ$y
zdMHz(`p|kP3W#871_=|Wz;=olgBAd0hmv-%;D5w-11Fet1LAn- at bZYIk|-u>BC4UD
zA=x~Hh7w66rC`FDEJV7IQsDgj at AphBxax*?L_ZWCuRmGPVFS>F?;@C$$tZb3J#p-s
zrBM<BJ%)_Fj%m#6?v at h4d*14Ml5y+?eIb0+*lLD^KHi5XaB-&ORJkpPwHG0gy%|-H
zJ1nxyGPiEDu<?o_tj8lnvWI|j9>m^kIZ&hw=yy~Yx9JR&LN*XW2a!q~(;-S|AW+ym
z?drY*<;ZUX!qdF;LNEaK5do+f<Vhw<gt0!*=JX61445!cbLd`lbhu<3I13&b$#71T
zlms*gn%LDJ%|q!9%g&3ixjaTGX(BqaXMuwS`IYMhA6P_%Bwq{o4qk9!7ZeRD at I3Ma
zP818dWC6TJf&e9i0z`;Jdag;H!4wWe(1MPEnDMp}OfC{AYJ&qmD8x1x2Q;C<5Px+~
z&W|CvnCYLp2kbaV5PT`npl)>-!SVJ>0Ngtc&TLSmh|on4Lve$}I0iw<05V8}h7?l-
zia`p8$pL~?SY^<NVU$itp~*o*feHi?DzK8Q5E?`ui-Cp$M1X`7l9*soNFYIb1dGUc
zGAC&iJB*?^W{^6B5$GXMIv7R41Q0y{V9F>E5`YJ&U_b(ZfPn%ck3{PQ57V^)<=<gH
z^u+H at X8`7s^}}I_JY!@V+G at Sv>6L?Odx#Fe at FXyX)ENK|07($|k1f~{l&ejbhC(5d
zj0Z5*)>MFj3$fgC;W&0 at 2#kU00(V(#8Vt}-HU`6iv at B_R1fk$|;z<a?Lq|ZU8ov~R
z=7qda^}0k#7 at m-(@ahbAA(##Xs(7N1&<9H6iV1={gs9+!LM2DI=Rk%J0)jL!kbV9r
z^f$rcbplr|CVi1FVWfJD#X)#`^5Vf(*qlbs5HxTHNE%_t%b!CUd?t1bnlh?y0LEhn
zuz4JkG>HZ=1tSJRk{=3l4Yb)P-pgvVO>TuI>iYt*66hTg=8=j8lr|8d_9Ou0!0#R|
zgQ)6qoJ|993kaJGKzAMTgtBEKTIYhHV*p^C13>l|h0n>~oj%v0Uy?*r+#W*q6HqV6
zU_rssFy8h9^H3o7vQYy?Duy`>kTNQD^Ec&}MC}Ty^Bxm`9|OoZUa7#0HVuO$gz}eA
zGLLdahtP6M3Sf3y8%F`pR1iSeNT7l(1GEi?pgQ1WL9jtG1GOcV58`8SxEv*z$ixW%
z4p48t2zV@(>Ev?kM3PRXnPKu890AN9P7t^Y2Hq?f0DwgEl|co^7W)GOthnn#;4B$3
zOoNed?j`XFB_L30q4=kV(Mtv3XsjCv1VdneZjoIS^;$roNN_$Cf>P+Ku<2f at nfW_~
zurx3&duU%K>8_*1ctA!8LQiLOP7cb at Nh21;w1dzD1pM}0M<8HqYz*`zb4of`u+VII
z=!6*R5C}00h&|&*jWk3HWE49drN=?^Q02%bXcIA^fY4Rf3i}~|AV3bnMZgp=J4EIN
zMh3!#3=)L));;?O{nL+h%^=+%)CJn%k;~mPV&xz`hXI)eCj_$0yMci_E`aC|U<c>S
za|5XA1uVux0yY{$xa9N|++5H&8zO3&skjH1M7liJ3PAwih_ at J+1_YalM+0hNmUZ%N
zL(R=Fo1uh>OG<OmZp|9dy4fjmEL(v?2Dzx7U*0s03|H=(4*}3Rs0YLcCD&#+p`g#T
zNRPn at nW&hegW#QWf%J90u`Ss<aV}UJ3|NZ!&jJP^w}cyE(LFSZk8ISS at Dl+Pn<dh~
zShcJMLpTJRw;v7Pz;F&okqd3kkbYfYCgNl%a8d(-gAZB*sd1n+V2@$<8}D!_UgO!~
z90n2^7zklFG8_g2L5>0jqZGjxm}(%G8x2H<RE`Ucz`(-fZXH3(@)a-9OB|+Wzn!-(
zG?9#CE(H`2U}m(IE*Ch)7m)CwLyQ*`c<a+!sMYKZEbaq(!6OqR`|DUCv<V#q{YQ|}
zZ$;Nu076M5sfLKCPa<0+^qdTYgpy$J>vWW9dMm{`!NodEcA`luFbaE!b9<S`x<V%A
z>zP at B)IhC%cS6ASQ!sEh5TF|rJRxy6yabB8Z5XmKhLNsodvh=XR)JQ0!M}0){C7A8
zTeO*O5qlGbyv9ztSy*5&HB5j&iOG34q;>}`j})jDd8tB~@n>;?nP|Y}uxb#7<6-yZ
zf#5rjC>(b-UB_KU#>33CA!8iY0`d(F4S~4zEC>)_hQRfCaojV_BLYvfHAsDdQU(So
zNI~Imm83zWYnu0TP|bvc@(%uqn4S_RU&%ZHth&<Rc^#D at 5WqnQ!3;DYlm*Wqf?zs@
zcw3z)(4<I(BZt5;VCgp23yR57CcZGHX#p;tMx923qHK~ul=cs}G3#EE_8B25I0>FB
zfQHhJpov36L3j!b5#X@{fba at aA=N1ulVNNPm~%ozo2CNCI?FMe>IKFbi(nhTN1j83
z+-wG61VeG?rMI9meA4BIsP|AT6HK)r4U6(P8lkw^AUE8)fN~*ViE)Ca2#2w`PH<H2
zqyRD-4KFY{#TWO42V0zPr+0G%IJ5qQ%9AOm!Pl@{=aINeC5Da|&S|`w=U+~TEI1Pp
z2M(M#nJh4ahzJK{6KKHE@`w?XkYRc6V3oCy2+7EQNO?C;an{P7V}gc<unA#1q0CxP
zAjE8ffuXYdqRZ(^N(hFD6F|o#yg8#KoKjwEINa at 6pkW}7tYYTzf(#g>fVA0Sv3!8C
z^BkxM8~~6fiC~mEjCuya)GkD&Uovii5jGGXeLjeC15Sc;v1<?tNGGFyqAnpo-6fXN
z$J}n{y0KWS7=Xag!jQnnVev^v+NSo8sDy!2uGF=1K7dt!N%0#KMY28#l%UF8-Q+t)
z1MVD*<3nS$gVE9lop=QegVwMT&~+7q!2%D{>iB)v at u}?N(%BrLIRVH{4~r9k2awX}
zeBsO_v>yP}WdL`H2i-R;6JhaTu*b-Es02lrRwU^OP9XL3{TD-mK|e|`G7>*`se=Gw
zf?s{$4{_f>LH9yCzgUlC=rneS9Rpx<9L5eNU$;BnUiaSSc!Hk`!rUOZgeI}3+jKCX
zR^Xt8D-sIC9e(hE9EW6z*$g3@@LgyiBFLd2AZn0HfSr`kLdb6g4rE_t4Crz}!0?fW
zHZP#&+ at N(Iu=Nn3j2YO1-dI{PS3wJjjkZPsX%|2>10#Vo(UhbD$L)F#=m7`PB7STN
zNFo>xy2iOS+-(7sE++MX;>1K895iVU+`@*563E`FZxjX}u at Lm(a&nvM4%rxCp-F2@
z<U5Tia3~-`E^h5gKs<*7+^~EAF7vnxAjT33O@@HEbj)&7KrAFmOAf<z$S8KwNeOUs
z_n at L^5~hTt#48DDLs2XmDHmkO>5vWeReP at nT&iGFQid4<9>c-I#0U-!RKvmW9z>#<
zB_0qNxPUN<M1$}=hj6)PVgyLAi3Siz;l6;0NxI^=^sO@(1WAUBV+b5cLx_7aW<m)V
z1_U67fZ#A?0Z|MH<px0YK?Oq4ycQ2A%nUG&JA;GPl10$SnMqonz~I2jOdZiejti)0
zI$%N)E`x(XkYJGnv5R3eUdYl&xZyprL_D4MKb8L*$2sRX=UC?)dvlIW#xb(#*oSP2
zL>)7P>=io0p2y0}-l-6U*0GPGj#Ua}hmg#WKHq-&-haaVxZn5tdc3addOi=KAsgbk
z-l9Ull^A-%`I`=^8SG{(4W2F9aB;b6PH7vvIjDLZKtsy85~?L<h`BBV9(G~&>BV*v
z668p?aduR(5isQ(MXQW8xpZdzyZiv~-&&+FC~dc_@=#<!RZ!udaXPUOy?KQzJ9I=)
z64+%VR}8~Cp>yQrOo$&3<v5T7aP(`Jw?>VsR>fPNf_`PzYGK{Cf>$x;cVKEIy^RtU
zxD!(F;F!=1kJ~ylP%okOuu>54FTbsYJoJ->iY at 51!A4|`su8PJW?laBeX#yC6)jxX
z79voaVUX^-Z@(K5BPvd)j>s^brY3+$AY2RuPj=_ek}-Y>CRDXD!0`M)Tswqrr<E~^
zmsbtOQV=HW=dbspt7KC(TtKK(nCpCi9!are=rda5gD;`qfNmM!NsSjN4{}Eas<xV=
zR+Xut)mSau at kprKd%o>Lyak8 at VU|3nXSTY6Gzb@>qo%I2LYq_k(BTegDDnW1D(o1j
zr1B@}yW0xCK##bmfw!Lq%Me}YZUV1%$HZ at -^5#Fdie0G;dDk^of`m at B^%I02uHuYF
zfVl!pG(S}`G;0|j#OyX;g(}*Sjux#0@!)&}hghEkljbgjNA?|pQotKHa~sl3_)X90
z2mod?8TfDMDf>$8q~{6`+io$KRKW}eao|9&G at AY)q>!IqOd;%Y<T&t)j)jp7o0mx|
z0+6c-8v3p2w4DcnAWQu&h}u0TK6p;9{~uP#rU;nTB6Y!kT<!&;OH=5ZX~!W=Q`Ay?
zuT)s%rWidrSYcql{03m-{YKU4hGBYzqKCIxKq=+xQ1Wg0O3OJ^8N!gM!eJ{?<+crF
zR;hO0U;q5QxsOud#+3M8v&7KZ&w`1SOz!UZsBy)a3p3}ff(!dj41FjD<Vh^>dPtqJ
zDKiE_&q?V`ii1%553`>xrx|AOt9OXw3e=%-E6k`{Jz|q|ZJ_BX{=*I at rKJNgX(M|}
zRn<vL`u*(IY9N#VJRt9`Qsr2pY)6ogwp%`w#-$`~H79HOEtP6-K`N8&=qkvQ51L~@
z(Pe<zWCvGq`Fzjde;&eqKq at lkhag2SGKliss^+<zO^awOYV5l6n5E|(9G(&qKmKi@
zB&!~XBD|!VB9i*_Ta^)R3^7cnrYwINXr<JHTTNQ|!R|bQ%f$70<Y}V9l8ey}Ca6 at G
z&7l8Rg{-VYb9LS2P<$D{NDW)=K`&f;1|xwJwOHuJtaZ2Qz8Z?)`~^}uTYvNB>*OU@
zhK>eRVQ2$Ay|4ADM1s4*GG5$a>_yXa6~j?ASg&_lj&Eh#Gg76m_RtVPqu$i0&c8kI
zftkdc9ajyj1K$&>RJZ7vcqW_UV^Q$hPe<|8^@q&OmEHKBI1jE-D4NIv=?P~HKJN|d
z^9FyEyBqxqQh04cXVrs=^(ffCh(p(ioXf5=9mx|`?CO%o$UJFst!1_3b<i}Lv{baq
zShS!I(!UWQT+iGXg=VlROk}o2?pvmdaLXBu2h*yb3_k4)%b5B_8;abG3jXL%OIo<X
zhg(DpHoO8c4qg!AYY8>F<?_(PuF1>7&7ViiV5;kdMaJ(v{?Sxe&i!0iOy`USs|Js1
zt~6FBNrKHa5ACSbC+%AlyT_6q7=rfnN*~l=3)HoZfz=!eklxGJ0>ozCXkYd%veDNX
z=yq}E2NtOB>QW+NQheYjYo#4FsFLVPw``?P#id+9Ge*cOF}f*t{S4lELJ1kwXL2{Q
zU4a=Hdi?wBLb!1D{ZuHcRNoaBAKsG3OE`|c5GBH%h@<!>fK%Og3fWCNVa at u?ZgGCA
z%bU-+4v4W~kQ0sK7xq}cS+b%OlX^R)46G_dEsPcd<YqHB*U&+2*urdd`^CHz4Z`u<
z7`X{!i{Ty{-J}JpO3OdVRXYT)HMEss*Cl1a1dWU9<CscRPEqYIZkqOzGb9ZbMUOGu
zw%Y6x<U_MV-j8V6w{eIwTp<1+F>dNX<YWk0m-+qP3e&18*9zuu`H3^b6m1MAaJaiB
zgv8`Vql4?oPex-GD5j_o8xs3Xas at HQgMkFYv?HP(QiQ2&mf;fu21$#Ry(!=}6(opP
zoL*zW6h6_kA`P?SWlo~cc{gVjB(7(hEJ1rID9Bfy7p6^U{qu3H@}!YD_rEJDG0a?C
zV&@_j;|JC^a9cwEE^@ZDcmQY1RaU*;N;jps2vuzuo7!dj%YKyIAKbixz%oH*n?6nR
zZzksUZb>GLV0m(|MNt?_vQ;zubcuA7Fgb~%B|m%me7oj5sg>{Zf>7#IxXb;V)188=
z4}Bg&zcZ7Zkzyc~BsxAR at j4A=&wLJak0&DMv}CTU%_M(gOkrDsN3?4CGR-M(<%WA@
z4N{x6I_E=jrOL)^32R2uRW%a%zMvqosHmGl3u5zMsPir5Sor0SM3)7XBql11u#=?y
zxT<NmKyOUa2}8?G4JWTyb1XXQV{HLr5i^^+By7b&yg~v=xyT7c$2^=7NIc-13DH>2
zkrHj$)p#hOYbOcB(d68a16iJ{G!=Nmkh(?Q;bm=!iD&DksXm=`uwihLe!E|>bFrZq
zlCq3Km+^a$+(`qovhVu>%XS>qF)KV#%v{ciYBec~k-({#)Ax0;*Y{abo4=(w^<BgP
z%R$T}C_T9Fotvx4^75#3&xKXU65~M%tziI72gewsBg<*OK^`~?A6YR)gzFT^h~*<D
zf9mg9?$EMv!TYIc?E(La at re499Wq=VT#=puF=yCniX$%JgezV9CLvgcc3{`O7X6xX
z`E5EKRv11K0)6oivgW+b$tSiOW<3zGqnRei2K0)tYxM4Ie_1diJ-$#?MaseXv{nE^
zYZhFGJ>O}l;$vQlKZLm5rRdtI+jRBzo&!Hi$0f1S&sd1pw9^NR<U6kA2vITk(5eK1
zHm*6qnuoy_XVK-fNZ!<y)~hIZ2QHp?(*t;580Y^cnt}eW#sGsziL+^|%>ZX6N*`p=
zY$R<_n=LA_h&GjBJ47O!iG+P#!idp7jqpm9n-xWPK7`}razeZbwzD<)zqi1>cDpL1
zXc={Y^)-<6wfn|@j>FgORRp!&S}n-sYy9Axqx!_g^o>_=TI_H(b1R$M6_|j`4=hTD
z{y+wk^6&Se86^9bB09h;{sn30ro45{k6W!&<9!f;EH$b{pHQ`UE2lmsB>lmz^8)fJ
ziv6vt at H@4XffQckpM`KHORdM!$b4QpL1Pslz4^6p5vAJC*d at lV8#&>lK36oQ^uP9j
z*ZYG?&`uyj+O-t0A;{GP=|I0m|2t^W3TAk~1i39K{2fTxHy6kbRkF6-;<5BE#DAsO
zCTx0Vh%kOuUeS at P^b?It=~lv0@^V);3rXZb!rO#2$r{6$`G1)+T5tJZF~YhY?UT#6
zwr|xCNIyRAUrd{i$+lgHt}nxfS%yhDs2Nww=|KL1FegUGxOAr9t+t$$b<Ub~@=fRH
z3d6ierCUBy6S(C%OqoH7A|trN-(-N=5_YvqD_UdbMBKV7s2DsFk!jXDDCpH^wAAPt
z;#-h at ybw4V$M at aIL*}N9r*>6s;J$(R2?m3tV%H<$KR<J;9IhfwKH%23&d6*f{#*YQ
z$l at XMnsYXrar_jdPf!&}!})XBRK05wI$q?t$Ga~KBUSfU_yT&T2~Ma#dDX63^}bZ(
z{gE}xHe^6rgq?wOK<g@$(4qEGJ)na%L%`{?3KM!nQ0A-AxkJmRE;~Ohy9cI>84I-m
zP`p0=YZZ4QW&H)b6IMAD*4Gf<sxIQw+bT4a at Jqyi)4}G<UQ|SjO^CL~%TGrDrHMOX
zuq6+M$X2)&`=SQ){(%sJ?Wjc1pmIt!tFzf;lChQh6d;bI>hY-VS<8~BXcmFwT8TZo
zG=o|cTl4%|gh%(7W6 at R2{ZM`u@?Nc+4l9WYVG0Np%4HtY8TMy95&}Qdq<umy2CueV
zF>yXgqN)+d-#@SO)!&W-ML&+(08!mh>w3kk3HvHoL<pL7$<D^kz(NSs%0tAq-yDcJ
z<lU`<*OVH>pq?P_hConj&#0PN<~VvF<zGYn)nj#7I*{`1$0K1^6T;iYdt<XS4 at l4g
z5;2VGlXePYf!cjS{$eyI6uy$SD3enaq^*Qu5kZlHuG$&+-kWYSbN(dY7*>-J{1$?O
zU!3BgiwFT)D~St|lK at j_Cmc%6u}jo84b7Ud4+AILR;sW)GX(Y6N%$a?Et01cpJU?n
zluvGiqN980Ul*HOg6~O&1q%wtWbjmPX)rh5Shzjrekuht9YLPJz@)AfFvcZ>iRJ9i
zP!yU+kmc($L!64aIVfCBjz>DUfYP;D%UHSM1EwFZ5-k*bCRk`=L8Czj9+BTJb9m-U
zJv(M>sQl*8?m3YmIM`}47b1{VQ)7Vh*Wf4wb^Txm_u^@R^qB&gV_3Fa3oaX97E<Oj
zAt7Sl3MaRPd`Z>p46+cj+q^SiN*Os3N}?*UKvZI+736qz>>n{R-VA%_S$sn6{gWNi
z-*}9 at as{HCIo$dKSB_&e{TOMuYhEYi4I!5ebm_}o(g(1BtbF-^-`q#Mj1=hUNgEsA
z|13o~!5iU4Q&)7kAWCIBAU4L~#61A81ilMf!{e;&bbGS at 8{dW6B%O5-N)qWY^W2Oy
zl|7;4OK9b|T&?P)8Z)jLq@*K?4-6sA-`&G}01*3umwR>|E*r at 6020c(>=E%9HjXsj
z>O^uHW2Nvbf0MUlA4f<lZQ&ci1-2jvYhFx6mcT%&hWaxsc5SU^k~mb(Cuz1;lO(u}
z|0P}sQipzrHJ5xp(`e3(#|EF6Y&#R|ZVW8+3W?&w*ZR~^1I5|7l{$5x0G!pY<#!jE
zGbry*v;9^yadQrG2wxqdSgQ=hJ&T#gS at 2Ocj!NUymf!**q<nRKDZiWyN3{46Wh|&q
z#AGo0HO^m_27E{q081yHq>o3M0T{7y<(>cO!%l@(4I8>7Cx&?Rdp(5!a`OfW5w5v;
zqZFnHTs&r`l(o`hR6~f01&*jP$wl6nn4Yn!-B$MKOKWyK|L9R7#$jr>Qh_~tpH?%<
zx1VqzwxBad-wp|{{lSmu#FaLs8 at f&G+<Se%JTd+G<BcsPNa&L>(BGSWItD_*j31;i
zqC79IT)Y0`&bLe0?z4 at 6%O%_}Z+3+_6J^ZzEzh!C%l!8B3Y&ZMqxPHS#qyWL6CPmv
zBZWQIV5m{Q)ZYRxDxH?hBqY+?;oo_KFuw!^s<xCA8IHiKSLD>)A#<elinO3;wSdbj
z!u^p&?`|f}uX5*amgeiR;I8q}D<CcmZku+~S8csf-p- at S>Gr|vX9g)V%C&cx>!*Ah
zTG2`NJZ^Ub+ILF%A(!VXk2{~YeuVu9QolTa^HcRM5?~y0v~CR*D$t}eq5}GhJhdf(
zX2E1pqz}UAoNYv~M*$mZW=!}5I20OJ;i_EI84|J?)5^i>CQ^~WDSsPAPE9cLOW=tk
z`FwIk>UTx$*_Y|bXZhz(U&2%_1 at ivAw=?Q5Uo56bE*&f}x&Buyi%$sbGTV+z{{H7d
z_xS|y$=?x?Cb6!cHy2heQG(9z9E<!oGCUDhU;LnVd3rnk&DVRl(?1Ww70sFiICG!r
zWi9$$`}z9Po4ef~j^4+7QPqlRdn0XE%d;PCyxV%pFQE6KW<NY?@;heVeh(MWK(0A|
z{<(9o$i-ERRK74-hW)QeJA?@n!ZPM%>!>Q$@b~rn_ZF|4H5;8}ckF?Ndphf!jz7%K
zTS7dQqgItV-hXLW;MbgSj4(UTc at rWq|F>o4X_1&@(SK`S8<Vw#Sg$y+S3x6WCx)O7
zJOhjg at RXtt{6G0?)~w5}Wn}yO2mL&WV%o1nohTXU%zwRmsp?@1urfrAmm}e5vLpAO
z!1P|=S3>R;!(O&I-1_ZlA_#pyb7GhEUXfpEy-A)}>rB2z+d&uGbvrp;RBNw3Nk=)F
zH8&Sk`LXoonF$Z*KshBCfiw{KGSb0DqC;vjNE%FtacrCWlbPL`t|t at iY#jqwY}CX3
zea5HX=7U)pEk}n{U;bzgX<pZMx)_Q at Yr*bD_Ca=F2Wtp>OpI{(Kq743g3$Zk^UW8*
zN&08_Dt(ciEeT!$d?c8<iXbR$vb&(QD!%&L!gv22kOX!%$zG<KO>%_jHSGjAJ%Bx1
zsfK_*ORHUKubk{<L)_-hiC+aN5hXn+Uk51PI{B?TJ~{_zWe#)HZg6 at 3&3{H8!+VXz
zQ{Giz=mq|S0UR{58>J%*hmd*~cKt7 at fvihxga7~FIv86yV3LRp94(R*U|&jjV(z26
z?&Mc-7)m?HU`^T+)kZlb!kPRu04xS9hM!eyQ!Q~}Gh)7kv3tZT7d&+6r!R`oQ{2#z
z+DXJBm|;L^W<0QH%hOwkD9p|y7|%ow5zhEYwVZ6k$=^NZA7Bio at MZI{!tUKtPH&jm
zJgl%?FL_r78qr(k!EEUQr^Jz$;We#CD-~`lP(3ZKqL}4eZDkc;gXiWoZ*=A5SEL!8
z>Cu_HQuef%on+~dZx09iwuR0GR+(5PdC+A3O|p-kiWP|qzo~Qu?PVCk+L!c_o5}t?
zJoptLuwI7<t{G(|r1rZ_|IlxY$rOIU#wcIL*euYXdWcP=Z!D269pDqs`3MhQ+0SJw
z5kRnf<0xL&K4CG`L5LL;{Q9BX^v;&{qv&TJ&OKj=J&AsY_tlW`Tv$Btkv7aw3`g{=
zuR<DKt`+bVM-6Ku_X0gjq)sR7X41P(Bqpl~tr0>mP{a$O^o*hc0;Rt$^Ye1*pw)C2
zpH87-8Q<N++?J7$BEMA at a!;x%p%pjy4BeT!B at Dnv^2Zt=^7*RMTZsYm#JLc2G8XM_
z6#blatMdMwa8*_S3AlbqzV~w;-L4kwcH>x|6p&E0h8EFFu~8Eul9YavsG5pm7zIsf
zwiWHdX;vs?sklxmj2M)2 at pt7^R&vPervXjY<gx0*W-E)U5|eq42f4yl#(>R_L9N{u
zTLu);<i7|nq==VLCzSGB$aI3WK$k;?4V>3u)I~9X6RINrv6;(Q{xz<;b3 at 4rth5l;
z%n#<AhJC^!3Ax7;AoYolgFwt at w?q}*4sl*+x&9thcz;Z9<nA}zg7|zC2U*E7x$^gc
zV5^2Q4j~SpyUo7mG^1xexaKEM=cD?>m2eF{Ef+}E6z8(|NK8=Hn|cBq?DwFBJ*8^-
zdY$ea*DqIwxh|NhOe#RorZdXWe8Jvia_<StrXUH`nifFV-Q)4dGHl%9wiF!71BPE@
znY4ZCMnVW`(SwuYeJ!6lOsml;4A6YlP2I^roGKHyr2gb+j~RqeM}^i at DyiAQNQU74
zL((4l2Lz~Q^*zdo0R=c8ejKxS#rR0727@=saX7#|x75J03xgM at g34g*n?}>IY6i>g
z`9Av0ASR>{Vg7BxOl-C{TroCbGB<Q8ip6$H=iLigZw(`@1p7GSQ$A8qOj(aZr{62Y
zTIVg#m4 at QNv3Qe>`ACuAt^9xEh0zj{A2Q%d6xtKw7n!S$N(vJ2uzl9_Rt2WdqVY0%
z9 at P;-m7GbpKE?laZeAyhhAS^93|e_?s_UMI3Snkve8WVcx_!yk>d4996-_}{Rd579
z=@pEDV+PI5(iz&d0Q!n_VVEA*2FYC(#!vYhJ8{SS=FbAxw5$ZFJ%HG at I$kL5=`l`u
zx at LxT(DN2#3_ccQZPGPWIus-(i?UcLKkx0#e%^UY>MRTB_LOiLjv}@GG&Jl#w(>n}
zTXTvKsIPHh+_#wgVb*tNEkcOL?H*g-DtJ9!P|g3r3F~XOIaF{BiW+G}8qj!|f%ATP
zZCvhtZS6ya?+d+s5Jhm#J`X{@UDUT{UG;~hiLsMl)ob8$`Jj%>ms#FLuz;Y?{dwL)
zNoy>E8EL9k4faJ-cAu#sdKjJV at EM=T$Q0io$*V;FQq=<)G4{SKv3;a)hB+^@>7sZ~
zqwN(xUem(5oAh<t$A{S*f>1OoM54#{iat4}$i5oVY-i&`uA<y&o!PmsssYt|l0?ec
zr6!~HVMjuXJ*C+T4~%CQV9R)z*3676J8YxtqcQRieo at 14{sioS!x?teezQ$1l|69&
zzBd=7A(Am!egWd&B+hD2+7hb{Dk}rGYOr#4^-hT&DtM|xkXw(KfQLe_JtmgsaKDPD
z+|O8Getu}RuSA#lFh5;WdsIut_F66s05+JvDLVp9Sr|ML7eMP(CB1_L5tD<*Zpe6o
zlP;_az>a`Vtnq_Mi at WF;^c^!(XKg1IAmDLM&1at=DU}i&P?3xn4x$A$jA>YnCBcD)
z#T-jX`T7gq1_(28gbwGlygc<)Z>1D@;7&Aq8n&E>`Le8kqDoW8zvRng{eXQ#_a|;8
zx&F7~DrkR28+GfUmd(^p;2RrhgK_F)9jpH8ThtRL#Ug)oR?bg at 6%H498+*%U*CZhh
zk6mEabe?)2q3ogNR(*l<Z%}=>VakHn at a_5%5+N10=BU(L`H{q`7tPfbHEqq&?nzFI
ztya~v(*c4(B9uU#WU at _p72)3-yPULRFb_reCztqhUI{>Aj^L(dB_7kNj2y$#IcPnO
zcAFw-xKJ{x-G!x9_$DBnC5NBMTD)~lM1RE6BsvRH?NK#nSxA7r)!(}+naCoaJs{m6
zN_2!LvEX!`P=%Alc7+Z1Zjd&Qbs+FSUwWd^fH3%-c^HJ0A*N5*Vpg}tKC*CCJ4xbY
z0d-D3Dud*igUvvxJa~MH-au at 9Ki4`U8U;~$Oae&<X=jfdFVI3D<EZz?bglZhHG#~+
z%HDs`7i}dUnDX!9Lv6AE at +k52m~hKU7sPA2?SHbS*|;D##lKIUzw|lK?fp=20=ElZ
zz5hWgNc}p$M!MJvXSbmJ_1j}3t=vAkx2j~Av2fa{iEIV+Kj`1kjhh3PobF!g`%d?t
z*q<Da`0FxLcJ%D5iplHZA2H8u@#p{bv}Z4*6UNWSwNN3v_n6?ltU=nz?>Xet*SNw!
zYRHNyd;ISDpR`XnrYA=b5~sCTP?9QDj at _)}zZ;XVMjFcy>{`+=2flUE+qCVJ)2q>Q
zOD1^6J>+`j>&ZV`;9g~Nu9 at UcEqr%ct8J5Rfua4I=;QUIzaMgH;(wWo^YxoL@%H}E
z!w%nsyFEwjXBpqsO)fA4sVLJxoP&--G1+?JE{kmQ`)_`1RsUS+12-FdmzVz83lFVd
z|1D}bd7Yb4VD60;(VT#qlOyzrASG_Z9^RnMDvB{B`*_Y5hIszHJpyx=aJThpfonZ~
ziY?$8e7Y!1d>sSz*#!S$MK<_MG9CS^a){=vlb&xYDf><wrtgX~gbQ+LeE`<XGqcUr
zd6ubO7Pmj-J<dO4RXc%QLLbexj66d^(Ec8q2hC4vf at aa*+G!<uzVZl?Ljfay;=rYM
z4{o`s&D<84iY4K1a<q}=T7TW-kd3{3y-9W|vD>9OjT!Gcs&4PN+SRR~Phn#P;w4Mi
zy1GSFrFF^Ac!lgp6*|u)u5(+Y1eZ?t9Kphp!a~O$JkUN;x8-t=R*E+C{X7v0HmQko
zHlkkSN+G&0oUsM1y-tE`?nA3`!`$JcJL4A>UzWg3MXlmq6f5%)Bs0tuV|T#lndr`+
zTJ+x?!rvBj at 5nrS8TI9h%TEE0^lNjo&+qO9uql7aaysd+(W34Q5AyqizRs+i8q=X9
z8*lAtaplG^mAjys`Cy%KVknQIO~+fpLD8}-s;%4Gw+u7cNed8UI^EA5EsGkPT!-8e
zcLB9qme5DTmA^INww)fnMdbGnj2&6mzq0vXyAU<qP!Psjc=85OrtbajG5d<4bhNrc
zs5b8V!yL*hvI^sEGdMyS=!6v~I9eGd4n at hPx_&cF6 at 0t+Te5kXkg495LlOnMz4F|9
zcU}5r!;iRhb~6z9!=nTm`>RPwp0QuR?|gb<GZt0#?y2qorFKhnd5R}y1Rkka`orVf
z3I_sfSSWS$AI{~+ihcFqVzgFXQ9VoShf3?0niV$_{st}^oCqBsHdlwPgVaz5ZFyHx
zsMkjUQQWUT!Ye%Pd;q-BY=x;Imb3OWe^(yotnpd`xD|iX3pBMoA9+~}q?+sN8ARMD
z8 at 7m-i)Tux&7M=%43N_QrtVs+t}~j3*<t5!S!us=r7@@Efyw(mhNGEa(U<zFl(WPr
z=?J0dJtKP=HUJ(YKNFT^$YlF<ZcE}v#@R~lS5w$h+5Y=q&5vNQz>jQOJ|u6MGPVaE
z>)#*)BB1l#-NWf9{_5uH>RlUnu3|!9Ea;FliLXHlE+mK}Wy&GlnPNyOFri^<%pZLN
zgc4ui1?74f$o<p<L;Jz3EJr#qPnD#4WajGkzoKQ#2aa}srn(9h1v;gM*jr1*Tcv8y
z&*~fr4HA$v&m4AM-XKNHn)i={l~{V9pTyAO8OJ>b*uacX7Z8iJejWHpcA)z3s at BE|
zH2Szx$TKl7Z2k4H;mWV^SVl}{CF9Guhdbh8-M<Bwi<r3m)NAtcbmm%{-wv_jDVwgP
zA at wB}gbhHxwnf4y@?vHy-`aR6on&StpCrZHb!n)nSoHoQ$kWFKT0M&y!SB7;8Qtz{
z*9Io9p^b!r^o1ooiYs$Xnn-uoml{D1{B(vG!IS>^{b~F6zgM}~jD$!YV{J-~Z#}w$
zcIUHr8+V69n_sFmR}#}2y5EO1isI918A<*4)2VSgse}KXRopvUk<8+}0OqeVtADaJ
zaF+xAYYjz};Kl#0qJz9m6CDKt?oraO6Dj8(Qj){d*EDS1i%GF?Bvth)`iX_eG at dy?
zdk_w~H`lTtPmPJ*wFV4{J-M_e$Y59!!q}%+dN9$^_JLvbZ7+XXB8zLqgay`i at UbmZ
zx5U=c1u)x1co*)1adM_}va_Gsep%LmSc<hXKX-|PjfQMh!x-0rjr9u1 at 8e6jK6t^u
z7C_E)oL*m%-rJcqwEaRu6pQeS^Tqg=DojGISF$QYIRvM0Q~V*<Je&*$MdM<}iV(z$
zmHZ3vp^442uMo|^s={u9sCDu0cwW=+@;vqb+&DJGful3OcymWd?CrvG*~;|ubV+%r
ze;-^huK|~g!;nZTCrry+A~mHnE3Gd3yEF!0wr~RZ&2i^6!oCs`WIs`bkjA74FYW(I
zV$*?%Uq}a<H<ra#9|C&G_sf<pURo9yV8)ycI`=WiaKWXS_gL*2ON5Fb?6$0v`4Ew^
zKBHxG;s?MW;_%_8X{$fGFB;sK%lkxfMZ&cCY8ON+PM9#2IjNmv_mG0{LO&l;D0+8A
z6(9d?6`E3IItY)9Qvci?6l3Igpl55$X^Tl7S%Iv*_JB8QE<ddjY^ti2`0Uj_;<^33
zrrvPC4S*nG8!j)dyv`f?dyPjZET}RS)sRS(oCfHpAx_?Octk&-#7rIhJzlfwi+*i=
zNdmL><k#22<VW37YSR4uUjB(<zt2RHskevpUSCa!6t8HZ`x8_|$=(cO_|J&GN~@O7
zvoQ}`N~|CufPbPePtHV;b759-ulS%9pA>nYFsviL_>{z^89wNdx&~!U$#C~ed4Y?0
zEq_{Qyq~YQBwTxi6yc<#Z%4<P at B<r at Vh3-|#oT*6<t^jlPXJgrS<kqqLKCLkjMV3p
zhOkMkZkPWh*Y0_}v7r;D^jib(KHe}z42EcBm73mlwfvW}FrTOfB(4~hrQjL(K{O?#
zyO`$$b_>BobeB5y+k9r?@Ud_E>?8#Ehh_sZ&&43vu+?EP?58#7g&cRTZ)JpYK4@{!
zH#Tc#6{@XnV+^vdgl{ESvd8rPW8(U)PgiobNYwE2AxbRFGo4fNYAw#0e;qt7`Usp<
z4;IhGSX^Co%D?jH;#Ir3v94!Z-z+wC;%|M1w(7AlBjfu%mp>s0 at F_GEB9kb62CAxk
zU6l;^xjZwk^(9)P at M7Z(5Tu%n&d_Qp8(I?6V|?RjeVEWL7gp>1?zI;E6VImlh-N7Z
zPqZhzs7$UuHpf*%*z1b}JGdvTyy8|<*Zsn<`$~UaE-XVq1 at F5AaS8EemA)=i5p}g6
z{ZFU3hRa4~`I+>kWne_z at +mzD9Yel^8!?t+{iGS`7aF&8dJIF1aYUz*IaBo`+1Pi!
zGs&M3giA&#j!Sme{h=caV&azNbfHGAgaexAMHjVNq}eX124vmjj(3WCxz&i6sh{aN
zY5I#`<&X~ft8t_1WZ1(6o1hmyGiwk=Fta1+t6a*@I&dg37DK-HmVeA16D}XO*npp%
z++b4Yy$#})YAA9>LuZ2FY=BRdz$HZ=&!A+W_^#YWlBgi&A){BGC*S at wC`L(t9<pI6
zQ+zo3U1&%khxvO^r?)o1p07q3{+~_5o~npIw6!vfu~*;^tK)UcScy?|0PDkxEd5%4
z-gSNZvmlmr`LhjH*qGFt6~_Bw2<DZR^Zx#>d#`6ao^bjCKh-({(BI-}_GZ#*EgxrQ
zJhA2gQoyXoT-QBZ>IhIXyIRqlzb*rl&7_opSH1Avr7YF|F1<So8{yD7<W6Du+g{7n
zImG^plgeS>YjXe6H5^oWSO3;VsdTRG9KEKjQ3|M)_ZDAfRfe|AjAPuz<e(Kxs1Co4
z76?3W3*jp+P-~vKdDM#O0H??RMC;d!YdS3Rq<gf6W*5koduD=mR&RS;e%GJ+=IHk~
z at FZlUbm<2oqA15VfEOM7-6c|Pg913 at eoJ4!av?Y~X(gQb(Tu_fGi?w{sdHAL7WUl+
zBB=_ATUIRT1rl?~HSo^ztQ6S+)ZDw`gseg6eM3i}N0gm5MF82{3kHud(cPkh(Y0zC
zX`}%vDa%P at O$6P<TQ{LzLZ#D<IfyRZeNN<h>h31<PgtMO5&KK)@KXi5O|_1iTAB`z
z+nL&XEY{{;{q>j9n8OLK>&u^GnI at 8|y*uXW?tYwO1F|!uneIq at 8PE}KK7!wRiTWeW
z1Z8r$#1B*nSlhc|`{<Inkm+a)^*(|u&A!*l(BeG6?(Y^_Idrm%4i!XMUPc(K+2qot
z81P2D#+Fl}D(~zIky6Iz3K;~va}Au2>Z=0-V{Df%5yCeq)q{_4|E5KmlpJBj>(RI_
zz015XGF=+RV~IXV>^)yr<Y0~{)@zW9PC;2>perf2nv_za6c5;Rlcl)MBwz!^t6J!k
zZ$^27H5~#B-m(%$B9v(F!aRa7qisI7 at w~C2tvcizH}kLQEDk?^6!zeHcTK<N5~sdG
ze(GQuaSvhh at R!NhsT-tQm0Tt_p~9FvU~dQsQ at yvSz+hhV$jf3ouU&UOQ?d3ZQ~Zrz
z2`m at QW2|r9r$lzt3vXXgHhRXWw@%aUbtZ<(e+pTqSxWQHVDYVyNFT`?A?}<hs05 at J
zBeE#P!e)-Sl+q%5eN*sFeT18Mw$J(9i3iWp{htW8y^o at -0wyp89@KME at PAzK(yL$I
zWLO^D at CmI;xtn+Y6Mrt>!!Q6nl&k?_G90L*O=xtKufbEKMIb3+3&vck5s`5_(>96b
zxpjBSp%HWK&78~Z2JC at z3g5+0piRF_=hfM)OcK~W-OL-#sf((oM-{PMN#*Ek1hA#o
z%)`_U{mZfw_zp<t3CO?BWO97FYjmwAqU#WGo~XDe+{Q|EurHO&=aK^#0q;DlesFrR
zXqb=NWsl>A)I-MS5u;dKxTHd|GoOaFp>s|{mr>jsyyS;qj#iTC%LotCqolXRW+l0x
zfM){(b>fomt3S6yCyyO942&GbUHK{S6F;Q at uXomk!Cbn3VrQfF2a<o`aGE0qjCmu6
zxT-;0Zt`$lE3P@$L6kuT1eHW=L1JMR+H6)c0|LI(<kB;_VTx{f)sU3u-tXqr2=>Mo
z7sFhegRs_szogsQuSqh at mcB~`(7s%@ost1Xw1fgP|7z;r7+gOD;lX(A6}TV%oKHMg
z#YOi^$<D%W(cYqIvVe4#a|t?Q`dB!8EvTRO7~eCaedN=KQ`Cu+T^ZcSBLvkvEVDGs
zD4iU%Pk+1KHXlH%wUtchFj~6kU6$G3L}*d2WD{7 at zK65mUd46IIyuu9d8dISOnvli
zpu;GzlF~BieF4)h)#d?zt8mlveiIK+bwIB_UY_nms-|2M`-ScigE-3FMK+9i$fKMn
zG1qUQz&(xhP_pWBS$h4M?;0P!z~>n;=IN=n!kqnj!u|u7wC3M0B&=#Vl>Dh~n!p(u
zzA%S*C?kCyr^`#SMt#aH`5hkK0cmwSm at 5rS_W+2VH4kkVD9-5Z9fh5g7EfrX1f}#3
zy!Om!)JKsFC?RHw0BWEpuM>39t*2Kw-_j?+P at Z#6O}^fEe4OIkxIiL<8f3iurMbCh
z1)}xr-%azZ=`#=2yq~I*RdnODgqkqp-`M+<z4=&X{EfcqCBN-&#3g;#`w7?ueX%II
zqZ{4%MH-wN*O)Acw#v7#xvahMzlFM at Q$mx!EeICNR;Cq^CfkoiVpEX at 7ohl1*XP}V
zp8o<)NhRzPTcar<5$W?Z3ML&HyCRK49j5jF4UyJAjMPhO`jgBHRsVSoI7 at 0Hiu^LZ
za)3;*4iPl~T(dA=h_eD#-jw)ami_<>DwA>W{F3m&Rug3X+87xvAYtA>B>pRb&=(zy
zdTgCvD|H|W-7i20 at IF5r?z*lIWf!@n&FchjONG5SfZOUt4Y1cb<TKD2okUvw`c~P6
z+oHyReH%8G%3}&VxK^`D{6e&5We`}^j(@sHuzf9ZP>95P_h1?SN8hL2P*f_R at FVBm
zxlpebg8JgHy06 at 4B_VcEMLEZarCdd4QmjLB!{93m0s6h5R7TXBQQVYz10FiA%Scyw
zIpxxkC|`N=wM(c9#6HpPFIkxMLlthcc_bf^c4?ascv!{+twnU%B=)Y<I_a?R99$HI
z{B$=`z}J_A)WL#O5W7sjFXuwz<L+)gS!D%flULF9`sRqfY}z4RAm`o5HpT9+!pHH{
zjrB44nU%3ohSdJqnr!oS1jB4womHMapOI=z9QvWpxJF=-?4d!qJMR#!Lyf=Ju43^?
zfk-nNOf)WQ?e=7!()3@^l%>_PpkzLxvO74?*9ub&wTbUv8D!wgp;DsZgvXycSBDD_
zhPJwiLUg+mNi0PV-pVA<Wna6Ra=dn>50GrbF#u?xUpXlis2aKaJKhcOEWk$x@~^dG
zc0FyJ%r}5V3(V#Yf(~!KcSLbafJgpqmn}%!Z`r-dJ2-Qma^nnKD5s+up7r7JH)q>k
zHP=4FqX-wpv;rj0Y^PqR<dz!!vCL^O5n^V!>;BL^!>LFWgg<^Z at RY+%jtxm>8C>37
z*$N4ErFyRpNhss~O&26I=<^I*)4DzSygkU_*zu}|9Y at T9hd^L<aa6kHAre`ipD?g2
z*^l(klmjYD7Coz$3t&;3L3=&VRdycwyqgjs at o@KLtt0Yj*mCFl>j4qVUx-WsewmDa
zaPlNRUk3ca%U3QH0WL<{!8rXR0a4#(*Keu4S(l%oo at _-+4h5xo>5TG@#252YXT(S6
zRruV9p((d>NgQtX1^w+aJQQfH?sHBw^a~^9r2I}}cZDslhpI{!IV*#Ojw?TNw**rR
z!O<oOb6 at tB4OKtBiqSTaHu5$Kf8 at x0&(S5*Ap#kq3+rFb$;!;V-`{y9L}=<N)JpGO
z;b3{%qzAlQls^0uMC+ruazaGmidToz$W|<O0OE5PDxLpg;a1n}DVr8wHzfdK<(-}|
z>Vxjf;C{7d{svmK)axRJ at daLbu0{HE!B08Io~wLh41M at 4uWW!M$SWzJ!MaU?y}D?7
z-(x6S*tJFQlYN!emoP6b;k#;@Cc(>Z%Clk(rdEA6Jsw%A_WyeBLt+WqO>OI*RM}>a
zdW!H#EQ;QLStR$gUukI3ZSw=1CFrLrqK}<#*3fWK1t#1wzt-iw{Jf+(q(E<qvl*8s
zy>Hw<sV>++qGeH7Oe1+m);)E3zg;Pxop!6?r*k>g%;En4F&X{kM#^Cy%e`wD2^wP}
zs5eXR*^Ja2h_Xnb62fVV7rf~gpXp6LcEu&F?0U^>J_w&%Rd0KmGyh`X4Mf%Q`qPac
z+~vtJ?IYWirY}1ZT3(X;02T`qnN`b6PDLZ0J}lEx?+cRsio<67X0>nK$r5-PxXU-B
zw*7&f#F+eCuEKQ0Vse)MqVFg?a#E8vFx_Xhn6!0)WT(lPY%sG$S;Bcv-IHZJ3Hh at 0
zO5OSKeuGKpnE#o7SVDljO1;e(_BsMU5&&eY?<-n7`mQw{^@IGgv?kcoBZZ^3Njg_j
zT>|R+96z)_y=?9hDmuDASahr}PS!aX at ap#YlCSVZ at FAd|ea%4!SnkEcA(5-kFVmZt
zxv- at h%##wPOY|=<PBVx4$(r$r3zW9 at co)g%^*JZo!;GTGs~}g|MCUcE{48qjwql?3
z#O5D$So!;kXf>QCa;89tOu%u$*$L-J_^+d`il6q|y}GXo?!A at SKv;<kI*|?cM^#VW
z!fkvI8bY;DOx(Tc$E!Q$Big4Kd!81G!NC7EdN|K)l{*58aD4O~`gVWa;+=sj6Muhf
zEnU1?=J~_>+n&SirS0ljwf at GhUz?p8S32T4o>IG?4NBfw>W=#vcd|aWEB?pZv)JOy
zX)+QOxhyQB)<(zT=h7)_d-NJr(u9{vR%QRnY*`Z^#gqDA`C{u;*TueN;8QET9lFAp
zGOe?TuO(LLSU~b^bgmP1OZ0tt*4>wrsZG~=jFk&uGWX`?zTJ+;ti6b{y7v?X+jNPu
zS!4#66*hl1*>YqCxkk8O+#H6;X4k=9{pd*_#LHk1ulW<-jDHGWY(#x}#JJ(c$cf^V
z23OWrV$*aCYnbSFwl_Jx8|byg-E`R&ZwYbq at A>n(ogS?66QNr8^hxPt?Qn?4Gndpm
z<p%nRbpCLjD#dWgK^)d0_gaB?6FV`1`Rf_QzKl-P1O at P1!58t__^~PuZUF(&pJu9j
zTOsvkD2^YC2}AtAb5r~8kkcq#+1O&3d3H8yA3o)6J*zS7X5o~Mp3PZX)mQ96GWm)|
z5Eq-aWG`kjIHZ=(M)!!q?Ls-{_KA5!=l1j{+Q;uU+w+rU!~GABub{p(yM|Ax;y7SE
znqX7m$^+}^tESsx_h5pPayMI4<NG;Bl0vHAp-PzDVtwmgegE at Uw*KGZbDGc7KSr_i
z8B=E?C|H$`%C^mg;)Orb`){8S*|XjWTt96J&f^wWVSdpg-2ZVw4Sfed`n>qD at Shd)
zMv;fvn at x`5M&BPdeN^EON1ym|se}I-H%%F7(ZVx4=u=cF`%f+eypF|;$EV&#T{BVZ
zvsP`oDvpScah1a~0-r84ICXA)x$d2q{h0UdV=qsUK1&@Qy*xLwJAkXj%4T=V2CPLd
z((Pr!j`_WBMo}rB?$t+`jJx~HydUDr?6qufabt1u>A0-4YLo0JzWdI+&ims|N39CX
z#8BBVL|MY+ZDF*Du|f+Ip{S?a*BFoL`3&}M?Baw`?&B;&+R>>Oj5=ft-}|2O6n8nL
zEQ+#;8lW}0!mKll&K$ORYB~<3no>?sTY#1>#XbY&f9jj&YLWTh6}!K-K{xaN#OvtY
zNjsKh*OxwTUDuoBHA#yf(d)<>c)~8nGV-j at 2VKYeJzG*UgLMugE17p5Y~N3jMiqV)
zUf44?WnWo{zOu$ZW<L);Q7ZO+E{B2Y>w$N0mr%+V{ahl4r{%lMem?FxaeHxx>w@*9
z-UR<=m=9vzVx+qnSYBgA>oWCykU+!E)45#Aue(=<#b9<W>qTJ=q;EgCXIqAUr7NBf
zcKg`4yHrZuJxaeiYFpMo3-4ajWO~WaiQ#EKN|Tk57`GPSuEZkVvDb>E-A=g733(mf
zcUONz(^MlUSJHg8jjDmUmb#V2l|M9*$>0mCZ1e%j%ewn;*_dBVVN2vNK9WoCY;@TU
z<jL3j%%5Ba&!3MH6~I^BJ8ztAhWS!0a%Be^K@@g&HZ(@D at o@2^>kVGx6O$J`v?T`v
z?K8IM-O79i3C2n$pYk=w8r?bte_=im5P=xJ1dyhzhC^5EDpu+BaF}y<TTWZ54gRmr
zxutiv#;WKZ$W|K7OP&ZZaRd*jnmR#SbSIgH3O?@`uz{eIjaq`w<AAS&*`u3Pp6U*#
z_b!DJmk`!Jg#UAF!AZKyzV?^I>mhR)iPfk6l_*9YagO`cM4LU%K%`Si(|ATjKEpBL
zcGYYTJ0f5K52h>-;D7`NCTwECS at uu8hj(^;+A4D6DnOdMjHgyXYvFk>m)l6RzqO|o
zp;s&%ySAdVENj&M?4A*<=+{{2&vMf|B~t%c$u}|H0ivw5-d=r2ND|HMH1S(-t6jXl
z`N at 4x12*`MXiy<*{?FUbnKIlqF|hA;leo(36$xj_{-mAwHbX^^o!K>BM(bR*gd9?W
zl<jx$Vv<<(P8Yfy;fXZ3rhj+w_XIx}vyw3B at U>3(INNFH3HvR7BPT^hD>*?iJrOBE
zanj8xGI*6+zG(EBqqW9Bh9)C>P~V+quDRF+9%Z~w+`2sQOX+7=<#)owg;0$WuLl#g
z<kkZAT%-->X<W#9>Q at Z0CzAEIy)3YplgFbHcNt9NqG$h3j at c81rOzC|CnBLf`N<b=
z+V-or!Ea)<+?51w*@D=NE+UiiKB7kTm3m`$;N}(AXplRk?G9Z=gZTrc7oauvj_R$t
zL~hq);$#y9BS!k?M7aK<foWX<Xk24$&pT{E<TKM}Gx%g=OfVN<vH3gx_S$Tl6MYyN
z-&p3c-aA7bf@%y%<>Ci9?F!5}N#+x%D)djr^%5U!%J0b!-87tOn7QLT?&5asmod6e
z4)9qvPcAI6UdE)Pxl-Cl8rb70uA^#6kH7yC^Iv7THeW>#CT*X`xlH=mV4QT&p`}p&
z(>dyjc+`#GcA}}WT<lrHfTrf=Mgw}Y4vw>@Q@;rl!nJ{S;nA~@7moX|wqF`s{itFi
zTE))VX<u7njIkp9w-z=+gw&{Gqb>PAUh#_J_BdXpbPn(2-d=3%o9!A&y#+R&y+?pI
z;$EmhVkdjS9`Xo0trpOHY3<aYWtGFHu~Fcw$4KCebvlvP1DWtXBNeskP>7*^W~T2G
zm#O@|w)N4OB~>f|MIALtKH|Mo^le=WPjz9%rz2bch-6;|$>tSlQ-_fEYU`g={>?GW
zGq8tga3R9KwOF(V08g8|WtzT^E%Dm0Lennp at rXU>7u#Et-76BM??x~o<>@)2rP(mY
z5B;z?`?B*qg_wVwMaQHCw*XwwBCM-6IYEL;KO=77$ItB#j|IL4=bs?&VeX5#_;UY;
zs~LsKa`d5$%DL8W_gm`Z!1o${2sheXa<{1smK<_-_!}i`Y`35ZZvXI2L^pj6`Gti;
zHtEOu`37xq!`er0M4I2WR^&B{D1utCw*R)GIpxGi1IrkJxb(L7_`a|~#ZpW~u#zAl
zMSt|3PH#P};?*V0_C6h--nEk#6aTp!YWIjxbEQ+iy1)y!d<%d7`Lt9XT{aw8SY}vl
zLX=F&dsT(nuI%GO5r52uYJ*2pFs#Vu*4WIB$+j?Yx at bzbK!nzsiW(jC8VkT=&xqDo
zL{NPe@!DLeqx^M7FpC;@crT#@Bcn-wpi7bZKzjl_*uchHKB=uzEMERvnHrYYo57gE
zzxW|B-y(i`<DpJ>K;Ed}$n|e)5$SXuDu`Qh!&mDj4A?DenW{gwa}&=XN}tO`#J7au
zqCgv%zp?f#b4P8z at Iq=eLRD-0bkVyt2BM^EESK72`KWPF5BI%xME1ZH$9*X*qu24B
z7twvA&ELH?Mc>_^Ve$S)Wk=5V^-34-kv~2#uE5u(HZhIq<8iPAA>^g^Bz*r{DG+Ec
zS_hf|W6;Y1PNf(ljgiU#vP*k?Ei%oHj>&NBFsZx%6z?TNM|}sSD@%Zn&iy_fhKla^
z{jD|I)Q+?6e`gKeL7VsX7QI99Xep&h-bEdg6=#HZ-cE9IS#n^FSmjllrR!|4s+9$C
zYUP`RcQaBa=1h#3zq{&Faf>qQbe$v5M$#=<;PHzO2#3AKr`B|OrtQQnR2Gx)C7RPJ
zpLA^pwDvqO(e{?<TE9=Ewbq(e%YGe8m}xO^X1lp$9Y1gdjSYP!T%P$lIF{I7(X-E_
zzlWD;%fV<9sukBHi1>NChDQb<m;{4mE at aLQuAmCCu^1JYLh|MNNY7-5Vt|381{L0k
z- at LfnrDrdPL9^1or;V)ZMCs~WASbUYUEO*~$7I4N>?5*0Wq{vo^MNOb8^LBYeYxED
z9mM3Jp;@X`^ufAaTV+-wg5oVySB-wDD}eXC<A(300(+E>%RH0sj%yb!whZHDMyf}i
z`G_`0ppAXTz_S6Shui%_f^az}su2wK511z&1a&vT-)|Icmg%}3 at Bfc|^s+#zkePRZ
zpC?-Z5>LTF0b1{fHWVdPo~@k0ErlULuFLsD99X-yJM76|g)FY;`$X&ecUNyd?#6qw
z?E_EEC#1U0plY$(0?jHeI(AwG#++d(&b7$^KyZmbIC|!t%T;P2a}H|QROwZ@*SC(q
zh#gLuuWYo``_6Vb=xynNWBD`(vj-^}-xJZpsvfZBE&-h}!8K_OU*6t<ndMZVFK+*$
zJ;Mr=$EY({W~iIf)|d;#AwDt6ZYC~1K3fPZ6`X+?7%^}vDYe_Xi(UPP1B%LReq4&V
z at U)}apRb)2I~&AXt;Bg|UhkSF3dSsy1OCCx$QPdS8V9!@JOSLVz2d+ZeA)I*7sB3M
znyJ%UgD3IUXbQ7Uzp8QUgKye?meKrL9I0E^d{T*Ammipf;AqU`8%EG1x=KL&lcH<J
z>%L$a(KhikA)r7 at a!~8fPkRf`Rb)Ja4c&-b0(@(kRdj3MWQGO%5yktdaB2Cx)xrmz
z- at NiS@;vW8jebmgfgZ1Fv<dp4_Y_>>oyZ@{{Kg|FG3+vgXf{bvw$NMLbCcXyV%*?F
zzrbi8RhQD!)s5`BdgmT@)^;U{h?ht1=}(aKuE_ at Z-?MveqJ6wyQL84lq<c?LRYb?z
zB+afU3B(7W9En^r99P<2yhrMAG_s$J1I}DRzBE8WX2R2v%9s{5N-vC|kGF9-xtNAR
zWDA(RaH~j%(YJ~sG at Buw@#VwbmYtU7e;ZRz8z1zeQmjO7%_I;#R?C>=60o(W347bT
z8R@$i5f}W#^Gn}9rW#A?-Ko%l*LH`w#%?qvrVtsv(r(EL8f}T5y^=<re``HD_{{NW
z&hdS%XkEkm11SsO-~I0=!Ud+uoojcQ3lL=9M8n+a2(samk9lg>k+MkRW+tFW?Ab^V
zHO$<fO>%%^jsrqBq384s(tFcyAfiVw9z%+PY&{yT>zUiTgHXewkX9vzCB2~53!U~r
zI%d at cCI<2Qz1D-b!lok}M7CnJCm)n5d;i=+kTUYJ9!3p*N}%}o`f%@`CXQae!K-vd
zqZTCHZo>oR9h`48AP^HIrmw*HC%i9Oz3?^kLoPNIPY!6^PpE=bDP>lb7WXP=1oZ at K
z!VndF86_~Xo{w!7>4*X(5ilDU+Z$(%_=MUdvp|CR-#5~e=-%~lS^`k)P-#8`qC0n{
zyd8 at T73|*g=wan-k&K5RnW3GY?yX?Hi?IR51mr+}1_lU=bXFjxK46pIg05N@^=}FJ
zNwxfab3=q|tg6ZbSXfIM4)Jz-cbH?_^riXjr<DE|v}(_0aY-wLi1Al at _7Xq?Z}cGR
ziN|8Z1NV at zW5jx^-TE)O&y+ts$yB#R;DVl;nGv+MSY&Op)nj{NSCih7<s!$Hpz!fZ
z!C at a8AGe{V&`<U?C4|TS0 at WNU<AxS<sWUMIpwcu_G|updp2UBAK!g=Q(dj2ixer=#
zU$n82f}wI1NkCJ~^@1PVYsgcXdaj7+tu99Z%gsvnn8`xD$I*Xd?12cx<tPColWfOe
z`P at 4jPnU2lKA|vLjTb;b>}P!nprol#DhO&k)PQkN3&8|D0T0S?z1t=zJqvlSCE>ss
z#fnlX)l at _&-{@ZgX|3E{E}PSMXlm9stxBdH8y$5<+ at 2QXWCK13e}E*)CGx3A6$J$J
z#M<43JS^(wfx^bLX*hGIz;J#2dP`~of%f5w;R8;vZ2^Iu))rXno2Wa~oe&&F=&s5)
zG6^B#kP_CGqFV@~C=VFYgGF0v83+9|ybxbF$R|dUZ%qVjV;ROl6okVADjOa{7^ufV
zobH(NC8kC()Q!S4R%9b4IhZlv>(dElF@;bnMT|&ho at k~TnDpe5Esi$YRVGb4W{iPO
zWx1ID&_Hm~jR-WDk?%PZSmJ61_B-K at H>MTTXEIolB*}t==(;*2G^s>e8&P&{apAz|
zj-@)CLdxoi+K}PGi=0409+DP73{1op%Lp`a3{sjS43v!#oi~`>3~wC}`f7=cDb|o_
zBLN7xas`BdSOgBp4y~)Iez?V8NyLJtP}@zR3Mqv!^r{{*MEM*^*&*u46G at v&Fn5+d
zbYX3sz2X!3Qq~IXpznhv_-d at 58osmo!}9|ObK-~$XW;^Y$M}K4*yvx8dj?5!5Jr^v
zN at MqjuKfeL#7RMpTaqT4CXo8VVPhf02nl5%1l$o05|E*z0>b7~AT0_6Er?hiBS_`i
z5Mh8onH2GC0+KHT5y=3jlMxCdNkGL-G*HDrNf1#aLHN=6 at j^kiK?>_29lgT#L{Ft4
z0vSS5D<KGq85skTWFke*OuQqfctIk3PUFs7(XxOWsIm%@2@(v8RT9jELMbT-P{2xt
zO^zTI67u9MES*261I8Ydr2r3D!XV-dA+l=HkdIgVEG-Bu4{n1Zg`t`kKoM>^Pcm;w
zM_Q+clxRK<51jc>b%|mhOB9Hxr-FRJ+*81iMZWx>>GrO}+(RfJXFF9BxYG!M5xRk4
zLYI+Hg$RsOxP~r at fJR})Y3Xq*uv1ZX=b-Sw^B7i^hjo$R1r(7`LsAmJyaqBAsLAXd
zpqq`mAg=^95JHO>+ino<K_merg(~(_r=eAYu^l2yEM!2DIwDx%>dZe6Pil8fja3!c
zEJMh)K!>|<hpvYN69^qY8gyi@*Se6`cxF$=!}}kXcz-A+C^_N?9-*P3m$L6Vsi-+@
z5eAZ7e8rgHm`pM9MVbruEu2z-pb;W4nDy>jS%mx*HdkdEs&EPY|6livL^<`Znus(X
zztMv~g-}o*opUozf{6fu0t%2q#DO3jH;9qJ^dOl6l7Ru?4}NHWa7TgwFo-Ah{X!QB
z2$DuGj^Dw!oaPgfyx7i!SOc<<%!E{f2ZwpZ1v~v=5S-XIXP^ovY)^4uPT)I;EQC{V
zJG-6&2T~t;f_D1<bOX1_0?-$?81O?Gu2GF6Y5A{8p6}%ijYMAte<9M7gz}XTqo5O?
z>*DuA<Adr8Ts!@6qS4s!fre-+sZP=Xh#n2nZA;er`K5-Ul8}ZXD26G1v$=rel$?wg
zvMc^EZ(*(krLUBfrqcl`sdQL=Str!*C13+YMmohQAhbGxJl3CI^Ed|5NIvkRVh{CO
zR7LKRNXO~*i|YYrqIIJ+ at en$i1K2w&2#W}?WC+5Y#wUp>@{&9uh?bBkV5*`b5QKq$
zy8XlC7(m2CJ^vy^iy%F_uk91C#NNLOxEs8Ov@)O!daNv81Y?R2{$AEo%z{6+s`f$H
z+w=8?VqBn-Kw*P&3P2epW(*^BrD+7lSOr9yIAdI~qjh0|x8PHPZU!#c(SH at At)&79
z>#Q8=D5K#U_WmL44q$0h&I{Mu2GED;;kJWKIw-A<6$hp6DhI?h1<^!Kw;*aKOc0SL
z2A%+~>Pa}r6v0yx6sN>UXbm`Al$qRLv+%jl%XqhAnSlJ%k<=+f`;AfbT~C8hL5A!?
zp-TW26y+9 at +#zz`ZeipLaW)*l$ue{Oz<xsi&0>(CU#|hK{0MjSsq=w-<cK5c5b_NZ
zwh5jf=&7j12eZd-fIUAAnPeHKFv{dCWg5dxI5rG~`C1{?A|ESaMv3w-Bx{s^W~qmo
z969Y)K8M<|eMp^KxB7$8+pwJ0_Zi`Un85~EgvVI=_!x<U9+#8qbiryro at qSbUBeEI
zR5dV^1E0KS2g8r75X6`aA_fDb(s^;$NMOSO2*D*m2W_7!0sz4ZVL4<#q69=U&>4Wa
zS;EobecE<IF-#a at GYXGSKK|Q)y-5jremp-ugVd8oNF#1YeKz7N at rDCHq6|uv6C}zI
zlvBUOkvI at XLIe+P*@%l6z<-gKB$3=ssE^c^=w at 4Sn?$faR8YfSYJNwgJ#s*VAreVC
zz5E`V4drwvDT_YM3W<7DqwWOakPMfok0>i5$eBna3wocW>`wX)1=fUO%2aU(69au|
zwT6JAiYvPM9D at Xbbo5nCRLO9uW6?wGv*LUy_<k#I(&j<^kqTdkrw22q4R at 7!L6Vwp
zf7or}I0%iy$AY1&4oF00A&G?{N=BIInw1IrkqQhY#ur!zQLkg+0P;HLf_gyFEsqKE
zwc at rb&zsc{u*vnP73W{gHv=b0(9_sLop2$Z0(~nd!3ZPVV2LP;`Z=|zu+E1ibAQ$8
zvV;$vC(+Ys3Flj}D=rfrz-Op5>aPC<_k5(W1p+?NK1{sd3C(thO^rqtZbxF*fmMr*
z%b{|Do){D0J_=?dW6et=0)U3~M1)L2pzry-kOJxFLP*p`h6ICMqt;pG9s!_;Re0#l
za(?^;rGc0Xgds8E*32_B%|+`~u~rAg^1P=oSC||O4E3F+j~zZG_{lh%8}ou-Ar=sX
z$ZEnw9^0hKF$czMy}aTdGjJ$^TB at jVgZiN1JvYnf`^W=CV*xkB2S~^XgD}*d`HpBG
zj9Cd3gmnN;L8f%2O+d{6(GO4s!k=h-dJ1Vp0ZjrzkYp at lA*D{|N76^uPmAkWNeAi=
zc+EbjD3}1CG&n0|z+oj*0o#ZKSIPzF{9f)4u<i$$@{t~Xoguc0CZQ at RqJl5K8vS5C
zlq25sbfiywnqr_M;>Uv$3f2lLj8J%eX2EFAd`Rmt`-)X}tuy^{8o6s+k2$tfn at o%p
zh8{xEE%h~(v(%lGB_e`-bA^bOrm7eSHK=Fj*dksKV4@(zW+HiFh at v8bB8G;!VrnLk
zDJcpl7*ZG at E(u_$DY-f*sU;*Wl`@b-)Il(kB2CUV4LIg!B0*y5r!=t$k~LKt8)Hf(
z!m{-5A3Zxm4A&`MxE0{jghE~DBrw=i6o%Y5>7%pRM51Z)Mn@$wL5C9nnDFi at q?76R
zjGX9pi=HWxHw74IG at I#F0LHrGU5yO2=!itwIb)sI$$Z5w;<S|mbxl;Tvx4Uq8=z$q
zK`azQQy_#PMSvh=9F?(vcQ+ldB3HmdJ^>0?{<q|fEsR7L&VAjwCgPR^Mht-fghWZj
zX+NRo9c=WF4n{N5WmG`^+ca2X8;7Vdh;0N29aEVGfSsQvngRhL90p)V{YS^ygn{-5
z257oKkyP?ja at 6YVbE#azbSJg&@*#wVf{2nr7=julN)?E3NSaYTpq{JGvBl>zt1Rw?
zO)wi08I2Pf8>8N1%m&(4Mk-jpRE8%t1*F3n28^O at R^yal(kmTLk{KRWh?b3Ei5z94
zNKjn5?u;OEh$V=F`<fx-DAVwhn2Y5E0H5lE32XEa9xKF=XbR=a9H7g=c~Zm44<QJO
z8~BhfK7+9AEd0qP3xgzdaK0TKETQ_ at s%kPD=OR$iqCyo7m+}?^>#%q+?N8PNucf at Y
zFW-Ye&GR2PPdG865l9fB_Y^iV82TYq>k2!Phspi)r$z1M{I?`J<m$2&vhl?5;~;1v
z0QV=*Lf#!e?=KGI!y&@HfpGoR$|Xcgy&;AEsEy#eP+ISG0)-+{ttO8*p1~)~V+V*m
z&ovC(jG1TH^a=9{OAppHvGH*WgdBtZu at I$yG5!jh!$zIc;<AMZC5DKpJ~;`JuHqw<
zKsg{LfJ6CzYCu3efwAM at G2)<oUQCbjNf1&CF$57M6a at hh5>ZJLK?EZBg88TVM1mMo
zw5(;12c;=rQ7M%J`Ufb6B^RU*H4q|hAwUHK?z=dg0Q7+>AkakmI3fnn44>X;7HTVm
ziyW{+O-}x;L;#X3QilA?H-Rof5LNDonJfsy07DAH{c(gelnQk!on20qA%z&JsfL<j
z36f$;B8Y~O8KzClh;~#kbOaD1GEyxp*BlN8hJpwp^ZZ_e_n`$Io{bOnv9J;#lkGvK
zsO%hzQ~|J(Z^$eUF+m-CFu<oHg+F1y7*E<zQwZUNlu`T38jcw-QAUs*McGjA0OO)@
z(Kpm24~?fDA*B(K=-$T%yDCy#sHPq-=w6&x50(A_`a|fWJpHIN3^7Dvl{G{`1Y=`E
zM=qwJqw!=jT0b2p8F!QC8!_KFIkSfQ_fiAD54mC`*hqmA$%BMC2If1XBS2wg`n7am
z>mwgd-u;Fq9_nqNiipF47~7vD#LBmbCL_{Y^Kf at 9`ZberuKp^$ytxgWm`@oLY<8H0
z+(g6Bv(;-Z&ww&01TUZ>z!fDzz+|2caqzcDkEt0j8rb74>UGO=+G^nLY{evyCS*0^
z1~WuEb}FzL<a5*uB;K9Jatt)Yqiy)?vNmtWu(X!!&gF}L3n{IW6g8B at F?LNNeNN|`
z(R{YFqqaQ+LEts%qYAWdw_u{A2uF)gD}rCXb42(|&~4~8kndyOgD-8x=@vUK%e-lr
zQ!%C9oE6BEQsQVv_>Qve&6>>RVGPVDrC5_CF{Y|(uN?MGIZ?~0Zig%&;7xmN&CtNZ
zt^5=0SUnId^E`1Qw at 9?|CE6VenLB3Y>Ew6*Bu at 7Bz6t!Jz4tudle-c7_(<?|qt9)T
z=s5qIDI}<qqK9Va)DS)fa7$rTpjF<Y<aR**clJ=``onC)w{4p{`|yos13kH0*Ls}X
zQKnfii7s9%P`da%<5d>j4sIqCbVGeQ6btDUHq(7I?XGB(D~hF|zcyD<FI6h};hHl*
zdf|-tm9{!O5;C!aOanRi!=ET~^%~00Zqc@)h&#EfE2c%6O=c6ycz&Y3C1TqGbQQZV
z1met&Z at B%aE0-k`b4k_ehpMTQ(6~{sUD!<0fY%Q#h*;3cM3m4RdMA6Oog=YfYET-9
z&NP at t>p~gDL!vyF>>qEx+;iXeFYySFC18W{kU08&khmNP1%e!>Yrrqua2Py9JO+L0
z9oP~Gf>=sF3~B&~WQ1UWh!Oz_5&(vlB$yzey_rNXOe6rn7%H#`5Fj9tH_Yk|wfB49
z)N%C$*+nO<@euDj*EWsFt{AK!qiY0s4KJ%eQfBtthV}uA2B?S!qC64__h2-Teg+fI
z_`s6^^auK4xcDIV`tg2-NOc^^sX7KTxzFqdVxo#+%4KP`p@@Cnd`w+6*3UqG{GW3I
zXMrgTV!9C`5DN%MxIWwMJi?aDRPhAJ9u8ONaO`3;A0vR<hH%vJI(VV(m^2R19_bIR
z5dR}1;5>La!0{bc;-N)#od_E`om7fR6*A1p;9T=3iWbl@%LQ2+`OcS?40-V75_4dz
z1^ze+3Bdv2Fh)Q~Kn`798C~3hdp<dh(+-sV!-;a#Pd+(dxnl*rDZ~A>P|r%yIcNwu
zLz at n61Asy4*#A~iGDs42suR>e=^Y?xA9N=OyhL(_B%qlYfLRGbk%XdO@>Gt#5)p=}
z`Ua$J<Vs2e4GjnY at DT@>d8oXU<@cdu*m%Q4IL%DI4=@A)fcs8GgFvu8Vb71;Muv*v
znvqXRZzD7z at FAmJJO~)!TM1U9ut5E_m6v6F7NL#B6ODoeM0L0xW_m4iI5_U(jOrBR
z>xpTwNIXb88*dIU8zH(lF!YWgCW0ByIT`5Dtb_>&5H^an1RC3I*aa0da3!J+kZkv)
zDrCDyzpXM3$|fCARg7w<x!@izA`j$?vVhZVw!;yGIaLarElHrnx_~B`WWi8|Ot>tF
zolc*?s6dCE77~-NW-P%rj2!n<YLTRTj$@@!Eil)iZ{0Rs1w}olp#o8L_K^Xb9hKcO
zXUHZTj2aT*odHNh2Q{z<3FNp=VA$bMSuney!KL9VhJwT~17IAJj@~<OxL1Rh_eQlK
zm{#@)dRr15FQ6R7AbnVnX&12?1)wQlh0r<>n286u*Dq0?#D@>w+_7Ap&)5KL0v$$3
zgo2U~Vwku*3B9c&V?WrNKffplPC6C?QJ0Fyiy)&Xz={|ngQP<}FCC at s5(^SHO%;2%
zXNuz-+lp!s$2R11IMJ=coMMr=v9OmgJm$vLq>GWFGl>tUW~Sm`(O}FGYC~n1i#XAk
zHZh(Uqa9>)^aU-57{)1-t1uKnAqOHv7Wn(Ok+gvk4dJJzi^rA`KgTCZg|LeZ_xa&X
zkTO9y+I3lq)}_*fUzs^TgCY^21nnR~2b{aOTQ$&(92G{Kh2|C>0w1Fycn@@<U(?Sa
zsfd^+sJ!wXK?2MZ-$8qM=@oPWD5^fss}`W1PiiZ|N)w18taTYw6U#A$a14T>#D!Bq
zMO7<8y!)yM-Xo^@91O=0Xke`H`ElGR<j~B)D8asBl4i~M7R=?H_SACSC|uRsK#wBH
zWeL+D6C at kJ?K=sA*%XkH9*8DNOatPLNXAd2d<Ma&)7v*e!$J+aMj&XeI_Naa<tSq>
z)|Ev#;0*$!kj>7Wore at C(m5jd?r?}Ab0cL*BtyOgECQI}hfOOclK at b<43S4(M=5Bg
z)X_XOlGlK1(P|_xqO8H9r|`xIg8_DFHWzwvZJNX|cR at DB+|bT5(%W!q8K#VI%@8z%
zvtc(iJaEE*;NEOF)WTbXr3hNY3EG!+v at Q&wJujpPMeewa1o*mFh8Gc=<8tlMyvvh^
zVp1ABLwD at wVJ=u=P0LjfrJTha at f}m-qa9>!MWcotfn at 6t*26HOnE!5kKu*R>fzK6C
zX7b>Rc#Zag4c_VDbi!mPTX`h|%R|Jaf>1KUT75GPJ4?v$V-;XbxSqA+0~j<j8f{93
zdMc5^YmwLR at I!#mnYL1ljEiAHGW7&JD?7E1qb*@3ILpkHE@|C{O$|nN?(<sCF4J6@
zLcD97%9G`#63TNzu%yC*q0uZIA>kBJZL1+uHe+oD@`=<KgDmG-itX<8B<dEJm@$k&
z7Vk$nG%iMEbb$c4Xf9Df6U0#thcs-q$m<zl&2ETPh0?f$U`&w+2Tbng5{L&(o at p(U
zf|F2<kuh7uOAb^9a4Z}u6q+dt0Zar%%NGEMV?c#TprVNy5U54R6%-k=aj?LHv!st&
z8yZ-c$xFDzjR{mpYReNKEFg$FlgzQ$G8{ZB>#F+QkaT(>s!;&{7^xUCDJJ%H`?7w!
z-alH+MIDZ`4#-3g4&teCd5|a+U0z14<Q3e8!ky7ogeUcg6cKkBxCr*BT!Ye6=a&)1
zgEANnw>Eh$23&_S7F^_*#vDeFq{IVN5X};xdf&;<jJtMzYtOD6dCNrX5tk?C0AVB$
z%$cTztCcbr)Ks9ma?yB`3*poSGXVJS_<hee%a&je+Kreb2nZWNs2h(zt?w~SM#g;t
z$3Zbj#E_X#l at u^@b~jVz;1tO&P0|$xLP%$+;TSL^O}o&6T{n4lqUxN4fMv;sY>K?|
z`$P1y1W6+(8<;Gh>xyJURZw~$fc^Q|&`cbzl87ia9MGx)Hrm3FP#zTfMh&}jzHCKb
z(aDH1bG-7WD2_}q=pnMv7=YGX7-q%EYz-7%mL4`ihV2ywHZq||fP!L-AfzV+qK3So
z-eOKzijOQOVd&@}p^2pCtc`Hdz`Vz>4~f_iktHY253xY-ieM0F1UCnVk={dd;2V{c
z2fP9ytf3&G|NI1_%nvfae at 67RC4j;nPK&`wy1-q27bNXNFk>Fr0AV3x0b-f)XMk<&
z8I(JU=%MDfz!|C^)IbEXZjpllRHz}iWOIL34k3;Q`A>0EG(ebC5zw%NK-u%Yoir~w
zs_Hm$4R)f$F2KxUWgPKTV6|3PjL4MvZMo(Yb6e&CqH95_f_y`3FfjN)Kg}~bFoDxB
z at aQClB3_SbbeM214IBYN1UEimLin*BG`x99<Y4bH53|pKY^0H(bBY#-(-3)NGa2U{
zctdRI0i7rh)4e|JIK6Y4!KjgEl4+hP<F%e1pUQyffYBsGy(L4@;a98~hMQpwE%H?#
z%Y`2Xn1jXIa1!?*RU~A(*g%m+Ocv8o$PghqLIWWA2hG+n%qC0~bKp>229xL%tF|y-
zyDliX8E;;_set0YDgpl(2lD_Q>>$D_Jck29y%NWR_I5iXl++J2zMm3YI1A)XE5U34
zQVpphf0zqXRE|LdWEnWXzP5CNv>)&La1BSp0W4BLACA<CUo?I&`bF>vJNaSx-b((w
z;yb`-b*#f7CSuzjQ{VyMD!cZ-0B?lD`;Dug4sr0g!8B$}eO|TSA}<+WfTc=8LLf*x
zDj9>SA at D5#CXNUe*mOy$!5?-}=Q8}t3Hd&u;0hZ*(lJGNpFiO4F$X;MPrm_^X8w-d
zS5BUXW at 4zHaC^Wnmiedj^jq}%_sa)<-OjS32yX-T9Q(@=*nMK3NAUcNz;#Iwh+gH`
zB3cb;*b^HHW)O-BmO_b1Wg`2OBXLibUHb??Z_GS?eF`YZ43Fm&boC&xAU<7Uh>|FW
z+#Q1b#mr=ch)5`ki3w-|V4$LvLXv=(1 at -|U|FH2hL=cG(eqoh7F#9|p`djKDkpr?q
z at u;ua2x_Y^{vZ%Af#A92<~|Xv1j=3!&knZ+hi!zQ)21h2t+AX)8depO1B!n)Tmj^U
zk#-CyhjdTeB|X9N_c#)X3RC-C0N}^USfHd62`2=@`vb2x%N3I`$2tx9!zsehF9AG<
z%KJibd{G7;bh1bK<+IO14<I^&paXvO(Fq91q!9%GL^7W;y)AqLuN2 at Xr+t7RNSi>M
zQgjGvLMp<dfcGcsexllk`yvI8gaG$IZX}vP#H>@cN+oonaBt{2213X%fItm0l#+s}
zBtLQ2#n8ezMF=oP0R(zQOFnbW9gp}m5f-Ue?{uG9`o0W*U!9E>JQ%Hpia*7&NQ{P&
z*R1CDKcxWn2IA8*6B9G*LGX~-7XafDRxfMkwXXmXHIg3x(gO at ZAp`(X)F7%5G#F{i
zetn$KGcz;gQmRy`uo*qW>pV#Nf?`prlB!^~G)V$P2@#X`siJ$H>FfOd9K}q(Y5wL1
zRPCghp=CJC6LWOSJlmH`-r<G8fyN}fiA({!z<;=D_y|ZyqaarJZPV!wdP4~I!!QiP
zd+zB}B{FOD#hWUbcN}9mc1H^c;u8^!Q&_Ry7_>4d5H=$*k7;t1)F`s()^frNjqQH8
zk$Py4RDAQz<7p6pbjt&NO|&#N3nE9X{Hjdk(Af<0nr5~$vIJ7l4p0n=elH9n7!VJg
z9gvWa=|TDpvKp3LXo(7hQ0cJUZ6gH(>p^eo1nBNc8DNlu8{U0jD0<8AeIW5wkf>q-
zTmQPOnU(z{q^%?j1p-hl12TjZB*qCz7=i@<pns!cXiw^{w^N#Sb=2|~imeUA7>*dx
z5)0G^QA0%<LX5LB8U!(RWB`C-K?#tK<p(js2!PC0vajU(V+sD?dE5Q^=|lCyqIQ}7
VH(_fwMQMNJF64 at Ep&@@BWMcQ%->m=u

diff --git a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-100-avr32.patch b/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-100-avr32.patch
deleted file mode 100644
index 6512f77..0000000
--- a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-100-avr32.patch
+++ /dev/null
@@ -1,16813 +0,0 @@
-diff -urN linux-2.6.28.2-0rig//arch/arm/mach-at91/include/mach/cpu.h linux-2.6.28.2/arch/arm/mach-at91/include/mach/cpu.h
---- linux-2.6.28.2-0rig//arch/arm/mach-at91/include/mach/cpu.h	2009-01-29 08:39:33.000000000 +0100
-+++ linux-2.6.28.2/arch/arm/mach-at91/include/mach/cpu.h	2009-01-29 08:52:44.000000000 +0100
-@@ -99,5 +99,6 @@
-  * definitions may reduce clutter in common drivers.
-  */
- #define cpu_is_at32ap7000()	(0)
-+#define cpu_is_at32ap7200()	(0)
- 
- #endif
-diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1005.c linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1005.c
---- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1005.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1005.c	2009-01-29 08:52:48.000000000 +0100
-@@ -0,0 +1,225 @@
-+/*
-+ * ATSTK1005 daughterboard-specific init code
-+ *
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/string.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/spi/spi.h>
-+
-+#include <asm/atmel-mci.h>
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/init.h>
-+#include <mach/portmux.h>
-+#include <mach/smc.h>
-+
-+#include "atstk1000.h"
-+
-+/* Oscillator frequencies. These are board specific */
-+unsigned long at32_board_osc_rates[4] = {
-+	[0] = 20000000,	/* 20 MHz on osc0 */
-+	[1] = 0,	/* Nothing on osc1 */
-+	[2] = 12000000,	/* 12 MHz on osc2 */
-+	[3] = 32768,	/* 32.768 kHz on RTC osc */
-+};
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+
-+static struct eth_addr __initdata hw_addr;
-+static struct eth_platform_data __initdata eth_data;
-+
-+static struct mci_platform_data mci_data __initdata = {
-+	.slot[0]	= {
-+		.detect_pin		= GPIO_PIN_NONE,
-+		.wp_pin			= GPIO_PIN_NONE,
-+		.bus_width		= 4,
-+	},
-+	.slot[1]	= {
-+		.detect_pin		= GPIO_PIN_PA(30),
-+		.wp_pin			= GPIO_PIN_PA(31),
-+		.bus_width		= 8,
-+	},
-+};
-+
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+	{
-+		/* AT45DB642D: 8MB DataFlash */
-+		.modalias	= "mtd_dataflash",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 0,
-+		.mode		= SPI_MODE_0,
-+	}, {
-+		/* QVGA display */
-+		.modalias	= "ltv350qv",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 2,
-+		.mode		= SPI_MODE_3,
-+	},
-+};
-+
-+static struct smc_timing nand_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 10,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 10,
-+
-+	.ncs_read_pulse		= 30,
-+	.nrd_pulse		= 15,
-+	.ncs_write_pulse	= 30,
-+	.nwe_pulse		= 15,
-+
-+	.read_cycle		= 30,
-+	.write_cycle		= 30,
-+
-+	.ncs_read_recover	= 0,
-+	.nrd_recover		= 15,
-+	.ncs_write_recover	= 0,
-+	.nwe_recover		= 50,
-+};
-+
-+static struct smc_config nand_config __initdata = {
-+	.bus_width		= 1,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.nwait_mode		= 0,
-+	.byte_write		= 0,
-+	.tdf_cycles		= 3,
-+	.tdf_mode		= 0,
-+};
-+
-+static struct mtd_partition nand_partitions[] = {
-+	{
-+		.name	= "u-boot",
-+		.offset	= 0,
-+		.size	= 131072,
-+	}, {
-+		.name	= "kernel",
-+		.offset	= 262144,
-+		.size	= 2097152,
-+	}, {
-+		.name	= "user",
-+		.offset	= 2359296,
-+		.size	= MTDPART_SIZ_FULL,
-+	},
-+};
-+
-+/* Isn't this rather more complicated than necessary? */
-+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
-+{
-+	*num_partitions = ARRAY_SIZE(nand_partitions);
-+	return nand_partitions;
-+}
-+
-+static struct atmel_nand_data nand_data __initdata = {
-+	.cle		= 21,
-+	.ale		= 22,
-+	.rdy_pin	= GPIO_PIN_PE(31),
-+	.enable_pin	= GPIO_PIN_PF(2),
-+	.det_pin	= GPIO_PIN_NONE,
-+	.partition_info	= nand_part_info,
-+};
-+
-+
-+/*
-+ * Grab ethernet address and PHY address provided by the boot loader.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	struct tag_ethernet *etag = &tag->u.ethernet;
-+
-+	if (etag->mac_index == 0) {
-+		eth_data.phy_mask = ~(1U << etag->mii_phy_addr);
-+		memcpy(&hw_addr.addr, etag->hw_address, sizeof(hw_addr.addr));
-+	}
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+/*
-+ * We need to get rid of this crap and pass the mac address to the
-+ * driver explicitly.
-+ */
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id != 0)
-+		return;
-+
-+	addr = hw_addr.addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(4, 0);	/* USART4: /dev/ttyS0, DB9 */
-+	at32_setup_serial_console(0);
-+}
-+
-+static int __init atstk1005_init(void)
-+{
-+	struct platform_device	*lcdc_pdev;
-+
-+	at32_add_device_usart(0);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data));
-+	lcdc_pdev = at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-+			fbmem_start, fbmem_size, 0);
-+	at32_add_device_mpop(0, lcdc_pdev, fbmem_start, fbmem_size);
-+	at32_add_device_mci(0, &mci_data);
-+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+
-+	/* NAND Flash */
-+	smc_set_timing(&nand_config, &nand_timing);
-+	smc_set_configuration(3, &nand_config);
-+	at32_add_device_nand(0, &nand_data);
-+
-+	/* USB OHCI/EHCI host */
-+	at32_add_device_ohci(0);
-+	at32_add_device_ehci(0);
-+
-+	return 0;
-+}
-+postcore_initcall(atstk1005_init);
-diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Kconfig linux-2.6.28.2/arch/avr32/boards/atstk1000/Kconfig
---- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Kconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/Kconfig	2009-01-29 08:52:48.000000000 +0100
-@@ -18,6 +18,10 @@
- 	bool "ATSTK1004"
- 	select CPU_AT32AP7002
- 
-+config BOARD_ATSTK1005
-+	bool "ATSTK1005"
-+	select CPU_AT32AP7200
-+
- config BOARD_ATSTK1006
- 	bool "ATSTK1006"
- 	select CPU_AT32AP7000
-diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Makefile linux-2.6.28.2/arch/avr32/boards/atstk1000/Makefile
---- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/Makefile	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/Makefile	2009-01-29 08:52:48.000000000 +0100
-@@ -2,4 +2,5 @@
- obj-$(CONFIG_BOARD_ATSTK1002)	+= atstk1002.o
- obj-$(CONFIG_BOARD_ATSTK1003)	+= atstk1003.o
- obj-$(CONFIG_BOARD_ATSTK1004)	+= atstk1004.o
-+obj-$(CONFIG_BOARD_ATSTK1005)	+= atstk1005.o
- obj-$(CONFIG_BOARD_ATSTK1006)	+= atstk1002.o
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atngw100_defconfig linux-2.6.28.2/arch/avr32/configs/atngw100_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atngw100_defconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atngw100_defconfig	2009-01-29 08:52:48.000000000 +0100
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 16:00:47 2008
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -130,11 +130,15 @@
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- # CONFIG_BOARD_ATSTK1000 is not set
- CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
- CONFIG_LOADER_U_BOOT=y
- 
- #
-@@ -177,7 +181,7 @@
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -615,6 +619,7 @@
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -664,6 +669,7 @@
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -706,7 +712,7 @@
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -720,6 +726,7 @@
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -751,11 +758,14 @@
- # CONFIG_DISPLAY_SUPPORT is not set
- # CONFIG_SOUND is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -806,6 +816,7 @@
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -880,11 +891,13 @@
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -898,13 +911,13 @@
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- # CONFIG_FS_POSIX_ACL is not set
-@@ -944,7 +957,7 @@
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1002_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1002_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1002_defconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atstk1002_defconfig	2009-01-29 08:52:49.000000000 +0100
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Mon Aug  4 16:02:27 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:28:45 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -129,20 +129,24 @@
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- CONFIG_BOARD_ATSTK1002=y
- # CONFIG_BOARD_ATSTK1003 is not set
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -186,7 +190,7 @@
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -360,7 +364,8 @@
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -421,12 +426,23 @@
- # CONFIG_MTD_DOC2001 is not set
- # CONFIG_MTD_DOC2001PLUS is not set
- # CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
- # CONFIG_MTD_ONENAND is not set
- 
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -502,7 +518,7 @@
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -561,7 +577,7 @@
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -590,6 +606,8 @@
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -606,8 +624,12 @@
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -634,6 +656,7 @@
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -663,7 +686,7 @@
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -683,6 +706,7 @@
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -725,7 +749,7 @@
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -739,6 +763,7 @@
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -784,6 +809,7 @@
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -797,6 +823,12 @@
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SND=m
-@@ -820,11 +852,14 @@
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -876,6 +911,7 @@
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -952,11 +988,13 @@
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -1017,7 +1055,7 @@
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -1031,7 +1069,8 @@
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -1039,6 +1078,12 @@
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
- CONFIG_MINIX_FS=m
-@@ -1173,7 +1218,7 @@
- #
- # Crypto core or helper
- #
--CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_ALGAPI=y
- CONFIG_CRYPTO_AEAD=m
- CONFIG_CRYPTO_BLKCIPHER=m
- CONFIG_CRYPTO_HASH=m
-@@ -1247,8 +1292,8 @@
- #
- # Compression
- #
--CONFIG_CRYPTO_DEFLATE=m
--# CONFIG_CRYPTO_LZO is not set
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
- # CONFIG_CRYPTO_HW is not set
- 
- #
-@@ -1258,7 +1303,7 @@
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
-@@ -1266,6 +1311,8 @@
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1003_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1003_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1003_defconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atstk1003_defconfig	2009-01-29 08:52:49.000000000 +0100
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:34:44 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -34,12 +34,9 @@
- CONFIG_SYSVIPC=y
- CONFIG_SYSVIPC_SYSCTL=y
- CONFIG_POSIX_MQUEUE=y
--CONFIG_BSD_PROCESS_ACCT=y
--CONFIG_BSD_PROCESS_ACCT_V3=y
--CONFIG_TASKSTATS=y
--CONFIG_TASK_DELAY_ACCT=y
--# CONFIG_TASK_XACCT is not set
--CONFIG_AUDIT=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
- # CONFIG_IKCONFIG is not set
- CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_CGROUPS is not set
-@@ -71,7 +68,7 @@
- CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
--# CONFIG_SLUB_DEBUG is not set
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
- CONFIG_SLUB=y
- # CONFIG_SLOB is not set
-@@ -90,6 +87,7 @@
- CONFIG_HAVE_CLK=y
- CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
- CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
-@@ -131,20 +129,24 @@
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7001=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- CONFIG_BOARD_ATSTK1003=y
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -188,7 +190,7 @@
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -239,40 +241,71 @@
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -331,7 +364,8 @@
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -397,7 +431,15 @@
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -458,9 +500,7 @@
- # CONFIG_SCSI_ISCSI_ATTRS is not set
- # CONFIG_SCSI_SAS_LIBSAS is not set
- # CONFIG_SCSI_SRP_ATTRS is not set
--CONFIG_SCSI_LOWLEVEL=y
--# CONFIG_ISCSI_TCP is not set
--# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
- # CONFIG_SCSI_DH is not set
- CONFIG_ATA=m
- # CONFIG_ATA_NONSTANDARD is not set
-@@ -477,7 +517,32 @@
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
- # CONFIG_VETH is not set
--# CONFIG_NET_ETHERNET is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
- # CONFIG_NETDEV_1000 is not set
- # CONFIG_NETDEV_10000 is not set
- 
-@@ -509,7 +574,7 @@
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -521,7 +586,7 @@
- CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
- CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_EVDEV is not set
-+CONFIG_INPUT_EVDEV=m
- # CONFIG_INPUT_EVBUG is not set
- 
- #
-@@ -538,6 +603,8 @@
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -555,7 +622,7 @@
- # Character devices
- #
- # CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -582,6 +649,7 @@
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -611,7 +679,7 @@
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -631,6 +699,7 @@
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -673,7 +742,7 @@
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -687,6 +756,7 @@
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -726,8 +796,8 @@
- CONFIG_SND_PCM_OSS=m
- CONFIG_SND_PCM_OSS_PLUGINS=y
- # CONFIG_SND_DYNAMIC_MINORS is not set
--CONFIG_SND_SUPPORT_OLD_API=y
--CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
- # CONFIG_SND_DRIVERS is not set
-@@ -738,11 +808,14 @@
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -750,7 +823,7 @@
- CONFIG_USB_GADGET=y
- # CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
--CONFIG_USB_GADGET_DEBUG_FS=y
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -787,33 +860,34 @@
- CONFIG_MMC_BLOCK=y
- CONFIG_MMC_BLOCK_BOUNCE=y
- # CONFIG_SDIO_UART is not set
--CONFIG_MMC_TEST=m
-+# CONFIG_MMC_TEST is not set
- 
- #
- # MMC/SD Host Controller Drivers
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
--CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_CLASS=m
- 
- #
- # LED drivers
- #
- CONFIG_LEDS_ATMEL_PWM=m
- # CONFIG_LEDS_PCA9532 is not set
--CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_GPIO=m
- # CONFIG_LEDS_PCA955X is not set
- 
- #
- # LED Triggers
- #
- CONFIG_LEDS_TRIGGERS=y
--CONFIG_LEDS_TRIGGER_TIMER=y
--CONFIG_LEDS_TRIGGER_HEARTBEAT=y
--CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -870,11 +944,13 @@
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -888,13 +964,13 @@
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -935,7 +1011,7 @@
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -958,16 +1034,39 @@
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
--# CONFIG_MINIX_FS is not set
-+CONFIG_MINIX_FS=m
- # CONFIG_OMFS_FS is not set
- # CONFIG_HPFS_FS is not set
- # CONFIG_QNX4FS_FS is not set
- # CONFIG_ROMFS_FS is not set
- # CONFIG_SYSV_FS is not set
- # CONFIG_UFS_FS is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
- 
- #
- # Partition Types
-@@ -1036,6 +1135,8 @@
- # CONFIG_SCHEDSTATS is not set
- # CONFIG_TIMER_STATS is not set
- # CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
- # CONFIG_DEBUG_RT_MUTEXES is not set
- # CONFIG_RT_MUTEX_TESTER is not set
- # CONFIG_DEBUG_SPINLOCK is not set
-@@ -1068,7 +1169,88 @@
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -1077,15 +1259,16 @@
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
- CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
--CONFIG_AUDIT_GENERIC=y
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1004_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1004_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1004_defconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atstk1004_defconfig	2009-01-29 08:52:49.000000000 +0100
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:38:56 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:35:14 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -30,8 +30,10 @@
- CONFIG_INIT_ENV_ARG_LIMIT=32
- CONFIG_LOCALVERSION=""
- # CONFIG_LOCALVERSION_AUTO is not set
--# CONFIG_SYSVIPC is not set
--# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- # CONFIG_TASKSTATS is not set
- # CONFIG_AUDIT is not set
-@@ -41,14 +43,16 @@
- # CONFIG_GROUP_SCHED is not set
- CONFIG_SYSFS_DEPRECATED=y
- CONFIG_SYSFS_DEPRECATED_V2=y
--# CONFIG_RELAY is not set
-+CONFIG_RELAY=y
- # CONFIG_NAMESPACES is not set
--# CONFIG_BLK_DEV_INITRD is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
- CONFIG_CC_OPTIMIZE_FOR_SIZE=y
- CONFIG_SYSCTL=y
- CONFIG_EMBEDDED=y
- # CONFIG_SYSCTL_SYSCALL is not set
- CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
- CONFIG_HOTPLUG=y
- CONFIG_PRINTK=y
-@@ -56,19 +60,23 @@
- CONFIG_ELF_CORE=y
- # CONFIG_COMPAT_BRK is not set
- # CONFIG_BASE_FULL is not set
--# CONFIG_FUTEX is not set
--# CONFIG_EPOLL is not set
--# CONFIG_SIGNALFD is not set
--# CONFIG_TIMERFD is not set
--# CONFIG_EVENTFD is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
--# CONFIG_SLUB is not set
--CONFIG_SLOB=y
--# CONFIG_PROFILING is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
- # CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
- CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
- # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
- # CONFIG_HAVE_IOREMAP_PROT is not set
- CONFIG_HAVE_KPROBES=y
-@@ -77,36 +85,68 @@
- # CONFIG_HAVE_DMA_ATTRS is not set
- # CONFIG_USE_GENERIC_SMP_HELPERS is not set
- CONFIG_HAVE_CLK=y
--# CONFIG_PROC_PAGE_MONITOR is not set
-+CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
--# CONFIG_MODULES is not set
--# CONFIG_BLOCK is not set
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
- CONFIG_CLASSIC_RCU=y
- 
- #
- # System Type and features
- #
--# CONFIG_TICK_ONESHOT is not set
--# CONFIG_NO_HZ is not set
--# CONFIG_HIGH_RES_TIMERS is not set
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
- CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7002=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- # CONFIG_BOARD_ATSTK1003 is not set
- CONFIG_BOARD_ATSTK1004=y
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -144,25 +184,43 @@
- CONFIG_NR_QUICK=2
- CONFIG_VIRT_TO_BUS=y
- # CONFIG_OWNERSHIP_TRACE is not set
--# CONFIG_NMI_DEBUGGING is not set
-+CONFIG_NMI_DEBUGGING=y
- # CONFIG_HZ_100 is not set
- CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
- # Power management options
- #
--# CONFIG_PM is not set
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
- CONFIG_ARCH_SUSPEND_POSSIBLE=y
- 
- #
- # CPU Frequency scaling
- #
--# CONFIG_CPU_FREQ is not set
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
- 
- #
- # Bus options
-@@ -183,40 +241,71 @@
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -230,6 +319,7 @@
- # Network testing
- #
- # CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
- # CONFIG_HAMRADIO is not set
- # CONFIG_CAN is not set
- # CONFIG_IRDA is not set
-@@ -257,6 +347,8 @@
- CONFIG_STANDALONE=y
- # CONFIG_PREVENT_FIRMWARE_BUILD is not set
- # CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
- # CONFIG_SYS_HYPERVISOR is not set
- # CONFIG_CONNECTOR is not set
- CONFIG_MTD=y
-@@ -271,6 +363,14 @@
- # User Modules And Translation Layers
- #
- CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
- # CONFIG_MTD_OOPS is not set
- 
- #
-@@ -311,11 +411,13 @@
- #
- # Self-contained MTD device drivers
- #
--# CONFIG_MTD_DATAFLASH is not set
--# CONFIG_MTD_M25P80 is not set
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_SLRAM is not set
- # CONFIG_MTD_PHRAM is not set
- # CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
- 
- #
- # Disk-On-Chip Device Drivers
-@@ -329,24 +431,186 @@
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
--# CONFIG_MISC_DEVICES is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
- # CONFIG_HAVE_IDE is not set
- 
- #
- # SCSI device support
- #
--# CONFIG_SCSI_DMA is not set
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
- # CONFIG_SCSI_NETLINK is not set
--# CONFIG_NETDEVICES is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
- # CONFIG_ISDN is not set
- # CONFIG_PHONE is not set
- 
- #
- # Input device support
- #
--# CONFIG_INPUT is not set
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
- 
- #
- # Hardware I/O ports
-@@ -357,8 +621,12 @@
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -371,7 +639,7 @@
- #
- CONFIG_SERIAL_ATMEL=y
- CONFIG_SERIAL_ATMEL_CONSOLE=y
--# CONFIG_SERIAL_ATMEL_PDC is not set
-+CONFIG_SERIAL_ATMEL_PDC=y
- # CONFIG_SERIAL_ATMEL_TTYAT is not set
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-@@ -380,14 +648,62 @@
- # CONFIG_IPMI_HANDLER is not set
- # CONFIG_HW_RANDOM is not set
- # CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
- # CONFIG_TCG_TPM is not set
--# CONFIG_I2C is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
- CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
- CONFIG_SPI_MASTER=y
- 
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -395,15 +711,19 @@
- # SPI Protocol Masters
- #
- # CONFIG_SPI_AT25 is not set
--# CONFIG_SPI_SPIDEV is not set
-+CONFIG_SPI_SPIDEV=m
- # CONFIG_SPI_TLE62X0 is not set
- CONFIG_ARCH_REQUIRE_GPIOLIB=y
- CONFIG_GPIOLIB=y
--# CONFIG_GPIO_SYSFS is not set
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
- 
- #
- # I2C GPIO expanders:
- #
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
- 
- #
- # PCI GPIO expanders:
-@@ -426,7 +746,7 @@
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -440,6 +760,7 @@
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -485,6 +806,7 @@
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -498,20 +820,51 @@
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
--# CONFIG_SOUND is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+# CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
- #
- CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -528,18 +881,54 @@
- # CONFIG_USB_GADGET_AT91 is not set
- # CONFIG_USB_GADGET_DUMMY_HCD is not set
- CONFIG_USB_GADGET_DUALSPEED=y
--# CONFIG_USB_ZERO is not set
--CONFIG_USB_ETH=y
--# CONFIG_USB_ETH_RNDIS is not set
--# CONFIG_USB_GADGETFS is not set
--# CONFIG_USB_FILE_STORAGE is not set
--# CONFIG_USB_G_SERIAL is not set
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
--# CONFIG_MMC is not set
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
--# CONFIG_NEW_LEDS is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -551,12 +940,28 @@
- # RTC interfaces
- #
- CONFIG_RTC_INTF_SYSFS=y
--# CONFIG_RTC_INTF_PROC is not set
-+CONFIG_RTC_INTF_PROC=y
- CONFIG_RTC_INTF_DEV=y
- # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
- # CONFIG_RTC_DRV_TEST is not set
- 
- #
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
- # SPI RTC drivers
- #
- # CONFIG_RTC_DRV_M41T94 is not set
-@@ -580,18 +985,62 @@
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
--# CONFIG_DMADEVICES is not set
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+# CONFIG_ATMEL_PDCA is not set
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
- # CONFIG_UIO is not set
- 
- #
- # File systems
- #
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
- # CONFIG_DNOTIFY is not set
--# CONFIG_INOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
- # CONFIG_QUOTA is not set
- # CONFIG_AUTOFS_FS is not set
- # CONFIG_AUTOFS4_FS is not set
--# CONFIG_FUSE_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
- 
- #
- # Pseudo filesystems
-@@ -603,14 +1052,22 @@
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
- #
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -618,8 +1075,85 @@
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
--# CONFIG_NLS is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
- # CONFIG_DLM is not set
- 
- #
-@@ -631,11 +1165,43 @@
- CONFIG_FRAME_WARN=1024
- CONFIG_MAGIC_SYSRQ=y
- # CONFIG_UNUSED_SYMBOLS is not set
--# CONFIG_DEBUG_FS is not set
-+CONFIG_DEBUG_FS=y
- # CONFIG_HEADERS_CHECK is not set
--# CONFIG_DEBUG_KERNEL is not set
--# CONFIG_DEBUG_BUGVERBOSE is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
- # CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
- # CONFIG_SAMPLES is not set
- 
- #
-@@ -644,7 +1210,88 @@
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -652,16 +1299,19 @@
- CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
--# CONFIG_CRC_CCITT is not set
--# CONFIG_CRC16 is not set
--# CONFIG_CRC_T10DIF is not set
--# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+CONFIG_CRC_T10DIF=m
-+CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
--# CONFIG_CRC7 is not set
-+CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
- CONFIG_HAS_IOPORT=y
- CONFIG_HAS_DMA=y
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1005_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1005_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1005_defconfig	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atstk1005_defconfig	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,1505 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Fri Nov  7 10:22:27 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+CONFIG_RELAY=y
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_GPIO_V2=y
-+CONFIG_TIMER_AST=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP720X=y
-+CONFIG_CPU_AT32AP7200=y
-+CONFIG_BOARD_ATSTK1000=y
-+# CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATSTK1002 is not set
-+# CONFIG_BOARD_ATSTK1003 is not set
-+# CONFIG_BOARD_ATSTK1004 is not set
-+CONFIG_BOARD_ATSTK1005=y
-+# CONFIG_BOARD_ATSTK1006 is not set
-+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
-+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
-+CONFIG_BOARD_ATSTK1000_EXTDAC=y
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+CONFIG_MTD_NAND_ATMEL=y
-+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+# CONFIG_ATMEL_TCLIB is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=m
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+
-+#
-+# USB Network Adapters
-+#
-+CONFIG_USB_CATC=m
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+CONFIG_USB_USBNET=m
-+# CONFIG_USB_NET_AX8817X is not set
-+CONFIG_USB_NET_CDCETHER=m
-+# CONFIG_USB_NET_DM9601 is not set
-+# CONFIG_USB_NET_GL620A is not set
-+# CONFIG_USB_NET_NET1080 is not set
-+# CONFIG_USB_NET_PLUSB is not set
-+# CONFIG_USB_NET_MCS7830 is not set
-+# CONFIG_USB_NET_RNDIS_HOST is not set
-+CONFIG_USB_NET_CDC_SUBSET=m
-+# CONFIG_USB_ALI_M5632 is not set
-+# CONFIG_USB_AN2720 is not set
-+CONFIG_USB_BELKIN=y
-+CONFIG_USB_ARMLINUX=y
-+# CONFIG_USB_EPSON2888 is not set
-+# CONFIG_USB_KC2190 is not set
-+# CONFIG_USB_NET_ZAURUS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+CONFIG_I2C_TINY_USB=m
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_LCD_LTV350QV=y
-+# CONFIG_LCD_ILI9320 is not set
-+# CONFIG_LCD_VGG2432A4 is not set
-+# CONFIG_LCD_PLATFORM is not set
-+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+CONFIG_SND_HWDEP=m
-+CONFIG_SND_RAWMIDI=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+CONFIG_SND_USB=y
-+CONFIG_SND_USB_AUDIO=m
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-+# CONFIG_HID_FF is not set
-+# CONFIG_USB_HIDDEV is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+# CONFIG_USB_DEVICE_CLASS is not set
-+CONFIG_USB_DYNAMIC_MINORS=y
-+CONFIG_USB_SUSPEND=y
-+# CONFIG_USB_OTG is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MON=y
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+CONFIG_USB_EHCI_HCD=y
-+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
-+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+CONFIG_USB_ACM=m
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_WDM=m
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# may also be needed; see USB_STORAGE Help for more information
-+#
-+CONFIG_USB_STORAGE=m
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_DPCM is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+CONFIG_USB_SERIAL=m
-+# CONFIG_USB_EZUSB is not set
-+CONFIG_USB_SERIAL_GENERIC=y
-+# CONFIG_USB_SERIAL_AIRCABLE is not set
-+# CONFIG_USB_SERIAL_ARK3116 is not set
-+# CONFIG_USB_SERIAL_BELKIN is not set
-+# CONFIG_USB_SERIAL_CH341 is not set
-+# CONFIG_USB_SERIAL_WHITEHEAT is not set
-+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-+# CONFIG_USB_SERIAL_CP2101 is not set
-+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-+# CONFIG_USB_SERIAL_EMPEG is not set
-+# CONFIG_USB_SERIAL_FTDI_SIO is not set
-+# CONFIG_USB_SERIAL_FUNSOFT is not set
-+# CONFIG_USB_SERIAL_VISOR is not set
-+# CONFIG_USB_SERIAL_IPAQ is not set
-+# CONFIG_USB_SERIAL_IR is not set
-+# CONFIG_USB_SERIAL_EDGEPORT is not set
-+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-+# CONFIG_USB_SERIAL_GARMIN is not set
-+# CONFIG_USB_SERIAL_IPW is not set
-+# CONFIG_USB_SERIAL_IUU is not set
-+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-+# CONFIG_USB_SERIAL_KEYSPAN is not set
-+# CONFIG_USB_SERIAL_KLSI is not set
-+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-+# CONFIG_USB_SERIAL_MCT_U232 is not set
-+# CONFIG_USB_SERIAL_MOS7720 is not set
-+# CONFIG_USB_SERIAL_MOS7840 is not set
-+# CONFIG_USB_SERIAL_MOTOROLA is not set
-+# CONFIG_USB_SERIAL_NAVMAN is not set
-+CONFIG_USB_SERIAL_PL2303=m
-+# CONFIG_USB_SERIAL_OTI6858 is not set
-+# CONFIG_USB_SERIAL_SPCP8X5 is not set
-+# CONFIG_USB_SERIAL_HP4X is not set
-+# CONFIG_USB_SERIAL_SAFE is not set
-+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-+# CONFIG_USB_SERIAL_TI is not set
-+# CONFIG_USB_SERIAL_CYBERJACK is not set
-+# CONFIG_USB_SERIAL_XIRCOM is not set
-+# CONFIG_USB_SERIAL_OPTION is not set
-+# CONFIG_USB_SERIAL_OMNINET is not set
-+# CONFIG_USB_SERIAL_DEBUG is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_BERRY_CHARGE is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_PHIDGET is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+CONFIG_USB_TEST=m
-+# CONFIG_USB_ISIGHTFW is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+CONFIG_MMC_TEST=m
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_RTC_DRV_AT32AP700X is not set
-+CONFIG_RTC_DRV_AVR32_AST=y
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_ATMEL_PDCA=y
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+CONFIG_CRC_ITU_T=m
-+CONFIG_CRC32=y
-+CONFIG_CRC7=m
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff -urN linux-2.6.28.2-0rig//arch/avr32/configs/atstk1006_defconfig linux-2.6.28.2/arch/avr32/configs/atstk1006_defconfig
---- linux-2.6.28.2-0rig//arch/avr32/configs/atstk1006_defconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/configs/atstk1006_defconfig	2009-01-29 09:11:15.000000000 +0100
-@@ -124,6 +124,7 @@
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
-@@ -137,9 +138,9 @@
- CONFIG_BOARD_ATSTK1006=y
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -355,7 +356,8 @@
- CONFIG_MTD_CHAR=y
- CONFIG_HAVE_MTD_OTP=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -419,7 +421,7 @@
- # CONFIG_MTD_DOC2001PLUS is not set
- CONFIG_MTD_NAND=y
- # CONFIG_MTD_NAND_VERIFY_WRITE is not set
--# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
- # CONFIG_MTD_NAND_MUSEUM_IDS is not set
- CONFIG_MTD_NAND_IDS=y
- # CONFIG_MTD_NAND_DISKONCHIP is not set
-@@ -519,7 +521,7 @@
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -581,7 +583,7 @@
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -610,6 +612,8 @@
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -626,8 +630,12 @@
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -704,6 +712,7 @@
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -752,6 +761,7 @@
- # CONFIG_SOFT_WATCHDOG is not set
- CONFIG_AT32AP700X_WDT=y
- CONFIG_SSB_POSSIBLE=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -814,6 +824,7 @@
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- # CONFIG_FB_METRONOME is not set
- # CONFIG_FB_MB862XX is not set
-@@ -830,6 +841,12 @@
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SOUND_OSS_CORE=y
-@@ -846,11 +863,7 @@
- # CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
--CONFIG_SND_DRIVERS=y
--# CONFIG_SND_DUMMY is not set
--# CONFIG_SND_MTPAV is not set
--# CONFIG_SND_SERIAL_U16550 is not set
--# CONFIG_SND_MPU401 is not set
-+# CONFIG_SND_DRIVERS is not set
- CONFIG_SND_SPI=y
- CONFIG_SND_AT73C213=m
- CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-@@ -858,9 +871,9 @@
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
- # CONFIG_USB_MUSB_HDRC is not set
-@@ -900,7 +913,7 @@
- CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_USB_CDC_COMPOSITE=m
- CONFIG_MMC=y
- # CONFIG_MMC_DEBUG is not set
- # CONFIG_MMC_UNSAFE_RESUME is not set
-@@ -1002,11 +1015,13 @@
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -1022,17 +1037,17 @@
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
--CONFIG_EXT4_FS=m
--CONFIG_EXT4DEV_COMPAT=y
-+# CONFIG_EXT4_FS is not set
-+# CONFIG_EXT4DEV_COMPAT=y
- # CONFIG_EXT4_FS_XATTR is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
--CONFIG_JBD2=m
-+# CONFIG_JBD2 is not set
- # CONFIG_JBD2_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -1075,7 +1090,7 @@
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-diff -urN linux-2.6.28.2-0rig//arch/avr32/include/asm/ast_regs.h linux-2.6.28.2/arch/avr32/include/asm/ast_regs.h
---- linux-2.6.28.2-0rig//arch/avr32/include/asm/ast_regs.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/include/asm/ast_regs.h	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,88 @@
-+/*
-+ * Register definitions for the Asynchronous Timer (AST)
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __AST_REGS_H__
-+#define __AST_REGS_H__
-+
-+/* Control Register */
-+#define AST_CR				0x0000
-+# define AST_CR_EN_BIT			0	/* Enable */
-+# define AST_CR_PCLR_BIT		1	/* Prescaler Clear */
-+# define AST_CR_CA0_BIT			8	/* Clear on Alarm */
-+# define AST_CR_CA1_BIT			9
-+# define AST_CR_PSEL_START		16	/* Prescale Select */
-+# define AST_CR_PSEL_SIZE		4
-+
-+/* Counter Value */
-+#define AST_CV				0x0004
-+
-+/* Status, Status Clear, Interrupt Enable/Disable/Mask, Wake Enable */
-+#define AST_SR				0x0008
-+#define AST_SCR				0x000c
-+#define AST_IER				0x0010
-+#define AST_IDR				0x0014
-+#define AST_IMR				0x0018
-+#define AST_WER				0x001c
-+# define AST_OVF_BIT			0	/* Overflow */
-+# define AST_ALARM0_BIT			8	/* Alarm event */
-+# define AST_ALARM1_BIT			9
-+# define AST_PER0_BIT			16	/* Periodic event */
-+# define AST_PER1_BIT			17
-+# define AST_BUSY_BIT			24	/* AST busy */
-+# define AST_READY_BIT			25	/* BUSY 1 -> 0 event */
-+# define AST_CLK_BUSY_BIT		28	/* CLOCK busy */
-+# define AST_CLK_READY_BIT		29	/* CKL_BUSY 1 -> 0 event */
-+
-+/* Alarm registers */
-+#define AST_AR0				0x0020
-+#define AST_AR1				0x0024
-+
-+/* Periodic Interval registers */
-+#define AST_PIR0			0x0030
-+#define AST_PIR1			0x0034
-+# define AST_PIRx_INSEL_START		0	/* Interval select */
-+# define AST_PIRx_INSEL_SIZE		4
-+
-+/* Clock Select register */
-+#define AST_CLOCK			0x0040
-+# define AST_CLOCK_CEN_BIT		0	/* Clock Enable */
-+# define AST_CLOCK_CSSEL_START		8	/* Clock Source */
-+# define AST_CLOCK_CSSEL_SIZE		2
-+#  define AST_CLOCK_SLOW		0	/* RC oscillator */
-+#  define AST_CLOCK_OSC32		1	/* 32 kHz oscillator */
-+#  define AST_CLOCK_PB			2	/* Peripheral Bus clock */
-+#  define AST_CLOCK_GC			3	/* Generic clock */
-+
-+/* Version register */
-+#define AST_VERSION			0x00fc
-+
-+/* Bit manipulation macros */
-+#define AST_BIT(name)						\
-+	(1 << AST_##name##_BIT)
-+#define AST_BF(name,value)					\
-+	(((value) & ((1 << AST_##name##_SIZE) - 1))		\
-+	 << AST_##name##_START)
-+#define AST_BFEXT(name,value)					\
-+	(((value) >> AST_##name##_START)			\
-+	 & ((1 << AST_##name##_SIZE) - 1))
-+#define AST_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << AST_##name##_SIZE) - 1)		\
-+		    << AST_##name##_START))			\
-+	 | AST_BF(name,value))
-+
-+/* Register access macros */
-+#define ast_readl(base, reg)					\
-+	__raw_readl(base + AST_##reg)
-+#define ast_writel(base, reg, value)				\
-+	__raw_writel(value, base + AST_##reg)
-+
-+struct platform_device;
-+void ast_time_init(struct platform_device *pdev, unsigned int clksel);
-+
-+#endif /* __AST_REGS_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/Kconfig linux-2.6.28.2/arch/avr32/Kconfig
---- linux-2.6.28.2-0rig//arch/avr32/Kconfig	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/Kconfig	2009-01-29 08:52:44.000000000 +0100
-@@ -85,6 +85,18 @@
- config PERFORMANCE_COUNTERS
- 	bool
- 
-+# The old "PIO" portmux/GPIO module used on AT32AP700x
-+config PORTMUX_PIO
-+	bool
-+
-+# The new "GPIO" portmux/GPIO module, version 2
-+config PORTMUX_GPIO_V2
-+	bool
-+
-+# Asynchronous Timer clocksource/clockevent driver
-+config TIMER_AST
-+	bool
-+
- config PLATFORM_AT32AP
- 	bool
- 	select SUBARCH_AVR32B
-@@ -101,6 +113,7 @@
- config CPU_AT32AP700X
- 	bool
- 	select PLATFORM_AT32AP
-+	select PORTMUX_PIO
- config CPU_AT32AP7000
- 	bool
- 	select CPU_AT32AP700X
-@@ -111,6 +124,16 @@
- 	bool
- 	select CPU_AT32AP700X
- 
-+# AP7200 derivatives
-+config CPU_AT32AP720X
-+	bool
-+	select PLATFORM_AT32AP
-+	select TIMER_AST
-+	select PORTMUX_GPIO_V2
-+config CPU_AT32AP7200
-+	bool
-+	select CPU_AT32AP720X
-+
- choice
- 	prompt "AVR32 board type"
- 	default BOARD_ATSTK1000
-@@ -148,14 +171,17 @@
- config LOAD_ADDRESS
- 	hex
- 	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config ENTRY_ADDRESS
- 	hex
- 	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config PHYS_OFFSET
- 	hex
- 	default 0x10000000 if CPU_AT32AP700X=y
-+	default 0x10000000 if CPU_AT32AP720X=y
- 
- source "kernel/Kconfig.preempt"
- 
-diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/cpu.c linux-2.6.28.2/arch/avr32/kernel/cpu.c
---- linux-2.6.28.2-0rig//arch/avr32/kernel/cpu.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/kernel/cpu.c	2009-01-29 08:52:49.000000000 +0100
-@@ -208,6 +208,7 @@
- 
- static const struct chip_id_map chip_names[] = {
- 	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
-+	{ .mid = 0x1f, .pn = 0x1e83, .name = "AT32AP720x" },
- };
- #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
- 
-diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/entry-avr32b.S linux-2.6.28.2/arch/avr32/kernel/entry-avr32b.S
---- linux-2.6.28.2-0rig//arch/avr32/kernel/entry-avr32b.S	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/kernel/entry-avr32b.S	2009-01-29 08:52:49.000000000 +0100
-@@ -112,7 +112,9 @@
- 
- 	/* Second level lookup */
- 	ld.w	r2, r3[r1 << 2]
-+#ifdef CONFIG_CPU_AT32AP700X
- 	mfsr	r0, SYSREG_TLBARLO
-+#endif
- 	bld	r2, _PAGE_BIT_PRESENT
- 	brcc	page_not_present
- 
-@@ -124,6 +126,8 @@
- 	andl	r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
- 	mtsr	SYSREG_TLBELO, r2
- 
-+	/* Later CPUs do this algorithm in hardware */
-+#ifdef CONFIG_CPU_AT32AP700X
- 	/* Figure out which entry we want to replace */
- 	mfsr	r1, SYSREG_MMUCR
- 	clz	r2, r0
-@@ -134,6 +138,7 @@
- 
- 1:	bfins	r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
- 	mtsr	SYSREG_MMUCR, r1
-+#endif /* CONFIG_CPU_AT32AP700X */
- 	tlbw
- 
- 	tlbmiss_restore
-@@ -751,8 +756,10 @@
- 
- 	lddsp	r4, sp[REG_SR]
- 	bfextu	r4, r4, SYSREG_M0_OFFSET, 3
-+#ifdef CONFIG_CPU_AT32AP700X
- 	cp.w	r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
- 	breq	2f
-+#endif
- 	cp.w	r4, MODE_USER >> SYSREG_M0_OFFSET
- #ifdef CONFIG_PREEMPT
- 	brne	3f
-@@ -786,6 +793,7 @@
- 	rete
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP700X
- 2:	get_thread_info	r0
- 	ld.w	r1, r0[TI_flags]
- 	bld	r1, TIF_CPU_GOING_TO_SLEEP
-@@ -796,6 +804,7 @@
- #endif
- 	sub	r1, pc, . - cpu_idle_skip_sleep
- 	stdsp	sp[REG_PC], r1
-+#endif
- #ifdef CONFIG_PREEMPT
- 3:	get_thread_info r0
- 	ld.w	r2, r0[TI_preempt_count]
-diff -urN linux-2.6.28.2-0rig//arch/avr32/kernel/time.c linux-2.6.28.2/arch/avr32/kernel/time.c
---- linux-2.6.28.2-0rig//arch/avr32/kernel/time.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/kernel/time.c	2009-01-29 08:52:49.000000000 +0100
-@@ -15,6 +15,8 @@
- 
- #include <asm/sysreg.h>
- 
-+#include <mach/cpu.h>
-+#include <mach/init.h>
- #include <mach/pm.h>
- 
- 
-@@ -116,6 +118,9 @@
- 	unsigned long counter_hz;
- 	int ret;
- 
-+	/* Make sure we don't get any interrupts until we ask for it. */
-+	sysreg_write(COMPARE, 0);
-+
- 	xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
- 	xtime.tv_nsec = 0;
- 
-@@ -130,12 +135,16 @@
- 	if (ret)
- 		pr_debug("timer: could not register clocksource: %d\n", ret);
- 
-+	if (!cpu_has_working_compare()) {
-+		platform_time_init();
-+		return;
-+	}
-+
- 	/* setup COMPARE clockevent */
- 	comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
- 	comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
- 	comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
- 
--	sysreg_write(COMPARE, 0);
- 	timer_irqaction.dev_id = &comparator;
- 
- 	ret = setup_irq(0, &timer_irqaction);
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 08:52:49.000000000 +0100
-@@ -23,6 +23,7 @@
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
- #include <mach/hmatrix.h>
-+#include <mach/pm.h>
- #include <mach/portmux.h>
- #include <mach/sram.h>
- 
-@@ -30,7 +31,7 @@
- 
- #include "clock.h"
- #include "pio.h"
--#include "pm.h"
-+#include "pm-v1.h"
- 
- 
- #define PBMEM(base)					\
-@@ -996,6 +997,7 @@
- void __init at32_map_usart(unsigned int hw_id, unsigned int line)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	switch (hw_id) {
- 	case 0:
-@@ -1155,6 +1157,7 @@
- static struct resource atmel_spi0_resource[] = {
- 	PBMEM(0xffe00000),
- 	IRQ(3),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 0);
- DEV_CLK(spi_clk, atmel_spi0, pba, 0);
-@@ -1162,6 +1165,7 @@
- static struct resource atmel_spi1_resource[] = {
- 	PBMEM(0xffe00400),
- 	IRQ(4),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 1);
- DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-@@ -1191,6 +1195,8 @@
- struct platform_device *__init
- at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- {
-+	unsigned long sram_buf;
-+
- 	/*
- 	 * Manage the chipselects as GPIOs, normally using the same pins
- 	 * the SPI controller expects; but boards can use other pins.
-@@ -1231,6 +1237,13 @@
- 		return NULL;
- 	}
- 
-+	sram_buf = sram_alloc(4096);
-+	if (sram_buf) {
-+		pdev->resource[2].start = sram_buf;
-+		pdev->resource[2].end = sram_buf + 4096 - 1;
-+		pdev->resource[2].flags = IORESOURCE_MEM;
-+	}
-+
- 	spi_register_board_info(b, n);
- 	platform_device_register(pdev);
- 	return pdev;
-@@ -1738,6 +1751,7 @@
- 		struct usba_ep_data ep[7];
- 	} usba_data;
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -1940,6 +1954,7 @@
- at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0 || !data)
- 		return NULL;
-@@ -2272,6 +2287,11 @@
- 	at32_init_pio(&pio4_device);
- }
- 
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
- struct gen_pool *sram_pool;
- 
- static int __init sram_init(void)
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap720x.c linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap720x.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap720x.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap720x.c	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,2303 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dw_dmac.h>
-+#include <linux/errno.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm.h>
-+#include <linux/spinlock.h>
-+#include <linux/spi/atmel_spi.h>
-+#include <linux/spi/spi.h>
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#include <asm/ast_regs.h>
-+#include <asm/atmel-mci.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/hmatrix.h>
-+#include <mach/init.h>
-+#include <mach/pm.h>
-+#include <mach/portmux.h>
-+#include <mach/sram.h>
-+
-+#include "clock.h"
-+#include "gpio-v2.h"
-+#include "pm-v3.h"
-+#include "sdc.h"
-+
-+#define PBMEM(base)					\
-+	{						\
-+		.start		= base,			\
-+		.end		= base + 0x3ff,		\
-+		.flags		= IORESOURCE_MEM,	\
-+	}
-+#define IRQ(num)					\
-+	{						\
-+		.start		= num,			\
-+		.end		= num,			\
-+		.flags		= IORESOURCE_IRQ,	\
-+	}
-+
-+#define select_peripheral(port, pin_mask, periph, flags)	\
-+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
-+			   GPIO_##periph, flags)
-+
-+#define DEV_CLK(_name, devname, bus, _index)			\
-+static struct clk devname##_##_name = {				\
-+	.name		= #_name,				\
-+	.dev		= &devname##_device.dev,		\
-+	.parent		= &bus##_clk,				\
-+	.mode		= bus##_clk_mode,			\
-+	.get_rate	= bus##_clk_get_rate,			\
-+	.index		= _index,				\
-+}
-+
-+static DEFINE_SPINLOCK(pm_lock);
-+
-+static unsigned long rcosc_get_rate(struct clk *clk)
-+{
-+	return 32768;
-+}
-+
-+static unsigned long osc_get_rate(struct clk *clk)
-+{
-+	return at32_board_osc_rates[clk->index];
-+}
-+
-+static void osc32_mode(struct clk *clk, int enabled)
-+{
-+	/* We never disable the 32 kHz oscillator */
-+	if (!enabled)
-+		return;
-+
-+	/* If it's already running, we're done. */
-+	if (pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY))
-+		return;
-+
-+	/* Enable it, unless someone did it for us already */
-+	if (!(sdc_readl(OSCCTRL32) & SDC_BIT(OSCCTRL32_OSC32EN))) {
-+		u32 value;
-+
-+		value = SDC_BF(OSCCTRL32_STARTUP, 5)
-+			| SDC_BF(OSCCTRL32_MODE, 0xd)
-+			| SDC_BIT(OSCCTRL32_OSC32EN);
-+
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0x55));
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0xaa));
-+	}
-+
-+	pr_info("Waiting for 32 kHz crystal oscillator to start...\n");
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY)))
-+		cpu_relax();
-+}
-+
-+static void oscn_mode(struct clk *clk, int enabled)
-+{
-+	unsigned int	i = clk->index;
-+	u32		mcctrl;
-+
-+	BUG_ON(i > 2);
-+
-+	/* Let's keep oscillators running for now... */
-+	if (!enabled)
-+		goto out;
-+
-+	/* If it's already running, we're done */
-+	if (pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i))
-+		goto out;
-+
-+	/* Enable it, unless someone did it for us already */
-+	mcctrl = pm_readl(MCCTRL);
-+	if (!(mcctrl & (PM_BIT(MCCTRL_OSC0EN) << i))) {
-+		/* TODO: Make OSC startup parameters configurable */
-+		pm_writel(OSCCTRL[i], PM_BF(OSCCTRLx_STARTUP, 5)
-+				| PM_BF(OSCCTRLx_MODE, 0xa));
-+		pm_writel(MCCTRL, mcctrl | (PM_BIT(MCCTRL_OSC0EN) << i));
-+	}
-+
-+	pr_debug("clk %s: waiting for clock to become ready...\n", clk->name);
-+	pr_debug("clk %s: MCCTRL=%08x OSCCTRL%u=%08x\n", clk->name,
-+			pm_readl(MCCTRL), i, pm_readl(OSCCTRL[i]));
-+
-+	while (!(pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i)))
-+		cpu_relax();
-+
-+out:
-+	pr_debug("clk %s: running\n", clk->name);
-+}
-+
-+static struct clk rcosc = {
-+	.name		= "rcosc",
-+	.get_rate	= rcosc_get_rate,
-+	.users		= 1,
-+};
-+static struct clk osc0 = {
-+	.name		= "osc0",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk osc1 = {
-+	.name		= "osc1",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 1,
-+};
-+static struct clk osc2 = {
-+	.name		= "osc2",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 2,
-+};
-+static struct clk osc32 = {
-+	.name		= "osc32k",
-+	.get_rate	= osc_get_rate,
-+	.mode		= osc32_mode,
-+	.index		= 3,
-+};
-+
-+static void pll_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long timeout;
-+	unsigned int index = clk->index;
-+	u32 status;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[index]);
-+
-+	if (enabled) {
-+		if (PM_BFEXT(PLLx_PLLMUL, ctrl) <= 1) {
-+			pr_debug("clk %s: failed to enable, rate not set\n",
-+					clk->name);
-+			return;
-+		}
-+
-+		ctrl |= PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+
-+		pr_debug("clk %s: waiting for lock...\n", clk->name);
-+		for (timeout = 10000; timeout; timeout--) {
-+			status = pm_readl(POSCSR);
-+			if (status & (PM_BIT(POSCSR_LOCK0) << index))
-+				break;
-+			udelay(10);
-+		}
-+
-+		if (!(status & (PM_BIT(POSCSR_LOCK0) << index)))
-+			pr_err("clk %s: timeout waiting for lock\n",
-+					clk->name);
-+		else
-+			pr_debug("clk %s: running\n", clk->name);
-+	} else {
-+		ctrl &= ~PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+		pr_debug("clk %s: stopped\n", clk->name);
-+	}
-+}
-+
-+
-+static unsigned long pll_get_rate(struct clk *clk)
-+{
-+	unsigned long rate;
-+	unsigned int div;
-+	unsigned int mul;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[clk->index]);
-+
-+	div = PM_BFEXT(PLLx_PLLDIV, ctrl);
-+	mul = PM_BFEXT(PLLx_PLLMUL, ctrl);
-+
-+	rate = clk->parent->get_rate(clk->parent);
-+	if (div != 0)
-+		rate = (rate + div / 2) / div;
-+	else
-+		rate = rate * 2;
-+	rate *= mul;
-+
-+	if (ctrl & PM_BF(PLLx_PLLOPT, 4))
-+		rate = (rate + 1) / 2;
-+
-+	return rate;
-+}
-+
-+static long pll_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long mul_best_fit = 0;
-+	unsigned long div;
-+	unsigned long div_min;
-+	unsigned long div_max;
-+	unsigned long div_best_fit = 0;
-+	unsigned long base;
-+	unsigned long fvco;
-+	unsigned long actual = 0;
-+	unsigned long rate_error_prev = ~0UL;
-+	u32 ctrl;
-+
-+	/* Rate must be between 25 MHz and 400 Mhz. */
-+	if (rate < 25000000UL || rate > 400000000UL)
-+		return -EINVAL;
-+
-+	base = clk->parent->get_rate(clk->parent);
-+
-+	/* PLL input frequency must be between 10 MHz and 200 MHz. */
-+	div_min = DIV_ROUND_UP(base, 200000000UL);
-+	div_max = base / 10000000UL;
-+
-+	if (div_max < div_min)
-+		return -EINVAL;
-+
-+	for (div = div_min; div <= div_max; div++) {
-+		unsigned long mul;
-+		unsigned long pll_in;
-+		unsigned long rate_error;
-+
-+		pll_in = (base + div / 2) / div;
-+		mul = (rate + pll_in / 2) / pll_in;
-+
-+		if (mul < 1)
-+			continue;
-+
-+		actual = pll_in * mul;
-+		rate_error = abs(actual - rate);
-+
-+		if (rate_error < rate_error_prev) {
-+			mul_best_fit = mul;
-+			div_best_fit = div;
-+			rate_error_prev = rate_error;
-+		}
-+
-+		if (rate_error == 0)
-+			break;
-+	}
-+
-+	if (div_best_fit == 0)
-+		return -EINVAL;
-+
-+	ctrl = 0;
-+	fvco = actual;
-+
-+	/*
-+	 * MUL=1 is not allowed. So we must double it and set the
-+	 * divide-by-two bit.
-+	 */
-+	if (mul_best_fit == 1) {
-+		ctrl |= PM_BF(PLLx_PLLOPT, 4);
-+		mul_best_fit *= 2;
-+		fvco = actual * 2;
-+	}
-+
-+	if (fvco > 200000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 3);
-+	else if (fvco > 100000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 2);
-+	else if (fvco > 50000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 1);
-+
-+	ctrl |= PM_BF(PLLx_PLLCOUNT, 31);
-+	ctrl |= PM_BF(PLLx_PLLMUL, mul_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLDIV, div_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLOSC, clk->parent->index);
-+
-+	if (apply) {
-+		if (actual != rate)
-+			return -EINVAL;
-+		if (clk->users > 0)
-+			return -EBUSY;
-+		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
-+				clk->name, rate, actual);
-+		pm_writel(PLL[clk->index], ctrl);
-+	}
-+
-+	return actual;
-+}
-+
-+static int pll_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int index = clk->index;
-+	u32 ctrl;
-+
-+	if (clk->users > 0)
-+		return -EBUSY;
-+
-+	ctrl = pm_readl(PLL[index]);
-+	BUG_ON(ctrl & PM_BIT(PLLx_PLLEN));
-+
-+	ctrl = PM_BFINS(PLLx_PLLOSC, parent->index, ctrl);
-+	pm_writel(PLL[index], ctrl);
-+
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+static struct clk pll0 = {
-+	.name		= "pll0",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk pll1 = {
-+	.name		= "pll1",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 1,
-+};
-+static struct clk pll2 = {
-+	.name		= "pll2",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 2,
-+};
-+
-+/*
-+ * The main clock can be either rcosc, osc0 or pll0.  The boot loader
-+ * may have chosen one for us, so we don't really know which one until
-+ * we have a look at the PM registers.
-+ */
-+static struct clk *main_clock;
-+
-+/*
-+ * Synchronous clocks are generated from the main clock. The clocks
-+ * must satisfy the constraint
-+ *   fCPU >= fHSB >= fPB
-+ * i.e. each clock must not be faster than its parent.
-+ */
-+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
-+{
-+	return main_clock->get_rate(main_clock) >> shift;
-+};
-+
-+static void cpu_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(CPUMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(CPUMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long cpu_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_CPUDIV))
-+		shift = PM_BFEXT(CKSEL_CPUSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	u32 control;
-+	unsigned long parent_rate, child_div, actual_rate, div;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(CKSEL);
-+
-+	if (control & PM_BIT(CKSEL_HSBDIV))
-+		child_div = 1 << (PM_BFEXT(CKSEL_HSBSEL, control) + 1);
-+	else
-+		child_div = 1;
-+
-+	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(CKSEL_CPUDIV);
-+	} else {
-+		unsigned int cpusel;
-+		div = (parent_rate + rate / 2) / rate;
-+		if (div > child_div)
-+			div = child_div;
-+		cpusel = (div > 1) ? (fls(div) - 2) : 0;
-+		control = PM_BIT(CKSEL_CPUDIV)
-+			| PM_BFINS(CKSEL_CPUSEL, cpusel, control);
-+		actual_rate = parent_rate / (1 << (cpusel + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply) {
-+		while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_CKRDY)))
-+			cpu_relax();
-+
-+		pm_writel(CKSEL, control);
-+	}
-+
-+	return actual_rate;
-+}
-+
-+static void hsb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(HSBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(HSBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long hsb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_HSBDIV))
-+		shift = PM_BFEXT(CKSEL_HSBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pba_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBAMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBAMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pba_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBADIV))
-+		shift = PM_BFEXT(CKSEL_PBASEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pbb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pbb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBBDIV))
-+		shift = PM_BFEXT(CKSEL_PBBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static struct clk cpu_clk = {
-+	.name		= "cpu",
-+	.get_rate	= cpu_clk_get_rate,
-+	.set_rate	= cpu_clk_set_rate,
-+	.users		= 1,
-+};
-+static struct clk hsb_clk = {
-+	.name		= "hsb",
-+	.parent		= &cpu_clk,
-+	.get_rate	= hsb_clk_get_rate,
-+};
-+static struct clk pba_clk = {
-+	.name		= "pba",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pba_clk_get_rate,
-+	.users		= 1,
-+	.index		= 1,
-+};
-+static struct clk pbb_clk = {
-+	.name		= "pbb",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 2,
-+};
-+static struct clk pbc_clk = {
-+	.name		= "pbc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 3,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  Generic Clocks
-+ * -------------------------------------------------------------------- */
-+
-+/* Mapping from GCCTRL:OSCSEL values to parent clocks */
-+static struct clk *const genclk_parent[] = {
-+	&rcosc,
-+	&osc32,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+};
-+
-+#define NR_GENERIC_CLOCKS	8
-+
-+static void genclk_mode(struct clk *clk, int enabled)
-+{
-+	u32 control;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (enabled)
-+		control |= PM_BIT(GCCTRL_CEN);
-+	else
-+		control &= PM_BIT(GCCTRL_CEN);
-+	pm_writel(GCCTRL[clk->index], control);
-+}
-+
-+static unsigned long genclk_get_rate(struct clk *clk)
-+{
-+	u32 control;
-+	unsigned long div = 1;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (control & PM_BIT(GCCTRL_DIVEN))
-+		div = 2 * (PM_BFEXT(GCCTRL_DIV, control) + 1);
-+
-+	return clk->parent->get_rate(clk->parent) / div;
-+}
-+
-+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long	parent_rate;
-+	unsigned long	actual_rate;
-+	unsigned long	div;
-+	u32		control;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	if (rate > 3 * parent_rate / 4) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(GCCTRL_DIVEN);
-+	} else {
-+		div = (parent_rate + rate) / (2 * rate) - 1;
-+		control = PM_BFINS(GCCTRL_DIV, div, control)
-+				| PM_BIT(GCCTRL_DIVEN);
-+		actual_rate = parent_rate / (2 * (div + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply)
-+		pm_writel(GCCTRL[clk->index], control);
-+
-+	return actual_rate;
-+}
-+
-+static int genclk_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int	i;
-+	u32		control;
-+
-+	pr_debug("clk %s: new parent %s (was %s)\n",
-+			clk->name, parent->name,
-+			clk->parent ? clk->parent->name : "<none>");
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	for (i = 0; i < ARRAY_SIZE(genclk_parent); i++) {
-+		if (parent == genclk_parent[i]) {
-+			control = PM_BFINS(GCCTRL_OSCSEL, i, control);
-+			break;
-+		}
-+	}
-+
-+	if (i >= ARRAY_SIZE(genclk_parent))
-+		return -EINVAL;
-+
-+	pm_writel(GCCTRL[clk->index], control);
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+#define DEFINE_GCLK(_name, i)				\
-+	static struct clk _name = {			\
-+		.name		= #_name,		\
-+		.mode		= genclk_mode,		\
-+		.get_rate	= genclk_get_rate,	\
-+		.set_rate	= genclk_set_rate,	\
-+		.set_parent	= genclk_set_parent,	\
-+		.index		= i,			\
-+	}
-+
-+DEFINE_GCLK(gclk0, 0);
-+DEFINE_GCLK(gclk1, 1);
-+DEFINE_GCLK(gclk2, 2);
-+DEFINE_GCLK(gclk3, 3);
-+DEFINE_GCLK(gclk4, 4);
-+DEFINE_GCLK(gclk5, 5);
-+
-+static void __init genclk_init_parent(struct clk *clk)
-+{
-+	unsigned int	parent;
-+	u32		control;
-+
-+	BUG_ON(clk->index > NR_GENERIC_CLOCKS);
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	parent = PM_BFEXT(GCCTRL_OSCSEL, control);
-+	if (parent >= ARRAY_SIZE(genclk_parent)) {
-+		/* Current parent is invalid. Reset to a sane value */
-+		parent = 0;
-+		control = PM_BF(GCCTRL_OSCSEL, parent);
-+	}
-+
-+	clk->parent = genclk_parent[parent];
-+}
-+
-+
-+/* --------------------------------------------------------------------
-+ *  System peripherals
-+ * -------------------------------------------------------------------- */
-+static struct dw_dma_platform_data dw_dmac0_data = {
-+	.nr_channels	= 4,
-+};
-+static struct pdca_pdata pdca_data = {
-+	.nr_channels	= 20,
-+};
-+
-+static struct resource intc_resource[] = {
-+	PBMEM(0xffd00000),
-+};
-+static struct resource pm_resource[] = {
-+	PBMEM(0xffd00400),
-+	IRQ(10),
-+};
-+static struct resource sdc_resource[] = {
-+	PBMEM(0xffd00800),
-+	IRQ(45),
-+};
-+static struct resource ast0_resource[] = {
-+	PBMEM(0xffd00c00),
-+	IRQ(11),
-+};
-+static struct resource ast1_resource[] = {
-+	PBMEM(0xffd01000),
-+	IRQ(12),
-+};
-+static struct resource wdt_resource[] = {
-+	PBMEM(0xffd01400),
-+};
-+static struct resource gpio_resource[] = {
-+	PBMEM(0xffd02000),
-+	{
-+		.start	= 16,
-+		.end	= 19,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+static struct resource pdca_resource[] = {
-+	{
-+		.start	= 0xffe00000,
-+		.end	= 0xffe01fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(1),
-+};
-+static struct resource smc_resource[] = {
-+	PBMEM(0xffe04400),
-+};
-+static struct resource dw_dmac0_resource[] = {
-+	{
-+		.start	= 0xff100000,
-+		.end	= 0xff1003ff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(5),
-+};
-+
-+struct platform_device at32_intc0_device = {
-+	.name		= "intc",
-+	.resource	= intc_resource,
-+	.num_resources	= ARRAY_SIZE(intc_resource),
-+};
-+static struct platform_device pm_device = {
-+	.name		= "pm",
-+	.resource	= pm_resource,
-+	.num_resources	= ARRAY_SIZE(pm_resource),
-+};
-+static struct platform_device sdc_device = {
-+	.name		= "sdc",
-+	.resource	= sdc_resource,
-+	.num_resources	= ARRAY_SIZE(sdc_resource),
-+};
-+static struct platform_device ast0_device = {
-+	.name		= "rtc-ast",
-+	.id		= 0,
-+	.resource	= ast0_resource,
-+	.num_resources	= ARRAY_SIZE(ast0_resource),
-+};
-+static struct platform_device ast1_device = {
-+	.name		= "timer-ast",
-+	.id		= 1,
-+	.resource	= ast1_resource,
-+	.num_resources	= ARRAY_SIZE(ast1_resource),
-+};
-+static struct platform_device wdt_device = {
-+	.name		= "at32_wdt",
-+	.id		= 0,
-+	.resource	= wdt_resource,
-+	.num_resources	= ARRAY_SIZE(wdt_resource),
-+};
-+static struct platform_device gpio_device = {
-+	.name		= "gpio",
-+	.id		= 0,
-+	.resource	= gpio_resource,
-+	.num_resources	= ARRAY_SIZE(gpio_resource),
-+};
-+static struct platform_device pdca_device = {
-+	.dev.platform_data = &pdca_data,
-+	.name		= "atmel_pdca",
-+	.id		= 0,
-+	.resource	= pdca_resource,
-+	.num_resources	= ARRAY_SIZE(pdca_resource),
-+};
-+static struct platform_device smc_device = {
-+	.name		= "smc",
-+	.id		= 0,
-+	.resource	= smc_resource,
-+	.num_resources	= ARRAY_SIZE(smc_resource),
-+};
-+static struct platform_device dw_dmac0_device = {
-+	.dev.platform_data = &dw_dmac0_data,
-+	.name		= "dw_dmac",
-+	.id		= 0,
-+	.resource	= dw_dmac0_resource,
-+	.num_resources	= ARRAY_SIZE(dw_dmac0_resource),
-+};
-+
-+DEV_CLK(pclk, at32_intc0, pba, 0);
-+DEV_CLK(pclk, pm, pba, 1);
-+DEV_CLK(pclk, sdc, pba, 2);
-+DEV_CLK(pclk, ast0, pba, 3);
-+DEV_CLK(pclk, ast1, pba, 4);
-+DEV_CLK(pclk, wdt, pba, 5);
-+DEV_CLK(pclk, gpio, pba, 8);
-+DEV_CLK(hclk, pdca, hsb, 9);
-+DEV_CLK(pclk, pdca, pbb, 0);
-+DEV_CLK(pclk, smc, pbb, 5);
-+DEV_CLK(hclk, dw_dmac0, hsb, 10);
-+
-+static struct clk ebi_hclk = {
-+	.name		= "ebi_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+};
-+static struct clk hramc_clk = {
-+	.name		= "hramc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 4,
-+};
-+static struct clk sdramc_clk = {
-+	.name		= "sdramc_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 6,
-+};
-+
-+static int __init system_device_init(void)
-+{
-+	platform_device_register(&at32_intc0_device);
-+	platform_device_register(&pm_device);
-+	platform_device_register(&sdc_device);
-+	platform_device_register(&ast0_device);
-+	platform_device_register(&ast1_device);
-+	platform_device_register(&wdt_device);
-+	platform_device_register(&gpio_device);
-+	platform_device_register(&pdca_device);
-+	platform_device_register(&smc_device);
-+	platform_device_register(&dw_dmac0_device);
-+
-+	return 0;
-+}
-+core_initcall(system_device_init);
-+
-+/* --------------------------------------------------------------------
-+ * HMATRIX
-+ * -------------------------------------------------------------------- */
-+
-+struct clk at32_hmatrix_clk = {
-+	.name		= "hmatrix_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 8,
-+	.users		= 0,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  USART
-+ * -------------------------------------------------------------------- */
-+
-+static struct atmel_uart_data atmel_usart0_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart0_resource[] = {
-+	PBMEM(0xffd03000),
-+	IRQ(24),
-+};
-+static struct platform_device atmel_usart0_device = {
-+	.name		= "atmel_usart",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data	= &atmel_usart0_data,
-+	},
-+	.resource	= atmel_usart0_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart0_resource),
-+};
-+DEV_CLK(usart, atmel_usart0, pba, 9);
-+
-+static struct atmel_uart_data atmel_usart1_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart1_resource[] = {
-+	PBMEM(0xffd03400),
-+	IRQ(25),
-+};
-+static struct platform_device atmel_usart1_device = {
-+	.name		= "atmel_usart",
-+	.id		= 1,
-+	.dev		= {
-+		.platform_data	= &atmel_usart1_data,
-+	},
-+	.resource	= atmel_usart1_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart1_resource),
-+};
-+DEV_CLK(usart, atmel_usart1, pba, 10);
-+
-+static struct atmel_uart_data atmel_usart2_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart2_resource[] = {
-+	PBMEM(0xffd03800),
-+	IRQ(26),
-+};
-+static struct platform_device atmel_usart2_device = {
-+	.name		= "atmel_usart",
-+	.id		= 2,
-+	.dev		= {
-+		.platform_data	= &atmel_usart2_data,
-+	},
-+	.resource	= atmel_usart2_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart2_resource),
-+};
-+DEV_CLK(usart, atmel_usart2, pba, 11);
-+
-+static struct atmel_uart_data atmel_usart3_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart3_resource[] = {
-+	PBMEM(0xffd03c00),
-+	IRQ(27),
-+};
-+static struct platform_device atmel_usart3_device = {
-+	.name		= "atmel_usart",
-+	.id		= 3,
-+	.dev		= {
-+		.platform_data	= &atmel_usart3_data,
-+	},
-+	.resource	= atmel_usart3_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart3_resource),
-+};
-+DEV_CLK(usart, atmel_usart3, pba, 12);
-+
-+static struct atmel_uart_data atmel_usart4_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart4_resource[] = {
-+	PBMEM(0xffd04000),
-+	IRQ(28),
-+};
-+static struct platform_device atmel_usart4_device = {
-+	.name		= "atmel_usart",
-+	.id		= 4,
-+	.dev		= {
-+		.platform_data	= &atmel_usart4_data,
-+	},
-+	.resource	= atmel_usart4_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart4_resource),
-+};
-+DEV_CLK(usart, atmel_usart4, pba, 13);
-+
-+static struct atmel_uart_data atmel_usart5_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart5_resource[] = {
-+	PBMEM(0xffd04400),
-+	IRQ(29),
-+};
-+static struct platform_device atmel_usart5_device = {
-+	.name		= "atmel_usart",
-+	.id		= 5,
-+	.dev		= {
-+		.platform_data	= &atmel_usart5_data,
-+	},
-+	.resource	= atmel_usart5_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart5_resource),
-+};
-+DEV_CLK(usart, atmel_usart5, pba, 14);
-+
-+static void __init configure_usart0_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PB, (1 << 14) | (1 << 15), PERIPH_B, 0);
-+}
-+
-+static void __init configure_usart1_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 8) | (1 << 9), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart2_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 16) | (1 << 17), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart3_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PC, (1 << 10) | (1 << 11), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart4_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 14) | (1 << 15), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart5_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PA, (1 << 22) | (1 << 23), PERIPH_A, 0);
-+}
-+
-+static struct platform_device *__initdata at32_usarts[6];
-+
-+void __init at32_map_usart(unsigned int hw_id, unsigned int line)
-+{
-+	struct platform_device *pdev;
-+
-+	switch (hw_id) {
-+	case 0:
-+		pdev = &atmel_usart0_device;
-+		configure_usart0_pins();
-+		break;
-+	case 1:
-+		pdev = &atmel_usart1_device;
-+		configure_usart1_pins();
-+		break;
-+	case 2:
-+		pdev = &atmel_usart2_device;
-+		configure_usart2_pins();
-+		break;
-+	case 3:
-+		pdev = &atmel_usart3_device;
-+		configure_usart3_pins();
-+		break;
-+	case 4:
-+		pdev = &atmel_usart4_device;
-+		configure_usart4_pins();
-+		break;
-+	case 5:
-+		pdev = &atmel_usart5_device;
-+		configure_usart5_pins();
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	if (PXSEG(pdev->resource[0].start) == P4SEG) {
-+		/* Addresses in the P4 segment are permanently mapped 1:1 */
-+		struct atmel_uart_data *data = pdev->dev.platform_data;
-+		data->regs = (void __iomem __force *)pdev->resource[0].start;
-+	}
-+
-+	pdev->id = line;
-+	at32_usarts[line] = pdev;
-+}
-+
-+struct platform_device *__init at32_add_device_usart(unsigned int id)
-+{
-+	platform_device_register(at32_usarts[id]);
-+	return at32_usarts[id];
-+}
-+
-+struct platform_device *atmel_default_console_device;
-+
-+void __init at32_setup_serial_console(unsigned int usart_id)
-+{
-+	atmel_default_console_device = at32_usarts[usart_id];
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Ethernet
-+ * -------------------------------------------------------------------- */
-+
-+static u64 macb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource macb0_resource[] __initdata = {
-+	PBMEM(0xffe04000),
-+	IRQ(8),
-+};
-+static struct clk macb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 8,
-+};
-+static struct clk macb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 4,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
-+{
-+	struct platform_device *pdev;
-+	u32 pin_mask_a;
-+	u32 pin_mask_c;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("macb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	if (platform_device_add_resources(pdev, macb0_resource,
-+				ARRAY_SIZE(macb0_resource)))
-+		goto out_free_pdev;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct eth_platform_data)))
-+		goto out_free_pdev;
-+
-+	pin_mask_a  = (1 << 4);  /* RXDV */
-+	pin_mask_c  = (1 << 10); /* MDC  */
-+	pin_mask_c |= (1 << 11); /* MDIO */
-+	pin_mask_c |= (1 << 12); /* TXCK */
-+	pin_mask_c |= (1 << 14); /* RXD0 */
-+	pin_mask_c |= (1 << 15); /* RXD1 */
-+	pin_mask_c |= (1 << 16); /* RXER */
-+	pin_mask_c |= (1 << 18); /* TXEN */
-+	pin_mask_c |= (1 << 19); /* TXD0 */
-+	pin_mask_c |= (1 << 20); /* TXD1 */
-+
-+	if (!data->is_rmii) {
-+		pin_mask_a |= (1<<0);  /* COL  */
-+		pin_mask_a |= (1<<1);  /* RXD2 */
-+		pin_mask_a |= (1<<2);  /* RXD3 */
-+		pin_mask_a |= (1<<3);  /* RXCK */
-+		pin_mask_a |= (1<<5);  /* TXER */
-+		pin_mask_a |= (1<<6);  /* TXD2 */
-+		pin_mask_a |= (1<<7);  /* TXD3 */
-+		pin_mask_c |= (1<<13); /* CRS  */
-+		pin_mask_c |= (1<<17); /* SPD  */
-+	}
-+
-+	select_peripheral(PA, pin_mask_a, PERIPH_B, 0);
-+	select_peripheral(PC, pin_mask_c, PERIPH_C, 0);
-+
-+	pdev->dev.dma_mask = &macb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	macb0_hclk.dev = &pdev->dev;
-+	macb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+out_free_pdev:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * SPI
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_spi_resource[][2] __initdata = {
-+	{
-+		PBMEM(0xffe05400),
-+		IRQ(36),
-+	}, {
-+		PBMEM(0xffe05800),
-+		IRQ(37),
-+	}, {
-+		PBMEM(0xffe05c00),
-+		IRQ(38),
-+	}, {
-+		PBMEM(0xffe06000),
-+		IRQ(39),
-+	}
-+};
-+static struct clk atmel_spi_clk[] = {
-+	{
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 9,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 10,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 11,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 12,
-+	}
-+};
-+static int __initdata atmel_spi_pins[][4] = {
-+	{
-+		/* SPI0 */
-+		GPIO_PIN_PB(3), GPIO_PIN_PB(4),
-+		GPIO_PIN_PB(5), GPIO_PIN_PB(6),
-+	}, {
-+		/* SPI1 */
-+		GPIO_PIN_PB(4), -1, -1, -1,
-+	}, {
-+		/* SPI2 */
-+		GPIO_PIN_PA(28), -1, -1, -1,
-+	}, {
-+		/* SPI3 */
-+		GPIO_PIN_PA(27), GPIO_PIN_PA(20),
-+		GPIO_PIN_PA(29), GPIO_PIN_PA(30),
-+	}
-+};
-+
-+
-+static void __init at32_spi_setup_dw_dma(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct dw_dma_slave	*rx_dws;
-+	struct dw_dma_slave	*tx_dws;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_dws = kmemdup(to_dw_dma_slave(pdata->rx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		rx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_dws = kmemdup(to_dw_dma_slave(pdata->tx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		tx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	rx_dws->slave.dma_dev = tx_dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	rx_dws->slave.reg_width = tx_dws->slave.reg_width
-+		= DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_dws->cfg_hi = DWC_CFGH_SRC_PER(2);
-+	tx_dws->cfg_hi = DWC_CFGH_DST_PER(3);
-+	rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+	tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	pdata->rx_dma_slave = &rx_dws->slave;
-+	pdata->tx_dma_slave = &tx_dws->slave;
-+}
-+
-+static void __init at32_spi_setup_pdca(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct pdca_slave	*rx_pslave;
-+	struct pdca_slave	*tx_pslave;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_pslave = kmemdup(dma_to_pdca_slave(pdata->rx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		rx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_pslave = kmemdup(dma_to_pdca_slave(pdata->tx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		tx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+
-+	rx_pslave->slave.dma_dev = &pdca_device.dev;
-+	tx_pslave->slave.dma_dev = &pdca_device.dev;
-+	rx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+	tx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_pslave->tx_periph_id = -1;
-+	tx_pslave->rx_periph_id = -1;
-+
-+	switch (id) {
-+	case 1:
-+		rx_pslave->rx_periph_id = 6;
-+		tx_pslave->tx_periph_id = 17;
-+		break;
-+	case 2:
-+		rx_pslave->rx_periph_id = 7;
-+		tx_pslave->tx_periph_id = 18;
-+		break;
-+	case 3:
-+		rx_pslave->rx_periph_id = 8;
-+		tx_pslave->tx_periph_id = 19;
-+		break;
-+	}
-+
-+	pdata->rx_dma_slave = &rx_pslave->slave;
-+	pdata->tx_dma_slave = &tx_pslave->slave;
-+}
-+
-+static void __init
-+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-+		unsigned int n, const int *pins)
-+{
-+	unsigned int	mode;
-+	unsigned int	cs;
-+	int		pin;
-+
-+	for (; n; n--, b++) {
-+		b->bus_num = bus_num;
-+		cs = b->chip_select;
-+		if (cs >= 4 || !gpio_is_valid(pins[cs]))
-+			continue;
-+
-+		pin = (int)b->controller_data;
-+		if (!pin || !gpio_is_valid(pin)) {
-+			pin = pins[cs];
-+			b->controller_data = (void *)pin;
-+		}
-+
-+		mode = AT32_GPIOF_OUTPUT;
-+		if (!(b->mode & SPI_CS_HIGH))
-+			mode |= AT32_GPIOF_HIGH;
-+		at32_select_gpio(pin, mode);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_spi(unsigned int id,
-+		struct spi_board_info *b, unsigned int n)
-+{
-+	struct atmel_spi_pdata	pdata;
-+	struct platform_device	*pdev;
-+
-+	BUILD_BUG_ON(ARRAY_SIZE(atmel_spi_resource)
-+			!= ARRAY_SIZE(atmel_spi_clk));
-+
-+	if (id >= ARRAY_SIZE(atmel_spi_resource))
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_spi", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_spi_resource[id],
-+				ARRAY_SIZE(atmel_spi_resource[id])))
-+		goto fail;
-+
-+	memset(&pdata, 0, sizeof(struct atmel_spi_pdata));
-+
-+	if (id == 0)
-+		at32_spi_setup_dw_dma(id, &pdata);
-+	else
-+		at32_spi_setup_pdca(id, &pdata);
-+	pdata.rx_dma_slave->dev = pdata.tx_dma_slave->dev = &pdev->dev;
-+
-+	if (platform_device_add_data(pdev, &pdata,
-+				sizeof(struct atmel_spi_pdata)))
-+		goto fail;
-+
-+	switch (id) {
-+	case 0:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 1), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 0) | (1 << 2), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(0, b, n, atmel_spi_pins[0]);
-+		break;
-+
-+	case 1:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 7), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 6) | (1 << 5), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(1, b, n, atmel_spi_pins[1]);
-+		break;
-+
-+	case 2:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 30), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 31) || (1 << 29), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(2, b, n, atmel_spi_pins[2]);
-+		break;
-+
-+	case 3:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 25), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 24) | (1 << 26), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(3, b, n, atmel_spi_pins[3]);
-+		break;
-+
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_spi_clk[id].dev = &pdev->dev;
-+	spi_register_board_info(b, n);
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * MMC
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_mci0_resource[] __initdata = {
-+	PBMEM(0xfff00000),
-+	IRQ(43),
-+};
-+/* MCI is on the PBC bus, but it is controlled by the PBBMASK register */
-+static struct clk atmel_mci0_pclk = {
-+	.name		= "mci_clk",
-+	.parent		= &pbc_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 16,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
-+{
-+	struct platform_device		*pdev;
-+	struct dw_dma_slave		*dws;
-+	u32 pin_mask_1 = 0;
-+	u32 pin_mask_2 = 0;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	/* Must have at least one usable slot */
-+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mci", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_mci0_resource,
-+				ARRAY_SIZE(atmel_mci0_resource)))
-+		goto fail;
-+
-+	if (data->dma_slave)
-+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	dws->slave.dev = &pdev->dev;
-+	dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
-+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
-+				| DWC_CFGH_DST_PER(1));
-+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	data->dma_slave = &dws->slave;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct mci_platform_data)))
-+		goto fail;
-+
-+	switch (data->slot[0].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 20); /* DATA4 */
-+		pin_mask_1 |= (1 << 21); /* DATA5 */
-+		pin_mask_1 |= (1 << 22); /* DATA6 */
-+		pin_mask_1 |= (1 << 23); /* DATA7 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_2 |= (1 << 19); /* DATA1 */
-+		pin_mask_2 |= (1 << 20); /* DATA2 */
-+		pin_mask_2 |= (1 << 21); /* DATA3 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_2 |= (1 << 18); /* DATA0 */
-+		pin_mask_2 |= (1 << 17); /* CMD   */
-+
-+		select_peripheral(PA, pin_mask_1, PERIPH_D, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, pin_mask_2, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, (1 << 16),  PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[0].detect_pin))
-+			at32_select_gpio(data->slot[0].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[0].wp_pin))
-+			at32_select_gpio(data->slot[0].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	pin_mask_1 = 0;
-+
-+	switch (data->slot[1].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 9); /* DATA7 */
-+		pin_mask_1 |= (1 << 8); /* DATA6 */
-+		pin_mask_1 |= (1 << 7); /* DATA5 */
-+		pin_mask_1 |= (1 << 6); /* DATA4 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_1 |= (1 << 5); /* DATA3 */
-+		pin_mask_1 |= (1 << 4); /* DATA2 */
-+		pin_mask_1 |= (1 << 3); /* DATA1 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_1 |= (1 << 2); /* DATA0 */
-+		pin_mask_1 |= (1 << 1); /* CMD   */
-+
-+		select_peripheral(PC, pin_mask_1, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PC, (1 << 0),   PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[1].detect_pin))
-+			at32_select_gpio(data->slot[1].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[1].wp_pin))
-+			at32_select_gpio(data->slot[1].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_mci0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  LCDC
-+ * -------------------------------------------------------------------- */
-+static u64 atmel_lcdfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_lcdfb0_resource[] __initdata = {
-+	{
-+		.start	= 0xff000000,
-+		.end	= 0xff000fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(3),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_lcdfb0_hck1 = {
-+	.name		= "hck1",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 7,
-+};
-+static struct clk atmel_lcdfb0_pixclk = {
-+	.name		= "lcdc_clk",
-+	.mode		= genclk_mode,
-+	.get_rate	= genclk_get_rate,
-+	.set_rate	= genclk_set_rate,
-+	.set_parent	= genclk_set_parent,
-+	.index		= 6,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-+		unsigned long fbmem_start, unsigned long fbmem_len,
-+		u64 pin_mask)
-+{
-+	struct {
-+		struct atmel_lcdfb_info	info;
-+		struct fb_monspecs	monspecs;
-+		struct fb_videomode	modedb[0];
-+	} *all_data;
-+	struct platform_device	*pdev;
-+	unsigned int		data_size;
-+	unsigned int		modedb_size;
-+	unsigned int		num_resources;
-+	int			ret;
-+
-+	if (id > 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_lcdfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_lcdfb0_resource);
-+	if (fbmem_len) {
-+		atmel_lcdfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_lcdfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+
-+	if (platform_device_add_resources(pdev, atmel_lcdfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	/*
-+	 * Allocate all data -- info struct, monspecs and modedb -- in
-+	 * a single chunk.
-+	 */
-+	modedb_size = data->default_monspecs->modedb_len
-+			* sizeof(struct fb_videomode);
-+	data_size = sizeof(*all_data) + modedb_size;
-+	all_data = kmalloc(data_size, GFP_KERNEL);
-+	if (!all_data)
-+		goto error;
-+
-+	memcpy(&all_data->info, data, sizeof(struct atmel_lcdfb_info));
-+	memcpy(&all_data->monspecs, data->default_monspecs,
-+			sizeof(struct fb_monspecs));
-+	memcpy(&all_data->modedb, data->default_monspecs->modedb, modedb_size);
-+
-+	ret = platform_device_add_data(pdev, all_data, data_size);
-+	kfree(all_data);
-+	if (ret)
-+		goto error;
-+
-+	/*
-+	 * Update internal pointers to use memory allocated by
-+	 * platform_device_add_data().
-+	 */
-+	all_data = pdev->dev.platform_data;
-+	all_data->info.default_monspecs = &all_data->monspecs;
-+	all_data->monspecs.modedb = all_data->modedb;
-+
-+	select_peripheral(PD, 0x7fffffff,  PERIPH_A, 0);
-+
-+	pdev->dev.dma_mask = &atmel_lcdfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_lcdfb0_hck1.dev = &pdev->dev;
-+	atmel_lcdfb0_pixclk.dev = &pdev->dev;
-+
-+	clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
-+	clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Media Post-Processor (MPOP)
-+ * -------------------------------------------------------------------- */
-+
-+static u64 atmel_mpopfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_mpopfb0_resource[] = {
-+	{
-+		/* Configuration interface */
-+		.start	= 0xffe02000,
-+		.end	= 0xffe02fff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		/* Data interface (output) */
-+		.start	= 0xf0000000,
-+		.end	= 0xf0ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(4),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_mpopfb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 12,
-+};
-+static struct clk atmel_mpopfb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 2,
-+};
-+
-+struct platform_device *__init at32_add_device_mpop(unsigned int id,
-+		struct platform_device *lcdc_pdev,
-+		unsigned long fbmem_start, unsigned long fbmem_len)
-+{
-+	struct platform_device		*pdev;
-+	struct atmel_mpopfb_info	info;
-+	unsigned int			num_resources;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mpopfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_mpopfb0_resource);
-+	if (fbmem_len) {
-+		atmel_mpopfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_mpopfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+	if (platform_device_add_resources(pdev, atmel_mpopfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	info.lcdc_pdev = lcdc_pdev;
-+	if (platform_device_add_data(pdev, &info, sizeof(info)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &atmel_mpopfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_mpopfb0_hclk.dev = &pdev->dev;
-+	atmel_mpopfb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  USB Host (OHCI/EHCI)
-+ * ------------------------------------------------------------------- */
-+
-+static u64 usbh_dma_mask = DMA_32BIT_MASK;
-+
-+static unsigned long parent_clk_get_rate(struct clk *clk)
-+{
-+	return clk->parent->get_rate(clk->parent);
-+}
-+
-+static void parent_clk_mode(struct clk *clk, int enabled)
-+{
-+	/* Parent clk enabled by clk core */
-+}
-+
-+/*
-+ * The UTMI clock is an internally controlled PLL. It is hardwired to
-+ * OSC2 and will run at 30 MHz or 60 MHz depending on the internal
-+ * UTMI <-> host controller data bus width.
-+ *
-+ * We can turn it on and off through the Power Manager. That's all.
-+ */
-+static void utmi_clk_mode(struct clk *clk, int enabled)
-+{
-+	u32 ppcr = pm_readl(PPCR);
-+
-+	if (enabled)
-+		/* Clear UTMI suspend signal */
-+		ppcr |= PM_BIT(PPCR_UTMI_CTRL);
-+	else
-+		/* Set UTMI suspend signal */
-+		ppcr &= ~PM_BIT(PPCR_UTMI_CTRL);
-+
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0x55));
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0xaa));
-+
-+	if (enabled)
-+		/* PLL startup time is 2.5 ms */
-+		udelay(2500);
-+}
-+
-+static unsigned long utmi_clk_get_rate(struct clk *clk)
-+{
-+	/*
-+	 * Not sure about this, but I think the UTMI interface on
-+	 * AP7200 is 16 bits wide, which means 30 MHz PHY clock.
-+	 */
-+	return 30000000;
-+}
-+
-+static struct clk usbh_utmi_clk = {
-+	.name		= "usbh_utmi_clk",
-+	.parent		= &osc2,
-+	.mode		= utmi_clk_mode,
-+	.get_rate	= utmi_clk_get_rate,
-+};
-+
-+static struct clk usbh_hclk = {
-+	.name		= "usbh_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 6,
-+};
-+
-+/*
-+ * UTMI and HSB clocks are shared between OHCI and EHCI. These wrappers
-+ * make sure both can use the clocks as if they had their own.
-+ */
-+static struct clk ohci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ohci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct clk ehci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ehci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+/*
-+ * The USBH needs both a 48 MHz and a 12 MHz clock, and the 12 MHz
-+ * must be generated by dividing the 48 MHz clock. There's only one
-+ * generic clock hooked up to the USBH which we must use to generate
-+ * both.
-+ *
-+ * This can be done because GCLK0 generates an additional "divided
-+ * clock", which is the normal clock output further divided by four
-+ * (this is hardcoded, but not surprisingly, exactly what we need.)
-+ *
-+ * So we generate the clocks as follows:
-+ *    OSC2 (12 MHz) -> PLL2 (48 MHz) --> GCLK0 undivided (48 MHz)
-+ *                                   |-> GCLK0 divided (12 MHz)
-+ *
-+ * This clock is only used by the OHCI part of the controller, not the
-+ * EHCI part.
-+ */
-+static struct clk ohci_gclk = {
-+	.name		= "ohci_clk",
-+	.parent		= &gclk0,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct resource usbh_ohci_resource[] __initdata = {
-+	{
-+		.start	= 0xff400000,
-+		.end	= 0xff400400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static struct resource usbh_ehci_resource[] __initdata = {
-+	{
-+		.start	= 0xff300000,
-+		.end	= 0xff300400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static void __init usbh_setup_pins(void)
-+{
-+	static bool already_done __initdata;
-+
-+	if (!already_done) {
-+		already_done = true;
-+		/* OC_EN_N | OC_FLAG_N */
-+		select_peripheral(PA, (1 << 18) | (1 << 19), PERIPH_D, 0);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_ohci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ohci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ohci_resource,
-+				ARRAY_SIZE(usbh_ohci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	clk_set_parent(&pll2, &osc2);
-+	if (clk_round_rate(&pll2, 48000000) != 48000000) {
-+		pr_debug("USBH OHCI: Cannot generate 48 MHz clock\n");
-+		goto error;
-+	}
-+	clk_set_rate(&pll2, 48000000);
-+
-+	clk_set_parent(&gclk0, &pll2);
-+	clk_set_rate(&gclk0, 48000000);
-+
-+	ohci_utmi_clk.dev = &pdev->dev;
-+	ohci_hclk.dev = &pdev->dev;
-+	ohci_gclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+struct platform_device *__init at32_add_device_ehci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ehci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ehci_resource,
-+				ARRAY_SIZE(usbh_ehci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	ehci_utmi_clk.dev = &pdev->dev;
-+	ehci_hclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  NAND Flash / SmartMedia
-+ * ------------------------------------------------------------------- */
-+static struct resource smc_cs3_resource[] __initdata = {
-+	{
-+		.start	= 0x24000000,
-+		.end	= 0x27ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		.start	= 0xffe04c00,
-+		.end	= 0xffe04fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+struct platform_device *__init
-+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_nand", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, smc_cs3_resource,
-+				ARRAY_SIZE(smc_cs3_resource)))
-+		goto error;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct atmel_nand_data)))
-+		goto error;
-+
-+	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
-+
-+	/* NANDOE | NANDWE */
-+	select_peripheral(PF, (1 << 0) | (1 << 1), PERIPH_A, 0);
-+
-+	if (gpio_is_valid(data->enable_pin))
-+		at32_select_gpio(data->enable_pin,
-+				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	if (gpio_is_valid(data->det_pin))
-+		at32_select_gpio(data->det_pin, 0);
-+	if (gpio_is_valid(data->rdy_pin))
-+		at32_select_gpio(data->rdy_pin, 0);
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ * Clock list
-+ * ------------------------------------------------------------------- */
-+static __initdata struct clk *init_clocks[] = {
-+	&rcosc,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&osc32,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+	&pbc_clk,
-+	&gclk0,
-+	&gclk1,
-+	&gclk2,
-+	&gclk3,
-+	&gclk4,
-+	&gclk5,
-+	&at32_intc0_pclk,
-+	&pm_pclk,
-+	&sdc_pclk,
-+	&ast0_pclk,
-+	&ast1_pclk,
-+	&wdt_pclk,
-+	&gpio_pclk,
-+	&pdca_hclk,
-+	&pdca_pclk,
-+	&ebi_hclk,
-+	&hramc_clk,
-+	&smc_pclk,
-+	&sdramc_clk,
-+	&dw_dmac0_hclk,
-+	&atmel_usart0_usart,
-+	&atmel_usart1_usart,
-+	&atmel_usart2_usart,
-+	&atmel_usart3_usart,
-+	&atmel_usart4_usart,
-+	&atmel_usart5_usart,
-+	&atmel_spi_clk[0],
-+	&atmel_spi_clk[1],
-+	&atmel_spi_clk[2],
-+	&atmel_spi_clk[3],
-+	&macb0_hclk,
-+	&macb0_pclk,
-+	&atmel_mci0_pclk,
-+	&atmel_lcdfb0_hck1,
-+	&atmel_lcdfb0_pixclk,
-+	&atmel_mpopfb0_hclk,
-+	&atmel_mpopfb0_pclk,
-+	&usbh_utmi_clk,
-+	&usbh_hclk,
-+	&ohci_utmi_clk,
-+	&ohci_hclk,
-+	&ohci_gclk,
-+	&ehci_utmi_clk,
-+	&ehci_hclk,
-+};
-+
-+static void pll_init_parent(struct clk *pll)
-+{
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[pll->index]);
-+	switch (PM_BFEXT(PLLx_PLLOSC, ctrl)) {
-+	case 0:
-+		pll->parent = &osc0;
-+		break;
-+	case 1:
-+		pll->parent = &osc1;
-+		break;
-+	case 2:
-+		pll->parent = &osc2;
-+		break;
-+	}
-+}
-+
-+static void ap7200_power_off(void)
-+{
-+	/*
-+	 * Clear all wakeup events so that we don't wake up
-+	 * immediately after we shut down.
-+	 */
-+	sdc_writel(ECR, ~0UL);
-+	sdc_readl(STATUS);
-+	asm volatile("sleep %0; sub pc, -2"
-+			:: "i"(CPU_SLEEP_SHUTDOWN)
-+			: "memory");
-+}
-+
-+void __init setup_platform(void)
-+{
-+	unsigned int	i;
-+	u32		cpu_mask;
-+	u32		hsb_mask;
-+	u32		pba_mask;
-+	u32		pbb_mask;
-+
-+	switch (PM_BFEXT(MCCTRL_MCSEL, pm_readl(MCCTRL))) {
-+	case 0:
-+		main_clock = &rcosc;
-+		break;
-+	case 1:
-+		main_clock = &osc0;
-+		break;
-+	case 2:
-+		main_clock = &pll0;
-+		break;
-+	}
-+
-+	cpu_clk.parent = main_clock;
-+
-+	pll_init_parent(&pll0);
-+	pll_init_parent(&pll1);
-+	pll_init_parent(&pll2);
-+
-+	genclk_init_parent(&gclk0);
-+	genclk_init_parent(&gclk1);
-+	genclk_init_parent(&gclk2);
-+	genclk_init_parent(&gclk3);
-+	genclk_init_parent(&gclk4);
-+	genclk_init_parent(&gclk5);
-+	genclk_init_parent(&atmel_lcdfb0_pixclk);
-+
-+	/*
-+	 * Turn on all clocks that have at least one user already, and
-+	 * turn off everything else. We only do this for module
-+	 * clocks, and even though it isn't particularly pretty to
-+	 * check the address of the mode function, it should do the
-+	 * trick...
-+	 */
-+	cpu_mask = 0x10003;
-+	hsb_mask = pba_mask = pbb_mask = 0;
-+
-+	/* Make sure we don't disable the power manager or the SDRAM */
-+	pm_pclk.users = 1;
-+	pm_pclk.parent->users = 1;
-+	ebi_hclk.users = 1;
-+
-+	/* Can't recursively call clk_enable() from any of the clk ops */
-+	sdc_pclk.users = 1;
-+
-+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
-+		struct clk *clk = init_clocks[i];
-+
-+		/* first, register clock */
-+		at32_clk_register(clk);
-+
-+		if (clk->users == 0)
-+			continue;
-+
-+		if (clk->mode == &cpu_clk_mode)
-+			cpu_mask |= 1 << clk->index;
-+		else if (clk->mode == &hsb_clk_mode)
-+			hsb_mask |= 1 << clk->index;
-+		else if (clk->mode == &pba_clk_mode)
-+			pba_mask |= 1 << clk->index;
-+		else if (clk->mode == &pbb_clk_mode)
-+			pbb_mask |= 1 << clk->index;
-+	}
-+
-+	pm_writel(CPUMASK, cpu_mask);
-+	pm_writel(HSBMASK, hsb_mask);
-+	pm_writel(PBAMASK, pba_mask);
-+	pm_writel(PBBMASK, pbb_mask);
-+
-+	at32_gpio_init(&gpio_device);
-+
-+	/* Enter shutdown mode when powering off. This happens very
-+	 * early, so board code may still override this. */
-+	pm_power_off = ap7200_power_off;
-+
-+	/* Enable WAKE pin */
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0x55));
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0xaa));
-+}
-+
-+void __init platform_time_init(void)
-+{
-+	ast_time_init(&ast1_device, AST_CLOCK_PB);
-+}
-+
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
-+struct gen_pool *sram_pool;
-+
-+static int __init sram_init(void)
-+{
-+	struct gen_pool *pool;
-+
-+	/* 1KiB granularity */
-+	pool = gen_pool_create(10, -1);
-+	if (!pool)
-+		goto fail;
-+
-+	if (gen_pool_add(pool, 0x08000000, 0x10000, -1))
-+		goto err_pool_add;
-+
-+	sram_pool = pool;
-+	return 0;
-+
-+err_pool_add:
-+	gen_pool_destroy(pool);
-+fail:
-+	pr_err("Failed to create SRAM pool\n");
-+	return -ENOMEM;
-+}
-+core_initcall(sram_init);
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/extint.c linux-2.6.28.2/arch/avr32/mach-at32ap/extint.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/extint.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/extint.c	2009-01-29 08:52:49.000000000 +0100
-@@ -17,6 +17,8 @@
- 
- #include <asm/io.h>
- 
-+#include <mach/cpu.h>
-+
- /* EIC register offsets */
- #define EIC_IER					0x0000
- #define EIC_IDR					0x0004
-@@ -26,24 +28,18 @@
- #define EIC_MODE				0x0014
- #define EIC_EDGE				0x0018
- #define EIC_LEVEL				0x001c
--#define EIC_NMIC				0x0024
- 
--/* Bitfields in NMIC */
--#define EIC_NMIC_ENABLE				(1 << 0)
-+/* This is only valid on v1 (AP700x) */
-+#define EIC_NMIC				0x0024
-+# define EIC_NMIC_ENABLE			(1 << 0)
- 
--/* Bit manipulation macros */
--#define EIC_BIT(name)					\
--	(1 << EIC_##name##_OFFSET)
--#define EIC_BF(name,value)				\
--	(((value) & ((1 << EIC_##name##_SIZE) - 1))	\
--	 << EIC_##name##_OFFSET)
--#define EIC_BFEXT(name,value)				\
--	(((value) >> EIC_##name##_OFFSET)		\
--	 & ((1 << EIC_##name##_SIZE) - 1))
--#define EIC_BFINS(name,value,old)			\
--	(((old) & ~(((1 << EIC_##name##_SIZE) - 1)	\
--		    << EIC_##name##_OFFSET))		\
--	 | EIC_BF(name,value))
-+/* These are only valid on v3 (AP720x) */
-+#define EIC_FILTER				0x0020
-+#define EIC_TEST				0x0024
-+#define EIC_ASYNC				0x0028
-+#define EIC_EN					0x0030
-+#define EIC_DIS					0x0034
-+#define EIC_CTRL				0x0038
- 
- /* Register access macros */
- #define eic_readl(port,reg)				\
-@@ -60,36 +56,68 @@
- static struct eic *nmi_eic;
- static bool nmi_enabled;
- 
-+static inline int eic_version(struct eic *eic)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static inline int eic_irq_bitmask(struct eic *eic, unsigned int irq)
-+{
-+	irq -= eic->first_irq;
-+
-+	if (eic_version(eic) > 2)
-+		irq++;
-+	return 1 << irq;
-+}
-+
- static void eic_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_unmask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IER, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IER, eic_irq_bitmask(eic, irq));
-+}
-+
-+/* The following two hooks are only used on v2+ controllers */
-+static void eic_enable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, EN, eic_irq_bitmask(eic, irq));
-+}
-+
-+static void eic_disable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, DIS, eic_irq_bitmask(eic, irq));
- }
- 
- static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
- 	struct irq_desc *desc;
--	unsigned int i = irq - eic->first_irq;
-+	unsigned int irq_bitmask = eic_irq_bitmask(eic, irq);
- 	u32 mode, edge, level;
- 	int ret = 0;
- 
-@@ -105,20 +133,20 @@
- 
- 	switch (flow_type) {
- 	case IRQ_TYPE_LEVEL_LOW:
--		mode |= 1 << i;
--		level &= ~(1 << i);
-+		mode |= irq_bitmask;
-+		level &= ~irq_bitmask;
- 		break;
- 	case IRQ_TYPE_LEVEL_HIGH:
--		mode |= 1 << i;
--		level |= 1 << i;
-+		mode |= irq_bitmask;
-+		level |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_RISING:
--		mode &= ~(1 << i);
--		edge |= 1 << i;
-+		mode &= ~irq_bitmask;
-+		edge |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_FALLING:
--		mode &= ~(1 << i);
--		edge &= ~(1 << i);
-+		mode &= ~irq_bitmask;
-+		edge &= ~irq_bitmask;
- 		break;
- 	default:
- 		ret = -EINVAL;
-@@ -160,6 +188,11 @@
- 	status = eic_readl(eic, ISR);
- 	pending = status & eic_readl(eic, IMR);
- 
-+	if (eic_version(eic) > 1) {
-+		status >>= 1;
-+		pending >>= 1;
-+	}
-+
- 	while (pending) {
- 		i = fls(pending) - 1;
- 		pending &= ~(1 << i);
-@@ -172,16 +205,34 @@
- {
- 	nmi_enabled = true;
- 
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, EN, 1 << 0);
-+			eic_writel(nmi_eic, IER, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, EN, 1 << 8);
-+			eic_writel(nmi_eic, IER, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+		}
-+	}
- 
- 	return 0;
- }
- 
- void nmi_disable(void)
- {
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, 0);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, IDR, 1 << 0);
-+			eic_writel(nmi_eic, DIS, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, IDR, 1 << 8);
-+			eic_writel(nmi_eic, DIS, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, 0);
-+		}
-+	}
- 
- 	nmi_enabled = false;
- }
-@@ -230,6 +281,15 @@
- 	eic_writel(eic, EDGE, 0UL);
- 	eic_writel(eic, LEVEL, 0UL);
- 
-+	/*
-+	 * v2+ controllers have an extra enable/disable/mask set of
-+	 * registers.
-+	 */
-+	if (eic_version(eic) >= 2) {
-+		eic_chip.enable = eic_enable_irq;
-+		eic_chip.disable = eic_disable_irq;
-+	}
-+
- 	eic->chip = &eic_chip;
- 
- 	for (i = 0; i < nr_of_irqs; i++) {
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.c linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.c	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,534 @@
-+/*
-+ * Atmel GPIO Port Multiplexer support
-+ *
-+ * Copyright (C) 2004-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/debugfs.h>
-+#include <linux/fs.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/portmux.h>
-+#include <mach/chip.h>
-+
-+#include "gpio-v2.h"
-+
-+/*
-+ * One chip corresponds with one bank of I/O registers. They're really
-+ * all on the same controller.
-+ */
-+struct atmel_gpio_chip {
-+	void __iomem	*regs;
-+	u32		pinmux_mask;
-+	struct		gpio_chip chip;
-+	char		name[8];
-+	unsigned int	bank;
-+	int		irq;
-+};
-+
-+/* ...which means we only have one clock and one platform device */
-+static struct clk *gpio_clk;
-+static struct atmel_gpio_chip gpio_dev[NR_GPIO_BANKS];
-+
-+/* Pin multiplexing API */
-+static DEFINE_SPINLOCK(gpio_lock);
-+
-+static struct atmel_gpio_chip *to_atmel_gpio_chip(struct gpio_chip *chip)
-+{
-+	return container_of(chip, struct atmel_gpio_chip, chip);
-+}
-+
-+static struct atmel_gpio_chip *pin_to_chip(unsigned int gpio)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int index;
-+
-+	index = gpio >> 5;
-+	if (index >= NR_GPIO_BANKS)
-+		return NULL;
-+	chip = &gpio_dev[index];
-+	if (!chip->regs)
-+		return NULL;
-+
-+	return chip;
-+}
-+
-+/* Pin multiplexing API */
-+
-+void __init at32_select_periph(unsigned int port, u32 pin_mask,
-+		unsigned int periph, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(gpiochip_is_requested(&chip->chip, port)
-+			|| unlikely(pin_mask & chip->pinmux_mask))) {
-+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
-+		       chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	switch (periph) {
-+	case GPIO_PERIPH_A:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_B:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_C:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	case GPIO_PERIPH_D:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	default:
-+		printk("%s: unknown function for pin mask %u\n",
-+				chip->name, pin_mask);
-+		goto fail;
-+	}
-+
-+	gpio_writel(chip, PUERS, pin_mask);
-+
-+	gpio_writel(chip, GPERC, pin_mask);
-+	if (!(flags & AT32_GPIOF_PULLUP))
-+		gpio_writel(chip, PUERC, pin_mask);
-+
-+	spin_unlock(&gpio_lock);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+void __init at32_select_gpio(unsigned int pin, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int pin_index = pin & 0x1f;
-+	u32 mask = 1 << pin_index;
-+
-+	chip = pin_to_chip(pin);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid pin %u\n", pin);
-+		goto fail;
-+	}
-+
-+	if (unlikely(test_and_set_bit(pin_index, &chip->pinmux_mask))) {
-+		printk("%s: pin %u is busy\n", chip->name, pin_index);
-+		goto fail;
-+	}
-+
-+	if (flags & AT32_GPIOF_PULLUP)
-+		gpio_writel(chip, PUERS, mask);
-+	else
-+		gpio_writel(chip, PUERC, mask);
-+	if (flags & AT32_GPIOF_MULTIDRV)
-+		gpio_writel(chip, ODMERS, mask);
-+	else
-+		gpio_writel(chip, ODMERC, mask);
-+	if (flags & AT32_GPIOF_DEGLITCH)
-+		gpio_writel(chip, GFERS, mask);
-+	else
-+		gpio_writel(chip, GFERC, mask);
-+
-+	if (flags & AT32_GPIOF_OUTPUT) {
-+		if (flags & AT32_GPIOF_HIGH)
-+			gpio_writel(chip, OVRS, mask);
-+		else
-+			gpio_writel(chip, OVRC, mask);
-+		gpio_writel(chip, ODERS, mask);
-+	} else {
-+		gpio_writel(chip, ODERC, mask);
-+	}
-+
-+	gpio_writel(chip, GPERS, mask);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/* Reserve a pin, preventing anyone else from changing its configuration. */
-+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(pin_mask & chip->pinmux_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
-+			chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	/* Reserve pins */
-+	chip->pinmux_mask |= pin_mask;
-+	spin_unlock(&gpio_lock);
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO API */
-+
-+static int get_pin_state(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+
-+	return (gpio_readl(gpio, PVR) >> offset) & 1;
-+}
-+
-+static void set_pin_state(struct gpio_chip *chip, unsigned int offset, int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (high)
-+		gpio_writel(gpio, OVRS, mask);
-+	else
-+		gpio_writel(gpio, OVRC, mask);
-+}
-+
-+static int direction_input(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	gpio_writel(gpio, ODERC, mask);
-+	return 0;
-+}
-+
-+static int direction_output(struct gpio_chip *chip, unsigned int offset,
-+		int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	set_pin_state(chip, offset, high);
-+	gpio_writel(gpio, ODERS, mask);
-+	return 0;
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO IRQ support */
-+
-+static void gpio_irq_mask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERC, 1 << (pin & 0x1f));
-+}
-+
-+static void gpio_irq_unmask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERS, 1 << (pin & 0x1f));
-+}
-+
-+static int gpio_irq_type(unsigned irq, unsigned type)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+	u32			mask = 1 << (pin & 0x1f);
-+
-+	switch (type) {
-+	case IRQ_TYPE_EDGE_FALLING:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1S, mask);
-+		break;
-+	case IRQ_TYPE_EDGE_RISING:
-+		gpio_writel(chip, IMR0S, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	case IRQ_TYPE_NONE:
-+		/* fall through */
-+	case IRQ_TYPE_EDGE_BOTH:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct irq_chip gpio_irqchip = {
-+	.name		= "gpio",
-+	.mask		= gpio_irq_mask,
-+	.unmask		= gpio_irq_unmask,
-+	.set_type	= gpio_irq_type,
-+};
-+
-+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+	struct atmel_gpio_chip	*chip = get_irq_chip_data(irq);
-+	unsigned int		gpio_irq;
-+
-+	gpio_irq = (unsigned int) get_irq_data(irq);
-+	for (;;) {
-+		u32		ifr;
-+		struct irq_desc	*d;
-+
-+		/* ack pending GPIO interrupts */
-+		ifr = gpio_readl(chip, IFR);
-+		if (!ifr)
-+			break;
-+		do {
-+			int pin;
-+
-+			pin = ffs(ifr) - 1;
-+			ifr &= ~(1 << pin);
-+			gpio_writel(chip, IFRC, (1 << pin));
-+
-+			pin += gpio_irq;
-+			d = &irq_desc[pin];
-+
-+			d->handle_irq(pin, d);
-+		} while (ifr);
-+	}
-+}
-+
-+static void __init
-+gpio_irq_setup(struct atmel_gpio_chip *chip, int irq, int gpio_irq)
-+{
-+	unsigned	i;
-+
-+	set_irq_chip_data(irq, chip);
-+	set_irq_data(irq, (void *) gpio_irq);
-+
-+	for (i = 0; i < 32; i++, gpio_irq++) {
-+		set_irq_chip_data(gpio_irq, chip);
-+		set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
-+				handle_simple_irq);
-+	}
-+
-+	set_irq_chained_handler(irq, gpio_irq_handler);
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+#ifdef CONFIG_DEBUG_FS
-+
-+#include <linux/seq_file.h>
-+
-+/*
-+ * This shows more info than the generic gpio dump code:
-+ * pullups, deglitching, open drain drive.
-+ */
-+static void gpio_bank_show(struct seq_file *s, struct gpio_chip *chip)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32		oder, ovr, puer, pder, gfer, odmer, ier, imr0, imr1;
-+	unsigned int	i;
-+	u32		mask;
-+
-+	oder = gpio_readl(gpio, ODER);
-+	ovr = gpio_readl(gpio, OVR);
-+	puer = gpio_readl(gpio, PUER);
-+	pder = gpio_readl(gpio, PDER);
-+	gfer = gpio_readl(gpio, GFER);
-+	odmer = gpio_readl(gpio, ODMER);
-+	ier = gpio_readl(gpio, IER);
-+	imr0 = gpio_readl(gpio, IMR0);
-+	imr1 = gpio_readl(gpio, IMR1);
-+
-+	for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
-+		const char *label;
-+
-+		label = gpiochip_is_requested(chip, i);
-+		if (!label)
-+			continue;
-+
-+		seq_printf(s, " gpio-%-3d ", chip->base + i);
-+		gpio_decode_pin(s, gpio->bank, i);
-+		seq_printf(s, " (%-12s) %s %s", label,
-+				(oder & mask) ? "out" : "in",
-+				(ovr & mask) ? "hi" : "lo");
-+		if ((puer & mask) && !(pder & mask))
-+			seq_printf(s, " pull-up");
-+		else if (!(puer & mask) && (pder & mask))
-+			seq_printf(s, " pull-down");
-+		else if ((puer & mask) && (pder & mask))
-+			seq_printf(s, " buskeeper");
-+		if (gfer & mask)
-+			seq_printf(s, " deglitch");
-+		if (odmer & mask)
-+			seq_printf(s, " open-drain");
-+		if ((gpio->irq >= 0) && (ier & mask)) {
-+			seq_printf(s, " irq-%d edge-",
-+					gpio_to_irq(chip->base + i));
-+			if (!(imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "both");
-+			else if ((imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "rising");
-+			else if (!(imr0 & mask) && (imr1 & mask))
-+				seq_printf(s, "falling");
-+			else
-+				seq_printf(s, "INVALID");
-+		}
-+		seq_printf(s, "\n");
-+	}
-+}
-+
-+#else
-+#define gpio_bank_show	NULL
-+#endif
-+
-+static int __init gpio_probe(struct platform_device *pdev)
-+{
-+	struct resource *regs;
-+	struct resource *irqs;
-+	int irq = -1;
-+	unsigned int i;
-+
-+	BUG_ON(pdev->id >= 1);
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return -ENXIO;
-+	}
-+	irqs = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (irqs)
-+		irq = irqs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		unsigned int gpio_irq_base;
-+		struct atmel_gpio_chip *chip;
-+
-+		chip = &gpio_dev[i];
-+		BUG_ON(!chip->regs);
-+
-+		chip->chip.label = chip->name;
-+		chip->chip.base = i * 32;
-+		chip->chip.ngpio = 32;
-+
-+		chip->chip.direction_input = direction_input;
-+		chip->chip.get = get_pin_state;
-+		chip->chip.direction_output = direction_output;
-+		chip->chip.set = set_pin_state;
-+		chip->chip.dbg_show = gpio_bank_show;
-+
-+		gpiochip_add(&chip->chip);
-+
-+		gpio_irq_base = GPIO_IRQ_BASE + (i * 32);
-+		if (irqs && irq <= irqs->end) {
-+			gpio_irq_setup(chip, irq, gpio_irq_base);
-+			chip->irq = irq;
-+			irq++;
-+		} else {
-+			chip->irq = -1;
-+		}
-+
-+		platform_set_drvdata(pdev, chip);
-+
-+		printk(KERN_DEBUG "%s: base 0x%p", chip->name, chip->regs);
-+		if (chip->irq >= 0)
-+			printk(" irq %d chains %d..%d", irq,
-+					gpio_irq_base, gpio_irq_base + 31);
-+		printk("\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_driver = {
-+	.probe		= gpio_probe,
-+	.driver		= {
-+		.name		= "gpio",
-+	},
-+};
-+
-+static int __init gpio_init(void)
-+{
-+	return platform_driver_register(&gpio_driver);
-+}
-+postcore_initcall(gpio_init);
-+
-+void __init at32_gpio_init(struct platform_device *pdev)
-+{
-+	int i;
-+	struct clk *clk;
-+	struct resource *regs;
-+	void __iomem *iomem_base;
-+	struct atmel_gpio_chip *chip;
-+
-+	if (pdev->id > 0) {
-+		dev_err(&pdev->dev, "only one GPIO controller supported\n");
-+		return;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return;
-+	}
-+
-+	clk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "no mck clock defined\n");
-+		return;
-+	}
-+	clk_enable(clk);
-+
-+	gpio_clk = clk;
-+
-+	/*
-+	 * We may get called too early for ioremap() to work. But we
-+	 * know that the GPIO registers are permanently mapped 1:1
-+	 */
-+	iomem_base = (void __iomem __force *)regs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		chip = &gpio_dev[i];
-+		snprintf(chip->name, sizeof(chip->name), "gpio%d", i);
-+		chip->regs = iomem_base + (i * 0x200);
-+		chip->bank = i;
-+
-+		/* start with irqs disabled and acked */
-+		gpio_writel(chip, IERC, ~0UL);
-+		gpio_writel(chip, IFRC, ~0UL);
-+	}
-+}
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.h linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/gpio-v2.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/gpio-v2.h	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+#ifndef __GPIO_REGS_H__
-+#define __GPIO_REGS_H__
-+
-+/* Register offsets */
-+struct gpio_regs {
-+	u32	GPER;
-+	u32	GPERS;
-+	u32	GPERC;
-+	u32	GPERT;
-+	u32	PMR0;
-+	u32	PMR0S;
-+	u32	PMR0C;
-+	u32	PMR0T;
-+	u32	PMR1;
-+	u32	PMR1S;
-+	u32	PMR1C;
-+	u32	PMR1T;
-+	u32	__reserved0[4];
-+	u32	ODER;
-+	u32	ODERS;
-+	u32	ODERC;
-+	u32	ODERT;
-+	u32	OVR;
-+	u32	OVRS;
-+	u32	OVRC;
-+	u32	OVRT;
-+	u32	PVR;
-+	u32	__reserved_PVRS;
-+	u32	__reserved_PVRC;
-+	u32	__reserved_PVRT;
-+	u32	PUER;
-+	u32	PUERS;
-+	u32	PUERC;
-+	u32	PUERT;
-+	u32	PDER;
-+	u32	PDERS;
-+	u32	PDERC;
-+	u32	PDERT;
-+	u32	IER;
-+	u32	IERS;
-+	u32	IERC;
-+	u32	IERT;
-+	u32	IMR0;
-+	u32	IMR0S;
-+	u32	IMR0C;
-+	u32	IMR0T;
-+	u32	IMR1;
-+	u32	IMR1S;
-+	u32	IMR1C;
-+	u32	IMR1T;
-+	u32	GFER;
-+	u32	GFERS;
-+	u32	GFERC;
-+	u32	GFERT;
-+	u32	IFR;
-+	u32	__reserved_IFRS;
-+	u32	IFRC;
-+	u32	__reserved_IFRT;
-+	u32	ODMER;
-+	u32	ODMERS;
-+	u32	ODMERC;
-+	u32	ODMERT;
-+	u32	__reserved1[4];
-+	u32	ODCR0;
-+	u32	ODCR0S;
-+	u32	ODCR0C;
-+	u32	ODCR0T;
-+	u32	ODCR1;
-+	u32	ODCR1S;
-+	u32	ODCR1C;
-+	u32	ODCR1T;
-+	u32	__reserved2[4];
-+	u32	OSRR0;
-+	u32	OSRR0S;
-+	u32	OSRR0C;
-+	u32	OSRR0T;
-+	u32	__reserved3[8];
-+	u32	STER;
-+	u32	STERS;
-+	u32	STERC;
-+	u32	STERT;
-+	u32	__reserved4[35];
-+	u32	VERSION;
-+};
-+
-+/* Register access macros */
-+#define __gpio_regs(bank) ((struct gpio_regs __iomem *)(bank)->regs)
-+#define gpio_readl(bank, reg)						\
-+	__raw_readl(&__gpio_regs(bank)->reg)
-+#define gpio_writel(bank, reg, value)					\
-+	__raw_writel(value, &__gpio_regs(bank)->reg)
-+
-+void at32_gpio_init(struct platform_device *pdev);
-+
-+#endif /* __GPIO_REGS_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hmatrix.c linux-2.6.28.2/arch/avr32/mach-at32ap/hmatrix.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hmatrix.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/hmatrix.c	2009-01-29 08:52:49.000000000 +0100
-@@ -54,6 +54,81 @@
- }
- 
- /**
-+ * hmatrix_set_default_master - set default master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ */
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MASTER_LAST);
-+
-+	reg = HMATRIX_SCFG(slave);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	value = __hmatrix_read_reg(reg);
-+	value &= ~(HMATRIX_SCFG_FIXED_DEFMSTR(HMATRIX_MAX_SLAVE)
-+			| HMATRIX_SCFG_DEFMSTR_MASK);
-+
-+	switch (master) {
-+	case HMATRIX_MASTER_NONE:
-+		value |= HMATRIX_SCFG_DEFMSTR_NONE;
-+		break;
-+	case HMATRIX_MASTER_LAST:
-+		value |= HMATRIX_SCFG_DEFMSTR_LAST;
-+		break;
-+	default:
-+		value |= HMATRIX_SCFG_DEFMSTR_FIXED;
-+		value |= HMATRIX_SCFG_FIXED_DEFMSTR(master);
-+		break;
-+	}
-+
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-+ * hmatrix_set_priority - set the priority of a master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ * @priority: Priority of @master when competing for access to @slave.
-+ *
-+ * Note that this is currently broken -- we need some way to enable
-+ * fixed-priority arbitration, and that happens to be broken on AP7000
-+ * rev C.
-+ */
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MAX_MASTER
-+			|| priority > HMATRIX_MAX_PRIO);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	if (master < 8) {
-+		reg = HMATRIX_PRAS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRAS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRAS_PRIO(master, priority);
-+	} else {
-+		reg = HMATRIX_PRBS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRBS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRBS_PRIO(master, priority);
-+	}
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-  * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
-  * @slave_id: operate on the SFR belonging to this slave
-  * @mask: mask of bits to be set in the SFR
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hsmc.c linux-2.6.28.2/arch/avr32/mach-at32ap/hsmc.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/hsmc.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/hsmc.c	2009-01-29 08:52:49.000000000 +0100
-@@ -229,10 +229,8 @@
- 	if (IS_ERR(pclk))
- 		return PTR_ERR(pclk);
- 	mck = clk_get(&pdev->dev, "mck");
--	if (IS_ERR(mck)) {
--		ret = PTR_ERR(mck);
--		goto out_put_pclk;
--	}
-+	if (IS_ERR(mck))
-+		mck = pclk;
- 
- 	ret = -ENOMEM;
- 	hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
-@@ -260,8 +258,8 @@
- 	clk_disable(pclk);
- 	kfree(hsmc);
- out_put_clocks:
--	clk_put(mck);
--out_put_pclk:
-+	if (mck != pclk)
-+		clk_put(mck);
- 	clk_put(pclk);
- 	hsmc = NULL;
- 	return ret;
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap700x.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap700x.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap700x.h	2009-01-29 08:52:49.000000000 +0100
-@@ -211,4 +211,135 @@
- 
- #define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
- 
-+/* Bitmask for all EBI data (D16..D31) pins on port E */
-+#define ATMEL_EBI_PE_DATA_ALL  (0x0000FFFF)
-+
-+/* LCDC on port C */
-+#define ATMEL_LCDC_PC_CC	(1ULL << 19)
-+#define ATMEL_LCDC_PC_HSYNC	(1ULL << 20)
-+#define ATMEL_LCDC_PC_PCLK	(1ULL << 21)
-+#define ATMEL_LCDC_PC_VSYNC	(1ULL << 22)
-+#define ATMEL_LCDC_PC_DVAL	(1ULL << 23)
-+#define ATMEL_LCDC_PC_MODE	(1ULL << 24)
-+#define ATMEL_LCDC_PC_PWR	(1ULL << 25)
-+#define ATMEL_LCDC_PC_DATA0	(1ULL << 26)
-+#define ATMEL_LCDC_PC_DATA1	(1ULL << 27)
-+#define ATMEL_LCDC_PC_DATA2	(1ULL << 28)
-+#define ATMEL_LCDC_PC_DATA3	(1ULL << 29)
-+#define ATMEL_LCDC_PC_DATA4	(1ULL << 30)
-+#define ATMEL_LCDC_PC_DATA5	(1ULL << 31)
-+
-+/* LCDC on port D */
-+#define ATMEL_LCDC_PD_DATA6	(1ULL << 0)
-+#define ATMEL_LCDC_PD_DATA7	(1ULL << 1)
-+#define ATMEL_LCDC_PD_DATA8	(1ULL << 2)
-+#define ATMEL_LCDC_PD_DATA9	(1ULL << 3)
-+#define ATMEL_LCDC_PD_DATA10	(1ULL << 4)
-+#define ATMEL_LCDC_PD_DATA11	(1ULL << 5)
-+#define ATMEL_LCDC_PD_DATA12	(1ULL << 6)
-+#define ATMEL_LCDC_PD_DATA13	(1ULL << 7)
-+#define ATMEL_LCDC_PD_DATA14	(1ULL << 8)
-+#define ATMEL_LCDC_PD_DATA15	(1ULL << 9)
-+#define ATMEL_LCDC_PD_DATA16	(1ULL << 10)
-+#define ATMEL_LCDC_PD_DATA17	(1ULL << 11)
-+#define ATMEL_LCDC_PD_DATA18	(1ULL << 12)
-+#define ATMEL_LCDC_PD_DATA19	(1ULL << 13)
-+#define ATMEL_LCDC_PD_DATA20	(1ULL << 14)
-+#define ATMEL_LCDC_PD_DATA21	(1ULL << 15)
-+#define ATMEL_LCDC_PD_DATA22	(1ULL << 16)
-+#define ATMEL_LCDC_PD_DATA23	(1ULL << 17)
-+
-+/* LCDC on port E */
-+#define ATMEL_LCDC_PE_CC	(1ULL << (32 + 0))
-+#define ATMEL_LCDC_PE_DVAL	(1ULL << (32 + 1))
-+#define ATMEL_LCDC_PE_MODE	(1ULL << (32 + 2))
-+#define ATMEL_LCDC_PE_DATA0	(1ULL << (32 + 3))
-+#define ATMEL_LCDC_PE_DATA1	(1ULL << (32 + 4))
-+#define ATMEL_LCDC_PE_DATA2	(1ULL << (32 + 5))
-+#define ATMEL_LCDC_PE_DATA3	(1ULL << (32 + 6))
-+#define ATMEL_LCDC_PE_DATA4	(1ULL << (32 + 7))
-+#define ATMEL_LCDC_PE_DATA8	(1ULL << (32 + 8))
-+#define ATMEL_LCDC_PE_DATA9	(1ULL << (32 + 9))
-+#define ATMEL_LCDC_PE_DATA10	(1ULL << (32 + 10))
-+#define ATMEL_LCDC_PE_DATA11	(1ULL << (32 + 11))
-+#define ATMEL_LCDC_PE_DATA12	(1ULL << (32 + 12))
-+#define ATMEL_LCDC_PE_DATA16	(1ULL << (32 + 13))
-+#define ATMEL_LCDC_PE_DATA17	(1ULL << (32 + 14))
-+#define ATMEL_LCDC_PE_DATA18	(1ULL << (32 + 15))
-+#define ATMEL_LCDC_PE_DATA19	(1ULL << (32 + 16))
-+#define ATMEL_LCDC_PE_DATA20	(1ULL << (32 + 17))
-+#define ATMEL_LCDC_PE_DATA21	(1ULL << (32 + 18))
-+
-+
-+#define ATMEL_LCDC(PORT, PIN)	(ATMEL_LCDC_##PORT##_##PIN)
-+
-+
-+#define ATMEL_LCDC_PRI_24B_DATA	(					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) |	\
-+		ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) |	\
-+		ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_ALT_24B_DATA (					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) |	\
-+		ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) |	\
-+		ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_PRI_15B_DATA (					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA16) |	\
-+		ATMEL_LCDC(PD, DATA17) | ATMEL_LCDC(PD, DATA18) |	\
-+		ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20))
-+
-+#define ATMEL_LCDC_ALT_15B_DATA	(					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PE, DATA16) |	\
-+		ATMEL_LCDC(PE, DATA17) | ATMEL_LCDC(PE, DATA18) |	\
-+		ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20))
-+
-+#define ATMEL_LCDC_PRI_CONTROL (					\
-+		ATMEL_LCDC(PC, CC)   | ATMEL_LCDC(PC, DVAL) |		\
-+		ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_ALT_CONTROL (					\
-+		ATMEL_LCDC(PE, CC)   | ATMEL_LCDC(PE, DVAL) |		\
-+		ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_CONTROL (						\
-+		ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) |		\
-+		ATMEL_LCDC(PC, PCLK))
-+
-+#define ATMEL_LCDC_PRI_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
-+
-+#define ATMEL_LCDC_ALT_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
-+
-+#define ATMEL_LCDC_PRI_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
-+
-+#define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
-+
- #endif /* __ASM_ARCH_AT32AP700X_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap720x.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/at32ap720x.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/at32ap720x.h	2009-01-29 08:52:49.000000000 +0100
-@@ -0,0 +1,105 @@
-+/*
-+ * Pin definitions for AT32AP7200
-+ *
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ASM_ARCH_AT32AP7200_H__
-+#define __ASM_ARCH_AT32AP7200_H__
-+
-+#define GPIO_PERIPH_A	0x00
-+#define GPIO_PERIPH_B	0x01
-+#define GPIO_PERIPH_C	0x02
-+#define GPIO_PERIPH_D	0x03
-+
-+#define NR_GPIO_BANKS	8
-+
-+/*
-+ * Pin numbers identifying specific GPIO pins on the chip. They can
-+ * also be converted to IRQ numbers by passing them through
-+ * gpio_to_irq().
-+ */
-+#define GPIO_BASE	(0)
-+
-+#define GPIO_PA_BASE	(GPIO_BASE + 0 * 32)
-+#define GPIO_PB_BASE	(GPIO_BASE + 1 * 32)
-+#define GPIO_PC_BASE	(GPIO_BASE + 2 * 32)
-+#define GPIO_PD_BASE	(GPIO_BASE + 3 * 32)
-+#define GPIO_PE_BASE	(GPIO_BASE + 4 * 32)
-+#define GPIO_PF_BASE	(GPIO_BASE + 5 * 32)
-+#define GPIO_PX_BASE	(GPIO_BASE + 6 * 32)
-+
-+#define GPIO_PIN_PA(N)	(GPIO_PA_BASE + (N))
-+#define GPIO_PIN_PB(N)	(GPIO_PB_BASE + (N))
-+#define GPIO_PIN_PC(N)	(GPIO_PC_BASE + (N))
-+#define GPIO_PIN_PD(N)	(GPIO_PD_BASE + (N))
-+#define GPIO_PIN_PE(N)	(GPIO_PE_BASE + (N))
-+#define GPIO_PIN_PF(N)	(GPIO_PF_BASE + (N))
-+#define GPIO_PIN_PX(N)	(GPIO_PX_BASE + (N))
-+
-+#define gpio_decode_pin(s, bank, offset)				\
-+	do {								\
-+		switch (bank) {						\
-+		case 7:							\
-+			offset += 32;					\
-+			/* fall through */				\
-+		case 6:							\
-+			seq_printf(s, "PX%-2u", offset);		\
-+			break;						\
-+		default:						\
-+			seq_printf(s, "P%c%-2u", bank + 'A', offset);	\
-+			break;						\
-+		}							\
-+	} while (0)
-+
-+/* HSB master IDs */
-+#define HMATRIX_MASTER_CPU_ICACHE		 0
-+#define HMATRIX_MASTER_CPU_DCACHE		 1
-+#define HMATRIX_MASTER_PDCA			 2
-+#define HMATRIX_MASTER_LCDC			 4
-+#define HMATRIX_MASTER_MPOP_IBI			 5
-+#define HMATRIX_MASTER_MPOP_OBI			 6
-+#define HMATRIX_MASTER_MPOP_OM			 7
-+#define HMATRIX_MASTER_DMACA_M0			 8
-+#define HMATRIX_MASTER_DMACA_M1			 9
-+#define HMATRIX_MASTER_USBB			10
-+#define HMATRIX_MASTER_USBH_EHCI		11
-+#define HMATRIX_MASTER_USBH_OHCI		12
-+#define HMATRIX_MASTER_MACB			13
-+
-+/* HSB slave IDs */
-+#define HMATRIX_SLAVE_BOOTROM			 0
-+#define HMATRIX_SLAVE_PBA			 1
-+#define HMATRIX_SLAVE_PBB			 2
-+#define HMATRIX_SLAVE_PBC			 3
-+#define HMATRIX_SLAVE_SRAM0			 4
-+#define HMATRIX_SLAVE_SRAM1			 5
-+#define HMATRIX_SLAVE_EBI			 6
-+#define HMATRIX_SLAVE_LCDC			 7
-+#define HMATRIX_SLAVE_MPOP			 8
-+#define HMATRIX_SLAVE_DMACA			 9
-+#define HMATRIX_SLAVE_USBB			10
-+#define HMATRIX_SLAVE_EHCI			11
-+#define HMATRIX_SLAVE_OHCI			12
-+
-+/* Bits in HMATRIX SFR6 (EBI) */
-+#define HMATRIX_EBI_SDRAM_ENABLE		(1 << 1)
-+#define HMATRIX_EBI_NAND_ENABLE			(1 << 3)
-+#define HMATRIX_EBI_CF0_ENABLE			(1 << 4)
-+#define HMATRIX_EBI_CF1_ENABLE			(1 << 5)
-+
-+/*
-+ * Base addresses of controllers that may be accessed early by
-+ * platform code.
-+ */
-+#define GPIO_HW_BASE	0xffd02000
-+#define INTC_BASE	0xffd00000
-+#define PM_BASE		0xffd00400
-+#define SDC_BASE	0xffd00800
-+#define SDRAMC_BASE	0xffe04800
-+#define HMATRIX_BASE	0xffe05000
-+
-+#endif /* __ASM_ARCH_AT32AP7200_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/chip.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/chip.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/chip.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/chip.h	2009-01-29 08:52:49.000000000 +0100
-@@ -12,6 +12,8 @@
- 
- #if defined(CONFIG_CPU_AT32AP700X)
- # include <mach/at32ap700x.h>
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include <mach/at32ap720x.h>
- #else
- # error Unknown chip type selected
- #endif
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/cpu.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/cpu.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/cpu.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/cpu.h	2009-01-29 08:52:49.000000000 +0100
-@@ -20,6 +20,19 @@
- # define cpu_is_at32ap7000()	(0)
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP720X
-+# define cpu_is_at32ap7200()	(1)
-+#else
-+# define cpu_is_at32ap7200()	(0)
-+#endif
-+
-+/*
-+ * Unfortunately, only AP700x has a non-broken COUNT/COMPARE
-+ * implementation. Other chips need to use different timers. The good
-+ * news is that these timers are usually better anyway.
-+ */
-+#define cpu_has_working_compare()	(cpu_is_at32ap7000())
-+
- /*
-  * Since this is AVR32, we will never run on any AT91 CPU. But these
-  * definitions may reduce clutter in common drivers.
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/hmatrix.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/hmatrix.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/hmatrix.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/hmatrix.h	2009-01-29 08:52:49.000000000 +0100
-@@ -15,6 +15,9 @@
- void hmatrix_write_reg(unsigned long offset, u32 value);
- u32 hmatrix_read_reg(unsigned long offset);
- 
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master);
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority);
- void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
- void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- 
-@@ -33,6 +36,7 @@
- # define HMATRIX_SCFG_DEFMSTR_NONE	(  0 << 16)	/* No default master */
- # define HMATRIX_SCFG_DEFMSTR_LAST	(  1 << 16)	/* Last def master */
- # define HMATRIX_SCFG_DEFMSTR_FIXED	(  2 << 16)	/* Fixed def master */
-+# define HMATRIX_SCFG_DEFMSTR_MASK	(  3 << 16)
- # define HMATRIX_SCFG_FIXED_DEFMSTR(m)	((m) << 18)	/* Fixed master ID */
- # define HMATRIX_SCFG_ARBT_ROUND_ROBIN	(  0 << 24)	/* RR arbitration */
- # define HMATRIX_SCFG_ARBT_FIXED_PRIO	(  1 << 24)	/* Fixed priority */
-@@ -52,4 +56,12 @@
- /* Special Function Register. Bit definitions are chip-specific */
- #define HMATRIX_SFR(s)			(0x0110 + 4 * (s))
- 
-+#define HMATRIX_MAX_SLAVE	15
-+#define HMATRIX_MAX_MASTER	15
-+#define HMATRIX_MAX_PRIO	15
-+
-+/* Special master IDs for use with hmatrix_set_default_master() */
-+#define HMATRIX_MASTER_NONE	16	/* No default master */
-+#define HMATRIX_MASTER_LAST	17	/* Last master stays connected */
-+
- #endif /* __HMATRIX_H */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/init.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/init.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/init.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/init.h	2009-01-29 08:52:49.000000000 +0100
-@@ -15,4 +15,10 @@
- 
- void at32_setup_serial_console(unsigned int usart_id);
- 
-+/*
-+ * Called from time_init() when a broken COUNT/COMPARE implementation
-+ * is detected.
-+ */
-+void platform_time_init(void);
-+
- #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/irq.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/irq.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/irq.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/irq.h	2009-01-29 08:52:49.000000000 +0100
-@@ -6,7 +6,7 @@
- #define AT32_EXTINT(n)	(EIM_IRQ_BASE + (n))
- 
- #define GPIO_IRQ_BASE	(EIM_IRQ_BASE + NR_EIM_IRQS)
--#define NR_GPIO_CTLR	(5 /*internal*/ + 1 /*external*/)
-+#define NR_GPIO_CTLR	(8 /*internal*/ + 1 /*external*/)
- #define NR_GPIO_IRQS	(NR_GPIO_CTLR * 32)
- 
- #define NR_IRQS		(GPIO_IRQ_BASE + NR_GPIO_IRQS)
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/pm.h linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/pm.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/include/mach/pm.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/include/mach/pm.h	2009-01-29 08:52:49.000000000 +0100
-@@ -11,13 +11,17 @@
- #define __ASM_AVR32_ARCH_PM_H
- 
- /* Possible arguments to the "sleep" instruction */
--#define CPU_SLEEP_IDLE		0
--#define CPU_SLEEP_FROZEN	1
--#define CPU_SLEEP_STANDBY	2
--#define CPU_SLEEP_STOP		3
--#define CPU_SLEEP_STATIC	5
-+#define CPU_SLEEP_IDLE		0x00
-+#define CPU_SLEEP_FROZEN	0x01
-+#define CPU_SLEEP_STANDBY	0x02
-+#define CPU_SLEEP_STOP		0x03
-+#define CPU_SLEEP_DEEPSTOP	0x04	/* Not valid on AP700x */
-+#define CPU_SLEEP_STATIC	0x05
-+#define CPU_SLEEP_SHUTDOWN	0x06	/* Not valid on AP700x */
-+#define CPU_SLEEP_UNMASK_IRQ	0x80	/* Not valid on AP700x */
- 
- #ifndef __ASSEMBLY__
-+#if defined(CONFIG_CPU_AT32AP700X)
- extern void cpu_enter_idle(void);
- extern void cpu_enter_standby(unsigned long sdramc_base);
- 
-@@ -37,15 +41,57 @@
- {
- 	/*
- 	 * If we're using the COUNT and COMPARE registers for
--	 * timekeeping, we can't use the IDLE state.
-+	 * timekeeping on AP7000, we can't use the IDLE state.
- 	 */
- 	if (disable_idle_sleep)
- 		cpu_relax();
- 	else
- 		cpu_enter_idle();
- }
-+#else
-+static inline void cpu_disable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enter_idle(void)
-+{
-+	/* Enable interrupts and sleep */
-+	asm volatile("sleep %0"
-+			:
-+			: "i"(CPU_SLEEP_IDLE | CPU_SLEEP_UNMASK_IRQ)
-+			: "memory");
-+}
-+
-+static inline void cpu_idle_sleep(void)
-+{
-+	local_irq_disable();
-+	if (!test_thread_flag(TIF_NEED_RESCHED))
-+		cpu_enter_idle();
-+	local_irq_enable();
-+}
-+#endif
- 
- void intc_set_suspend_handler(unsigned long offset);
-+
-+extern unsigned long at32_get_reset_cause(void);
-+
- #endif
- 
-+#define AT32_RCAUSE_POR		(1 <<  0)	/* Power-On Reset */
-+#define AT32_RCAUSE_BOD		(1 <<  1)	/* Brown-Out Detected */
-+#define AT32_RCAUSE_EXT		(1 <<  2)	/* External Reset */
-+#define AT32_RCAUSE_WDT		(1 <<  3)	/* Watchdog Timeout */
-+#define AT32_RCAUSE_JTAG	(1 <<  4)	/* JTAG Reset */
-+#define AT32_RCAUSE_NTAE	(1 <<  5)	/* NanoTrace Access Error */
-+#define AT32_RCAUSE_SLEEP	(1 <<  6)	/* Shutdown or Static mode */
-+#define AT32_RCAUSE_CPUERR	(1 <<  7)	/* CPU Error */
-+#define AT32_RCAUSE_OCDRST	(1 <<  8)	/* OCD Reset */
-+#define AT32_RCAUSE_JTAGHARD	(1 <<  9)	/* JTAG Hard Reset */
-+
- #endif /* __ASM_AVR32_ARCH_PM_H */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/Makefile linux-2.6.28.2/arch/avr32/mach-at32ap/Makefile
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/Makefile	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/Makefile	2009-01-29 08:52:49.000000000 +0100
-@@ -1,9 +1,14 @@
--obj-y				+= pdc.o clock.o intc.o extint.o pio.o hsmc.o
-+obj-y				+= pdc.o clock.o intc.o extint.o hsmc.o
- obj-y				+= hmatrix.o
--obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_PORTMUX_PIO)	+= pio.o
-+obj-$(CONFIG_PORTMUX_GPIO_V2)	+= gpio-v2.o
-+obj-$(CONFIG_TIMER_AST)		+= timer-ast.o
- obj-$(CONFIG_CPU_FREQ_AT32AP)	+= cpufreq.o
- obj-$(CONFIG_PM)		+= pm.o
- 
-+obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_CPU_AT32AP720X)	+= at32ap720x.o pm-at32ap720x.o
-+
- ifeq ($(CONFIG_PM_DEBUG),y)
- CFLAGS_pm.o	+= -DDEBUG
- endif
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap700x.S linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap700x.S
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap700x.S	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap700x.S	2009-01-29 08:52:50.000000000 +0100
-@@ -12,12 +12,9 @@
- #include <asm/thread_info.h>
- #include <mach/pm.h>
- 
--#include "pm.h"
-+#include "pm-v1.h"
- #include "sdramc.h"
- 
--/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
--#define PM_BASE	-0x100000
--
- 	.section .bss, "wa", @nobits
- 	.global	disable_idle_sleep
- 	.type	disable_idle_sleep, @object
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap720x.S linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap720x.S
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-at32ap720x.S	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-at32ap720x.S	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,110 @@
-+/*
-+ * Low-level Power Management code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <asm/asm.h>
-+#include <asm/asm-offsets.h>
-+#include <asm/thread_info.h>
-+#include <mach/pm.h>
-+
-+#include "pm-v3.h"
-+#include "sdramc.h"
-+
-+#ifdef CONFIG_PM
-+	.section .init.text, "ax", @progbits
-+
-+	.global	pm_exception
-+	.type	pm_exception, @function
-+pm_exception:
-+	/*
-+	 * Exceptions are masked when we switch to this handler, so
-+	 * we'll only get "unrecoverable" exceptions (offset 0.)
-+	 */
-+	sub	r12, pc, . - .Lpanic_msg
-+	lddpc	pc, .Lpanic_addr
-+
-+	.align	2
-+.Lpanic_addr:
-+	.long	panic
-+.Lpanic_msg:
-+	.asciz	"Unrecoverable exception during suspend\n"
-+	.size	pm_exception, . - pm_exception
-+
-+	.global	pm_irq0
-+	.type	pm_irq0, @function
-+pm_irq0:
-+	/* Disable interrupts and return after the sleep instruction */
-+	mfsr	r9, SYSREG_RSR_INT0
-+	mtsr	SYSREG_RAR_INT0, r8
-+	sbr	r9, SYSREG_GM_OFFSET
-+	mtsr	SYSREG_RSR_INT0, r9
-+	rete
-+
-+	/*
-+	 * void cpu_enter_standby(unsigned long sdramc_base)
-+	 *
-+	 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
-+	 * are suspended and interrupts are disabled. Interrupts
-+	 * marked as 'wakeup' event sources may still come along and
-+	 * get us out of here.
-+	 *
-+	 * The SDRAM will be put into self-refresh mode (which does
-+	 * not require a clock from the CPU), and the CPU will be put
-+	 * into "frozen" mode (HSB bus stopped). The SDRAM controller
-+	 * will automatically bring the SDRAM into normal mode on the
-+	 * first access, and the power manager will automatically
-+	 * start the HSB and CPU clocks upon a wakeup event.
-+	 */
-+	.global	pm_standby
-+	.type	pm_standby, @function
-+pm_standby:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self Refresh */
-+	sync	0			/* flush write buffer */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+	sleep	CPU_SLEEP_FROZEN | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+	retal	r12
-+	.size	pm_standby, . - pm_standby
-+
-+	.global	pm_suspend_to_ram
-+	.type	pm_suspend_to_ram, @function
-+pm_suspend_to_ram:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	mov	r11, 0
-+	cache	r11[2], 8		/* clean all dcache lines */
-+	sync	0			/* flush write buffer */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self refresh */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+
-+	sleep	CPU_SLEEP_STOP | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+
-+	retal	r12
-+	.size	pm_suspend_to_ram, . - pm_suspend_to_ram
-+
-+	.global	pm_sram_end
-+	.type	pm_sram_end, @function
-+pm_sram_end:
-+	.size	pm_sram_end, 0
-+
-+#endif /* CONFIG_PM */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm.h	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm.h	1970-01-01 01:00:00.000000000 +0100
-@@ -1,112 +0,0 @@
--/*
-- * Register definitions for the Power Manager (PM)
-- */
--#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
--#define __ARCH_AVR32_MACH_AT32AP_PM_H__
--
--/* PM register offsets */
--#define PM_MCCTRL				0x0000
--#define PM_CKSEL				0x0004
--#define PM_CPU_MASK				0x0008
--#define PM_HSB_MASK				0x000c
--#define PM_PBA_MASK				0x0010
--#define PM_PBB_MASK				0x0014
--#define PM_PLL0					0x0020
--#define PM_PLL1					0x0024
--#define PM_IER					0x0040
--#define PM_IDR					0x0044
--#define PM_IMR					0x0048
--#define PM_ISR					0x004c
--#define PM_ICR					0x0050
--#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
--#define PM_RCAUSE				0x00c0
--
--/* Bitfields in CKSEL */
--#define PM_CPUSEL_OFFSET			0
--#define PM_CPUSEL_SIZE				3
--#define PM_CPUDIV_OFFSET			7
--#define PM_CPUDIV_SIZE				1
--#define PM_HSBSEL_OFFSET			8
--#define PM_HSBSEL_SIZE				3
--#define PM_HSBDIV_OFFSET			15
--#define PM_HSBDIV_SIZE				1
--#define PM_PBASEL_OFFSET			16
--#define PM_PBASEL_SIZE				3
--#define PM_PBADIV_OFFSET			23
--#define PM_PBADIV_SIZE				1
--#define PM_PBBSEL_OFFSET			24
--#define PM_PBBSEL_SIZE				3
--#define PM_PBBDIV_OFFSET			31
--#define PM_PBBDIV_SIZE				1
--
--/* Bitfields in PLL0 */
--#define PM_PLLEN_OFFSET				0
--#define PM_PLLEN_SIZE				1
--#define PM_PLLOSC_OFFSET			1
--#define PM_PLLOSC_SIZE				1
--#define PM_PLLOPT_OFFSET			2
--#define PM_PLLOPT_SIZE				3
--#define PM_PLLDIV_OFFSET			8
--#define PM_PLLDIV_SIZE				8
--#define PM_PLLMUL_OFFSET			16
--#define PM_PLLMUL_SIZE				8
--#define PM_PLLCOUNT_OFFSET			24
--#define PM_PLLCOUNT_SIZE			6
--#define PM_PLLTEST_OFFSET			31
--#define PM_PLLTEST_SIZE				1
--
--/* Bitfields in ICR */
--#define PM_LOCK0_OFFSET				0
--#define PM_LOCK0_SIZE				1
--#define PM_LOCK1_OFFSET				1
--#define PM_LOCK1_SIZE				1
--#define PM_WAKE_OFFSET				2
--#define PM_WAKE_SIZE				1
--#define PM_CKRDY_OFFSET				5
--#define PM_CKRDY_SIZE				1
--#define PM_MSKRDY_OFFSET			6
--#define PM_MSKRDY_SIZE				1
--
--/* Bitfields in GCCTRL0 */
--#define PM_OSCSEL_OFFSET			0
--#define PM_OSCSEL_SIZE				1
--#define PM_PLLSEL_OFFSET			1
--#define PM_PLLSEL_SIZE				1
--#define PM_CEN_OFFSET				2
--#define PM_CEN_SIZE				1
--#define PM_DIVEN_OFFSET				4
--#define PM_DIVEN_SIZE				1
--#define PM_DIV_OFFSET				8
--#define PM_DIV_SIZE				8
--
--/* Bitfields in RCAUSE */
--#define PM_POR_OFFSET				0
--#define PM_POR_SIZE				1
--#define PM_EXT_OFFSET				2
--#define PM_EXT_SIZE				1
--#define PM_WDT_OFFSET				3
--#define PM_WDT_SIZE				1
--#define PM_NTAE_OFFSET				4
--#define PM_NTAE_SIZE				1
--
--/* Bit manipulation macros */
--#define PM_BIT(name)					\
--	(1 << PM_##name##_OFFSET)
--#define PM_BF(name,value)				\
--	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
--	 << PM_##name##_OFFSET)
--#define PM_BFEXT(name,value)				\
--	(((value) >> PM_##name##_OFFSET)		\
--	 & ((1 << PM_##name##_SIZE) - 1))
--#define PM_BFINS(name,value,old)\
--	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
--		    << PM_##name##_OFFSET))		\
--	 | PM_BF(name,value))
--
--/* Register access macros */
--#define pm_readl(reg)							\
--	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
--#define pm_writel(reg,value)						\
--	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
--
--#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v1.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v1.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v1.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v1.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,112 @@
-+/*
-+ * Register definitions for the Power Manager (PM)
-+ */
-+#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
-+#define __ARCH_AVR32_MACH_AT32AP_PM_H__
-+
-+/* PM register offsets */
-+#define PM_MCCTRL				0x0000
-+#define PM_CKSEL				0x0004
-+#define PM_CPU_MASK				0x0008
-+#define PM_HSB_MASK				0x000c
-+#define PM_PBA_MASK				0x0010
-+#define PM_PBB_MASK				0x0014
-+#define PM_PLL0					0x0020
-+#define PM_PLL1					0x0024
-+#define PM_IER					0x0040
-+#define PM_IDR					0x0044
-+#define PM_IMR					0x0048
-+#define PM_ISR					0x004c
-+#define PM_ICR					0x0050
-+#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
-+#define PM_RCAUSE				0x00c0
-+
-+/* Bitfields in CKSEL */
-+#define PM_CPUSEL_OFFSET			0
-+#define PM_CPUSEL_SIZE				3
-+#define PM_CPUDIV_OFFSET			7
-+#define PM_CPUDIV_SIZE				1
-+#define PM_HSBSEL_OFFSET			8
-+#define PM_HSBSEL_SIZE				3
-+#define PM_HSBDIV_OFFSET			15
-+#define PM_HSBDIV_SIZE				1
-+#define PM_PBASEL_OFFSET			16
-+#define PM_PBASEL_SIZE				3
-+#define PM_PBADIV_OFFSET			23
-+#define PM_PBADIV_SIZE				1
-+#define PM_PBBSEL_OFFSET			24
-+#define PM_PBBSEL_SIZE				3
-+#define PM_PBBDIV_OFFSET			31
-+#define PM_PBBDIV_SIZE				1
-+
-+/* Bitfields in PLL0 */
-+#define PM_PLLEN_OFFSET				0
-+#define PM_PLLEN_SIZE				1
-+#define PM_PLLOSC_OFFSET			1
-+#define PM_PLLOSC_SIZE				1
-+#define PM_PLLOPT_OFFSET			2
-+#define PM_PLLOPT_SIZE				3
-+#define PM_PLLDIV_OFFSET			8
-+#define PM_PLLDIV_SIZE				8
-+#define PM_PLLMUL_OFFSET			16
-+#define PM_PLLMUL_SIZE				8
-+#define PM_PLLCOUNT_OFFSET			24
-+#define PM_PLLCOUNT_SIZE			6
-+#define PM_PLLTEST_OFFSET			31
-+#define PM_PLLTEST_SIZE				1
-+
-+/* Bitfields in ICR */
-+#define PM_LOCK0_OFFSET				0
-+#define PM_LOCK0_SIZE				1
-+#define PM_LOCK1_OFFSET				1
-+#define PM_LOCK1_SIZE				1
-+#define PM_WAKE_OFFSET				2
-+#define PM_WAKE_SIZE				1
-+#define PM_CKRDY_OFFSET				5
-+#define PM_CKRDY_SIZE				1
-+#define PM_MSKRDY_OFFSET			6
-+#define PM_MSKRDY_SIZE				1
-+
-+/* Bitfields in GCCTRL0 */
-+#define PM_OSCSEL_OFFSET			0
-+#define PM_OSCSEL_SIZE				1
-+#define PM_PLLSEL_OFFSET			1
-+#define PM_PLLSEL_SIZE				1
-+#define PM_CEN_OFFSET				2
-+#define PM_CEN_SIZE				1
-+#define PM_DIVEN_OFFSET				4
-+#define PM_DIVEN_SIZE				1
-+#define PM_DIV_OFFSET				8
-+#define PM_DIV_SIZE				8
-+
-+/* Bitfields in RCAUSE */
-+#define PM_POR_OFFSET				0
-+#define PM_POR_SIZE				1
-+#define PM_EXT_OFFSET				2
-+#define PM_EXT_SIZE				1
-+#define PM_WDT_OFFSET				3
-+#define PM_WDT_SIZE				1
-+#define PM_NTAE_OFFSET				4
-+#define PM_NTAE_SIZE				1
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)					\
-+	(1 << PM_##name##_OFFSET)
-+#define PM_BF(name,value)				\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
-+	 << PM_##name##_OFFSET)
-+#define PM_BFEXT(name,value)				\
-+	(((value) >> PM_##name##_OFFSET)		\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
-+		    << PM_##name##_OFFSET))		\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define pm_readl(reg)							\
-+	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
-+#define pm_writel(reg,value)						\
-+	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
-+
-+#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v3.h linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v3.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/pm-v3.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/pm-v3.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,283 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __PM_V3_H__
-+#define __PM_V3_H__
-+
-+#include <mach/chip.h>
-+
-+/* PM Register offsets */
-+#ifndef __ASSEMBLY__
-+struct pm_regs {
-+	u32	MCCTRL;			/* Main Clock Control */
-+	u32	CKSEL;			/* Clock Select */
-+	u32	CPUMASK;		/* CPU Clock Mask */
-+	u32	HSBMASK;		/* HSB Clock Mask */
-+	u32	PBAMASK;		/* PBA Clock Mask */
-+	u32	PBBMASK;		/* PBB Clock Mask */
-+	u32	PBADIVMASK;		/* Divided PBA Clock Mask */
-+	u32	PBBDIVMASK;		/* Divided PBB Clock Mask */
-+	u32	__reserved1[8];
-+	u32	PLL[3];			/* PLL Control */
-+	u32	__reserved2[13];
-+	u32	OSCCTRL[3];		/* Oscillator Control */
-+	u32	__reserved3[5];
-+	u32	OSCCTRL32;		/* 32 kHz Oscillator Control */
-+	u32	__reserved4[7];
-+	u32	IER;			/* Interrupt Enable */
-+	u32	IDR;			/* Interrupt Disable */
-+	u32	IMR;			/* Interrupt Mask */
-+	u32	ISR;			/* Interrupt Status */
-+	u32	ICR;			/* Interrupt Clear */
-+	u32	POSCSR;			/* Power and Oscillator Status */
-+	u32	__reserved5[10];
-+	u32	GCCTRL[8];		/* Generic Clock Control */
-+	u32	__reserved6[8];
-+	u32	RCCR;			/* RC Oscillator Calibration */
-+	u32	BGCR;			/* Bandgap Calibration */
-+	u32	VREGCR;			/* Buck Regulator Calibration */
-+	u32	BOD;			/* BOD Level */
-+	u32	PPCR;			/* Peripheral Power Control */
-+	u32	__reserved7[11];
-+	u32	RCAUSE;			/* Reset Cause */
-+	u32	WCAUSE;			/* Wake Cause */
-+	u32	AWEN;			/* Asynchronous Wake Enable */
-+	u32	__reserved8[14];
-+	u32	GPLP;			/* General Purpose Low-Power */
-+};
-+#endif
-+
-+/* Assembly-friendly register offsets; same as above */
-+#define PM_MCCTRL			0x0000
-+#define PM_CKSEL			0x0004
-+#define PM_CPUMASK			0x0008
-+#define PM_HSBMASK			0x000c
-+#define PM_PBAMASK			0x0010
-+#define PM_PBBMASK			0x0014
-+#define PM_PBADIVMASK			0x0018
-+#define PM_PBBDIVMASK			0x001c
-+#define PM_PLL0				0x0040
-+#define PM_PLL1				0x0044
-+#define PM_PLL2				0x0048
-+#define PM_OSCCTRL0			0x0080
-+#define PM_OSCCTRL1			0x0084
-+#define PM_OSCCTRL2			0x0088
-+#define PM_OSCCTRL32			0x00a0
-+#define PM_IER				0x00c0
-+#define PM_IDR				0x00c4
-+#define PM_IMR				0x00c8
-+#define PM_ISR				0x00cc
-+#define PM_ICR				0x00d0
-+#define PM_POSCSR			0x00d4
-+#define PM_GCCTRL			0x0100
-+#define PM_RCCR				0x0140
-+#define PM_BGCR				0x0144
-+#define PM_VREGCR			0x0148
-+#define PM_BOD				0x014c
-+#define PM_PPCR				0x0150
-+#define PM_RC_RCAUSE			0x0180
-+#define PM_WCAUSE			0x0184
-+#define PM_AWEN				0x0188
-+#define PM_GPLP				0x01c0
-+
-+/* Bits in MCCTRL */
-+#define PM_MCCTRL_MCSEL_START		0
-+#define PM_MCCTRL_MCSEL_SIZE		2
-+#define PM_MCCTRL_OSC0EN_BIT		2
-+#define PM_MCCTRL_OSC1EN_BIT		3
-+#define PM_MCCTRL_OSC2EN_BIT		4
-+#define PM_MCCTRL_CRIPEL_BIT		24
-+
-+/* Bits in CKSEL */
-+#define PM_CKSEL_CPUSEL_START		0
-+#define PM_CKSEL_CPUSEL_SIZE		3
-+#define PM_CKSEL_CPUDIV_BIT		7
-+#define PM_CKSEL_HSBSEL_START		8
-+#define PM_CKSEL_HSBSEL_SIZE		3
-+#define PM_CKSEL_HSBDIV_BIT		15
-+#define PM_CKSEL_PBASEL_START		16
-+#define PM_CKSEL_PBASEL_SIZE		3
-+#define PM_CKSEL_PBADIV_BIT		23
-+#define PM_CKSEL_PBBSEL_START		24
-+#define PM_CKSEL_PBBSEL_SIZE		3
-+#define PM_CKSEL_PBBDIV_BIT		31
-+
-+/* Bits in CPUMASK */
-+#define PM_CPUMASK_SYSTIMER_BIT		16
-+
-+/* Bits in PLLx */
-+#define PM_PLLx_PLLEN_BIT		0
-+#define PM_PLLx_PLLOSC_START		1
-+#define PM_PLLx_PLLOSC_SIZE		2
-+#define PM_PLLx_PLLOPT_START		3
-+#define PM_PLLx_PLLOPT_SIZE		3
-+#define PM_PLLx_PLLBPL_BIT		7
-+#define PM_PLLx_PLLDIV_START		8
-+#define PM_PLLx_PLLDIV_SIZE		6
-+#define PM_PLLx_PLLMUL_START		16
-+#define PM_PLLx_PLLMUL_SIZE		6
-+#define PM_PLLx_PLLCOUNT_START		24
-+#define PM_PLLx_PLLCOUNT_SIZE		6
-+#define PM_PLLx_PLLIOTESTEN_BIT		30
-+#define PM_PLLx_PLLTEST_BIT		31
-+
-+/* Bits in OSCCTRLx */
-+#define PM_OSCCTRLx_MODE_START		0
-+#define PM_OSCCTRLx_MODE_SIZE		4
-+#define PM_OSCCTRLx_STARTUP_START	8
-+#define PM_OSCCTRLx_STARTUP_SIZE	3
-+
-+/* Bits in OSCCTRL32 */
-+#define PM_OSCCTRL32_OSC32EN_BIT	0
-+#define PM_OSCCTRL32_MODE_START		8
-+#define PM_OSCCTRL32_MODE_SIZE		3
-+#define PM_OSCCTRL32_STARTUP_START	16
-+#define PM_OSCCTRL32_STARTUP_SIZE	3
-+
-+/* Bits in IER/IDR/IMR/ISR/ICR */
-+#define PM_ISR_OSC0RDY_BIT		0
-+#define PM_ISR_OSC1RDY_BIT		1
-+#define PM_ISR_OSC2RDY_BIT		2
-+#define PM_ISR_OSC32RDY_BIT		7
-+#define PM_ISR_LOCK0_BIT		8
-+#define PM_ISR_LOCK1_BIT		9
-+#define PM_ISR_LOCK2_BIT		10
-+#define PM_ISR_LOCK0LOST_BIT		16
-+#define PM_ISR_LOCK1LOST_BIT		17
-+#define PM_ISR_LOCK2LOST_BIT		18
-+#define PM_ISR_CKRDY_BIT		24
-+#define PM_ISR_MSKRDY_BIT		25
-+#define PM_ISR_WAKE_BIT			26
-+#define PM_ISR_BODDET_BIT		27
-+#define PM_ISR_PERRDY_BIT		28
-+
-+/* Bits in POSCSR */
-+#define PM_POSCSR_OSC0RDY_BIT		0
-+#define PM_POSCSR_OSC1RDY_BIT		1
-+#define PM_POSCSR_OSC32RDY_BIT		7
-+#define PM_POSCSR_LOCK0_BIT		8
-+#define PM_POSCSR_LOCK1_BIT		9
-+#define PM_POSCSR_LOCK0LOST_BIT		16
-+#define PM_POSCSR_LOCK1LOST_BIT		17
-+#define PM_POSCSR_CKRDY_BIT		24
-+#define PM_POSCSR_MSKRDY_BIT		25
-+#define PM_POSCSR_WAKE_BIT		26
-+#define PM_POSCSR_BODDET_BIT		27
-+#define PM_POSCSR_PERRDY_BIT		28
-+
-+/* Bits in GCCTRL */
-+#define PM_GCCTRL_CEN_BIT		0
-+#define PM_GCCTRL_DIVEN_BIT		1
-+#define PM_GCCTRL_OSCSEL_START		8
-+#define PM_GCCTRL_OSCSEL_SIZE		4
-+#define PM_GCCTRL_DIV_START		16
-+#define PM_GCCTRL_DIV_SIZE		8
-+
-+/* Bits in RCCR */
-+#define PM_RCCR_CALIB_START		0
-+#define PM_RCCR_CALIB_SIZE		10
-+#define PM_RCCR_FCD_BIT			16
-+#define PM_RCCR_KEY_START		24
-+#define PM_RCCR_KEY_SIZE		8
-+
-+/* Bits in BGCR */
-+#define PM_BGCR_CALIB_START		0
-+#define PM_BGCR_CALIB_SIZE		3
-+#define PM_BGCR_FCD_BIT			16
-+#define PM_BGCR_KEY_START		24
-+#define PM_BGCR_KEY_SIZE		8
-+
-+/* Bits in VREGCR */
-+#define PM_VREGCR_CALIB_START		0
-+#define PM_VREGCR_CALIB_SIZE		3
-+#define PM_VREGCR_FCD_BIT		16
-+#define PM_VREGCR_KEY_START		24
-+#define PM_VREGCR_KEY_SIZE		8
-+
-+/* Bits in BOD */
-+#define PM_BOD_LEVEL_START		0
-+#define PM_BOD_LEVEL_SIZE		6
-+#define PM_BOD_HYST_BIT			6
-+#define PM_BOD_CTRL_START		8
-+#define PM_BOD_CTRL_SIZE		2
-+#define PM_BOD_FCD_BIT			16
-+#define PM_BOD_KEY_START		24
-+#define PM_BOD_KEY_SIZE			8
-+
-+/* Bits in PPCR */
-+#define PM_PPCR_EBI_VOLT_BIT		0
-+#define PM_PPCR_UTMI_CTRL_BIT		1
-+#define PM_PPCR_KEY_START		24
-+#define PM_PPCR_KEY_SIZE		8
-+
-+/* Bits in RC_RCAUSE */
-+#define PM_RC_RCAUSE_POR_BIT		0
-+#define PM_RC_RCAUSE_BOD_BIT		1
-+#define PM_RC_RCAUSE_EXT_BIT		2
-+#define PM_RC_RCAUSE_WDT_BIT		3
-+#define PM_RC_RCAUSE_JTAG_BIT		4
-+#define PM_RC_RCAUSE_NTAE_BIT		5
-+#define PM_RC_RCAUSE_SLEEP_BIT		6
-+#define PM_RC_RCAUSE_CPUERR_BIT		7
-+#define PM_RC_RCAUSE_OCDRST_BIT		8
-+#define PM_RC_RCAUSE_JTAGHARD_BIT	9
-+
-+/* Bits in WCAUSE */
-+#define PM_WCAUSE_PERIPH0_BIT		0
-+#define PM_WCAUSE_PERIPH1_BIT		1
-+#define PM_WCAUSE_EIC_BIT		16
-+#define PM_WCAUSE_RTC_BIT		17
-+
-+/* Constants for MCCTRL:MCSEL */
-+#define PM_MCSEL_SLOW			0
-+#define PM_MCSEL_OSC0			1
-+#define PM_MCSEL_PLL0			2
-+
-+/* Constants for OSCCTRLx:MODE */
-+#define PM_MODE_EXT_CLOCK		0
-+#define PM_MODE_CRYSTAL_ACG		1
-+#define PM_MODE_CRYSTAL_G0		4
-+#define PM_MODE_CRYSTAL_G1		5
-+#define PM_MODE_CRYSTAL_G2		6
-+#define PM_MODE_CRYSTAL_G3		7
-+
-+/* Constants for GCCTRL:OSCSEL */
-+#define PM_OSCSEL_SLOW			0
-+#define PM_OSCSEL_CLK32			1
-+#define PM_OSCSEL_OSC0			2
-+#define PM_OSCSEL_OSC1			3
-+#define PM_OSCSEL_PLL0			4
-+#define PM_OSCSEL_PLL1			5
-+
-+/* Constants for BOD:CTRL */
-+#define PM_CTRL_OFF1			0
-+#define PM_CTRL_ENABLED			1
-+#define PM_CTRL_ENABLED_NORESET		2
-+#define PM_CTRL_OFF2			3
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)						\
-+	(1 << PM_##name##_BIT)
-+#define PM_BF(name,value)					\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))		\
-+	 << PM_##name##_START)
-+#define PM_BFEXT(name,value)					\
-+	(((value) >> PM_##name##_START)				\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)		\
-+		    << PM_##name##_START))			\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define __pm_regs ((struct pm_regs __iomem __force *)PM_BASE)
-+#define pm_readl(reg)						\
-+	__raw_readl(&__pm_regs->reg)
-+#define pm_writel(reg, value)					\
-+	__raw_writel(value, &__pm_regs->reg)
-+
-+#endif /* __PM_V3_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/sdc.h linux-2.6.28.2/arch/avr32/mach-at32ap/sdc.h
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/sdc.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/sdc.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,103 @@
-+/* SDC */
-+
-+/* Register offsets */
-+#define SDC_CTRL			0x0000
-+#define SDC_ASYNC			0x0004
-+#define SDC_SYNC			0x0008
-+#define SDC_FILTERDUR			0x000c
-+#define SDC_OSCCTRL32			0x0010
-+#define SDC_STATUS			0x0014
-+#define SDC_ECR				0x0018
-+#define SDC_IER				0x001c
-+#define SDC_IDR				0x0020
-+#define SDC_IMR				0x0024
-+#define SDC_GPLP			0x0040
-+
-+/* Bits in CTRL */
-+#define SDC_CTRL_PIN_EN_BIT		0
-+#define SDC_CTRL_AST_EN_BIT		8
-+#define SDC_CTRL_WDT_EN_BIT		9
-+#define SDC_CTRL_OCD_EN_BIT		10
-+#define SDC_CTRL_JTAG_EN_BIT		11
-+#define SDC_CTRL_CORE_POR_TEST_BIT	23
-+#define SDC_CTRL_KEY_START		24
-+#define SDC_CTRL_KEY_SIZE		8
-+
-+/* Bits in ASYNC */
-+#define SDC_ASYNC_MODE_BIT		4
-+#define SDC_ASYNC_POL_BIT		8
-+#define SDC_ASYNC_KEY_START		24
-+#define SDC_ASYNC_KEY_SIZE		8
-+
-+/* Bits in SYNC */
-+#define SDC_SYNC_EN_BIT			0
-+#define SDC_SYNC_MODE_BIT		4
-+#define SDC_SYNC_POL_BIT		8
-+#define SDC_SYNC_FILTER_BIT		12
-+#define SDC_SYNC_KEY_START		24
-+#define SDC_SYNC_KEY_SIZE		8
-+
-+/* Bits in FILTERDUR */
-+#define SDC_FILTERDUR_Duration_START	0
-+#define SDC_FILTERDUR_Duration_SIZE	16
-+#define SDC_FILTERDUR_KEY_START		24
-+#define SDC_FILTERDUR_KEY_SIZE		8
-+
-+/* Bits in OSCCTRL32 */
-+#define SDC_OSCCTRL32_OSC32EN_BIT	0
-+#define SDC_OSCCTRL32_MODE_START	8
-+#define SDC_OSCCTRL32_MODE_SIZE		4
-+#define SDC_OSCCTRL32_STARTUP_START	16
-+#define SDC_OSCCTRL32_STARTUP_SIZE	3
-+#define SDC_OSCCTRL32_KEY_START		24
-+#define SDC_OSCCTRL32_KEY_SIZE		8
-+
-+/* Bits in STATUS */
-+#define SDC_STATUS_PIN_EVENT_BIT	0
-+#define SDC_STATUS_AST_EVENT_BIT	8
-+#define SDC_STATUS_WDT_EVENT_BIT	9
-+#define SDC_STATUS_OCD_EVENT_BIT	10
-+#define SDC_STATUS_JTAG_EVENT_BIT	11
-+#define SDC_STATUS_PIN_BIT		16
-+#define SDC_STATUS_BUSY_BIT		24
-+#define SDC_STATUS_SWTCH_BIT		30
-+#define SDC_STATUS_VBAT_BIT		31
-+
-+/* Bits in ECR */
-+#define SDC_ECR_PIN_EVENT_BIT		0
-+#define SDC_ECR_AST_EVENT_BIT		8
-+#define SDC_ECR_WDT_EVENT_BIT		9
-+#define SDC_ECR_OCD_EVENT_BIT		10
-+#define SDC_ECR_JTAG_EVENT_BIT		11
-+
-+/* Bits in IER */
-+#define SDC_IER_PIN_EVENT_BIT		0
-+#define SDC_IER_READY_BIT		24
-+
-+/* Bits in IDR */
-+#define SDC_IDR_PIN_EVENT_BIT		0
-+#define SDC_IDR_READY_BIT		24
-+
-+/* Bits in IMR */
-+#define SDC_IMR_PIN_EVENT_BIT		0
-+#define SDC_IMR_READY_BIT		24
-+
-+/* Bit manipulation macros */
-+#define SDC_BIT(name)						\
-+	(1 << SDC_##name##_BIT)
-+#define SDC_BF(name,value)					\
-+	(((value) & ((1 << SDC_##name##_SIZE) - 1))		\
-+	 << SDC_##name##_START)
-+#define SDC_BFEXT(name,value)					\
-+	(((value) >> SDC_##name##_START)			\
-+	 & ((1 << SDC_##name##_SIZE) - 1))
-+#define SDC_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << SDC_##name##_SIZE) - 1)		\
-+		    << SDC_##name##_START))			\
-+	 | SDC_BF(name,value))
-+
-+/* Register access macros */
-+#define sdc_readl(reg)						\
-+	__raw_readl((void __iomem __force *)(SDC_BASE + SDC_##reg))
-+#define sdc_writel(reg, value)					\
-+	__raw_writel(value, (void __iomem __force *)(SDC_BASE + SDC_##reg))
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/timer-ast.c linux-2.6.28.2/arch/avr32/mach-at32ap/timer-ast.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/timer-ast.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/timer-ast.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,191 @@
-+/*
-+ * Asynchronous Timer (AST) used as clocksource / clockevent
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/clockchips.h>
-+#include <linux/clocksource.h>
-+#include <linux/interrupt.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/ast_regs.h>
-+
-+static void __iomem *ast_regs;
-+
-+static inline void ast_wait_ready(void)
-+{
-+	while (ast_readl(ast_regs, SR) & AST_BIT(BUSY))
-+		cpu_relax();
-+}
-+
-+static cycle_t read_ast_counter(void)
-+{
-+	return ast_readl(ast_regs, CV);
-+}
-+
-+static struct clocksource ast_clksrc = {
-+	.name	= "ast",
-+	.rating	= 400,
-+	.read	= read_ast_counter,
-+	.mask	= CLOCKSOURCE_MASK(32),
-+	.shift	= 16,
-+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static irqreturn_t ast_clkevt_interrupt(int irq, void *dev_id)
-+{
-+	struct clock_event_device *clkevt = dev_id;
-+
-+	/*
-+	 * We make sure delta is always long enough so that the BUSY
-+	 * bit is never set at this point.
-+	 */
-+	ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+	clkevt->event_handler(clkevt);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ast_clkevt_irqaction = {
-+	.handler	= ast_clkevt_interrupt,
-+	.flags		= IRQF_TIMER | IRQF_DISABLED,
-+	.name		= "timer-ast",
-+};
-+
-+static int ast_next_event(unsigned long delta,
-+		struct clock_event_device *clkevt)
-+{
-+	ast_wait_ready();
-+	ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) + delta);
-+
-+	return 0;
-+}
-+
-+static void ast_mode(enum clock_event_mode mode,
-+		struct clock_event_device *evdev)
-+{
-+	switch (mode) {
-+	case CLOCK_EVT_MODE_ONESHOT:
-+	case CLOCK_EVT_MODE_RESUME:
-+		/* Make sure we don't trigger an alarm before we get
-+		 * around to reprogramming it.
-+		 */
-+		ast_wait_ready();
-+		ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) - 1);
-+		ast_wait_ready();
-+		ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+		ast_wait_ready();
-+		ast_writel(ast_regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case CLOCK_EVT_MODE_UNUSED:
-+	case CLOCK_EVT_MODE_SHUTDOWN:
-+		ast_writel(ast_regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static struct clock_event_device ast_clkevt = {
-+	.name		= "ast",
-+	.features	= CLOCK_EVT_FEAT_ONESHOT,
-+	.shift		= 16,
-+	.rating		= 400,
-+	.cpumask	= CPU_MASK_CPU0,
-+	.set_next_event	= ast_next_event,
-+	.set_mode	= ast_mode,
-+};
-+
-+void __init ast_time_init(struct platform_device *pdev, unsigned int clksel)
-+{
-+	struct clk *clk, *pclk;
-+	struct resource *regs;
-+	unsigned long ast_hz;
-+	int irq;
-+	int ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		pr_debug("AST: No MMIO resource\n");
-+		return;
-+	}
-+
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk) {
-+		pr_debug("AST: No peripheral clock (pclk)\n");
-+		return;
-+	}
-+	clk_enable(pclk);
-+
-+	/* Too early for ioremap() */
-+	ast_regs = (void __iomem __force *)regs->start;
-+
-+	switch (clksel) {
-+	case AST_CLOCK_SLOW:
-+		clk = clk_get(NULL, "rcosc");
-+		break;
-+	case AST_CLOCK_OSC32:
-+		clk = clk_get(NULL, "osc32");
-+		break;
-+	case AST_CLOCK_PB:
-+		clk = pclk;
-+		break;
-+	case AST_CLOCK_GC:
-+		clk = clk_get(&pdev->dev, "gclk");
-+		break;
-+	default:
-+		clk = NULL;
-+		break;
-+	}
-+
-+	if (!clk) {
-+		pr_debug("AST: clock %u invalid, using pb clock\n", clksel);
-+		clk = pclk;
-+	}
-+	clk_enable(clk);
-+
-+	ast_writel(ast_regs, CLOCK,
-+			AST_BF(CLOCK_CSSEL, clksel) | AST_BIT(CLOCK_CEN));
-+	ast_writel(ast_regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR));
-+
-+	/* Using hardcoded divide-by-two prescaler */
-+	ast_hz = clk_get_rate(clk) / 2;
-+	ast_clksrc.mult = clocksource_hz2mult(ast_hz, ast_clksrc.shift);
-+
-+	ret = clocksource_register(&ast_clksrc);
-+	if (ret)
-+		pr_debug("AST: could not register clocksource: %d\n", ret);
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		pr_debug("AST: No IRQ resource, won't setup clockevent\n");
-+		return;
-+	}
-+
-+	ast_clkevt.mult = div_sc(ast_hz, NSEC_PER_SEC, ast_clkevt.shift);
-+	ast_clkevt.max_delta_ns = clockevent_delta2ns((u32)~0U, &ast_clkevt);
-+	ast_clkevt.min_delta_ns = clockevent_delta2ns(2, &ast_clkevt) + 100;
-+
-+	ast_clkevt_irqaction.dev_id = &ast_clkevt;
-+
-+	ret = setup_irq(irq, &ast_clkevt_irqaction);
-+	if (ret) {
-+		pr_debug("AST: Could not request IRQ %d: %d\n", irq, ret);
-+		return;
-+	}
-+
-+	clockevents_register_device(&ast_clkevt);
-+
-+	pr_info("Using Asynchronous Timer %d @ %lu.%03lu Mhz"
-+			" (regs 0x%p, irq %d)\n",
-+			pdev->id, ((ast_hz + 500) / 1000) / 1000,
-+			((ast_hz + 500) / 1000) % 1000, ast_regs, irq);
-+}
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mm/tlb.c linux-2.6.28.2/arch/avr32/mm/tlb.c
---- linux-2.6.28.2-0rig//arch/avr32/mm/tlb.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mm/tlb.c	2009-01-29 08:52:50.000000000 +0100
-@@ -12,7 +12,13 @@
- #include <asm/mmu_context.h>
- 
- /* TODO: Get the correct number from the CONFIG1 system register */
--#define NR_TLB_ENTRIES 32
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# define NR_TLB_ENTRIES 32
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# define NR_TLB_ENTRIES 64
-+#else
-+# error Unknown CPU type
-+#endif
- 
- static void show_dtlb_entry(unsigned int index)
- {
-@@ -85,9 +91,15 @@
- 		u32 tlbar = sysreg_read(TLBARLO);
- 
- 		rp = 32 - fls(tlbar);
--		if (rp == 32) {
-+		if (NR_TLB_ENTRIES > 32 && rp >= 32) {
-+			tlbar = sysreg_read(TLBARHI);
-+			rp = 64 - fls(tlbar);
-+		}
-+		if (rp >= NR_TLB_ENTRIES) {
- 			rp = 0;
- 			sysreg_write(TLBARLO, -1L);
-+			if (NR_TLB_ENTRIES > 32)
-+				sysreg_write(TLBARHI, -1L);
- 		}
- 
- 		mmucr = SYSREG_BFINS(DRP, rp, mmucr);
-@@ -131,16 +143,22 @@
- 
- 	if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
- 		unsigned int entry;
--		u32 tlbarlo;
-+		u32 tlbarlo, tlbarhi;
- 
- 		/* Clear the "valid" bit */
- 		sysreg_write(TLBEHI, tlbehi);
- 
- 		/* mark the entry as "not accessed" */
- 		entry = SYSREG_BFEXT(DRP, mmucr);
--		tlbarlo = sysreg_read(TLBARLO);
--		tlbarlo |= (0x80000000UL >> entry);
--		sysreg_write(TLBARLO, tlbarlo);
-+		if (NR_TLB_ENTRIES > 32 && entry > 32) {
-+			tlbarhi = sysreg_read(TLBARHI);
-+			tlbarhi |= (0x80000000UL >> (entry - 32));
-+			sysreg_write(TLBARHI, tlbarhi);
-+		} else {
-+			tlbarlo = sysreg_read(TLBARLO);
-+			tlbarlo |= (0x80000000UL >> entry);
-+			sysreg_write(TLBARLO, tlbarlo);
-+		}
- 
- 		/* update the entry with valid bit clear */
- 		__builtin_tlbw();
-@@ -179,9 +197,10 @@
- 		unsigned long flags;
- 		int size;
- 
--		local_irq_save(flags);
- 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- 
-+		local_irq_save(flags);
-+
- 		if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
- 			mm->context = NO_CONTEXT;
- 			if (mm == current->mm)
-diff -urN linux-2.6.28.2-0rig//drivers/dma/atmel_pdca.c linux-2.6.28.2/drivers/dma/atmel_pdca.c
---- linux-2.6.28.2-0rig//drivers/dma/atmel_pdca.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/dma/atmel_pdca.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,668 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#define DEBUG
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/scatterlist.h>
-+#include <linux/spinlock.h>
-+
-+/*
-+ * Since each descriptor can hold a whole scatterlist, we don't need
-+ * many of them.
-+ */
-+#define NR_DESCS_PER_CHANNEL	8
-+
-+static struct pdca_desc *pdca_desc_entry(struct list_head *node)
-+{
-+	return list_entry(node, struct pdca_desc, desc_node);
-+}
-+
-+static struct pdca_desc *pdca_next_desc(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	if (desc->desc_node.next != &pch->queue)
-+		return pdca_desc_entry(desc->desc_node.next);
-+	return NULL;
-+}
-+
-+static struct pdca_desc *pdca_desc_get(struct pdca_chan *pch)
-+{
-+	struct pdca_desc		*desc = NULL;
-+
-+	spin_lock_bh(&pch->lock);
-+	if (likely(!list_empty(&pch->freelist))) {
-+		desc = pdca_desc_entry(pch->freelist.next);
-+		list_del(&desc->desc_node);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+
-+	return desc;
-+}
-+
-+static dma_cookie_t pdca_assign_cookie(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	dma_cookie_t cookie = pch->chan.cookie;
-+
-+	if (++cookie < 0)
-+		cookie = 1;
-+
-+	pch->chan.cookie = cookie;
-+	desc->txd.cookie = cookie;
-+
-+	return cookie;
-+}
-+
-+static void pdca_desc_done(struct pdca_chan *pch, struct pdca_desc *desc)
-+{
-+	struct dma_async_tx_descriptor	*txd = &desc->txd;
-+	dma_async_tx_callback		callback;
-+	void				*param;
-+
-+	pch->completed = txd->cookie;
-+	callback = txd->callback;
-+	param = txd->callback_param;
-+
-+	dev_vdbg(&pch->chan.dev, "  completed %u\n", txd->cookie);
-+
-+	/*
-+	 * We can only handle scatterlists, so this is easy. No other
-+	 * drivers do the right thing with scatterlists though...
-+	 *
-+	 * Note that we ensure that at least one of these flags are
-+	 * set when the descriptor is prepared, as we never need to
-+	 * unmap the peripheral side.
-+	 */
-+	if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_FROM_DEVICE);
-+	if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_TO_DEVICE);
-+
-+	list_move(&desc->desc_node, &pch->freelist);
-+
-+	if (callback)
-+		callback(param);
-+}
-+
-+static void pdca_chan_tasklet(unsigned long param)
-+{
-+	struct pdca_chan		*pch = (struct pdca_chan *)param;
-+	void __iomem			*regs = pch->regs;
-+	struct pdca_desc		*cur;
-+	struct pdca_desc		*next;
-+	struct scatterlist		*cur_sg;
-+	struct scatterlist		*next_sg;
-+	u32				intflags;
-+	u32				status;
-+
-+	spin_lock(&pch->lock);
-+
-+	cur = pdca_desc_entry(pch->queue.next);
-+	next = pdca_next_desc(pch, cur);
-+
-+	cur_sg = pch->cur_sg;
-+	next_sg = pch->next_sg;
-+
-+	intflags = PDCA_TERR | PDCA_TRC | PDCA_RCZ;
-+
-+	status = pdca_readl(regs, ISR);
-+	dev_vdbg(&pch->chan.dev, "tasklet: status=%08x\n", status);
-+
-+	if (status & PDCA_TRC) {
-+		if (cur_sg) {
-+			if (sg_is_last(cur_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  cur sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (next_sg && sg_is_last(next_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  next sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (!cur) {
-+				dev_vdbg(&pch->chan.dev, "  all done\n");
-+				pdca_writel(regs, CR, PDCA_CR_TDIS);
-+				cur_sg = next_sg = NULL;
-+				intflags = 0;
-+				goto done;
-+			}
-+			cur_sg = next_sg ? sg_next(next_sg) : NULL;
-+		}
-+
-+		if (!cur_sg) {
-+			dev_vdbg(&pch->chan.dev, "  load sg from %u\n",
-+					cur->txd.cookie);
-+			cur_sg = cur->sg;
-+			pdca_writel(regs, PSR, cur->periph_id);
-+			pdca_writel(regs, MR, cur->reg_width);
-+		}
-+		dev_vdbg(&pch->chan.dev, "  START: %08x count: %08x\n",
-+				sg_dma_address(cur_sg),
-+				sg_dma_len(cur_sg) >> cur->reg_width);
-+		pdca_writel(regs, MAR, sg_dma_address(cur_sg));
-+		pdca_writel(regs, TCR, sg_dma_len(cur_sg) >> cur->reg_width);
-+
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id) {
-+				dev_vdbg(&pch->chan.dev,
-+						"loading next_sg from %u\n",
-+						next->txd.cookie);
-+				next_sg = next->sg;
-+			}
-+		}
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	} else if (next_sg && (status & PDCA_RCZ)) {
-+		if (sg_is_last(cur_sg)) {
-+			dev_vdbg(&pch->chan.dev, "  cur sg was last in %u\n",
-+					cur->txd.cookie);
-+			next = pdca_next_desc(pch, cur);
-+			pdca_desc_done(pch, cur);
-+			cur = next;
-+			next = NULL;
-+		}
-+
-+		cur_sg = next_sg;
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id)
-+				next_sg = next->sg;
-+		}
-+
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			dev_vdbg(&pch->chan.dev, "  no next sg\n");
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	}
-+
-+done:
-+	if (status & PDCA_TERR) {
-+		/*
-+		 * Head of queue is busted. We must remove it, clear
-+		 * the error and restart the queue.
-+		 */
-+		pdca_writel(regs, TCRR, 0);
-+		pdca_writel(regs, TCR, 0);
-+		pdca_writel(regs, CR, PDCA_CR_ECLR);
-+		cur_sg = next_sg = NULL;
-+
-+		if (!cur)
-+			dev_err(&pch->chan.dev,
-+					"Transfer Error with empty queue\n");
-+		else {
-+			dev_vdbg(&pch->chan.dev,
-+					"  %u is busted\n", cur->txd.cookie);
-+			pdca_desc_done(pch, cur);
-+		}
-+
-+		if (list_empty(&pch->queue)) {
-+			pdca_writel(regs, CR, PDCA_CR_TDIS);
-+			intflags = 0;
-+		}
-+	}
-+
-+	pch->cur_sg = cur_sg;
-+	pch->next_sg = next_sg;
-+
-+	dev_vdbg(&pch->chan.dev, "  enabling interrupts: %08x\n", intflags);
-+	pdca_writel(regs, IER, intflags);
-+	pdca_readl(regs, SR);
-+
-+	spin_unlock(&pch->lock);
-+}
-+
-+static irqreturn_t pdca_interrupt(int irq, void *dev_id)
-+{
-+	struct pdca_dev			*pdca = dev_id;
-+	struct pdca_chan		*pch;
-+	void __iomem			*regs;
-+	unsigned long			pending;
-+	unsigned int			chan;
-+
-+	pending = intc_get_pending(irq);
-+	if (unlikely(!pending))
-+		return IRQ_NONE;
-+
-+	do {
-+		chan = __ffs(pending);
-+		pch = &pdca->chan[chan];
-+		regs = pch->regs;
-+		pdca_writel(regs, IDR, ~0UL);
-+		tasklet_schedule(&pch->tasklet);
-+		pdca_readl(regs, IMR);
-+		pending &= ~(1 << chan);
-+	} while (pending);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static dma_cookie_t pdca_tx_submit(struct dma_async_tx_descriptor *txd)
-+{
-+	struct pdca_desc		*desc = txd_to_pdca_desc(txd);
-+	struct pdca_chan		*pch = dma_to_pdca_chan(txd->chan);
-+	void __iomem			*regs = pch->regs;
-+	dma_cookie_t			cookie;
-+
-+	spin_lock_bh(&pch->lock);
-+	cookie = pdca_assign_cookie(pch, desc);
-+	dev_vdbg(&pch->chan.dev, "submitted %u\n", cookie);
-+	list_add_tail(&desc->desc_node, &pch->queue);
-+	pdca_writel(regs, CR, PDCA_CR_TEN);
-+	pdca_writel(regs, IER, PDCA_TERR | PDCA_RCZ);
-+	/* The tasklet will kickstart the queue if necessary */
-+	spin_unlock_bh(&pch->lock);
-+
-+	return cookie;
-+}
-+
-+static struct dma_async_tx_descriptor *pdca_prep_slave_sg(struct dma_chan *chan,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		enum dma_data_direction direction, unsigned long flags)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_slave		*pslave = pch->pslave;
-+	struct pdca_desc		*desc;
-+	unsigned int			periph_id;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		periph_id = pslave->tx_periph_id;
-+		flags |= DMA_COMPL_SKIP_DEST_UNMAP;
-+		break;
-+	case DMA_FROM_DEVICE:
-+		periph_id = pslave->rx_periph_id;
-+		flags |= DMA_COMPL_SKIP_SRC_UNMAP;
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	desc = pdca_desc_get(pch);
-+	if (!desc) {
-+		dev_err(&chan->dev,
-+			"not enough descriptors available\n");
-+		return NULL;
-+	}
-+	desc->sg = sgl;
-+	desc->sg_len = sg_len;
-+	desc->periph_id = periph_id;
-+	desc->reg_width = pslave->slave.reg_width;
-+	desc->txd.flags = flags;
-+
-+	return &desc->txd;
-+}
-+
-+static void pdca_terminate_all(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_desc		*desc, *_desc;
-+	void __iomem			*regs = pch->regs;
-+
-+	spin_lock_bh(&pch->lock);
-+	pdca_writel(regs, CR, PDCA_CR_TDIS);
-+	pdca_writel(regs, TCRR, 0);
-+	pdca_writel(regs, TCR, 0);
-+	while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		cpu_relax();
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->queue, desc_node)
-+		pdca_desc_done(pch, desc);
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static enum dma_status pdca_is_tx_complete(struct dma_chan *chan,
-+		dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	dma_cookie_t			last_used;
-+	dma_cookie_t			last_complete;
-+
-+	last_complete = pch->completed;
-+	last_used = chan->cookie;
-+
-+	if (done)
-+		*done = last_complete;
-+	if (used)
-+		*used = last_used;
-+
-+	return dma_async_is_complete(cookie, last_complete, last_used);
-+}
-+
-+static void pdca_issue_pending(struct dma_chan *chan)
-+{
-+	/* We always issue descriptors ASAP */
-+}
-+
-+static int pdca_alloc_chan_resources(struct dma_chan *chan,
-+		struct dma_client *client)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct dma_slave		*slave = client->slave;
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * Channels doing slave DMA can only handle one client. This
-+	 * controller can only do slave DMA.
-+	 */
-+	if (chan->client_count)
-+		return -EBUSY;
-+	if (!slave || !slave->dma_dev || slave->dma_dev != pdca->dma.dev)
-+		return -EINVAL;
-+
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		dev_err(&chan->dev, "DMA channel not idle!\n");
-+
-+	/*
-+	 * We may get called multiple times if a client rejects the
-+	 * channel...
-+	 */
-+	if (!pch->enabled) {
-+		pch->enabled = true;
-+		clk_enable(pdca->pclk);
-+		clk_enable(pdca->hclk);
-+	}
-+
-+	pch->chan.cookie = pch->completed = 1;
-+	pch->pslave = dma_to_pdca_slave(slave);
-+
-+	while (pch->descs_allocated < NR_DESCS_PER_CHANNEL) {
-+		struct pdca_desc	*desc;
-+
-+		desc = kzalloc(sizeof(struct pdca_desc), GFP_KERNEL);
-+		if (!desc) {
-+			dev_info(&chan->dev, "only allocated %d descriptors\n",
-+					pch->descs_allocated);
-+			break;
-+		}
-+
-+		dma_async_tx_descriptor_init(&desc->txd, chan);
-+		desc->txd.tx_submit = pdca_tx_submit;
-+		desc->txd.flags = DMA_CTRL_ACK;
-+		INIT_LIST_HEAD(&desc->txd.tx_list);
-+		list_add(&desc->desc_node, &pch->freelist);
-+		pch->descs_allocated++;
-+	}
-+
-+	return pch->descs_allocated ? 0 : -ENOMEM;
-+}
-+
-+static void pdca_free_chan_resources(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct pdca_desc		*desc, *_desc;
-+
-+	WARN_ON(!list_empty(&pch->queue));
-+	WARN_ON(pdca_readl(pch->regs, SR) & PDCA_SR_TEN);
-+	WARN_ON(pdca_readl(pch->regs, IMR));
-+
-+	clk_disable(pdca->hclk);
-+	clk_disable(pdca->pclk);
-+	pch->enabled = false;
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->freelist, desc_node) {
-+		list_del(&desc->desc_node);
-+		kfree(desc);
-+	}
-+
-+	pch->descs_allocated = 0;
-+}
-+
-+static void pdca_suspend_channel(struct pdca_dev *pdca, struct pdca_chan *pch)
-+{
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * REVISIT this whole business.
-+	 *
-+	 * The plan is to ensure that the PDCA doesn't do any bus
-+	 * transactions when we're suspended or shut down. Ideally,
-+	 * the client should make sure that all transfers have already
-+	 * been completed or terminated when we reach suspend_late(),
-+	 * but just in case that didn't happen, we should just stop
-+	 * the controller and turn it back on when resuming. Hopefully
-+	 * it will simply continue where it left off.
-+	 *
-+	 * We _probably_ need to save some sort of state to make this
-+	 * happen. Or we can just rely on interrupts being globally
-+	 * disabled at least until we reach resume_early. But that
-+	 * might not be the case for shutdown.
-+	 */
-+	tasklet_kill(&pch->tasklet);
-+	spin_lock_bh(&pch->lock);
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN) {
-+		pdca_writel(regs, CR, PDCA_CR_TDIS);
-+		while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+			cpu_relax();
-+
-+		clk_disable(pdca->hclk);
-+		clk_disable(pdca->pclk);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static void __init pdca_init_channel(struct pdca_dev *pdca, unsigned int i)
-+{
-+	struct pdca_chan		*pch = &pdca->chan[i];
-+
-+	pch->chan.device = &pdca->dma;
-+	pch->chan.chan_id = i;
-+	pch->regs = pdca->regs + i * PDCA_CHAN_SIZE;
-+	tasklet_init(&pch->tasklet, pdca_chan_tasklet, (unsigned long)pch);
-+	spin_lock_init(&pch->lock);
-+	INIT_LIST_HEAD(&pch->freelist);
-+	INIT_LIST_HEAD(&pch->queue);
-+
-+	list_add_tail(&pch->chan.device_node, &pdca->dma.channels);
-+}
-+
-+static int __init pdca_probe(struct platform_device *pdev)
-+{
-+	struct pdca_pdata		*pdata;
-+	struct resource			*mmio;
-+	struct pdca_dev			*pdca;
-+	size_t				mmio_len;
-+	size_t				size;
-+	unsigned int			i;
-+	int				irq;
-+	int				ret;
-+
-+	pdata = pdev->dev.platform_data;
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	irq = platform_get_irq(pdev, 0);
-+	if (!pdata || pdata->nr_channels > 32 || !mmio || !irq) {
-+		dev_dbg(&pdev->dev, "invalid params from platform code\n");
-+		return -EINVAL;
-+	}
-+
-+	mmio_len = mmio->end - mmio->start + 1;
-+	if (!request_mem_region(mmio->start, mmio_len, "atmel_pdca")) {
-+		dev_dbg(&pdev->dev, "mmio resource busy\n");
-+		return -EBUSY;
-+	}
-+
-+	size = sizeof(struct pdca_dev);
-+	size += pdata->nr_channels * sizeof(struct pdca_chan);
-+	pdca = kzalloc(size, GFP_KERNEL);
-+	if (!pdca) {
-+		dev_dbg(&pdev->dev, "insufficient memory\n");
-+		ret = -ENOMEM;
-+		goto err_alloc_pdca;
-+	}
-+
-+	pdca->hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(pdca->hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		ret = PTR_ERR(pdca->hclk);
-+		goto err_get_hclk;
-+	}
-+	pdca->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(pdca->pclk)) {
-+		dev_dbg(&pdev->dev, "no PB clock\n");
-+		ret = PTR_ERR(pdca->pclk);
-+		goto err_get_pclk;
-+	}
-+
-+	pdca->regs = ioremap(mmio->start, mmio_len);
-+	if (!pdca->regs) {
-+		dev_dbg(&pdev->dev, "ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	INIT_LIST_HEAD(&pdca->dma.channels);
-+	for (i = 0; i < pdata->nr_channels; i++, pdca->dma.chancnt++)
-+		pdca_init_channel(pdca, i);
-+
-+	ret = request_irq(irq, pdca_interrupt, 0, pdev->dev.bus_id, pdca);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "request_irq failed\n");
-+		goto err_irq;
-+	}
-+
-+	dma_cap_set(DMA_SLAVE, pdca->dma.cap_mask);
-+	pdca->dma.dev = &pdev->dev;
-+	pdca->dma.device_alloc_chan_resources = pdca_alloc_chan_resources;
-+	pdca->dma.device_free_chan_resources = pdca_free_chan_resources;
-+	pdca->dma.device_prep_slave_sg = pdca_prep_slave_sg;
-+	pdca->dma.device_terminate_all = pdca_terminate_all;
-+	pdca->dma.device_is_tx_complete = pdca_is_tx_complete;
-+	pdca->dma.device_issue_pending = pdca_issue_pending;
-+
-+	platform_set_drvdata(pdev, pdca);
-+	dma_async_device_register(&pdca->dma);
-+
-+	dev_info(&pdev->dev, "Atmel PDCA at 0x%08lx (irq %d) %u channels\n",
-+			(unsigned long)mmio->start, irq, pdca->dma.chancnt);
-+
-+	return 0;
-+
-+err_irq:
-+	iounmap(pdca->regs);
-+err_ioremap:
-+	clk_put(pdca->pclk);
-+err_get_pclk:
-+	clk_put(pdca->hclk);
-+err_get_hclk:
-+	kfree(pdca);
-+err_alloc_pdca:
-+	release_resource(mmio);
-+	return ret;
-+}
-+
-+static int __exit pdca_remove(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+	struct resource		*mmio;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+
-+	dma_async_device_unregister(&pdca->dma);
-+	free_irq(platform_get_irq(pdev, 0), pdca);
-+	clk_put(pdca->pclk);
-+	clk_put(pdca->hclk);
-+	iounmap(pdca->regs);
-+	kfree(pdca);
-+
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_resource(mmio);
-+
-+	return 0;
-+}
-+
-+static void pdca_shutdown(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+}
-+
-+static int pdca_suspend_late(struct platform_device *pdev, pm_message_t state)
-+{
-+	return 0;
-+}
-+
-+static int pdca_resume_early(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+
-+static struct platform_driver pdca_driver = {
-+	.remove		= __exit_p(pdca_remove),
-+	.shutdown	= pdca_shutdown,
-+	.suspend_late	= pdca_suspend_late,
-+	.resume_early	= pdca_resume_early,
-+	.driver		= {
-+		.name	= "atmel_pdca",
-+	},
-+};
-+
-+static int __init pdca_init(void)
-+{
-+	return platform_driver_probe(&pdca_driver, pdca_probe);
-+}
-+subsys_initcall(pdca_init);
-+
-+static void __exit pdca_exit(void)
-+{
-+	platform_driver_unregister(&pdca_driver);
-+}
-+module_exit(pdca_exit);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("Atmel PDCA DMA Controller driver");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-diff -urN linux-2.6.28.2-0rig//drivers/dma/dw_dmac.c linux-2.6.28.2/drivers/dma/dw_dmac.c
---- linux-2.6.28.2-0rig//drivers/dma/dw_dmac.c	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/dma/dw_dmac.c	2009-01-29 08:52:50.000000000 +0100
-@@ -545,109 +545,51 @@
- 	return NULL;
- }
- 
--static struct dma_async_tx_descriptor *
--dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
--		unsigned int sg_len, enum dma_data_direction direction,
--		unsigned long flags)
-+static struct dw_desc *dwc_init_slave_descs(struct dw_dma_chan *dwc,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		u32 ctllo, dma_addr_t src_reg, dma_addr_t dst_reg,
-+		unsigned int reg_width, unsigned long flags)
- {
--	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
--	struct dw_dma_slave	*dws = dwc->dws;
--	struct dw_desc		*prev;
--	struct dw_desc		*first;
--	u32			ctllo;
--	dma_addr_t		reg;
--	unsigned int		reg_width;
--	unsigned int		mem_width;
--	unsigned int		i;
-+	struct dma_chan		*chan = &dwc->chan;
- 	struct scatterlist	*sg;
-+	struct dw_desc		*desc;
-+	struct dw_desc		*first = NULL;
-+	struct dw_desc		*prev = NULL;
-+	unsigned int		align_mask;
-+	unsigned int		i;
- 	size_t			total_len = 0;
- 
--	dev_vdbg(&chan->dev, "prep_dma_slave\n");
--
--	if (unlikely(!dws || !sg_len))
--		return NULL;
--
--	reg_width = dws->slave.reg_width;
--	prev = first = NULL;
--
--	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
--
--	switch (direction) {
--	case DMA_TO_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_DST_WIDTH(reg_width)
--				| DWC_CTLL_DST_FIX
--				| DWC_CTLL_SRC_INC
--				| DWC_CTLL_FC_M2P);
--		reg = dws->slave.tx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
-+	align_mask = (1 << reg_width) - 1;
-+	for_each_sg(sgl, sg, sg_len, i) {
-+		u32		len;
-+		u32		desc_len;
-+		u32		mem;
-+
-+		mem = sg_phys(sg);
-+		len = sg_dma_len(sg);
-+		total_len += len;
- 
-+		while (len) {
-+			desc_len = min(len, DWC_MAX_COUNT << reg_width);
- 			desc = dwc_desc_get(dwc);
- 			if (!desc) {
- 				dev_err(&chan->dev,
- 					"not enough descriptors available\n");
- 				goto err_desc_get;
- 			}
-+			len -= desc_len;
- 
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
--
--			desc->lli.sar = mem;
--			desc->lli.dar = reg;
--			desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> mem_width;
-+			if (unlikely((mem & align_mask) || (len & align_mask)))
-+				goto err_align;
- 
--			if (!first) {
--				first = desc;
--			} else {
--				prev->lli.llp = desc->txd.phys;
--				dma_sync_single_for_device(chan->dev.parent,
--						prev->txd.phys,
--						sizeof(prev->lli),
--						DMA_TO_DEVICE);
--				list_add_tail(&desc->desc_node,
--						&first->txd.tx_list);
--			}
--			prev = desc;
--			total_len += len;
--		}
--		break;
--	case DMA_FROM_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_SRC_WIDTH(reg_width)
--				| DWC_CTLL_DST_INC
--				| DWC_CTLL_SRC_FIX
--				| DWC_CTLL_FC_P2M);
--
--		reg = dws->slave.rx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
--
--			desc = dwc_desc_get(dwc);
--			if (!desc) {
--				dev_err(&chan->dev,
--					"not enough descriptors available\n");
--				goto err_desc_get;
--			}
--
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
--
--			desc->lli.sar = reg;
--			desc->lli.dar = mem;
--			desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> reg_width;
-+			desc->lli.sar = src_reg ? src_reg : mem;
-+			desc->lli.dar = dst_reg ? dst_reg : mem;
-+			desc->lli.ctllo = ctllo;
-+			desc->lli.ctlhi = desc_len >> reg_width;
-+			dev_vdbg(&dwc->chan.dev,
-+					"  s%08x d%08x c%08x:%08x\n",
-+					desc->lli.sar, desc->lli.dar,
-+					ctllo, desc_len >> reg_width);
- 
- 			if (!first) {
- 				first = desc;
-@@ -661,11 +603,8 @@
- 						&first->txd.tx_list);
- 			}
- 			prev = desc;
--			total_len += len;
-+			mem += desc_len;
- 		}
--		break;
--	default:
--		return NULL;
- 	}
- 
- 	if (flags & DMA_PREP_INTERRUPT)
-@@ -679,13 +618,69 @@
- 
- 	first->len = total_len;
- 
--	return &first->txd;
-+	return first;
- 
-+err_align:
-+	dwc_desc_put(dwc, desc);
- err_desc_get:
- 	dwc_desc_put(dwc, first);
- 	return NULL;
- }
- 
-+static struct dma_async_tx_descriptor *
-+dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-+		unsigned int sg_len, enum dma_data_direction direction,
-+		unsigned long flags)
-+{
-+	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-+	struct dw_dma_slave	*dws = dwc->dws;
-+	struct dw_desc		*first;
-+	u32			ctllo;
-+	unsigned int		reg_width;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	if (unlikely(!dws || !sg_len))
-+		return NULL;
-+
-+	reg_width = dws->slave.reg_width;
-+	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_FIX
-+				| DWC_CTLL_SRC_INC
-+				| DWC_CTLL_FC_M2P);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				0, dws->slave.tx_reg, reg_width, flags);
-+		break;
-+	case DMA_FROM_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_DST_INC
-+				| DWC_CTLL_SRC_FIX
-+				| DWC_CTLL_FC_P2M);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				dws->slave.rx_reg, 0, reg_width, flags);
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	if (unlikely(!first)) {
-+		dma_unmap_sg(chan->dev.parent, sgl, sg_len, direction);
-+		return NULL;
-+	}
-+
-+	return &first->txd;
-+}
-+
- static void dwc_terminate_all(struct dma_chan *chan)
- {
- 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-@@ -1109,7 +1104,7 @@
- {
- 	return platform_driver_probe(&dw_driver, dw_probe);
- }
--module_init(dw_init);
-+subsys_initcall(dw_init);
- 
- static void __exit dw_exit(void)
- {
-diff -urN linux-2.6.28.2-0rig//drivers/dma/Kconfig linux-2.6.28.2/drivers/dma/Kconfig
---- linux-2.6.28.2-0rig//drivers/dma/Kconfig	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/dma/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -38,6 +38,20 @@
- 	help
- 	  Enable support for the Intel(R) IOP Series RAID engines.
- 
-+config ATMEL_PDCA
-+	tristate "Atmel Peripheral DMA Controller A support"
-+	depends on AVR32
-+	select DMA_ENGINE
-+	default y if CPU_AT32AP7200
-+	help
-+	  Support the Atmel Peripheral DMA Controller found on AVR32
-+	  UC3 chips as well as newer AP7 chips. This controller is
-+	  similar to the PDC found on AT32AP7000 and various AT91
-+	  chips, but has its own register bank.
-+
-+	  This controller only supports peripheral (slave) transfers,
-+	  not memory-to-memory transfers.
-+
- config DW_DMAC
- 	tristate "Synopsys DesignWare AHB DMA support"
- 	depends on AVR32
-diff -urN linux-2.6.28.2-0rig//drivers/dma/Makefile linux-2.6.28.2/drivers/dma/Makefile
---- linux-2.6.28.2-0rig//drivers/dma/Makefile	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/dma/Makefile	2009-01-29 08:52:50.000000000 +0100
-@@ -4,6 +4,7 @@
- obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
- ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
- obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
-+obj-$(CONFIG_ATMEL_PDCA) += atmel_pdca.o
- obj-$(CONFIG_FSL_DMA) += fsldma.o
- obj-$(CONFIG_MV_XOR) += mv_xor.o
- obj-$(CONFIG_DW_DMAC) += dw_dmac.o
-diff -urN linux-2.6.28.2-0rig//drivers/mmc/host/atmel-mci-regs.h linux-2.6.28.2/drivers/mmc/host/atmel-mci-regs.h
---- linux-2.6.28.2-0rig//drivers/mmc/host/atmel-mci-regs.h	2009-01-29 08:39:27.000000000 +0100
-+++ linux-2.6.28.2/drivers/mmc/host/atmel-mci-regs.h	2009-01-29 08:52:50.000000000 +0100
-@@ -10,13 +10,21 @@
- #ifndef __DRIVERS_MMC_ATMEL_MCI_H__
- #define __DRIVERS_MMC_ATMEL_MCI_H__
- 
--/* MCI Register Definitions */
-+/*
-+ * MCI Register Definitions. Registers and bitfields marked with [2]
-+ * are only available in MCI2.
-+ */
- #define MCI_CR			0x0000	/* Control */
- # define MCI_CR_MCIEN		(  1 <<  0)	/* MCI Enable */
- # define MCI_CR_MCIDIS		(  1 <<  1)	/* MCI Disable */
-+# define MCI_CR_PWSEN		(  1 <<  2)	/* Powersave Enable[2] */
-+# define MCI_CR_PWSDIS		(  1 <<  3)	/* Powersave Disable[2] */
-+# define MCI_CR_IOWAITEN	(  1 <<  4)	/* SDIO Read Wait Enable[2] */
-+# define MCI_CR_IOWAITDIS	(  1 <<  5)	/* SDIO Read Wait Disable[2] */
- # define MCI_CR_SWRST		(  1 <<  7)	/* Software Reset */
- #define MCI_MR			0x0004	/* Mode */
- # define MCI_MR_CLKDIV(x)	((x) <<  0)	/* Clock Divider */
-+# define MCI_MR_PWSDIV(x)	((x) <<  8)	/* Powersave Divider[2] */
- # define MCI_MR_RDPROOF		(  1 << 11)	/* Read Proof */
- # define MCI_MR_WRPROOF		(  1 << 12)	/* Write Proof */
- #define MCI_DTOR		0x0008	/* Data Timeout */
-@@ -56,6 +64,9 @@
- #define MCI_BLKR		0x0018	/* Block */
- # define MCI_BCNT(x)		((x) <<  0)	/* Data Block Count */
- # define MCI_BLKLEN(x)		((x) << 16)	/* Data Block Length */
-+#define MCI_CSTOR		0x001c	/* Completion Signal Timeout[2] */
-+# define MCI_CSTOCYC(x)		((x) <<  0)	/* CST cycles */
-+# define MCI_CSTOMUL(x)		((x) <<  4)	/* CST multiplier */
- #define MCI_RSPR		0x0020	/* Response 0 */
- #define MCI_RSPR1		0x0024	/* Response 1 */
- #define MCI_RSPR2		0x0028	/* Response 2 */
-@@ -66,24 +77,45 @@
- #define MCI_IER			0x0044	/* Interrupt Enable */
- #define MCI_IDR			0x0048	/* Interrupt Disable */
- #define MCI_IMR			0x004c	/* Interrupt Mask */
--# define MCI_CMDRDY		(  1 <<   0)	/* Command Ready */
--# define MCI_RXRDY		(  1 <<   1)	/* Receiver Ready */
--# define MCI_TXRDY		(  1 <<   2)	/* Transmitter Ready */
--# define MCI_BLKE		(  1 <<   3)	/* Data Block Ended */
--# define MCI_DTIP		(  1 <<   4)	/* Data Transfer In Progress */
--# define MCI_NOTBUSY		(  1 <<   5)	/* Data Not Busy */
--# define MCI_SDIOIRQA		(  1 <<   8)	/* SDIO IRQ in slot A */
--# define MCI_SDIOIRQB		(  1 <<   9)	/* SDIO IRQ in slot B */
--# define MCI_RINDE		(  1 <<  16)	/* Response Index Error */
--# define MCI_RDIRE		(  1 <<  17)	/* Response Direction Error */
--# define MCI_RCRCE		(  1 <<  18)	/* Response CRC Error */
--# define MCI_RENDE		(  1 <<  19)	/* Response End Bit Error */
--# define MCI_RTOE		(  1 <<  20)	/* Response Time-Out Error */
--# define MCI_DCRCE		(  1 <<  21)	/* Data CRC Error */
--# define MCI_DTOE		(  1 <<  22)	/* Data Time-Out Error */
--# define MCI_OVRE		(  1 <<  30)	/* RX Overrun Error */
--# define MCI_UNRE		(  1 <<  31)	/* TX Underrun Error */
-+# define MCI_CMDRDY		(  1 <<  0)	/* Command Ready */
-+# define MCI_RXRDY		(  1 <<  1)	/* Receiver Ready */
-+# define MCI_TXRDY		(  1 <<  2)	/* Transmitter Ready */
-+# define MCI_BLKE		(  1 <<  3)	/* Data Block Ended */
-+# define MCI_DTIP		(  1 <<  4)	/* Data Transfer In Progress */
-+# define MCI_NOTBUSY		(  1 <<  5)	/* Data Not Busy */
-+# define MCI_SDIOIRQA		(  1 <<  8)	/* SDIO IRQ in slot A */
-+# define MCI_SDIOIRQB		(  1 <<  9)	/* SDIO IRQ in slot B */
-+# define MCI_RINDE		(  1 << 16)	/* Response Index Error */
-+# define MCI_RDIRE		(  1 << 17)	/* Response Direction Error */
-+# define MCI_RCRCE		(  1 << 18)	/* Response CRC Error */
-+# define MCI_RENDE		(  1 << 19)	/* Response End Bit Error */
-+# define MCI_RTOE		(  1 << 20)	/* Response Time-Out Error */
-+# define MCI_DCRCE		(  1 << 21)	/* Data CRC Error */
-+# define MCI_DTOE		(  1 << 22)	/* Data Time-Out Error */
-+# define MCI_OVRE		(  1 << 30)	/* RX Overrun Error */
-+# define MCI_UNRE		(  1 << 31)	/* TX Underrun Error */
-+#define MCI_DMA			0x0050	/* DMA Configuration[2] */
-+# define MCI_DMA_OFFSET(x)	((x) <<  0)	/* DMA write buffer offset */
-+# define MCI_DMA_CHKSIZE_1	(  0 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_4	(  1 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_8	(  2 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_16	(  3 <<  5)	/* DMA chunk size */
-+# define MCI_DMAEN		(  1 <<  8)	/* DMA HW handshake enable */
-+#define MCI_CFG			0x0054	/* Configuration[2] */
-+# define MCI_CFG_FIFOMODE	(  1 <<  0)	/* Start transfer ASAP */
-+# define MCI_CFG_FERRCTRL	(  1 <<  4)	/* xrun flags clear-on-read */
-+# define MCI_CFG_HSMODE		(  1 <<  8)	/* Use high-speed signaling */
-+# define MCI_CFG_LSYNC		(  1 << 12)	/* Synchronize on last block */
-+#define MCI_WPMR		0x00e4	/* Write Protect Mode[2] */
-+# define MCI_WP_EN		(  1 <<  0)	/* WP Enable */
-+# define MCI_WP_KEY		(0x4d4349 << 8)	/* WP Key */
-+#define MCI_WPSR		0x00e8	/* Write Protect Status[2] */
-+# define MCI_GET_WP_VS(x)	((x) & 0x0f)
-+# define MCI_GET_WP_VSRC(x)	(((x) >> 8) & 0xffff)
-+#define MCI_VERSION		0x00fc	/* MCI Core Version[2] */
-+#define MCI_FIFO_APERTURE	0x0200	/* FIFO Aperture[2] */
- 
-+/* This is not including the FIFO Aperture on MCI2 */
- #define MCI_REGS_SIZE		0x100
- 
- /* Register access macros */
-diff -urN linux-2.6.28.2-0rig//drivers/mmc/host/Kconfig linux-2.6.28.2/drivers/mmc/host/Kconfig
---- linux-2.6.28.2-0rig//drivers/mmc/host/Kconfig	2009-01-29 08:39:27.000000000 +0100
-+++ linux-2.6.28.2/drivers/mmc/host/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -125,6 +125,17 @@
- 
- 	  If unsure, say N.
- 
-+config MMC_ATMELMCI_DMA
-+	bool "Atmel MCI DMA support (EXPERIMENTAL)"
-+	depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL
-+	help
-+	  Say Y here to have the Atmel MCI driver use a DMA engine to
-+	  do data transfers and thus increase the throughput and
-+	  reduce the CPU utilization. Note that this is highly
-+	  experimental and may cause the driver to lock up.
-+
-+	  If unsure, say N.
-+
- config MMC_IMX
- 	tristate "Motorola i.MX Multimedia Card Interface support"
- 	depends on ARCH_IMX
-diff -urN linux-2.6.28.2-0rig//drivers/mtd/nand/atmel_nand.c linux-2.6.28.2/drivers/mtd/nand/atmel_nand.c
---- linux-2.6.28.2-0rig//drivers/mtd/nand/atmel_nand.c	2009-01-29 08:39:27.000000000 +0100
-+++ linux-2.6.28.2/drivers/mtd/nand/atmel_nand.c	2009-01-29 08:52:50.000000000 +0100
-@@ -456,7 +456,7 @@
- 	platform_set_drvdata(pdev, host);
- 	atmel_nand_enable(host);
- 
--	if (host->board->det_pin) {
-+	if (gpio_is_valid(host->board->det_pin)) {
- 		if (gpio_get_value(host->board->det_pin)) {
- 			printk("No SmartMedia card inserted.\n");
- 			res = ENXIO;
-diff -urN linux-2.6.28.2-0rig//drivers/rtc/Kconfig linux-2.6.28.2/drivers/rtc/Kconfig
---- linux-2.6.28.2-0rig//drivers/rtc/Kconfig	2009-01-29 08:39:30.000000000 +0100
-+++ linux-2.6.28.2/drivers/rtc/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -633,6 +633,22 @@
- 	  will be used.  The default of zero is normally OK to use, but
- 	  on some systems other software needs to use that register.
- 
-+config RTC_DRV_AVR32_AST
-+	tristate "AVR32 Asynchronous Timer"
-+	depends on AVR32
-+	help
-+	  RTC driver for the AVR32 Asynchronous Timers. The AST is a
-+	  simple and flexible timer that can be used both as a
-+	  high-resolution system timer and an RTC, depending on what
-+	  clock source it is running from.
-+
-+	  If you say yes here, and add one or more platform_device
-+	  called "rtc-ast", those devices will be clocked from a
-+	  32.768 kHz crystal oscillator and used as RTCs.
-+
-+	  This driver can also be built as a module. If so, the module
-+	  will be called rtc-ast.
-+
- config RTC_DRV_BFIN
- 	tristate "Blackfin On-Chip RTC"
- 	depends on BLACKFIN && !BF561
-diff -urN linux-2.6.28.2-0rig//drivers/rtc/Makefile linux-2.6.28.2/drivers/rtc/Makefile
---- linux-2.6.28.2-0rig//drivers/rtc/Makefile	2009-01-29 08:39:30.000000000 +0100
-+++ linux-2.6.28.2/drivers/rtc/Makefile	2009-01-29 08:52:50.000000000 +0100
-@@ -20,6 +20,7 @@
- obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
- obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
- obj-$(CONFIG_RTC_DRV_AT91SAM9)	+= rtc-at91sam9.o
-+obj-$(CONFIG_RTC_DRV_AVR32_AST)	+= rtc-ast.o
- obj-$(CONFIG_RTC_DRV_BFIN)	+= rtc-bfin.o
- obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
- obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
-diff -urN linux-2.6.28.2-0rig//drivers/rtc/rtc-ast.c linux-2.6.28.2/drivers/rtc/rtc-ast.c
---- linux-2.6.28.2-0rig//drivers/rtc/rtc-ast.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/rtc/rtc-ast.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,546 @@
-+/*
-+ * An RTC driver for the AVR32 Asynchronous Timer
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+
-+#include <asm/ast_regs.h>
-+
-+/*
-+ * The AST - ASynchronous Timer - is built around a simple cycle
-+ * counter that can be driven from one of four selectable clocks with
-+ * a selectable power-of-two prescaler. It also has two alarms (ALARM0
-+ * and ALARM1) and two periodic event generators (PER0 and PER1). The
-+ * latter can be driven by different tappings of the same prescaler
-+ * that drives the counter.
-+ *
-+ * This driver uses the 32.768 kHz crystal oscillator as a clock
-+ * source and a prescaler that gives a 1 Hz counter frequency. It uses
-+ * ALARM0 to support both "old-school" and "wake" alarms, PER0 to
-+ * support periodic interrupts (PIE) up to 16.384 kHz (at power-of-two
-+ * intervals), and PER1 to support a 1 Hz update interrupt (UIE).
-+ *
-+ * Watchdog interrupts seem to be undocumented and unsupported by
-+ * everyone else, so those are not supported for now.
-+ *
-+ * The AST can wake the system from any sleep mode given that the
-+ * source clock is running. On AT32AP720x, the 32.768 kHz crystal
-+ * oscillator runs in all sleep modes except "static" and "shutdown".
-+ */
-+
-+/* 32768 Hz means up to 60 us for synchronization + a bit of slack */
-+#define AST_SYNC_TIMEOUT_US	100
-+
-+#define AST_CLK_RATE		32768
-+#define AST_1S_PRESCALER	14	/* log2(32768) - 1 */
-+
-+struct rtc_ast {
-+	/* Protects I/O registers */
-+	spinlock_t		lock;
-+
-+	struct rtc_device	*rtc;
-+	void __iomem		*regs;
-+	struct clk		*osc32;
-+	struct clk		*pclk;
-+};
-+
-+/*
-+ * Because the AST is, well, asynchronous, we must make sure we don't
-+ * write to certain registers while the previous write is being
-+ * synchronized between clock domains. This affects writes to CR, CV,
-+ * SCR, WER, PIRx and ARx. To keep the delays minimal, we always
-+ * synchronize _before_ writes to these registers.
-+ *
-+ * This function is also used to synchronize when changing the clock
-+ * source, using a different bit in the status register.
-+ */
-+static int ast_wait_ready(void __iomem *regs, unsigned int busy_mask)
-+{
-+	unsigned long	timeout = AST_SYNC_TIMEOUT_US;
-+
-+	while (ast_readl(regs, SR) & busy_mask) {
-+		udelay(1);
-+		if (--timeout == 0)
-+			return -ETIMEDOUT;
-+		cpu_relax();
-+	}
-+
-+	return 0;
-+}
-+
-+static void rtc_ast_release(struct device *dev)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	/* Disable all interrupts */
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	clk_disable(ast->pclk);
-+}
-+
-+static int rtc_ast_ioctl(struct device *dev, unsigned int cmd,
-+		unsigned long arg)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	switch (cmd) {
-+		/* REVISIT: Should perhaps verify that irq_task is NULL */
-+	case RTC_AIE_ON:
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case RTC_AIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	case RTC_UIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER1));
-+			ast_writel(ast->regs, IER, AST_BIT(PER1));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+
-+		break;
-+	case RTC_UIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#if 0
-+	case RTC_PIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			break;
-+		ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+		spin_unlock_irq(&ast->lock);
-+
-+		ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		break;
-+	case RTC_PIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#endif
-+	default:
-+		ret = -ENOIOCTLCMD;
-+		break;
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+	rtc_time_to_tm(ast_readl(ast->regs, CV), tm);
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_mmss(struct device *dev, unsigned long secs)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (!ret)
-+		ast_writel(ast->regs, CV, secs);
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+	unsigned long	secs;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(tm, &secs);
-+	if (!ret)
-+		ret = rtc_ast_set_mmss(dev, secs);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	rtc_time_to_tm(ast_readl(ast->regs, AR0), &alrm->time);
-+	alrm->enabled = !!(ast_readl(ast->regs, IMR) & AST_BIT(ALARM0));
-+	alrm->pending = !!(ast_readl(ast->regs, SR) & AST_BIT(ALARM0));
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned long	seconds;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(&alrm->time, &seconds);
-+	if (ret)
-+		return ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	/*
-+	 * REVISIT: The alarm may trigger before we are done here.
-+	 * Who's responsible for handling that?
-+	 *
-+	 * We don't want to clear the ALARM0 flag before we update AR0
-+	 * because the previous value of AR0 might trigger an alarm
-+	 * right after we clear the flag.
-+	 */
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+	ast_writel(ast->regs, AR0, seconds);
-+
-+	/* Try to avoid synchronization penalty */
-+	if (ast_readl(ast->regs, SR) & AST_BIT(ALARM0)) {
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			goto unlock;
-+		ast_writel(ast->regs, SCR, AST_BIT(ALARM0));
-+	}
-+
-+	if (alrm->enabled)
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_proc(struct device *dev, struct seq_file *seq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	u32		imr;
-+
-+	clk_enable(ast->pclk);
-+	imr = ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	return seq_printf(seq,
-+			"periodic_IRQ\t: %s\n"
-+			"update_IRQ\t: %s\n"
-+			"periodic_freq\t: %d\n",
-+			(imr & AST_BIT(PER0)) ? "yes" : "no",
-+			(imr & AST_BIT(PER1)) ? "yes" : "no",
-+			ast->rtc->irq_freq);
-+}
-+
-+static int rtc_ast_irq_set_freq(struct device *dev, int freq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned int	pres_bit;
-+	int		ret;
-+
-+	/* RTC core currently ensures this. */
-+	BUG_ON(!freq);
-+
-+	pres_bit = __ffs(freq);
-+	if (pres_bit > AST_1S_PRESCALER)
-+		return -EINVAL;
-+	pres_bit = AST_1S_PRESCALER - pres_bit;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+
-+	ast_writel(ast->regs, PIR0, pres_bit);
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_irq_set_state(struct device *dev, int enabled)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	if (enabled) {
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+			ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+	} else {
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static const struct rtc_class_ops rtc_ast_ops = {
-+	.release	= rtc_ast_release,
-+	.ioctl		= rtc_ast_ioctl,
-+	.read_time	= rtc_ast_read_time,
-+	.set_time	= rtc_ast_set_time,
-+	.read_alarm	= rtc_ast_read_alarm,
-+	.set_alarm	= rtc_ast_set_alarm,
-+	.proc		= rtc_ast_proc,
-+	.set_mmss	= rtc_ast_set_mmss,
-+	.irq_set_freq	= rtc_ast_irq_set_freq,
-+	.irq_set_state	= rtc_ast_irq_set_state,
-+};
-+
-+static irqreturn_t rtc_ast_interrupt(int irq, void *dev_id)
-+{
-+	struct rtc_ast	*ast = dev_id;
-+	unsigned long	events;
-+	unsigned long	num;
-+	u32		status;
-+	u32		pending;
-+	irqreturn_t	ret = IRQ_NONE;
-+
-+	clk_enable(ast->pclk);
-+	spin_lock(&ast->lock);
-+
-+	status = ast_readl(ast->regs, SR);
-+	pending = status & ast_readl(ast->regs, IMR);
-+	if (unlikely(!pending))
-+		goto out;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, SCR, pending);
-+
-+	events = RTC_IRQF;
-+	num = 0;
-+	if (pending & AST_BIT(ALARM0)) {
-+		num++;
-+		events |= RTC_AF;
-+	}
-+	if (pending & AST_BIT(PER0)) {
-+		num++;
-+		events |= RTC_PF;
-+	}
-+	if (pending & AST_BIT(PER1)) {
-+		num++;
-+		events |= RTC_UF;
-+	}
-+
-+	rtc_update_irq(ast->rtc, num, events);
-+	ret = IRQ_HANDLED;
-+
-+out:
-+	spin_unlock(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init rtc_ast_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	struct rtc_ast	*ast;
-+	int		irq;
-+	int		ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no irq\n");
-+		return -ENXIO;
-+	}
-+
-+	ast = kzalloc(sizeof(struct rtc_ast), GFP_KERNEL);
-+	if (!ast) {
-+		dev_dbg(&pdev->dev, "out of memory\n");
-+		return -ENOMEM;
-+	}
-+
-+	ast->osc32 = clk_get(NULL, "osc32k");
-+	if (IS_ERR(ast->osc32)) {
-+		ret = PTR_ERR(ast->osc32);
-+		dev_dbg(&pdev->dev, "no 32 kHz oscillator\n");
-+		goto err_osc32;
-+	}
-+
-+	ast->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(ast->pclk)) {
-+		ret = PTR_ERR(ast->pclk);
-+		dev_dbg(&pdev->dev, "no peripheral clock\n");
-+		goto err_pclk;
-+	}
-+
-+	spin_lock_init(&ast->lock);
-+
-+	ast->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!ast->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	clk_enable(ast->osc32);
-+	clk_enable(ast->pclk);
-+
-+	/* Initialize the AST if it isn't running already */
-+	if (!(ast_readl(ast->regs, CR) & AST_BIT(CR_EN))) {
-+		ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		ast_writel(ast->regs, CLOCK,
-+				AST_BF(CLOCK_CSSEL, AST_CLOCK_OSC32)
-+				| AST_BIT(CLOCK_CEN));
-+		ret = ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		if (ret) {
-+			dev_dbg(&pdev->dev,
-+				"timed out selecting clock source\n");
-+			goto err_clksel;
-+		}
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CV, 0);
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR)
-+				| AST_BF(CR_PSEL, AST_1S_PRESCALER));
-+	}
-+
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, WER, 0);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR0, AST_1S_PRESCALER);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR1, AST_1S_PRESCALER);
-+
-+	ret = request_irq(irq, rtc_ast_interrupt, 0, "rtc-ast", ast);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
-+		goto err_request_irq;
-+	}
-+
-+	ast->rtc = rtc_device_register("rtc-ast", &pdev->dev,
-+			&rtc_ast_ops, THIS_MODULE);
-+	if (IS_ERR(ast->rtc)) {
-+		dev_dbg(&pdev->dev, "could not register rtc device\n");
-+		ret = PTR_ERR(ast->rtc);
-+		goto err_register;
-+	}
-+
-+	ast->rtc->max_user_freq = AST_CLK_RATE / 2;
-+	ast->rtc->irq_freq = 1;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	clk_disable(ast->pclk);
-+	platform_set_drvdata(pdev, ast);
-+	device_init_wakeup(&pdev->dev, 1);
-+
-+	dev_info(&pdev->dev, "AVR32 Asynchronous Timer at %08lx irq %d\n",
-+			(unsigned long)regs->start, irq);
-+
-+	return 0;
-+
-+err_register:
-+	free_irq(irq, ast);
-+err_request_irq:
-+err_clksel:
-+	clk_disable(ast->pclk);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+err_ioremap:
-+	clk_put(ast->pclk);
-+err_pclk:
-+	clk_put(ast->osc32);
-+err_osc32:
-+	kfree(ast);
-+	return ret;
-+}
-+
-+static int __exit rtc_ast_remove(struct platform_device *pdev)
-+{
-+	struct rtc_ast *ast = platform_get_drvdata(pdev);
-+
-+	device_init_wakeup(&pdev->dev, 0);
-+
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	free_irq(platform_get_irq(pdev, 0), ast);
-+	rtc_device_unregister(ast->rtc);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+	clk_put(ast->pclk);
-+	clk_put(ast->osc32);
-+	kfree(ast);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver rtc_ast_driver = {
-+	.remove		= __exit_p(rtc_ast_remove),
-+	.driver		= {
-+		.name	= "rtc-ast",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+static int __init rtc_ast_init(void)
-+{
-+	return platform_driver_probe(&rtc_ast_driver, rtc_ast_probe);
-+}
-+module_init(rtc_ast_init);
-+
-+static void __exit rtc_ast_exit(void)
-+{
-+	platform_driver_unregister(&rtc_ast_driver);
-+}
-+module_exit(rtc_ast_exit);
-+
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-+MODULE_DESCRIPTION("AVR32 Asynchronous Timer RTC");
-+MODULE_LICENSE("GPL");
-diff -urN linux-2.6.28.2-0rig//drivers/spi/atmel_spi.c linux-2.6.28.2/drivers/spi/atmel_spi.c
---- linux-2.6.28.2-0rig//drivers/spi/atmel_spi.c	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/spi/atmel_spi.c	2009-01-29 09:29:00.000000000 +0100
-@@ -1,306 +1,445 @@
- /*
-  * Driver for Atmel AT32 and AT91 SPI Controllers
-  *
-- * Copyright (C) 2006 Atmel Corporation
-+ * Copyright (C) 2006-2008 Atmel Corporation
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License version 2 as
-  * published by the Free Software Foundation.
-  */
- 
--#include <linux/kernel.h>
--#include <linux/init.h>
- #include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/platform_device.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
- #include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/init.h>
- #include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/wait.h>
-+#include <linux/workqueue.h>
-+#include <linux/spi/atmel_spi.h>
- #include <linux/spi/spi.h>
- 
--#include <asm/io.h>
--#include <mach/board.h>
--#include <mach/gpio.h>
- #include <mach/cpu.h>
- 
- #include "atmel_spi.h"
- 
--/*
-- * The core SPI transfer engine just talks to a register bank to set up
-- * DMA transfers; transfer queue progress is driven by IRQs.  The clock
-- * framework provides the base clock, subdivided for each spi_device.
-- *
-- * Newer controllers, marked with "new_1" flag, have:
-- *  - CR.LASTXFER
-- *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-- *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-- *  - SPI_CSRx.CSAAT
-- *  - SPI_CSRx.SBCR allows faster clocking
-+#define BUFFER_SIZE		PAGE_SIZE
-+#define INVALID_DMA_ADDRESS	0xffffffff
-+#define MAX_SG_SEGS		8
-+
-+/**
-+ * struct atmel_spi - SPI master controller state
-+ * @lock: Spinlock protecting the @queue, @stay and @stopping fields
-+ *	as well as the hardware registers.
-+ * @regs: Base address of the hardware registers.
-+ * @wait: Waitqueue used to wait for DMA completion or errors.
-+ * @pending: Number of DMA transfers currently pending.
-+ * @pending_bytes: Number of bytes submitted for DMA but not yet
-+ *	accounted for.
-+ * @error: Data transfer error detected by interrupt handler. When this
-+ *	is set to a nonzero value, the DMA engine is stopped, @pending
-+ *	is set to 0 and @wait is triggered.
-+ * @buffer: Scratch buffer for use when the upper layers didn't provide
-+ *	a TX or RX buffer.
-+ * @buffer_dma: DMA address of @buffer.
-+ * @buffer_size: Length of @buffer in bytes.
-+ * @queue: SPI messages queued for transfer.
-+ * @workqueue: Per-controller workqueue.
-+ * @work: Queue processing work struct.
-+ * @stay: If the last SPI message caused the SPI device to stay active,
-+ *	this points to the SPI device associated with that message. NULL
-+ *	otherwise.
-+ * @clk: Bus clock connected to the controller.
-+ * @base_hz: Base clock rate in Hz used for baud rate calculations.
-+ * @stopping: Queue is being stopped. No new messages are started.
-+ * @always_bounce: Always do transfers to/from bounce buffer.
-+ * @pdev: Platform device associated with the controller.
-  */
- struct atmel_spi {
- 	spinlock_t		lock;
--
- 	void __iomem		*regs;
--	int			irq;
--	struct clk		*clk;
--	struct platform_device	*pdev;
--	unsigned		new_1:1;
--	struct spi_device	*stay;
- 
--	u8			stopping;
--	struct list_head	queue;
--	struct spi_transfer	*current_transfer;
--	unsigned long		current_remaining_bytes;
--	struct spi_transfer	*next_transfer;
--	unsigned long		next_remaining_bytes;
-+	wait_queue_head_t	wait;
-+	int			pending;
-+	size_t			pending_bytes;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct scatterlist	tx_sg[MAX_SG_SEGS];
-+	struct scatterlist	rx_sg[MAX_SG_SEGS];
-+	unsigned int		sg_len;
-+	struct dma_async_tx_descriptor *tx_desc;
-+	struct dma_async_tx_descriptor *rx_desc;
-+	struct dma_chan		*tx_chan;
-+	struct dma_chan		*rx_chan;
-+	struct dma_client	rx_client;
-+	struct dma_client	tx_client;
-+#endif
-+	int			error;
- 
- 	void			*buffer;
- 	dma_addr_t		buffer_dma;
-+	size_t			buffer_size;
-+
-+	struct list_head	queue;
-+	struct workqueue_struct	*workqueue;
-+	struct work_struct	work;
-+	struct spi_device	*stay;
-+	struct clk		*clk;
-+	unsigned long		base_hz;
-+	bool			stopping;
-+	bool			always_bounce;
-+
-+	struct platform_device	*pdev;
-+#ifdef CONFIG_DEBUG_FS
-+	struct dentry		*debugfs_root;
-+#endif
- };
- 
--#define BUFFER_SIZE		PAGE_SIZE
--#define INVALID_DMA_ADDRESS	0xffffffff
-+/**
-+ * struct atmel_spi_device - Controller-specific per-slave state
-+ * @npcs_pin: GPIO pin ID hooked up to this SPI slave.
-+ * @csr: CSRn register value used when talking to this SPI slave.
-+ */
-+struct atmel_spi_device {
-+	unsigned int		npcs_pin;
-+	u32			csr;
-+};
- 
- /*
-- * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-- * they assume that spi slave device state will not change on deselect, so
-- * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-- * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-- * controllers have CSAAT and friends.
-- *
-- * Since the CSAAT functionality is a bit weird on newer controllers as
-- * well, we use GPIO to control nCSx pins on all controllers, updating
-- * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-- * support active-high chipselects despite the controller's belief that
-- * only active-low devices/systems exists.
-+ * Version 2 of the SPI controller has
-+ *  - CR.LASTXFER
-+ *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-+ *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-+ *  - SPI_CSRx.CSAAT
-+ *  - SPI_CSRx.SBCR allows faster clocking
-  *
-- * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-- * right when driven with GPIO.  ("Mode Fault does not allow more than one
-- * Master on Chip Select 0.")  No workaround exists for that ... so for
-- * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-- * and (c) will trigger that first erratum in some cases.
-+ * We can determine the controller version by reading the VERSION
-+ * register, but I haven't checked that it exists on all chips, and
-+ * this is cheaper anyway.
-  */
-+static bool atmel_spi_is_v2(void)
-+{
-+	return !cpu_is_at91rm9200();
-+}
- 
--static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
-+static bool atmel_spi_xfer_is_last(struct spi_message *msg,
-+		struct spi_transfer *xfer)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
--	int i;
--	u32 csr;
--	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
--
--	/* Make sure clock polarity is correct */
--	for (i = 0; i < spi->master->num_chipselect; i++) {
--		csr = spi_readl(as, CSR0 + 4 * i);
--		if ((csr ^ cpol) & SPI_BIT(CPOL))
--			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
--	}
-+	return &xfer->transfer_list == msg->transfers.prev;
-+}
- 
--	mr = spi_readl(as, MR);
--	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+/*-------------------------------------------------------------------------*/
- 
--	dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
--			gpio, active ? " (high)" : "",
--			mr);
-+/*
-+ * GCC doesn't eliminate _all_ the dead code, only some of it. In
-+ * particular, the file operations appear to be difficult even if the
-+ * file operations struct itself gets eliminated.
-+ *
-+ * So let's do the CPP dance.
-+ */
-+#ifdef CONFIG_DEBUG_FS
- 
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, active);
--	spi_writel(as, MR, mr);
--}
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
- 
--static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
-+static int atmel_spi_queue_show(struct seq_file *s, void *v)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
-+	struct atmel_spi	*as = s->private;
-+	struct spi_message	*msg;
-+	struct spi_transfer	*xfer;
- 
--	/* only deactivate *this* device; sometimes transfers to
--	 * another device may be active when this routine is called.
--	 */
--	mr = spi_readl(as, MR);
--	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
--		mr = SPI_BFINS(PCS, 0xf, mr);
--		spi_writel(as, MR, mr);
-+	spin_lock_irq(&as->lock);
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		seq_printf(s, "msg to %s:%s DMA mapped, status %d actual %u\n",
-+				msg->spi->dev.bus_id,
-+				msg->is_dma_mapped ? "" : " Not",
-+				msg->status, msg->actual_length);
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			seq_printf(s, "  t%p r%p l%u%s %u bits %u us %u Hz\n",
-+					xfer->tx_buf, xfer->rx_buf, xfer->len,
-+					xfer->cs_change ? "cs_change" : "",
-+					xfer->bits_per_word,
-+					xfer->delay_usecs,
-+					xfer->speed_hz);
-+		}
- 	}
-+	spin_unlock_irq(&as->lock);
- 
--	dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
--			gpio, active ? " (low)" : "",
--			mr);
--
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, !active);
-+	return 0;
- }
- 
--static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
--					struct spi_transfer *xfer)
-+static int atmel_spi_queue_open(struct inode *inode, struct file *file)
- {
--	return msg->transfers.prev == &xfer->transfer_list;
-+	return single_open(file, atmel_spi_queue_show, inode->i_private);
- }
- 
--static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
-+static const struct file_operations atmel_spi_queue_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_queue_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
-+
-+static void atmel_spi_show_status_reg(struct seq_file *s,
-+		const char *regname, u32 value)
- {
--	return xfer->delay_usecs == 0 && !xfer->cs_change;
-+	static const char	*sr_bit[] = {
-+		[0]	= "RDRF",
-+		[1]	= "TDRE",
-+		[2]	= "MODF",
-+		[3]	= "OVRES",
-+		[4]	= "ENDRX",
-+		[5]	= "ENDTX",
-+		[6]	= "RXBUFF",
-+		[7]	= "TXBUFE",
-+		[8]	= "NSSR",
-+		[9]	= "TXEMPTY",
-+		[16]	= "SPIENS",
-+	};
-+	unsigned int		i;
-+
-+	seq_printf(s, "%s:\t0x%08x", regname, value);
-+	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
-+		if (value & (1 << i)) {
-+			if (sr_bit[i])
-+				seq_printf(s, " %s", sr_bit[i]);
-+			else
-+				seq_printf(s, " UNKNOWN(%u)", i);
-+		}
-+	}
-+	seq_putc(s, '\n');
- }
- 
--static void atmel_spi_next_xfer_data(struct spi_master *master,
--				struct spi_transfer *xfer,
--				dma_addr_t *tx_dma,
--				dma_addr_t *rx_dma,
--				u32 *plen)
-+static int atmel_spi_regs_show(struct seq_file *s, void *v)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	u32			len = *plen;
-+	struct atmel_spi	*as = s->private;
-+	unsigned int		i;
-+	u32			value;
-+	u32			*buf;
-+
-+	buf = kmalloc(0x200, GFP_KERNEL);
-+	if (!buf)
-+		return -ENOMEM;
- 
--	/* use scratch buffer only when rx or tx data is unspecified */
--	if (xfer->rx_buf)
--		*rx_dma = xfer->rx_dma + xfer->len - len;
--	else {
--		*rx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--	}
--	if (xfer->tx_buf)
--		*tx_dma = xfer->tx_dma + xfer->len - len;
--	else {
--		*tx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--		memset(as->buffer, 0, len);
--		dma_sync_single_for_device(&as->pdev->dev,
--				as->buffer_dma, len, DMA_TO_DEVICE);
-+	/* Grab a more or less consistent snapshot */
-+	spin_lock_irq(&as->lock);
-+	memcpy_fromio(buf, as->regs, 0x200);
-+	spin_unlock_irq(&as->lock);
-+
-+	value = buf[SPI_MR / 4];
-+	seq_printf(s, "MR:\t0x%08x%s%s%s%s%s%s PCS=%x DLYBCS=%u\n",
-+			value,
-+			(value & SPI_BIT(MSTR)) ? " MSTR" : "",
-+			(value & SPI_BIT(PS)) ? " PS" : "",
-+			(value & SPI_BIT(PCSDEC)) ? " PCSDEC" : "",
-+			(value & SPI_BIT(FDIV)) ? " FDIV" : "",
-+			(value & SPI_BIT(MODFDIS)) ? " MODFDIS" : "",
-+			(value & SPI_BIT(LLB)) ? " LLB" : "",
-+			SPI_BFEXT(PCS, value),
-+			SPI_BFEXT(DLYBCS, value));
-+
-+	atmel_spi_show_status_reg(s, "SR", buf[SPI_SR / 4]);
-+	atmel_spi_show_status_reg(s, "IMR", buf[SPI_IMR / 4]);
-+
-+	for (i = 0; i < 4; i++) {
-+		value = buf[SPI_CSR0 / 4 + i];
-+		seq_printf(s, "CSR%u:\t0x%08x%s%s%s\n",
-+				i, value,
-+				(value & SPI_BIT(CPOL)) ? " CPOL" : "",
-+				(value & SPI_BIT(NCPHA)) ? " NCPHA" : "",
-+				(value & SPI_BIT(CSAAT)) ? " CSAAT" : "");
-+		seq_printf(s, "\t\tBITS=%u SCBR=%u DLYBS=%u DLYBCT=%u\n",
-+				SPI_BFEXT(BITS, value) + 8,
-+				SPI_BFEXT(SCBR, value),
-+				SPI_BFEXT(DLYBS, value),
-+				SPI_BFEXT(DLYBCT, value));
- 	}
- 
--	*plen = len;
-+	seq_printf(s, "RPR:\t0x%08x\n", buf[SPI_RPR / 4]);
-+	seq_printf(s, "RCR:\t0x%08x\n", buf[SPI_RCR / 4]);
-+	seq_printf(s, "TPR:\t0x%08x\n", buf[SPI_TPR / 4]);
-+	seq_printf(s, "TCR:\t0x%08x\n", buf[SPI_TCR / 4]);
-+	seq_printf(s, "RNPR:\t0x%08x\n", buf[SPI_RNPR / 4]);
-+	seq_printf(s, "RNCR:\t0x%08x\n", buf[SPI_RNCR / 4]);
-+	seq_printf(s, "TNPR:\t0x%08x\n", buf[SPI_TNPR / 4]);
-+	seq_printf(s, "TNCR:\t0x%08x\n", buf[SPI_TNCR / 4]);
-+
-+	value = buf[SPI_PTSR / 4];
-+	seq_printf(s, "PTSR:\t0x%08x%s%s\n", value,
-+			(value & SPI_BIT(RXTEN)) ? " RXTEN" : "",
-+			(value & SPI_BIT(TXTEN)) ? " TXTEN" : "");
-+
-+	kfree(buf);
-+
-+	return 0;
- }
- 
--/*
-- * Submit next transfer for DMA.
-- * lock is held, spi irq is blocked
-- */
--static void atmel_spi_next_xfer(struct spi_master *master,
--				struct spi_message *msg)
-+static int atmel_spi_regs_open(struct inode *inode, struct file *file)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_transfer	*xfer;
--	u32			len, remaining;
--	u32			ieval;
--	dma_addr_t		tx_dma, rx_dma;
--
--	if (!as->current_transfer)
--		xfer = list_entry(msg->transfers.next,
--				struct spi_transfer, transfer_list);
--	else if (!as->next_transfer)
--		xfer = list_entry(as->current_transfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--	else
--		xfer = NULL;
--
--	if (xfer) {
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+	return single_open(file, atmel_spi_regs_show, inode->i_private);
-+}
- 
--		len = xfer->len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		remaining = xfer->len - len;
-+static const struct file_operations atmel_spi_regs_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_regs_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
- 
--		spi_writel(as, RPR, rx_dma);
--		spi_writel(as, TPR, tx_dma);
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
-+	struct dentry	*root;
-+	struct dentry	*node;
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RCR, len);
--		spi_writel(as, TCR, len);
-+	root = debugfs_create_dir(as->pdev->dev.bus_id, NULL);
-+	if (IS_ERR(root))
-+		/* Debugfs not enabled */
-+		return;
-+	if (!root)
-+		/* Debugfs enabled, but failed to create directory */
-+		goto err_root;
-+
-+	node = debugfs_create_file("regs", S_IRUSR, root, as,
-+			&atmel_spi_regs_fops);
-+	if (!node)
-+		goto err;
-+	node = debugfs_create_file("queue", S_IRUSR, root, as,
-+			&atmel_spi_queue_fops);
-+	if (!node)
-+		goto err;
-+
-+	as->debugfs_root = root;
-+	return;
-+
-+err:
-+	debugfs_remove_recursive(root);
-+err_root:
-+	dev_err(&as->pdev->dev, "failed to initialize debugfs\n");
-+}
- 
--		dev_dbg(&msg->spi->dev,
--			"  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	} else {
--		xfer = as->next_transfer;
--		remaining = as->next_remaining_bytes;
--	}
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
-+	debugfs_remove_recursive(as->debugfs_root);
-+}
- 
--	as->current_transfer = xfer;
--	as->current_remaining_bytes = remaining;
-+#else
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
- 
--	if (remaining > 0)
--		len = remaining;
--	else if (!atmel_spi_xfer_is_last(msg, xfer)
--			&& atmel_spi_xfer_can_be_chained(xfer)) {
--		xfer = list_entry(xfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--		len = xfer->len;
--	} else
--		xfer = NULL;
-+}
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
- 
--	as->next_transfer = xfer;
-+}
-+#endif
- 
--	if (xfer) {
--		u32	total;
-+/*
-+ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-+ * they assume that spi slave device state will not change on deselect, so
-+ * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-+ * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-+ * controllers have CSAAT and friends.
-+ *
-+ * Since the CSAAT functionality is a bit weird on newer controllers as
-+ * well, we use GPIO to control nCSx pins on all controllers, updating
-+ * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-+ * support active-high chipselects despite the controller's belief that
-+ * only active-low devices/systems exists.
-+ *
-+ * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-+ * right when driven with GPIO.  ("Mode Fault does not allow more than one
-+ * Master on Chip Select 0.")  No workaround exists for that ... so for
-+ * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-+ * and (c) will trigger that first erratum in some cases.
-+ *
-+ * TODO: Test if the atmel_spi_is_v2() branch below works on
-+ * AT91RM9200 if we use some other register than CSR0. However, don't
-+ * do this unconditionally since AP7000 has an errata where the BITS
-+ * field in CSR0 overrides all other CSRs.
-+ */
- 
--		total = len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		as->next_remaining_bytes = total - len;
-+static void atmel_spi_set_csr(struct atmel_spi *as,
-+		struct spi_device *spi, u32 csr)
-+{
-+	if (atmel_spi_is_v2())
-+		spi_writel(as, CSR0, csr);
-+	else
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
-+}
- 
--		spi_writel(as, RNPR, rx_dma);
--		spi_writel(as, TNPR, tx_dma);
-+static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
-+{
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RNCR, len);
--		spi_writel(as, TNCR, len);
-+	if (atmel_spi_is_v2()) {
-+		/*
-+		 * Always use CSR0. This ensures that the clock
-+		 * switches to the correct idle polarity before we
-+		 * toggle the CS.
-+		 */
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
-+				| SPI_BIT(MSTR));
-+		spi_readl(as, MR);
-+		dev_vdbg(&spi->dev, "activate %u%s, csr0: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				asd->csr);
- 
--		dev_dbg(&msg->spi->dev,
--			"  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--		ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
-+		gpio_set_value(asd->npcs_pin, active);
- 	} else {
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
--	}
-+		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+		int i;
-+		u32 mr;
-+		u32 csr;
-+
-+		/* Make sure clock polarity is correct */
-+		for (i = 0; i < spi->master->num_chipselect; i++) {
-+			csr = spi_readl(as, CSR0 + 4 * i);
-+			if ((csr ^ cpol) & SPI_BIT(CPOL))
-+				spi_writel(as, CSR0 + 4 * i,
-+						csr ^ SPI_BIT(CPOL));
-+		}
- 
--	/* REVISIT: We're waiting for ENDRX before we start the next
--	 * transfer because we need to handle some difficult timing
--	 * issues otherwise. If we wait for ENDTX in one transfer and
--	 * then starts waiting for ENDRX in the next, it's difficult
--	 * to tell the difference between the ENDRX interrupt we're
--	 * actually waiting for and the ENDRX interrupt of the
--	 * previous transfer.
--	 *
--	 * It should be doable, though. Just not now...
--	 */
--	spi_writel(as, IER, ieval);
--	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
-+		mr = spi_readl(as, MR);
-+		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+		dev_vdbg(&spi->dev, "activate %u%s, mr: %08x csr: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				mr, csr);
-+		if (spi->chip_select != 0)
-+			gpio_set_value(asd->npcs_pin, active);
-+		spi_writel(as, MR, mr);
-+	}
- }
- 
--static void atmel_spi_next_message(struct spi_master *master)
-+static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_device	*spi;
--
--	BUG_ON(as->current_transfer);
--
--	msg = list_entry(as->queue.next, struct spi_message, queue);
--	spi = msg->spi;
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
-+	u32 mr;
- 
--	dev_dbg(master->dev.parent, "start message %p for %s\n",
--			msg, spi->dev.bus_id);
-+	/* only deactivate *this* device; sometimes transfers to
-+	 * another device may be active when this routine is called.
-+	 */
-+	mr = spi_readl(as, MR);
-+	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
-+		mr = SPI_BFINS(PCS, 0xf, mr);
-+		spi_writel(as, MR, mr);
-+	}
- 
--	/* select chip if it's not still active */
--	if (as->stay) {
--		if (as->stay != spi) {
--			cs_deactivate(as, as->stay);
--			cs_activate(as, spi);
--		}
--		as->stay = NULL;
--	} else
--		cs_activate(as, spi);
-+	dev_vdbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
-+			asd->npcs_pin, active ? " (low)" : "",
-+			mr);
- 
--	atmel_spi_next_xfer(master, msg);
-+	if (atmel_spi_is_v2() || spi->chip_select != 0)
-+		gpio_set_value(asd->npcs_pin, !active);
- }
- 
- /*
-@@ -338,162 +477,460 @@
- 	return 0;
- }
- 
--static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
-+static void atmel_spi_dma_unmap_xfer(struct atmel_spi *as,
- 				     struct spi_transfer *xfer)
- {
- 	if (xfer->tx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->tx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->tx_dma,
- 				 xfer->len, DMA_TO_DEVICE);
- 	if (xfer->rx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->rx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->rx_dma,
- 				 xfer->len, DMA_FROM_DEVICE);
- }
- 
--static void
--atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
--		struct spi_message *msg, int status, int stay)
-+static void atmel_spi_dma_unmap_msg(struct atmel_spi *as, struct spi_message *msg)
- {
--	if (!stay || status < 0)
--		cs_deactivate(as, msg->spi);
--	else
--		as->stay = msg->spi;
-+	struct spi_transfer	*xfer;
- 
--	list_del(&msg->queue);
--	msg->status = status;
-+	if (!msg->is_dma_mapped)
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list)
-+			atmel_spi_dma_unmap_xfer(as, xfer);
-+}
- 
--	dev_dbg(master->dev.parent,
--		"xfer complete: %u bytes transferred\n",
--		msg->actual_length);
-+static void atmel_spi_handle_error(struct atmel_spi *as,
-+		struct spi_message *msg, int err)
-+{
-+	unsigned int timeout;
- 
--	spin_unlock(&as->lock);
--	msg->complete(msg->context);
--	spin_lock(&as->lock);
-+	/* Drain the buffers so that the hardware is ready for a new message */
-+	for (timeout = 1000; timeout; timeout--)
-+		if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
-+			break;
-+	if (!timeout)
-+		dev_warn(&msg->spi->dev,
-+			 "timeout waiting for TXEMPTY");
-+	while (spi_readl(as, SR) & SPI_BIT(RDRF))
-+		spi_readl(as, RDR);
- 
--	as->current_transfer = NULL;
--	as->next_transfer = NULL;
-+	/* Clear any overrun happening while cleaning up */
-+	spi_readl(as, SR);
- 
--	/* continue if needed */
--	if (list_empty(&as->queue) || as->stopping)
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--	else
--		atmel_spi_next_message(master);
-+	msg->status = err;
-+	as->error = 0;
- }
- 
--static irqreturn_t
--atmel_spi_interrupt(int irq, void *dev_id)
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
- {
--	struct spi_master	*master = dev_id;
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_transfer	*xfer;
--	u32			status, pending, imr;
--	int			ret = IRQ_NONE;
-+	int err;
- 
--	spin_lock(&as->lock);
-+	wait_event(as->wait, as->pending == 0);
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev,
-+				"transfer error %d (%u/%u remaining)\n",
-+				err, spi_readl(as, TCR), spi_readl(as, RCR));
- 
--	xfer = as->current_transfer;
--	msg = list_entry(as->queue.next, struct spi_message, queue);
-+		spi_writel(as, TNCR, 0);
-+		spi_writel(as, RNCR, 0);
-+		spi_writel(as, TCR, 0);
-+		spi_writel(as, RCR, 0);
- 
--	imr = spi_readl(as, IMR);
--	status = spi_readl(as, SR);
--	pending = status & imr;
-+		atmel_spi_handle_error(as, msg, err);
- 
--	if (pending & SPI_BIT(OVRES)) {
--		int timeout;
-+		return err;
-+	}
- 
--		ret = IRQ_HANDLED;
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
- 
--		spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
--				     | SPI_BIT(OVRES)));
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	dma_addr_t	rx_dma;
-+	dma_addr_t	tx_dma;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
-+
-+	if (!bits)
-+		bits = spi->bits_per_word;
-+
-+	/* PDC stuff starts here */
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		wait_event(as->wait, as->pending < 2);
- 
- 		/*
--		 * When we get an overrun, we disregard the current
--		 * transfer. Data will not be copied back from any
--		 * bounce buffer and msg->actual_len will not be
--		 * updated with the last xfer.
--		 *
--		 * We will also not process any remaning transfers in
--		 * the message.
--		 *
--		 * First, stop the transfer and unmap the DMA buffers.
-+		 * This gives the RX side a slight advantage, making
-+		 * overruns less likely.
- 		 */
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--		if (!msg->is_dma_mapped)
--			atmel_spi_dma_unmap_xfer(master, xfer);
-+		spi_writel(as, PTCR, SPI_BIT(TXTDIS));
-+
-+		len = xfer->len - submitted;
-+		if (xfer->rx_buf) {
-+			rx_dma = xfer->rx_dma + submitted;
-+		} else {
-+			rx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+		}
-+		if (xfer->tx_buf) {
-+			tx_dma = xfer->tx_dma + submitted;
-+		} else {
-+			tx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+			memset(as->buffer, 0, len);
-+		}
-+
-+		submitted += len;
-+		if (bits > 8)
-+			len >>= 1;
-+
-+		spin_lock_irq(&as->lock);
-+		if (as->error) {
-+			spin_unlock_irq(&as->lock);
-+			atmel_spi_wait_idle(as, msg);
-+			return 0;
-+		}
-+
-+		spi_writel(as, RNPR, rx_dma);
-+		spi_writel(as, RNCR, len);
-+		spi_writel(as, TNPR, tx_dma);
-+		spi_writel(as, TNCR, len);
-+		spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
-+				| SPI_BIT(OVRES));
-+		spi_writel(as, PTCR, SPI_BIT(RXTEN) | SPI_BIT(TXTEN));
-+		as->pending++;
-+		spin_unlock_irq(&as->lock);
-+	}
- 
--		/* REVISIT: udelay in irq is unfriendly */
-+	as->pending_bytes += submitted;
-+
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
- 		if (xfer->delay_usecs)
- 			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
-+
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
- 
--		dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
--			 spi_readl(as, TCR), spi_readl(as, RCR));
-+	return xfer->cs_change;
-+}
- 
--		/*
--		 * Clean up DMA registers and make sure the data
--		 * registers are empty.
--		 */
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		spi_writel(as, RCR, 0);
--		spi_writel(as, TCR, 0);
--		for (timeout = 1000; timeout; timeout--)
--			if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
--				break;
--		if (!timeout)
--			dev_warn(master->dev.parent,
--				 "timeout waiting for TXEMPTY");
--		while (spi_readl(as, SR) & SPI_BIT(RDRF))
--			spi_readl(as, RDR);
--
--		/* Clear any overrun happening while cleaning up */
--		spi_readl(as, SR);
--
--		atmel_spi_msg_done(master, as, msg, -EIO, 0);
--	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
--		ret = IRQ_HANDLED;
-+#else /* Use DMA engine framework, not PDC */
- 
--		spi_writel(as, IDR, pending);
-+static void atmel_spi_dma_complete(void *param)
-+{
-+	struct atmel_spi	*as = param;
- 
--		if (as->current_remaining_bytes == 0) {
--			msg->actual_length += xfer->len;
-+	as->pending = 0;
-+	as->sg_len = 0;
-+	wake_up(&as->wait);
-+}
- 
--			if (!msg->is_dma_mapped)
--				atmel_spi_dma_unmap_xfer(master, xfer);
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
-+{
-+	struct dma_chan			*tx_chan = as->tx_chan;
-+	struct dma_chan			*rx_chan = as->rx_chan;
-+	struct dma_device		*dma = rx_chan->device;
-+	struct dma_async_tx_descriptor	*tx_desc;
-+	struct dma_async_tx_descriptor	*rx_desc;
-+	int				err;
-+
-+	dev_vdbg(&msg->spi->dev, "wait_idle: sg_len=%u\n", as->sg_len);
-+
-+	if (!as->sg_len)
-+		return 0;
-+
-+	sg_mark_end(as->tx_sg + (as->sg_len - 1));
-+	sg_mark_end(as->rx_sg + (as->sg_len - 1));
-+	as->pending = 1;
-+	smp_wmb();
-+
-+	tx_desc = dma->device_prep_slave_sg(tx_chan,
-+			as->tx_sg, as->sg_len, DMA_TO_DEVICE,
-+			DMA_COMPL_SKIP_SRC_UNMAP | DMA_CTRL_ACK);
-+	rx_desc = dma->device_prep_slave_sg(rx_chan,
-+			as->rx_sg, as->sg_len, DMA_FROM_DEVICE,
-+			DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP
-+			| DMA_CTRL_ACK);
-+	rx_desc->callback = atmel_spi_dma_complete;
-+	rx_desc->callback_param = as;
-+	rx_desc->tx_submit(rx_desc);
-+	tx_desc->tx_submit(tx_desc);
-+	dma->device_issue_pending(rx_chan);
-+	dma->device_issue_pending(tx_chan);
-+
-+	spi_writel(as, IER, SPI_BIT(OVRES));
-+	wait_event(as->wait, !as->pending);
-+	spi_writel(as, IDR, SPI_BIT(OVRES));
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev, "transfer error %d\n", err);
- 
--			/* REVISIT: udelay in irq is unfriendly */
--			if (xfer->delay_usecs)
--				udelay(xfer->delay_usecs);
--
--			if (atmel_spi_xfer_is_last(msg, xfer)) {
--				/* report completed message */
--				atmel_spi_msg_done(master, as, msg, 0,
--						xfer->cs_change);
--			} else {
--				if (xfer->cs_change) {
--					cs_deactivate(as, msg->spi);
--					udelay(1);
--					cs_activate(as, msg->spi);
--				}
-+		dma->device_terminate_all(tx_chan);
-+		dma->device_terminate_all(rx_chan);
-+
-+		atmel_spi_handle_error(as, msg, err);
-+
-+		return err;
-+	}
-+
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
-+	sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+	sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	unsigned int	i;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
-+
-+	if (!bits)
-+		bits = spi->bits_per_word;
-+
-+	i = as->sg_len;
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		if (i == MAX_SG_SEGS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				return 0;
-+			i = 0;
-+		}
-+
-+		len = xfer->len - submitted;
-+		if (!xfer->rx_buf || !xfer->tx_buf)
-+			len = min(len, BUFFER_SIZE);
-+
-+		if (xfer->rx_buf) {
-+			sg_set_buf(&as->rx_sg[i], xfer->rx_buf + submitted, len);
-+			as->rx_sg[i].dma_address = xfer->rx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->rx_sg[i], as->buffer, len);
-+			as->rx_sg[i].dma_address = as->buffer_dma;
-+		}
-+		if (xfer->tx_buf) {
-+			sg_set_buf(&as->tx_sg[i], xfer->tx_buf + submitted, len);
-+			as->tx_sg[i].dma_address = xfer->tx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->tx_sg[i], as->buffer, len);
-+			as->tx_sg[i].dma_address = as->buffer_dma;
-+			memset(as->buffer, 0, len);
-+		}
-+
-+		submitted += len;
-+		as->sg_len = ++i;
-+	}
-+
-+	as->pending_bytes += submitted;
- 
--				/*
--				 * Not done yet. Submit the next transfer.
--				 *
--				 * FIXME handle protocol options for xfer
--				 */
--				atmel_spi_next_xfer(master, msg);
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
-+		if (xfer->delay_usecs)
-+			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
-+
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
-+
-+	return xfer->cs_change;
-+}
-+
-+#endif /* PDC vs. DMA engine */
-+
-+static void atmel_spi_work(struct work_struct *work)
-+{
-+	struct atmel_spi	*as;
-+
-+	as = container_of(work, struct atmel_spi, work);
-+
-+	spin_lock_irq(&as->lock);
-+	while (!list_empty(&as->queue)) {
-+		struct spi_message	*msg;
-+		struct spi_transfer	*xfer;
-+		struct spi_device	*spi;
-+		int			cs_change = 0;
-+
-+		if (as->stopping)
-+			break;
-+
-+		msg = list_entry(as->queue.next, struct spi_message, queue);
-+		spin_unlock_irq(&as->lock);
-+
-+		spi = msg->spi;
-+
-+		if (as->stay) {
-+			if (as->stay != spi) {
-+				cs_deactivate(as, as->stay);
-+				cs_activate(as, spi);
- 			}
-+			as->stay = NULL;
- 		} else {
--			/*
--			 * Keep going, we still have data to send in
--			 * the current transfer.
--			 */
--			atmel_spi_next_xfer(master, msg);
-+			cs_activate(as, spi);
-+		}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+		sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+		sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+#endif
-+
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			if (msg->status != -EINPROGRESS)
-+				break;
-+			cs_change = atmel_spi_submit_xfer(as, spi, msg, xfer);
-+		}
-+
-+		if (msg->status == -EINPROGRESS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				cs_change = 1;
-+			else
-+				msg->status = 0;
- 		}
-+		if (!cs_change)
-+			cs_deactivate(as, spi);
-+		else
-+			as->stay = spi;
-+
-+		atmel_spi_dma_unmap_msg(as, msg);
-+
-+		msg->complete(msg->context);
-+		spin_lock_irq(&as->lock);
-+		list_del(&msg->queue);
- 	}
-+	spin_unlock_irq(&as->lock);
-+}
-+
-+static irqreturn_t atmel_spi_interrupt(int irq, void *dev_id)
-+{
-+	struct atmel_spi	*as = dev_id;
-+	u32			status;
-+	u32			mask;
-+	u32			pending;
-+
-+	spin_lock(&as->lock);
-+
-+	status = spi_readl(as, SR);
-+	mask = spi_readl(as, IMR);
-+	pending = status & mask;
-+
-+	if (pending & SPI_BIT(OVRES)) {
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+#endif
-+		spi_writel(as, IDR, ~0UL);
-+		as->error = -EIO;
-+		as->pending = 0;
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+	} else if (pending & SPI_BIT(RXBUFF)) {
-+		spi_writel(as, IDR, ~0UL);
-+		as->pending = 0;
-+	} else if (pending & SPI_BIT(ENDRX)) {
-+		spi_writel(as, IDR, SPI_BIT(ENDRX));
-+		as->pending--;
-+#endif
-+	} else {
-+		dev_err(&as->pdev->dev,
-+			"unexpected interrupt: SR=0x%08x MR=0x%08x\n",
-+				status, mask);
-+		spi_writel(as, IDR, pending);
-+	}
-+
-+	spi_readl(as, IMR);
-+	wake_up(&as->wait);
- 
- 	spin_unlock(&as->lock);
- 
--	return ret;
-+	return IRQ_HANDLED;
- }
- 
- /* the spi->mode bits understood by this driver: */
-@@ -502,6 +939,7 @@
- static int atmel_spi_setup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as;
-+	struct atmel_spi_device	*asd;
- 	u32			scbr, csr;
- 	unsigned int		bits = spi->bits_per_word;
- 	unsigned long		bus_hz;
-@@ -536,21 +974,14 @@
- 	}
- 
- 	/* see notes above re chipselect */
--	if (cpu_is_at91rm9200()
-+	if (!atmel_spi_is_v2()
- 			&& spi->chip_select == 0
- 			&& (spi->mode & SPI_CS_HIGH)) {
- 		dev_dbg(&spi->dev, "setup: can't be active-high\n");
- 		return -EINVAL;
- 	}
- 
--	/*
--	 * Pre-new_1 chips start out at half the peripheral
--	 * bus speed.
--	 */
--	bus_hz = clk_get_rate(as->clk);
--	if (!as->new_1)
--		bus_hz /= 2;
--
-+	bus_hz = as->base_hz;
- 	if (spi->max_speed_hz) {
- 		/*
- 		 * Calculate the lowest divider that satisfies the
-@@ -589,11 +1020,20 @@
- 
- 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
- 	npcs_pin = (unsigned int)spi->controller_data;
--	if (!spi->controller_state) {
-+	asd = spi->controller_state;
-+	if (!asd) {
-+		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
-+		if (!asd)
-+			return -ENOMEM;
-+
- 		ret = gpio_request(npcs_pin, spi->dev.bus_id);
--		if (ret)
-+		if (ret) {
-+			kfree(asd);
- 			return ret;
--		spi->controller_state = (void *)npcs_pin;
-+		}
-+
-+		asd->npcs_pin = npcs_pin;
-+		spi->controller_state = asd;
- 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
- 	} else {
- 		unsigned long		flags;
-@@ -605,11 +1045,14 @@
- 		spin_unlock_irqrestore(&as->lock, flags);
- 	}
- 
-+	asd->csr = csr;
-+
- 	dev_dbg(&spi->dev,
- 		"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
- 		bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
- 
--	spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
-+	if (!atmel_spi_is_v2())
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
- 
- 	return 0;
- }
-@@ -620,74 +1063,81 @@
- 	struct spi_transfer	*xfer;
- 	unsigned long		flags;
- 	struct device		*controller = spi->master->dev.parent;
-+	int			ret;
- 
- 	as = spi_master_get_devdata(spi->master);
- 
--	dev_dbg(controller, "new message %p submitted for %s\n",
-+	dev_vdbg(controller, "new message %p submitted for %s\n",
- 			msg, spi->dev.bus_id);
- 
- 	if (unlikely(list_empty(&msg->transfers)
- 			|| !spi->max_speed_hz))
- 		return -EINVAL;
- 
--	if (as->stopping)
--		return -ESHUTDOWN;
--
- 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- 		if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
- 			dev_dbg(&spi->dev, "missing rx or tx buf\n");
- 			return -EINVAL;
- 		}
- 
--		/* FIXME implement these protocol options!! */
--		if (xfer->bits_per_word || xfer->speed_hz) {
--			dev_dbg(&spi->dev, "no protocol options yet\n");
--			return -ENOPROTOOPT;
-+		if (xfer->bits_per_word && (xfer->bits_per_word < 8
-+					|| xfer->bits_per_word > 16)) {
-+			dev_dbg(&spi->dev, "unsupported bits_per_word\n");
-+			return -EINVAL;
-+		}
-+		if (xfer->speed_hz) {
-+			unsigned long divider;
-+			divider = DIV_ROUND_UP(as->base_hz, xfer->speed_hz);
-+
-+			if (divider > 255) {
-+				dev_dbg(&spi->dev, "speed_hz too low\n");
-+				return -EINVAL;
-+			}
- 		}
- 
- 		/*
- 		 * DMA map early, for performance (empties dcache ASAP) and
- 		 * better fault reporting.  This is a DMA-only driver.
--		 *
--		 * NOTE that if dma_unmap_single() ever starts to do work on
--		 * platforms supported by this driver, we would need to clean
--		 * up mappings for previously-mapped transfers.
- 		 */
- 		if (!msg->is_dma_mapped) {
--			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
-+			if (atmel_spi_dma_map_xfer(as, xfer) < 0) {
-+				/* Ick */
-+				while (xfer->transfer_list.prev != &msg->transfers) {
-+					xfer = list_entry(xfer->transfer_list.prev,
-+							struct spi_transfer,
-+							transfer_list);
-+					atmel_spi_dma_unmap_xfer(as, xfer);
-+				}
-+
- 				return -ENOMEM;
-+			}
- 		}
- 	}
- 
--#ifdef VERBOSE
--	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
--		dev_dbg(controller,
--			"  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len,
--			xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	}
--#endif
--
- 	msg->status = -EINPROGRESS;
- 	msg->actual_length = 0;
- 
- 	spin_lock_irqsave(&as->lock, flags);
--	list_add_tail(&msg->queue, &as->queue);
--	if (!as->current_transfer)
--		atmel_spi_next_message(spi->master);
-+	if (as->stopping) {
-+		ret = -ESHUTDOWN;
-+	} else {
-+		list_add_tail(&msg->queue, &as->queue);
-+		queue_work(as->workqueue, &as->work);
-+		ret = 0;
-+	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
--	return 0;
-+	return ret;
- }
- 
- static void atmel_spi_cleanup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
-+	struct atmel_spi_device	*asd = spi->controller_state;
- 	unsigned		gpio = (unsigned) spi->controller_data;
- 	unsigned long		flags;
- 
--	if (!spi->controller_state)
-+	if (!asd)
- 		return;
- 
- 	spin_lock_irqsave(&as->lock, flags);
-@@ -697,14 +1147,131 @@
- 	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
-+	spi->controller_state = NULL;
- 	gpio_free(gpio);
-+	kfree(asd);
-+}
-+
-+static void atmel_spi_stop_queue(struct atmel_spi *as)
-+{
-+	struct spi_message	*msg;
-+
-+	/*
-+	 * Prevent any new messages from being submitted, cancel any
-+	 * submitted but not-yet-started messages, and wait for any
-+	 * ongoing messages to complete.
-+	 */
-+	as->stopping = true;
-+	smp_wmb();
-+	cancel_work_sync(&as->work);
-+
-+	/* Terminate anything that was left over */
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		atmel_spi_dma_unmap_msg(as, msg);
-+		msg->status = -ESHUTDOWN;
-+		msg->complete(msg->context);
-+	}
-+}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+static enum dma_state_client atmel_spi_dma_chan_avail(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (!*pchan) {
-+		as->stopping = false;
-+		*pchan = chan;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_chan_removed(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (chan == *pchan) {
-+		atmel_spi_stop_queue(as);
-+		*pchan = NULL;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_rx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, rx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA RX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_tx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, tx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA TX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
- }
-+#endif
- 
- /*-------------------------------------------------------------------------*/
- 
- static int __init atmel_spi_probe(struct platform_device *pdev)
- {
- 	struct resource		*regs;
-+	struct resource		*buf;
-+	struct atmel_spi_pdata	*pdata;
- 	int			irq;
- 	struct clk		*clk;
- 	int			ret;
-@@ -719,6 +1286,14 @@
- 	if (irq < 0)
- 		return irq;
- 
-+	pdata = pdev->dev.platform_data;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	if (!pdata) {
-+		dev_dbg(&pdev->dev, "no platform data\n");
-+		return -ENXIO;
-+	}
-+#endif
-+
- 	clk = clk_get(&pdev->dev, "spi_clk");
- 	if (IS_ERR(clk))
- 		return PTR_ERR(clk);
-@@ -738,31 +1313,65 @@
- 
- 	as = spi_master_get_devdata(master);
- 
--	/*
--	 * Scratch buffer is used for throwaway rx and tx data.
--	 * It's coherent to minimize dcache pollution.
--	 */
--	as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
--					&as->buffer_dma, GFP_KERNEL);
--	if (!as->buffer)
--		goto out_free;
-+	buf = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (buf) {
-+		as->buffer_dma = buf->start;
-+		as->buffer_size
-+			= rounddown_pow_of_two(buf->end - buf->start + 1);
-+		if (as->buffer_size) {
-+			as->buffer = (void __force *)ioremap(buf->start,
-+					as->buffer_size);
-+			if (as->buffer)
-+				as->always_bounce = true;
-+		}
-+	}
-+
-+	if (!as->buffer) {
-+		/*
-+		 * Scratch buffer is used for throwaway rx and tx data.
-+		 * It's coherent to minimize dcache pollution.
-+		 */
-+		as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
-+						&as->buffer_dma, GFP_KERNEL);
-+		if (!as->buffer)
-+			goto out_free;
-+	}
- 
- 	spin_lock_init(&as->lock);
-+	init_waitqueue_head(&as->wait);
- 	INIT_LIST_HEAD(&as->queue);
-+	INIT_WORK(&as->work, atmel_spi_work);
- 	as->pdev = pdev;
-+	as->clk = clk;
- 	as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
- 	if (!as->regs)
- 		goto out_free_buffer;
--	as->irq = irq;
--	as->clk = clk;
--	if (!cpu_is_at91rm9200())
--		as->new_1 = 1;
- 
--	ret = request_irq(irq, atmel_spi_interrupt, 0,
--			pdev->dev.bus_id, master);
-+	ret = request_irq(irq, atmel_spi_interrupt, 0, pdev->dev.bus_id, as);
- 	if (ret)
- 		goto out_unmap_regs;
- 
-+	as->workqueue = create_singlethread_workqueue(pdev->dev.bus_id);
-+	if (!as->workqueue)
-+		goto out_free_irq;
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	as->rx_client.event_callback = atmel_spi_dma_rx_event;
-+	dma_cap_set(DMA_SLAVE, as->rx_client.cap_mask);
-+	as->rx_client.slave = pdata->rx_dma_slave;
-+	pdata->rx_dma_slave->rx_reg = regs->start + SPI_RDR + 3;
-+
-+	as->tx_client.event_callback = atmel_spi_dma_tx_event;
-+	dma_cap_set(DMA_SLAVE, as->tx_client.cap_mask);
-+	as->tx_client.slave = pdata->tx_dma_slave;
-+	pdata->tx_dma_slave->tx_reg = regs->start + SPI_TDR + 3;
-+
-+	dma_async_client_register(&as->rx_client);
-+	dma_async_client_register(&as->tx_client);
-+	dma_async_client_chan_request(&as->rx_client);
-+	dma_async_client_chan_request(&as->tx_client);
-+#endif
-+
- 	/* Initialize the hardware */
- 	clk_enable(clk);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
-@@ -771,9 +1380,19 @@
- 	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
- 	spi_writel(as, CR, SPI_BIT(SPIEN));
- 
-+	/* v1 chips start out at half the peripheral bus speed. */
-+	as->base_hz = clk_get_rate(clk);
-+	if (!atmel_spi_is_v2())
-+		as->base_hz /= 2;
-+
- 	/* go! */
- 	dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
- 			(unsigned long)regs->start, irq);
-+	if (as->always_bounce)
-+		dev_info(&pdev->dev, "Using bounce buffer at 0x%08x len %zu\n",
-+				as->buffer_dma, as->buffer_size);
-+
-+	atmel_spi_init_debugfs(as);
- 
- 	ret = spi_register_master(master);
- 	if (ret)
-@@ -782,10 +1401,17 @@
- 	return 0;
- 
- out_reset_hw:
-+	atmel_spi_cleanup_debugfs(as);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
- 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
- 	clk_disable(clk);
--	free_irq(irq, master);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+out_free_irq:
-+	free_irq(irq, as);
- out_unmap_regs:
- 	iounmap(as->regs);
- out_free_buffer:
-@@ -801,34 +1427,34 @@
- {
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
- 
--	/* reset the hardware and block queue progress */
--	spin_lock_irq(&as->lock);
--	as->stopping = 1;
--	spi_writel(as, CR, SPI_BIT(SWRST));
--	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
--	spi_readl(as, SR);
--	spin_unlock_irq(&as->lock);
-+	/* Stop the queue */
-+	atmel_spi_stop_queue(as);
- 
--	/* Terminate remaining queued transfers */
--	list_for_each_entry(msg, &as->queue, queue) {
--		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
--		 * but we shouldn't depend on that...
--		 */
--		msg->status = -ESHUTDOWN;
--		msg->complete(msg->context);
--	}
-+	atmel_spi_cleanup_debugfs(as);
- 
--	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
--			as->buffer_dma);
-+	/* Shut down the hardware */
-+	spi_writel(as, CR, SPI_BIT(SWRST));
-+	spi_readl(as, SR);
- 
-+	/* Clean up */
-+	spi_unregister_master(master);
-+	free_irq(platform_get_irq(pdev, 0), as);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+	if (as->always_bounce)
-+		iounmap((void __iomem __force *)as->buffer);
-+	else
-+		dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
-+				as->buffer_dma);
-+	iounmap(as->regs);
- 	clk_disable(as->clk);
- 	clk_put(as->clk);
--	free_irq(as->irq, master);
--	iounmap(as->regs);
- 
--	spi_unregister_master(master);
-+	spi_master_put(master);
- 
- 	return 0;
- }
-@@ -840,7 +1466,9 @@
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
-+	atmel_spi_stop_queue(as);
- 	clk_disable(as->clk);
-+
- 	return 0;
- }
- 
-@@ -850,6 +1478,9 @@
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
- 	clk_enable(as->clk);
-+	as->stopping = false;
-+	smp_wmb();
-+
- 	return 0;
- }
- 
-@@ -871,7 +1502,12 @@
- 
- static int __init atmel_spi_init(void)
- {
--	return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	int ret;
-+
-+	ret = platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	if (ret)
-+		pr_notice("atmel_spi probe failed: %d\n", ret);
-+	return ret;
- }
- module_init(atmel_spi_init);
- 
-@@ -882,6 +1518,6 @@
- module_exit(atmel_spi_exit);
- 
- MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
--MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen at atmel.com>");
--MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-+MODULE_LICENSE("GPL v2");
- MODULE_ALIAS("platform:atmel_spi");
-diff -urN linux-2.6.28.2-0rig//drivers/spi/Kconfig linux-2.6.28.2/drivers/spi/Kconfig
---- linux-2.6.28.2-0rig//drivers/spi/Kconfig	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/spi/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -53,9 +53,14 @@
- 
- comment "SPI Master Controller Drivers"
- 
-+config SPI_ATMEL_HAVE_PDC
-+	def_bool y
-+	depends on (ARCH_AT91 || CPU_AT32AP700X)
-+
- config SPI_ATMEL
- 	tristate "Atmel SPI Controller"
- 	depends on (ARCH_AT91 || AVR32)
-+	depends on SPI_ATMEL_HAVE_PDC || DMA_ENGINE
- 	help
- 	  This selects a driver for the Atmel SPI Controller, present on
- 	  many AT32 (AVR32) and AT91 (ARM) chips.
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ehci-avr32.c linux-2.6.28.2/drivers/usb/host/ehci-avr32.c
---- linux-2.6.28.2-0rig//drivers/usb/host/ehci-avr32.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/ehci-avr32.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,213 @@
-+/*
-+ * AVR32 EHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ehci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ehci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+}
-+
-+static int ehci_avr32_setup(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
-+	int		ret;
-+
-+	ehci_avr32_start_clocks(dev);
-+
-+	ehci->caps = hcd->regs;
-+	ehci->regs = hcd->regs
-+		+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
-+	dbg_hcs_params(ehci, "reset");
-+	dbg_hcc_params(ehci, "reset");
-+
-+	/* cache this readonly data; minimize chip reads */
-+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-+
-+	ret = ehci_halt(ehci);
-+	if (ret)
-+		goto err;
-+
-+	/* data structure init */
-+	ret = ehci_init(hcd);
-+	if (ret)
-+		goto err;
-+
-+	ehci->sbrn = 0x20;
-+	ehci_port_power(ehci, 0);
-+
-+	return 0;
-+
-+err:
-+	ehci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ehci_avr32_shutdown(struct usb_hcd *hcd)
-+{
-+	ehci_shutdown(hcd);
-+	ehci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ehci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (EHCI)",
-+	.hcd_priv_size		= sizeof(struct ehci_hcd),
-+
-+	.irq			= ehci_irq,
-+	.flags			= HCD_MEMORY | HCD_USB2,
-+
-+	.reset			= ehci_avr32_setup,
-+	.start			= ehci_run,
-+	.stop			= ehci_stop,
-+	.shutdown		= ehci_avr32_shutdown,
-+
-+	.urb_enqueue		= ehci_urb_enqueue,
-+	.urb_dequeue		= ehci_urb_dequeue,
-+	.endpoint_disable	= ehci_endpoint_disable,
-+
-+	.get_frame_number	= ehci_get_frame,
-+
-+	.hub_status_data	= ehci_hub_status_data,
-+	.hub_control		= ehci_hub_control,
-+	.bus_suspend		= ehci_bus_suspend,
-+	.bus_resume		= ehci_bus_resume,
-+	.relinquish_port	= ehci_relinquish_port,
-+	.port_handed_over	= ehci_port_handed_over,
-+};
-+
-+static int ehci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*reg_res;
-+	struct usb_hcd		*hcd;
-+	struct ehci_hcd		*ehci;
-+	int			irq;
-+	int			ret;
-+
-+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!reg_res) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+
-+	if (!request_mem_region(reg_res->start,
-+				reg_res->end - reg_res->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+
-+	hcd = usb_create_hcd(&ehci_avr32_hc_driver, &pdev->dev, "ehci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = reg_res->start;
-+	hcd->rsrc_len = reg_res->end - reg_res->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ehci = hcd_to_ehci(hcd);
-+	ehci->big_endian_mmio = 1;
-+	ehci->big_endian_desc = 1;
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(reg_res->start, reg_res->end - reg_res->start + 1);
-+err_request_mmio:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ehci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ehci_avr32_suspend	NULL
-+#define ehci_avr32_resume	NULL
-+
-+static struct platform_driver ehci_hcd_avr32_driver = {
-+	.probe		= ehci_avr32_probe,
-+	.remove		= ehci_avr32_remove,
-+	.suspend	= ehci_avr32_suspend,
-+	.resume		= ehci_avr32_resume,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.driver		= {
-+		.name	= "ehci",
-+	},
-+};
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ehci-hcd.c linux-2.6.28.2/drivers/usb/host/ehci-hcd.c
---- linux-2.6.28.2-0rig//drivers/usb/host/ehci-hcd.c	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/ehci-hcd.c	2009-01-29 08:52:50.000000000 +0100
-@@ -1014,6 +1014,11 @@
- #define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ehci-avr32.c"
-+#define PLATFORM_DRIVER		ehci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_PPC_PS3
- #include "ehci-ps3.c"
- #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/Kconfig linux-2.6.28.2/drivers/usb/host/Kconfig
---- linux-2.6.28.2-0rig//drivers/usb/host/Kconfig	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -73,12 +73,12 @@
- 
- config USB_EHCI_BIG_ENDIAN_MMIO
- 	bool
--	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_BIG_ENDIAN_DESC
- 	bool
--	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_FSL
-@@ -196,17 +196,19 @@
- config USB_OHCI_BIG_ENDIAN_DESC
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_BIG_ENDIAN_MMIO
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_LITTLE_ENDIAN
- 	bool
- 	depends on USB_OHCI_HCD
--	default n if STB03xxx || PPC_MPC52xx
-+	default n if STB03xxx || PPC_MPC52xx || AVR32
- 	default y
- 
- config USB_UHCI_HCD
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci-avr32.c linux-2.6.28.2/drivers/usb/host/ohci-avr32.c
---- linux-2.6.28.2-0rig//drivers/usb/host/ohci-avr32.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/ohci-avr32.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,208 @@
-+/*
-+ * AVR32 OHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+/* Grr! The core layer doesn't let us keep private data anywhere! */
-+static struct clk	*ohci_clk;
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ohci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(ohci_clk);
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ohci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+	clk_disable(ohci_clk);
-+}
-+
-+static int ohci_avr32_start(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
-+	int		ret;
-+
-+	ohci_avr32_start_clocks(dev);
-+
-+	ret = ohci_init(ohci);
-+	if (ret)
-+		goto err_ohci_init;
-+
-+	ret = ohci_run(ohci);
-+	if (likely(!ret))
-+		return 0;
-+
-+	ohci_stop(hcd);
-+
-+err_ohci_init:
-+	ohci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ohci_avr32_stop(struct usb_hcd *hcd)
-+{
-+	ohci_stop(hcd);
-+	ohci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ohci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (OHCI)",
-+	.hcd_priv_size		= sizeof(struct ohci_hcd),
-+
-+	.irq			= ohci_irq,
-+	.flags			= HCD_USB11 | HCD_MEMORY,
-+
-+	.start			= ohci_avr32_start,
-+	.stop			= ohci_avr32_stop,
-+	.shutdown		= ohci_shutdown,
-+
-+	.urb_enqueue		= ohci_urb_enqueue,
-+	.urb_dequeue		= ohci_urb_dequeue,
-+	.endpoint_disable	= ohci_endpoint_disable,
-+	.get_frame_number	= ohci_get_frame,
-+	.hub_status_data	= ohci_hub_status_data,
-+	.hub_control		= ohci_hub_control,
-+#ifdef CONFIG_PM
-+	.bus_suspend		= ohci_bus_suspend,
-+	.bus_resume		= ohci_bus_resume,
-+#endif
-+	.start_port_reset	= ohci_start_port_reset,
-+};
-+
-+static int ohci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*regs;
-+	struct usb_hcd		*hcd;
-+	int			irq;
-+	int			ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+	ohci_clk = clk_get(&pdev->dev, "ohci_clk");
-+	if (IS_ERR(ohci_clk)) {
-+		dev_dbg(&pdev->dev, "no OHCI clock\n");
-+		ret = -ENXIO;
-+		goto err_ohci_clk;
-+	}
-+
-+	if (!request_mem_region(regs->start, regs->end - regs->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+	hcd = usb_create_hcd(&ohci_avr32_hc_driver, &pdev->dev, "ohci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = regs->start;
-+	hcd->rsrc_len = regs->end - regs->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ohci_hcd_init(hcd_to_ohci(hcd));
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(regs->start, regs->end - regs->start + 1);
-+err_request_mmio:
-+	clk_put(ohci_clk);
-+err_ohci_clk:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ohci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(ohci_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ohci_avr32_suspend	NULL
-+#define ohci_avr32_resume	NULL
-+
-+static struct platform_driver ohci_hcd_avr32_driver = {
-+	.probe		= ohci_avr32_probe,
-+	.remove		= ohci_avr32_remove,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.suspend	= ohci_avr32_suspend,
-+	.resume		= ohci_avr32_resume,
-+	.driver		= {
-+		.owner	= THIS_MODULE,
-+		.name	= "ohci",
-+	},
-+};
-+MODULE_ALIAS("platform:ohci");
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci.h linux-2.6.28.2/drivers/usb/host/ohci.h
---- linux-2.6.28.2-0rig//drivers/usb/host/ohci.h	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/ohci.h	2009-01-29 08:52:50.000000000 +0100
-@@ -646,8 +646,10 @@
-  * some big-endian SOC implementations.  Same thing happens with PSW access.
-  */
- 
--#ifdef CONFIG_PPC_MPC52xx
-+#if defined(CONFIG_PPC_MPC52xx)
- #define big_endian_frame_no_quirk(ohci)	(ohci->flags & OHCI_QUIRK_FRAME_NO)
-+#elif defined(CONFIG_AVR32)
-+#define big_endian_frame_no_quirk(ohci)	1
- #else
- #define big_endian_frame_no_quirk(ohci)	0
- #endif
-diff -urN linux-2.6.28.2-0rig//drivers/usb/host/ohci-hcd.c linux-2.6.28.2/drivers/usb/host/ohci-hcd.c
---- linux-2.6.28.2-0rig//drivers/usb/host/ohci-hcd.c	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/host/ohci-hcd.c	2009-01-29 08:52:50.000000000 +0100
-@@ -1042,6 +1042,11 @@
- #define PLATFORM_DRIVER		ohci_hcd_at91_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ohci-avr32.c"
-+#define PLATFORM_DRIVER		ohci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_ARCH_PNX4008
- #include "ohci-pnx4008.c"
- #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
-diff -urN linux-2.6.28.2-0rig//drivers/usb/Kconfig linux-2.6.28.2/drivers/usb/Kconfig
---- linux-2.6.28.2-0rig//drivers/usb/Kconfig	2009-01-29 08:39:25.000000000 +0100
-+++ linux-2.6.28.2/drivers/usb/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -56,6 +56,7 @@
- 	default y if PPC_83xx
- 	default y if SOC_AU1200
- 	default y if ARCH_IXP4XX
-+	default y if AVR32
- 	default PCI
- 
- # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
-diff -urN linux-2.6.28.2-0rig//drivers/watchdog/at32ap700x_wdt.c linux-2.6.28.2/drivers/watchdog/at32ap700x_wdt.c
---- linux-2.6.28.2-0rig//drivers/watchdog/at32ap700x_wdt.c	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/watchdog/at32ap700x_wdt.c	1970-01-01 01:00:00.000000000 +0100
-@@ -1,449 +0,0 @@
--/*
-- * Watchdog driver for Atmel AT32AP700X devices
-- *
-- * Copyright (C) 2005-2006 Atmel Corporation
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- *
-- * Errata: WDT Clear is blocked after WDT Reset
-- *
-- * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-- * register, preventing the program to clear the next Watchdog Timer Reset.
-- *
-- * If you still want to use the WDT after a WDT reset a small code can be
-- * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-- * and use a GPIO pin to reset the system. This method requires that one of the
-- * GPIO pins are available and connected externally to the RESET_N pin. After
-- * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-- * the pin tristated with pullup.
-- */
--
--#include <linux/init.h>
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/moduleparam.h>
--#include <linux/miscdevice.h>
--#include <linux/fs.h>
--#include <linux/platform_device.h>
--#include <linux/watchdog.h>
--#include <linux/uaccess.h>
--#include <linux/io.h>
--#include <linux/spinlock.h>
--
--#define TIMEOUT_MIN		1
--#define TIMEOUT_MAX		2
--#define TIMEOUT_DEFAULT		TIMEOUT_MAX
--
--/* module parameters */
--static int timeout =  TIMEOUT_DEFAULT;
--module_param(timeout, int, 0);
--MODULE_PARM_DESC(timeout,
--		"Timeout value. Limited to be 1 or 2 seconds. (default="
--		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
--
--static int nowayout = WATCHDOG_NOWAYOUT;
--module_param(nowayout, int, 0);
--MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
--		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
--
--/* Watchdog registers and write/read macro */
--#define WDT_CTRL		0x00
--#define WDT_CTRL_EN		   0
--#define WDT_CTRL_PSEL		   8
--#define WDT_CTRL_KEY		  24
--
--#define WDT_CLR			0x04
--
--#define WDT_RCAUSE		0x10
--#define WDT_RCAUSE_POR		   0
--#define WDT_RCAUSE_EXT		   2
--#define WDT_RCAUSE_WDT		   3
--#define WDT_RCAUSE_JTAG		   4
--#define WDT_RCAUSE_SERP		   5
--
--#define WDT_BIT(name)		(1 << WDT_##name)
--#define WDT_BF(name, value)	((value) << WDT_##name)
--
--#define wdt_readl(dev, reg)				\
--	__raw_readl((dev)->regs + WDT_##reg)
--#define wdt_writel(dev, reg, value)			\
--	__raw_writel((value), (dev)->regs + WDT_##reg)
--
--struct wdt_at32ap700x {
--	void __iomem		*regs;
--	spinlock_t		io_lock;
--	int			timeout;
--	int			boot_status;
--	unsigned long		users;
--	struct miscdevice	miscdev;
--};
--
--static struct wdt_at32ap700x *wdt;
--static char expect_release;
--
--/*
-- * Disable the watchdog.
-- */
--static inline void at32_wdt_stop(void)
--{
--	unsigned long psel;
--
--	spin_lock(&wdt->io_lock);
--	psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Enable and reset the watchdog.
-- */
--static inline void at32_wdt_start(void)
--{
--	/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
--	unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
--
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Pat the watchdog timer.
-- */
--static inline void at32_wdt_pat(void)
--{
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CLR, 0x42);
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Watchdog device is opened, and watchdog starts running.
-- */
--static int at32_wdt_open(struct inode *inode, struct file *file)
--{
--	if (test_and_set_bit(1, &wdt->users))
--		return -EBUSY;
--
--	at32_wdt_start();
--	return nonseekable_open(inode, file);
--}
--
--/*
-- * Close the watchdog device.
-- */
--static int at32_wdt_close(struct inode *inode, struct file *file)
--{
--	if (expect_release == 42) {
--		at32_wdt_stop();
--	} else {
--		dev_dbg(wdt->miscdev.parent,
--			"unexpected close, not stopping watchdog!\n");
--		at32_wdt_pat();
--	}
--	clear_bit(1, &wdt->users);
--	expect_release = 0;
--	return 0;
--}
--
--/*
-- * Change the watchdog time interval.
-- */
--static int at32_wdt_settimeout(int time)
--{
--	/*
--	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
--	 * 2 ^ 16 allowing up to 2 seconds timeout.
--	 */
--	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
--		return -EINVAL;
--
--	/*
--	 * Set new watchdog time. It will be used when at32_wdt_start() is
--	 * called.
--	 */
--	wdt->timeout = time;
--	return 0;
--}
--
--/*
-- * Get the watchdog status.
-- */
--static int at32_wdt_get_status(void)
--{
--	int rcause;
--	int status = 0;
--
--	rcause = wdt_readl(wdt, RCAUSE);
--
--	switch (rcause) {
--	case WDT_BIT(RCAUSE_EXT):
--		status = WDIOF_EXTERN1;
--		break;
--	case WDT_BIT(RCAUSE_WDT):
--		status = WDIOF_CARDRESET;
--		break;
--	case WDT_BIT(RCAUSE_POR):  /* fall through */
--	case WDT_BIT(RCAUSE_JTAG): /* fall through */
--	case WDT_BIT(RCAUSE_SERP): /* fall through */
--	default:
--		break;
--	}
--
--	return status;
--}
--
--static struct watchdog_info at32_wdt_info = {
--	.identity	= "at32ap700x watchdog",
--	.options	= WDIOF_SETTIMEOUT |
--			  WDIOF_KEEPALIVEPING |
--			  WDIOF_MAGICCLOSE,
--};
--
--/*
-- * Handle commands from user-space.
-- */
--static long at32_wdt_ioctl(struct file *file,
--				unsigned int cmd, unsigned long arg)
--{
--	int ret = -ENOTTY;
--	int time;
--	void __user *argp = (void __user *)arg;
--	int __user *p = argp;
--
--	switch (cmd) {
--	case WDIOC_GETSUPPORT:
--		ret = copy_to_user(argp, &at32_wdt_info,
--				sizeof(at32_wdt_info)) ? -EFAULT : 0;
--		break;
--	case WDIOC_GETSTATUS:
--		ret = put_user(0, p);
--		break;
--	case WDIOC_GETBOOTSTATUS:
--		ret = put_user(wdt->boot_status, p);
--		break;
--	case WDIOC_SETOPTIONS:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		if (time & WDIOS_DISABLECARD)
--			at32_wdt_stop();
--		if (time & WDIOS_ENABLECARD)
--			at32_wdt_start();
--		ret = 0;
--		break;
--	case WDIOC_KEEPALIVE:
--		at32_wdt_pat();
--		ret = 0;
--		break;
--	case WDIOC_SETTIMEOUT:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		ret = at32_wdt_settimeout(time);
--		if (ret)
--			break;
--		/* Enable new time value */
--		at32_wdt_start();
--		/* fall through */
--	case WDIOC_GETTIMEOUT:
--		ret = put_user(wdt->timeout, p);
--		break;
--	}
--
--	return ret;
--}
--
--static ssize_t at32_wdt_write(struct file *file, const char __user *data,
--				size_t len, loff_t *ppos)
--{
--	/* See if we got the magic character 'V' and reload the timer */
--	if (len) {
--		if (!nowayout) {
--			size_t i;
--
--			/*
--			 * note: just in case someone wrote the magic
--			 * character five months ago...
--			 */
--			expect_release = 0;
--
--			/*
--			 * scan to see whether or not we got the magic
--			 * character
--			 */
--			for (i = 0; i != len; i++) {
--				char c;
--				if (get_user(c, data + i))
--					return -EFAULT;
--				if (c == 'V')
--					expect_release = 42;
--			}
--		}
--		/* someone wrote to us, we should pat the watchdog */
--		at32_wdt_pat();
--	}
--	return len;
--}
--
--static const struct file_operations at32_wdt_fops = {
--	.owner		= THIS_MODULE,
--	.llseek		= no_llseek,
--	.unlocked_ioctl	= at32_wdt_ioctl,
--	.open		= at32_wdt_open,
--	.release	= at32_wdt_close,
--	.write		= at32_wdt_write,
--};
--
--static int __init at32_wdt_probe(struct platform_device *pdev)
--{
--	struct resource	*regs;
--	int ret;
--
--	if (wdt) {
--		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
--		return -EBUSY;
--	}
--
--	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	if (!regs) {
--		dev_dbg(&pdev->dev, "missing mmio resource\n");
--		return -ENXIO;
--	}
--
--	wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
--	if (!wdt) {
--		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
--		return -ENOMEM;
--	}
--
--	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
--	if (!wdt->regs) {
--		ret = -ENOMEM;
--		dev_dbg(&pdev->dev, "could not map I/O memory\n");
--		goto err_free;
--	}
--
--	spin_lock_init(&wdt->io_lock);
--	wdt->boot_status = at32_wdt_get_status();
--
--	/* Work-around for watchdog silicon errata. */
--	if (wdt->boot_status & WDIOF_CARDRESET) {
--		dev_info(&pdev->dev, "CPU must be reset with external "
--				"reset or POR due to silicon errata.\n");
--		ret = -EIO;
--		goto err_iounmap;
--	} else {
--		wdt->users = 0;
--	}
--	wdt->miscdev.minor = WATCHDOG_MINOR;
--	wdt->miscdev.name = "watchdog";
--	wdt->miscdev.fops = &at32_wdt_fops;
--
--	if (at32_wdt_settimeout(timeout)) {
--		at32_wdt_settimeout(TIMEOUT_DEFAULT);
--		dev_dbg(&pdev->dev,
--			"default timeout invalid, set to %d sec.\n",
--			TIMEOUT_DEFAULT);
--	}
--
--	ret = misc_register(&wdt->miscdev);
--	if (ret) {
--		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
--		goto err_iounmap;
--	}
--
--	platform_set_drvdata(pdev, wdt);
--	wdt->miscdev.parent = &pdev->dev;
--	dev_info(&pdev->dev,
--		"AT32AP700X WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
--		wdt->regs, wdt->timeout, nowayout);
--
--	return 0;
--
--err_iounmap:
--	iounmap(wdt->regs);
--err_free:
--	kfree(wdt);
--	wdt = NULL;
--	return ret;
--}
--
--static int __exit at32_wdt_remove(struct platform_device *pdev)
--{
--	if (wdt && platform_get_drvdata(pdev) == wdt) {
--		/* Stop the timer before we leave */
--		if (!nowayout)
--			at32_wdt_stop();
--
--		misc_deregister(&wdt->miscdev);
--		iounmap(wdt->regs);
--		kfree(wdt);
--		wdt = NULL;
--		platform_set_drvdata(pdev, NULL);
--	}
--	return 0;
--}
--
--static void at32_wdt_shutdown(struct platform_device *pdev)
--{
--	at32_wdt_stop();
--}
--
--#ifdef CONFIG_PM
--static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
--{
--	at32_wdt_stop();
--	return 0;
--}
--
--static int at32_wdt_resume(struct platform_device *pdev)
--{
--	if (wdt->users)
--		at32_wdt_start();
--	return 0;
--}
--#else
--#define at32_wdt_suspend NULL
--#define at32_wdt_resume NULL
--#endif
--
--/* work with hotplug and coldplug */
--MODULE_ALIAS("platform:at32_wdt");
--
--static struct platform_driver at32_wdt_driver = {
--	.remove		= __exit_p(at32_wdt_remove),
--	.suspend	= at32_wdt_suspend,
--	.resume		= at32_wdt_resume,
--	.driver		= {
--		.name	= "at32_wdt",
--		.owner	= THIS_MODULE,
--	},
--	.shutdown	= at32_wdt_shutdown,
--};
--
--static int __init at32_wdt_init(void)
--{
--	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
--}
--module_init(at32_wdt_init);
--
--static void __exit at32_wdt_exit(void)
--{
--	platform_driver_unregister(&at32_wdt_driver);
--}
--module_exit(at32_wdt_exit);
--
--MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt at atmel.com>");
--MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
--MODULE_LICENSE("GPL");
--MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff -urN linux-2.6.28.2-0rig//drivers/watchdog/at32_wdt.c linux-2.6.28.2/drivers/watchdog/at32_wdt.c
---- linux-2.6.28.2-0rig//drivers/watchdog/at32_wdt.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/watchdog/at32_wdt.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,620 @@
-+/*
-+ * Watchdog driver for Atmel AVR32 devices
-+ *
-+ * Copyright (C) 2005-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ *
-+ * AT32AP700x Errata: WDT Clear is blocked after WDT Reset
-+ *
-+ * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-+ * register, preventing the program to clear the next Watchdog Timer Reset.
-+ *
-+ * If you still want to use the WDT after a WDT reset a small code can be
-+ * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-+ * and use a GPIO pin to reset the system. This method requires that one of the
-+ * GPIO pins are available and connected externally to the RESET_N pin. After
-+ * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-+ * the pin tristated with pullup.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/platform_device.h>
-+#include <linux/watchdog.h>
-+#include <linux/uaccess.h>
-+#include <linux/io.h>
-+#include <linux/log2.h>
-+#include <linux/spinlock.h>
-+
-+#include <mach/cpu.h>
-+#include <mach/pm.h>
-+
-+/*
-+ * AT32AP700x uses a 16-bit prescaler. This limits the timeout range
-+ * somewhat. Later chips use a 32-bit prescaler.
-+ */
-+#define TIMEOUT_MIN		1
-+#ifdef CONFIG_CPU_AT32AP700X
-+# define TIMEOUT_MAX		2
-+# define TIMEOUT_DEFAULT	TIMEOUT_MAX
-+#else
-+# define TIMEOUT_MAX		131072
-+# define TIMEOUT_DEFAULT	64
-+#endif
-+
-+/* module parameters */
-+static int timeout =  TIMEOUT_DEFAULT;
-+module_param(timeout, int, 0);
-+MODULE_PARM_DESC(timeout,
-+		"Timeout value. Any power of two between 1 and "
-+		__MODULE_STRING(TIMEOUT_MAX) " seconds. (default="
-+		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
-+
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
-+		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+/* Watchdog registers and write/read macro */
-+#define WDT_CTRL		0x00
-+#define WDT_CTRL_EN		   0
-+#define WDT_CTRL_PSEL		   8
-+#define WDT_CTRL_CEN		  16
-+#define WDT_CTRL_CSEL		  17
-+#define WDT_CTRL_KEY		  24
-+
-+#define WDT_CLR			0x04
-+
-+#define WDT_BIT(name)		(1 << WDT_##name)
-+#define WDT_BF(name, value)	((value) << WDT_##name)
-+
-+#define wdt_readl(dev, reg)				\
-+	__raw_readl((dev)->regs + WDT_##reg)
-+#define wdt_writel(dev, reg, value)			\
-+	__raw_writel((value), (dev)->regs + WDT_##reg)
-+
-+struct wdt_at32 {
-+	void __iomem		*regs;
-+	struct clk		*pclk;
-+	struct clk		*src_clk;
-+	spinlock_t		io_lock;
-+	int			timeout;
-+	int			boot_status;
-+	unsigned long		users;
-+	struct miscdevice	miscdev;
-+};
-+
-+static struct wdt_at32 *wdt;
-+static char expect_release;
-+
-+static inline void wdt_clk_enable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_enable(w->pclk);
-+}
-+
-+static inline void wdt_clk_disable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_disable(w->pclk);
-+}
-+
-+static inline int at32_wdt_version(void)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static unsigned long at32_wdt_calc_psel(int timeout)
-+{
-+	if (at32_wdt_version() == 1)
-+		/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
-+		return (timeout > 1) ? 0xf : 0xe;
-+
-+	return order_base_2(timeout) + 14;
-+}
-+
-+/*
-+ * Disable the watchdog.
-+ */
-+static inline void at32_wdt_stop(void)
-+{
-+	unsigned long ctrl;
-+	unsigned long ctrl_mask = 0;
-+
-+	switch (at32_wdt_version()) {
-+	case 3:
-+		ctrl_mask |= (1 << WDT_CTRL_CEN) | (1 << WDT_CTRL_CSEL);
-+		/* fall through */
-+	case 2:
-+		ctrl_mask |= 0x1f << WDT_CTRL_PSEL;
-+		break;
-+	case 1:
-+		ctrl_mask |= 0x0f << WDT_CTRL_PSEL;
-+		break;
-+	}
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	ctrl = wdt_readl(wdt, CTRL);
-+	ctrl &= ctrl_mask;
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Enable and reset the watchdog.
-+ */
-+static inline void at32_wdt_start(void)
-+{
-+	unsigned long psel;
-+	unsigned long ctrl;
-+
-+	psel = at32_wdt_calc_psel(wdt->timeout);
-+	ctrl = WDT_BIT(CTRL_EN) | WDT_BF(CTRL_PSEL, psel);
-+
-+	if (at32_wdt_version() >= 3)
-+		ctrl |= wdt_readl(wdt, CTRL)
-+			& (WDT_BIT(CTRL_CSEL) | WDT_BIT(CTRL_CEN));
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Pat the watchdog timer.
-+ */
-+static inline void at32_wdt_pat(void)
-+{
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CLR, 0x42);
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Watchdog device is opened, and watchdog starts running.
-+ */
-+static int at32_wdt_open(struct inode *inode, struct file *file)
-+{
-+	if (test_and_set_bit(1, &wdt->users))
-+		return -EBUSY;
-+
-+	at32_wdt_start();
-+	return nonseekable_open(inode, file);
-+}
-+
-+/*
-+ * Close the watchdog device.
-+ */
-+static int at32_wdt_close(struct inode *inode, struct file *file)
-+{
-+	if (expect_release == 42) {
-+		at32_wdt_stop();
-+	} else {
-+		dev_dbg(wdt->miscdev.parent,
-+			"unexpected close, not stopping watchdog!\n");
-+		at32_wdt_pat();
-+	}
-+	clear_bit(1, &wdt->users);
-+	expect_release = 0;
-+	return 0;
-+}
-+
-+/*
-+ * Change the watchdog time interval.
-+ */
-+static int at32_wdt_settimeout(int time)
-+{
-+	/*
-+	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max
-+	 * prescaler is 2 ^ 16 (or 2 ^ 32) allowing up to TIMEOUT_MAX
-+	 * seconds timeout.
-+	 */
-+	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX)
-+			|| !is_power_of_2(time))
-+		return -EINVAL;
-+
-+	/*
-+	 * Set new watchdog time. It will be used when at32_wdt_start() is
-+	 * called.
-+	 */
-+	wdt->timeout = time;
-+	return 0;
-+}
-+
-+/*
-+ * Get the watchdog status.
-+ */
-+static int at32_wdt_get_status(void)
-+{
-+	int rcause;
-+	int status = 0;
-+
-+	rcause = at32_get_reset_cause();
-+
-+	switch (rcause) {
-+	case AT32_RCAUSE_BOD:
-+		status = WDIOF_POWERUNDER;
-+		break;
-+	case AT32_RCAUSE_EXT:
-+		status = WDIOF_EXTERN1;
-+		break;
-+	case AT32_RCAUSE_JTAG:
-+	case AT32_RCAUSE_JTAGHARD:
-+	case AT32_RCAUSE_OCDRST:
-+		status = WDIOF_EXTERN2;
-+		break;
-+	case AT32_RCAUSE_WDT:
-+		status = WDIOF_CARDRESET;
-+		break;
-+	case AT32_RCAUSE_POR:
-+	case AT32_RCAUSE_NTAE:
-+	case AT32_RCAUSE_SLEEP:
-+	case AT32_RCAUSE_CPUERR:
-+	default:
-+		break;
-+	}
-+
-+	return status;
-+}
-+
-+static struct watchdog_info at32_wdt_info = {
-+	.identity	= "at32 watchdog",
-+	.options	= WDIOF_SETTIMEOUT |
-+			  WDIOF_KEEPALIVEPING |
-+			  WDIOF_MAGICCLOSE,
-+};
-+
-+/*
-+ * Handle commands from user-space.
-+ */
-+static long at32_wdt_ioctl(struct file *file,
-+				unsigned int cmd, unsigned long arg)
-+{
-+	int ret = -ENOTTY;
-+	int time;
-+	void __user *argp = (void __user *)arg;
-+	int __user *p = argp;
-+
-+	switch (cmd) {
-+	case WDIOC_GETSUPPORT:
-+		ret = copy_to_user(argp, &at32_wdt_info,
-+				sizeof(at32_wdt_info)) ? -EFAULT : 0;
-+		break;
-+	case WDIOC_GETSTATUS:
-+		ret = put_user(0, p);
-+		break;
-+	case WDIOC_GETBOOTSTATUS:
-+		ret = put_user(wdt->boot_status, p);
-+		break;
-+	case WDIOC_SETOPTIONS:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		if (time & WDIOS_DISABLECARD)
-+			at32_wdt_stop();
-+		if (time & WDIOS_ENABLECARD)
-+			at32_wdt_start();
-+		ret = 0;
-+		break;
-+	case WDIOC_KEEPALIVE:
-+		at32_wdt_pat();
-+		ret = 0;
-+		break;
-+	case WDIOC_SETTIMEOUT:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		ret = at32_wdt_settimeout(time);
-+		if (ret)
-+			break;
-+		/* Enable new time value */
-+		at32_wdt_start();
-+		/* fall through */
-+	case WDIOC_GETTIMEOUT:
-+		ret = put_user(wdt->timeout, p);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static ssize_t at32_wdt_write(struct file *file, const char __user *data,
-+				size_t len, loff_t *ppos)
-+{
-+	/* See if we got the magic character 'V' and reload the timer */
-+	if (len) {
-+		if (!nowayout) {
-+			size_t i;
-+
-+			/*
-+			 * note: just in case someone wrote the magic
-+			 * character five months ago...
-+			 */
-+			expect_release = 0;
-+
-+			/*
-+			 * scan to see whether or not we got the magic
-+			 * character
-+			 */
-+			for (i = 0; i != len; i++) {
-+				char c;
-+				if (get_user(c, data + i))
-+					return -EFAULT;
-+				if (c == 'V')
-+					expect_release = 42;
-+			}
-+		}
-+		/* someone wrote to us, we should pat the watchdog */
-+		at32_wdt_pat();
-+	}
-+	return len;
-+}
-+
-+static const struct file_operations at32_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.llseek		= no_llseek,
-+	.unlocked_ioctl	= at32_wdt_ioctl,
-+	.open		= at32_wdt_open,
-+	.release	= at32_wdt_close,
-+	.write		= at32_wdt_write,
-+};
-+
-+static int __init at32_wdt_enable_source_clock(struct platform_device *pdev)
-+{
-+	struct clk	*clk;
-+	unsigned int	csel;
-+	u32		ctrl;
-+
-+	/* Only v3+ have selectable source clock */
-+	if (at32_wdt_version() < 3)
-+		return 0;
-+
-+	csel = 1;
-+
-+	/*
-+	 * Prefer the much more accurate crystal oscillator in favor
-+	 * of the RC oscillator.
-+	 */
-+	clk = clk_get(NULL, "osc32");
-+	if (IS_ERR(clk)) {
-+		csel = 0;
-+		clk = clk_get(NULL, "rcosc");
-+	}
-+	if (IS_ERR(clk)) {
-+		dev_dbg(&pdev->dev, "No source clock\n");
-+		return -ENXIO;
-+	}
-+
-+	clk_enable(clk);
-+
-+	dev_info(&pdev->dev, "Using 32 kHz %s oscillator\n",
-+			csel ? "crystal" : "RC");
-+
-+	wdt_clk_enable(wdt);
-+	ctrl = (csel << WDT_CTRL_CSEL) | (1 << WDT_CTRL_CEN);
-+
-+	/*
-+	 * Make sure the WDT is disabled, and disable any clocks that
-+	 * may have been selected earlier.
-+	 */
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	/* Select the new clock */
-+	wdt_writel(wdt, CTRL, ctrl | (0x55 << WDT_CTRL_KEY));
-+	wdt_writel(wdt, CTRL, ctrl | (0xaa << WDT_CTRL_KEY));
-+
-+	/* Wait for the new clock to become usable */
-+	while (!(wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN)))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+	return 0;
-+}
-+
-+static void at32_wdt_disable_source_clock(void)
-+{
-+	wdt_clk_enable(wdt);
-+
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+}
-+
-+static int __init at32_wdt_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	int ret;
-+
-+	if (wdt) {
-+		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
-+		return -EBUSY;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "missing mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	wdt = kzalloc(sizeof(struct wdt_at32), GFP_KERNEL);
-+	if (!wdt) {
-+		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
-+		return -ENOMEM;
-+	}
-+
-+	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!wdt->regs) {
-+		ret = -ENOMEM;
-+		dev_dbg(&pdev->dev, "could not map I/O memory\n");
-+		goto err_free;
-+	}
-+
-+	if (!cpu_is_at32ap7000()) {
-+		wdt->pclk = clk_get(&pdev->dev, "pclk");
-+		if (IS_ERR(wdt->pclk)) {
-+			dev_dbg(&pdev->dev, "no peripheral clock\n");
-+			ret = -ENXIO;
-+			goto err_iounmap;
-+		}
-+	}
-+
-+	ret = at32_wdt_enable_source_clock(pdev);
-+	if (ret)
-+		goto err_put_clk;
-+
-+	spin_lock_init(&wdt->io_lock);
-+	wdt->boot_status = at32_wdt_get_status();
-+
-+	/* Work-around for watchdog silicon errata. */
-+	if (cpu_is_at32ap7000()
-+			&& (wdt->boot_status & WDIOF_CARDRESET)) {
-+		dev_info(&pdev->dev, "CPU must be reset with external "
-+				"reset or POR due to silicon errata.\n");
-+		ret = -EIO;
-+		goto err_disable_source_clock;
-+	} else {
-+		wdt->users = 0;
-+	}
-+	wdt->miscdev.minor = WATCHDOG_MINOR;
-+	wdt->miscdev.name = "watchdog";
-+	wdt->miscdev.fops = &at32_wdt_fops;
-+
-+	if (at32_wdt_settimeout(timeout)) {
-+		at32_wdt_settimeout(TIMEOUT_DEFAULT);
-+		dev_dbg(&pdev->dev,
-+			"default timeout invalid, set to %d sec.\n",
-+			TIMEOUT_DEFAULT);
-+	}
-+
-+	ret = misc_register(&wdt->miscdev);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
-+		goto err_iounmap;
-+	}
-+
-+	platform_set_drvdata(pdev, wdt);
-+	wdt->miscdev.parent = &pdev->dev;
-+	dev_info(&pdev->dev,
-+		"AT32 WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
-+		wdt->regs, wdt->timeout, nowayout);
-+
-+	return 0;
-+
-+err_disable_source_clock:
-+	at32_wdt_disable_source_clock();
-+err_put_clk:
-+	if (!cpu_is_at32ap7000())
-+		clk_put(wdt->pclk);
-+err_iounmap:
-+	iounmap(wdt->regs);
-+err_free:
-+	kfree(wdt);
-+	wdt = NULL;
-+	return ret;
-+}
-+
-+static int __exit at32_wdt_remove(struct platform_device *pdev)
-+{
-+	if (wdt && platform_get_drvdata(pdev) == wdt) {
-+		/* Stop the timer before we leave */
-+		if (!nowayout) {
-+			at32_wdt_stop();
-+			at32_wdt_disable_source_clock();
-+		}
-+
-+		misc_deregister(&wdt->miscdev);
-+		if (!cpu_is_at32ap7000())
-+			clk_put(wdt->pclk);
-+		iounmap(wdt->regs);
-+		kfree(wdt);
-+		wdt = NULL;
-+		platform_set_drvdata(pdev, NULL);
-+	}
-+	return 0;
-+}
-+
-+static void at32_wdt_shutdown(struct platform_device *pdev)
-+{
-+	at32_wdt_stop();
-+}
-+
-+#ifdef CONFIG_PM
-+static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-+{
-+	at32_wdt_stop();
-+	return 0;
-+}
-+
-+static int at32_wdt_resume(struct platform_device *pdev)
-+{
-+	if (wdt->users)
-+		at32_wdt_start();
-+	return 0;
-+}
-+#else
-+#define at32_wdt_suspend NULL
-+#define at32_wdt_resume NULL
-+#endif
-+
-+/* work with hotplug and coldplug */
-+MODULE_ALIAS("platform:at32_wdt");
-+
-+static struct platform_driver at32_wdt_driver = {
-+	.remove		= __exit_p(at32_wdt_remove),
-+	.suspend	= at32_wdt_suspend,
-+	.resume		= at32_wdt_resume,
-+	.driver		= {
-+		.name	= "at32_wdt",
-+		.owner	= THIS_MODULE,
-+	},
-+	.shutdown	= at32_wdt_shutdown,
-+};
-+
-+static int __init at32_wdt_init(void)
-+{
-+	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
-+}
-+module_init(at32_wdt_init);
-+
-+static void __exit at32_wdt_exit(void)
-+{
-+	platform_driver_unregister(&at32_wdt_driver);
-+}
-+module_exit(at32_wdt_exit);
-+
-+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt at atmel.com>");
-+MODULE_DESCRIPTION("Watchdog driver for Atmel AVR32 devices");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff -urN linux-2.6.28.2-0rig//drivers/watchdog/Kconfig linux-2.6.28.2/drivers/watchdog/Kconfig
---- linux-2.6.28.2-0rig//drivers/watchdog/Kconfig	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/watchdog/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -237,12 +237,12 @@
- 
- # AVR32 Architecture
- 
--config AT32AP700X_WDT
--	tristate "AT32AP700x watchdog"
--	depends on CPU_AT32AP700X
-+config AT32_WDT
-+	tristate "AVR32 On-Chip Watchdog Timer"
-+	depends on AVR32
- 	help
--	  Watchdog timer embedded into AT32AP700x devices. This will reboot
--	  your system when the timeout is reached.
-+	  Watchdog timer embedded into AT32AP700x and similar devices.
-+	  This will reboot your system when the timeout is reached.
- 
- # BLACKFIN Architecture
- 
-diff -urN linux-2.6.28.2-0rig//drivers/watchdog/Makefile linux-2.6.28.2/drivers/watchdog/Makefile
---- linux-2.6.28.2-0rig//drivers/watchdog/Makefile	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/watchdog/Makefile	2009-01-29 08:52:50.000000000 +0100
-@@ -45,7 +45,7 @@
- # ARM26 Architecture
- 
- # AVR32 Architecture
--obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
-+obj-$(CONFIG_AT32_WDT) += at32_wdt.o
- 
- # BLACKFIN Architecture
- obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
-diff -urN linux-2.6.28.2-0rig//drivers/video/atmel_lcdfb.c linux-2.6.28.2/drivers/video/atmel_lcdfb.c
---- linux-2.6.28.2-0rig//drivers/video/atmel_lcdfb.c	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/video/atmel_lcdfb.c	2009-01-29 08:52:50.000000000 +0100
-@@ -178,7 +178,7 @@
- static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
- 	.type		= FB_TYPE_PACKED_PIXELS,
- 	.visual		= FB_VISUAL_TRUECOLOR,
--	.xpanstep	= 0,
-+	.xpanstep	= 1,
- 	.ypanstep	= 1,
- 	.ywrapstep	= 0,
- 	.accel		= FB_ACCEL_NONE,
-@@ -239,7 +239,7 @@
- }
- 
- static void atmel_lcdfb_update_dma(struct fb_info *info,
--			       struct fb_var_screeninfo *var)
-+                                   struct fb_var_screeninfo *var)
- {
- 	struct atmel_lcdfb_info *sinfo = info->par;
- 	struct fb_fix_screeninfo *fix = &info->fix;
-@@ -251,6 +251,8 @@
- 	dma_addr &= ~3UL;
- 
- 	/* Set framebuffer DMA base address and pixel offset */
-+	dev_dbg(info->device, "%s:\n", __func__);
-+        dev_dbg(info->device, "  *setting dma addr: 0x%lx \n", dma_addr); 
- 	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
- 
- 	atmel_lcdfb_update_dma2d(sinfo, var);
-@@ -493,6 +495,7 @@
- 	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
- 		 info->var.xres, info->var.yres,
- 		 info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * bpp:        %u\n", info->var.bits_per_pixel);
- 
- 	atmel_lcdfb_stop_nowait(sinfo);
- 
-@@ -594,7 +597,12 @@
- 	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
- 	/* Enable FIFO & DMA errors */
- 	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
--
-+        
-+        /* !!!HACK for logging end of frame and underruns 
-+           when connected to MPOP. */
-+        if( info->var.bits_per_pixel == 32 )
-+          lcdc_writel(sinfo, ATMEL_LCDC_IER, 0x70);
-+        
- 	/* ...wait for DMA engine to become idle... */
- 	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
- 		msleep(10);
-@@ -695,7 +703,7 @@
- }
- 
- static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
--			       struct fb_info *info)
-+                                   struct fb_info *info)
- {
- 	dev_dbg(info->device, "%s\n", __func__);
- 
-@@ -827,7 +835,8 @@
- 	info->fix = atmel_lcdfb_fix;
- 
- 	/* Enable LCDC Clocks */
--	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
-+	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()
-+			|| cpu_is_at32ap7200()) {
- 		sinfo->bus_clk = clk_get(dev, "hck1");
- 		if (IS_ERR(sinfo->bus_clk)) {
- 			ret = PTR_ERR(sinfo->bus_clk);
-diff -urN linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c linux-2.6.28.2/drivers/video/atmel_mpopfb.c
---- linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/drivers/video/atmel_mpopfb.c	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,1127 @@
-+/*
-+ *  Driver for AT91/AT32 LCD Controller
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file COPYING in the main directory of this archive for
-+ * more details.
-+ */
-+
-+#define DEBUG
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+
-+#include <mach/board.h>
-+#include <mach/cpu.h>
-+
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#define mpop_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
-+#define mpop_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
-+
-+#define	ATMEL_MPOPFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
-+                                         | FBINFO_PARTIAL_PAN_OK        \
-+                                         | FBINFO_HWACCEL_XPAN          \
-+                                         | FBINFO_HWACCEL_YPAN)
-+
-+static struct atmel_mpopfb_rgbconv_coeffs atmel_mpop_ycrcb2rgb_coeffs = {
-+	.r1 = 298,
-+	.r2 = 0,
-+	.r3 = 409,
-+	.r4 = -56992,
-+	.g1 = 298,
-+	.g2 = -100,
-+	.g3 = -208,
-+	.g4 = 34784,
-+	.b1 = 298,
-+	.b2 = 516,
-+	.b3 = 0,
-+	.b4 = -70688,
-+};
-+
-+static struct fb_fix_screeninfo atmel_mpopfb_fix __initdata = {
-+	.type		= FB_TYPE_PLANES,
-+	.visual		= FB_VISUAL_TRUECOLOR,
-+	.xpanstep	= 16,
-+	.ypanstep	= 1,
-+	.ywrapstep	= 1,
-+	.accel		= FB_ACCEL_NONE,
-+};
-+
-+static void atmel_mpopfb_update_sar(struct fb_info *info,
-+		struct fb_var_screeninfo *var)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_fix_screeninfo *fix = &info->fix;
-+	u32 y_sar, u_sar, v_sar, o1_sar, o2_sar, cursor_sar, next_sar;
-+
-+	u32 chroma_xres_virtual;
-+	u32 chroma_yres_virtual;
-+	u32 chroma_xres;
-+	u32 chroma_yres;
-+	u32 chroma_xoffset;
-+	u32 chroma_yoffset;
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual / 2;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres / 2;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset / 2;
-+		break;
-+	case 16:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	case 24:
-+		chroma_xres_virtual = var->xres_virtual;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	}
-+
-+	/* Setup pointer to YUV planes in YUV framebuffer. */
-+	y_sar = fix->smem_start + var->xoffset
-+		+ var->yoffset * var->xres_virtual;
-+	u_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ chroma_xoffset + chroma_yoffset * chroma_xres_virtual;
-+	v_sar = u_sar + chroma_xres_virtual * chroma_yres_virtual;
-+	next_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ 2 * chroma_xres_virtual * chroma_yres_virtual;
-+	o1_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize;
-+	o2_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize;
-+	cursor_sar = next_sar;
-+
-+	if (sinfo->baseimg_info.flip) {
-+		/* If we flip we must start with the last line in the frame. */
-+		y_sar += var->xres_virtual * (var->yres - 1);
-+		u_sar += chroma_xres_virtual * (chroma_yres - 1);
-+		v_sar += chroma_xres_virtual * (chroma_yres - 1);
-+	}
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * y_sar = 0x%x\n", y_sar);
-+	dev_dbg(info->device, "  * u_sar = 0x%x\n", u_sar);
-+	dev_dbg(info->device, "  * v_sar = 0x%x\n", v_sar);
-+	dev_dbg(info->device, "  * o1_sar = 0x%x\n", o1_sar);
-+	dev_dbg(info->device, "  * o2_sar = 0x%x\n", o2_sar);
-+	dev_dbg(info->device, "  * cursor_sar = 0x%x\n", cursor_sar);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_Y_SAR, y_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_U_SAR, u_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_V_SAR, v_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SAR, o1_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SAR, o2_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SAR, cursor_sar);
-+}
-+
-+static void atmel_mpopfb_free_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+
-+	dma_free_writecombine(info->device, info->fix.smem_len,
-+			(void __force *)info->screen_base,
-+			info->fix.smem_start);
-+}
-+
-+/**
-+ *	atmel_mpopfb_alloc_video_memory - Allocate framebuffer memory
-+ *	@sinfo: the frame buffer to allocate memory for
-+ */
-+static int atmel_mpopfb_alloc_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	info->fix.smem_len = (var->xres_virtual * var->yres_virtual
-+			* ((var->bits_per_pixel + 7) / 8));
-+
-+	info->screen_base
-+		= (void __iomem __force *)dma_alloc_writecombine(info->device,
-+				info->fix.smem_len,
-+				(dma_addr_t *)&info->fix.smem_start,
-+				GFP_KERNEL);
-+
-+	if (!info->screen_base)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+/**
-+ *      atmel_mpopfb_check_var - Validates a var passed in.
-+ *      @var: frame buffer variable screen structure
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Checks to see if the hardware supports the state requested by
-+ *	var passed in. This function does not alter the hardware
-+ *	state!!!  This means the data stored in struct fb_info and
-+ *	struct atmel_mpopfb_info do not change. This includes the var
-+ *	inside of struct fb_info.  Do NOT change these. This function
-+ *	can be called on its own if we intent to only test a mode and
-+ *	not actually set it. The stuff in modedb.c is a example of
-+ *	this. If the var passed in is slightly off by what the
-+ *	hardware can support then we alter the var PASSED in to what
-+ *	we can do. If the hardware doesn't support mode change a
-+ *	-EINVAL will be returned by the upper layers. You don't need
-+ *	to implement this function then. If you hardware doesn't
-+ *	support changing the resolution then this function is not
-+ *	needed. In this case the driver would just provide a var that
-+ *	represents the static state the screen is in.
-+ *
-+ *	Returns negative errno on error, or zero on success.
-+ */
-+static int atmel_mpopfb_check_var(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	struct device *dev = info->device;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(dev, "%s:\n", __func__);
-+	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
-+	dev_dbg(dev, "  offset: (%u,%u)\n", var->xoffset, var->yoffset);
-+	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
-+
-+	/*
-+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
-+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
-+	 */
-+
-+	if (var->vmode & FB_VMODE_CONUPDATE) {
-+		var->vmode |= FB_VMODE_YWRAP;
-+		var->xoffset = info->var.xoffset;
-+		var->yoffset = info->var.yoffset;
-+	}
-+
-+	/* Horizontal size must be a multiple of 16 pixels */
-+
-+	/*
-+	 *  Some very basic checks
-+	 */
-+	if (!var->xres)
-+		var->xres = 1;
-+	if (!var->yres)
-+		var->yres = 1;
-+	if (var->xres > var->xres_virtual)
-+		var->xres_virtual = var->xres;
-+	if (var->yres > var->yres_virtual)
-+		var->yres_virtual = var->yres;
-+	if (var->bits_per_pixel > 16)
-+		var->bits_per_pixel = 24;
-+	else if (var->bits_per_pixel > 12)
-+		var->bits_per_pixel = 16;
-+	else
-+		var->bits_per_pixel = 12;
-+
-+	/* Horizontal size and offset must be a multiple of 16 pixels */
-+	var->xres = (var->xres + 15) & ~15UL;
-+	var->xres_virtual = (var->xres_virtual + 15) & ~15UL;
-+	var->xoffset = (var->xoffset + 15) & ~15UL;
-+
-+	if (var->xres_virtual < var->xoffset + var->xres)
-+		var->xres_virtual = var->xoffset + var->xres;
-+	if (var->yres_virtual < var->yoffset + var->yres)
-+		var->yres_virtual = var->yoffset + var->yres;
-+
-+	/* Check that the scaled image will fit into the LCD display. */
-+	if (sinfo->baseimg_info.xsize > lcdc_info->var.xres) {
-+		dev_err(dev, "baseimage is wider than screen: %d > %d\n",
-+			sinfo->baseimg_info.xsize, lcdc_info->var.xres);
-+		return -EINVAL;
-+	}
-+
-+	if (sinfo->baseimg_info.ysize > lcdc_info->var.yres) {
-+		dev_err(dev, "baseimage is higher than screen: %d > %d\n",
-+			sinfo->baseimg_info.ysize, lcdc_info->var.yres);
-+		return -EINVAL;
-+	}
-+
-+	/* Check that it is possible to scale to given size. */
-+	if (ATMEL_MPOP_CALC_SCALE(var->xres, sinfo->baseimg_info.xsize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->xres,
-+					sinfo->baseimg_info.xsize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from width %d to %d Max %s\n",
-+			var->xres, sinfo->baseimg_info.xsize,
-+			ATMEL_MPOP_CALC_SCALE(var->xres,
-+					      sinfo->baseimg_info.xsize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	if (ATMEL_MPOP_CALC_SCALE(var->yres, sinfo->baseimg_info.ysize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->yres,
-+					sinfo->baseimg_info.ysize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from height %d to %d Max %s\n",
-+			var->yres, sinfo->baseimg_info.ysize,
-+			ATMEL_MPOP_CALC_SCALE(var->yres,
-+					      sinfo->baseimg_info.ysize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
-+	var->transp.msb_right = 0;
-+	var->transp.offset = var->transp.length = 0;
-+
-+	switch (var->bits_per_pixel) {
-+	case 12:
-+	case 16:
-+	case 24:
-+		var->red.offset = 0;
-+		var->green.offset = 8;
-+		var->blue.offset = 16;
-+		var->red.length = var->green.length = var->blue.length = 8;
-+		break;
-+	default:
-+		dev_err(dev, "color depth %d not supported\n",
-+			var->bits_per_pixel);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running) {
-+		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
-+
-+		/* Enable all error interrupts. */
-+		mpop_writel(sinfo, ATMEL_MPOP_INTEN, 0x7);
-+
-+		/*
-+		 * Enable the MPOP. When the LCD controller starts
-+		 * reading from the slave interface it will start
-+		 * generating a frame.
-+		 */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+			    ATMEL_MPOP_CR_EN_MASK
-+			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
-+
-+		sinfo->running = 1;
-+	}
-+}
-+
-+static void atmel_mpopfb_stop(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running)
-+		/* Not running. Already stopped. */
-+		return;
-+
-+	dev_dbg(sinfo->info->device, "Stopping MPOP.\n");
-+
-+	/* Disable the MPOP. This will force the MPOP to be reset. */
-+	mpop_writel(sinfo, ATMEL_MPOP_CR, 0);
-+
-+	/* Disable all interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTDIS, ~0UL);
-+
-+	/* Looks like we stopped the MPOP... */
-+	dev_dbg(sinfo->info->device, "MPOP stopped.\n");
-+
-+	sinfo->running = 0;
-+}
-+
-+static void atmel_mpopfb_connect_to_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Connecting MPOP to LCDC:\n");
-+
-+	/* Start the mpop if it is not running. */
-+	atmel_mpopfb_start(sinfo);
-+
-+	if (sinfo->connected_to_lcdc)
-+		/* Already connected. */
-+		return;
-+
-+	/*
-+	 * Set framebuffer pointer in LCDC to point to the slave
-+	 * interface of the MPOP.
-+	 */
-+	dev_dbg(sinfo->info->device, "  * Attaching to LCDC.\n");
-+	sinfo->lcdc_old_smem_start = lcdc_info->fix.smem_start;
-+	lcdc_info->fix.smem_start = (unsigned long)sinfo->slave_base;
-+	sinfo->lcdc_old_bits_per_pixel = lcdc_info->var.bits_per_pixel;
-+	lcdc_info->var.bits_per_pixel = 32;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 1;
-+}
-+
-+static void atmel_mpopfb_disconnect_from_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Disconnecting MPOP from LCDC:\n");
-+
-+	if (!sinfo->connected_to_lcdc)
-+		/* Already disconnected. */
-+		return;
-+
-+	/* Restore lcdc's old framebuffer pointer and pixel-format. */
-+	lcdc_info->fix.smem_start = sinfo->lcdc_old_smem_start;
-+	lcdc_info->var.bits_per_pixel = sinfo->lcdc_old_bits_per_pixel;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 0;
-+
-+	/* We must stop the mpop to reset it. */
-+	atmel_mpopfb_stop(sinfo);
-+}
-+
-+static void atmel_mpopfb_put_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	dev_dbg(sinfo->info->device, "Overlay palette = :\n");
-+	for (i = 0; i < 256; i++) {
-+		dev_dbg(sinfo->info->device, "%d -> 0x%x\n", i,
-+			*((int *)&palette->entry[i]));
-+		mpop_writel(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i,
-+			    *((int *)&palette->entry[i]));
-+	}
-+}
-+
-+static void atmel_mpopfb_get_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	for (i = 0; i < 256; i++)
-+		*((int *)&palette->entry[i]) =
-+		    mpop_readl(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i);
-+}
-+
-+static void atmel_mpopfb_put_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i,
-+				*((int *)&palette->entry[i]));
-+}
-+
-+static void atmel_mpopfb_get_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		*((int *)&palette->entry[i])
-+			= mpop_readl(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i);
-+}
-+
-+/**
-+ *      atmel_mpopfb_set_par - Alters the hardware state.
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Using the fb_var_screeninfo in fb_info we set the resolution
-+ *	of the this particular framebuffer. This function alters the
-+ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
-+ *	not alter var in fb_info since we are using that data. This
-+ *	means we depend on the data in var inside fb_info to be
-+ *	supported by the hardware.  atmel_lcdfb_check_var is always called
-+ *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
-+ *	change the resolution you don't need this function.
-+ *
-+ */
-+static int atmel_mpopfb_set_par(struct fb_info *info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	u32 yuv_format;
-+	u32 xscale, yscale;
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
-+			info->var.xres, info->var.yres,
-+			info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * offset: (%u,%u)\n",
-+			info->var.xoffset, info->var.yoffset);
-+	dev_dbg(info->device, "  * bpp: %u\n", info->var.bits_per_pixel);
-+
-+	/* Setup the output picture size. We must use the size of the lcdcfb. */
-+	dev_dbg(info->device, "  * output frame resolution: %ux%u \n",
-+			lcdc_info->var.xres, lcdc_info->var.yres);
-+	mpop_writel(sinfo, ATMEL_MPOP_DISP_MAX_COORD,
-+			((lcdc_info->var.xres - 1) << ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET)
-+			| ((lcdc_info->var.yres - 1) << ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup base picture. */
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_420;
-+		break;
-+	case 16:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_422;
-+		break;
-+	case 24:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_444;
-+		break;
-+	}
-+
-+	xscale = ATMEL_MPOP_CALC_SCALE(info->var.xres, sinfo->baseimg_info.xsize);
-+	yscale = ATMEL_MPOP_CALC_SCALE(info->var.yres, sinfo->baseimg_info.ysize);
-+
-+	dev_dbg(info->device, "  * baseimg output size = %ux%u \n",
-+			sinfo->baseimg_info.xsize, sinfo->baseimg_info.ysize);
-+	dev_dbg(info->device, "  * resize scales = %ux%u \n", xscale, yscale);
-+	dev_dbg(info->device, "  * yuv format = %u \n", yuv_format);
-+	mpop_writel(sinfo, ATMEL_MPOP_YCR,
-+			yuv_format << ATMEL_MPOP_YCR_YUVFORMAT_OFFSET
-+			| xscale << ATMEL_MPOP_YCR_XRESIZE_OFFSET
-+			| yscale << ATMEL_MPOP_YCR_YRESIZE_OFFSET);
-+
-+	/* Setup conversion coefficients. */
-+	mpop_writel(sinfo, ATMEL_MPOP_R2R1,
-+			((sinfo->rgbconv_coeffs.r1 << ATMEL_MPOP_R1_OFFSET) & ATMEL_MPOP_R1_MASK)
-+			| ((sinfo->rgbconv_coeffs.r2 << ATMEL_MPOP_R2_OFFSET) & ATMEL_MPOP_R2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_R4R3,
-+			((sinfo->rgbconv_coeffs.r3 << ATMEL_MPOP_R3_OFFSET) & ATMEL_MPOP_R3_MASK)
-+			| ((sinfo->rgbconv_coeffs.r4 << ATMEL_MPOP_R4_OFFSET) & ATMEL_MPOP_R4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G2G1,
-+			((sinfo->rgbconv_coeffs.g1 << ATMEL_MPOP_G1_OFFSET) & ATMEL_MPOP_G1_MASK)
-+			| ((sinfo->rgbconv_coeffs.g2 << ATMEL_MPOP_G2_OFFSET) & ATMEL_MPOP_G2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G4G3,
-+			((sinfo->rgbconv_coeffs.g3 << ATMEL_MPOP_G3_OFFSET) & ATMEL_MPOP_G3_MASK)
-+			| ((sinfo->rgbconv_coeffs.g4 << ATMEL_MPOP_G4_OFFSET) & ATMEL_MPOP_G4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B2B1,
-+			((sinfo->rgbconv_coeffs.b1 << ATMEL_MPOP_B1_OFFSET) & ATMEL_MPOP_B1_MASK)
-+			| ((sinfo->rgbconv_coeffs.b2 << ATMEL_MPOP_B2_OFFSET) & ATMEL_MPOP_B2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B4B3,
-+			((sinfo->rgbconv_coeffs.b3 << ATMEL_MPOP_B3_OFFSET) & ATMEL_MPOP_B3_MASK)
-+			| ((sinfo->rgbconv_coeffs.b4 << ATMEL_MPOP_B4_OFFSET) & ATMEL_MPOP_B4_MASK));
-+
-+	info->fix.line_length = info->var.xres_virtual;
-+	info->fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+	/* Setup stride. We can flip the image by negating the 
-+	   stride, but we must then set the SAR registers to point
-+	   to the last line in the image. */
-+	if (sinfo->baseimg_info.flip) {
-+		dev_dbg(info->device, "  * flip \n");
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, -info->var.xres_virtual);
-+	} else
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, info->var.xres_virtual);
-+
-+	/* Setup input image size. */
-+	mpop_writel(sinfo, ATMEL_MPOP_YUV_MAX_COORD,
-+			((info->var.xres - 1) << ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET)
-+			| ((info->var.yres - 1) << ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup size and position of output base image after scaling. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_SIZE,
-+			sinfo->baseimg_info.xsize << ATMEL_MPOP_RGB_SIZE_X_OFFSET
-+			| sinfo->baseimg_info.ysize << ATMEL_MPOP_RGB_SIZE_Y_OFFSET);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_POS,
-+			(sinfo->baseimg_info.xpos << ATMEL_MPOP_RGB_POS_X_OFFSET)
-+			| (sinfo->baseimg_info.ypos << ATMEL_MPOP_RGB_POS_Y_OFFSET));
-+
-+	dev_dbg(info->device, "  * baseimg pos: (%u,%u) \n",
-+			sinfo->baseimg_info.xpos, sinfo->baseimg_info.ypos);
-+
-+	/* Setup Word Transfer Count. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_WTC,
-+			DIV_ROUND_UP(info->var.xres * info->var.yres
-+				* var->bits_per_pixel, 32));
-+
-+	/* Set overlay parameters. */
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize << ATMEL_MPOP_O1_SIZE_O1_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize << ATMEL_MPOP_O1_SIZE_O1_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			 * sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize << ATMEL_MPOP_O2_SIZE_O2_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize << ATMEL_MPOP_O2_SIZE_O2_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize *
-+				sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize
-+				* sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize, 16));
-+
-+	/* Enable base overlay + any other enabled overlays. */
-+	mpop_writel(sinfo, ATMEL_MPOP_OCR, ATMEL_MPOP_OCR_RGBEN_MASK);
-+
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_CURSOREN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O1EN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O2EN_MASK);
-+
-+	/* Set background to black. */
-+	mpop_writel(sinfo, ATMEL_MPOP_BGCOLOR, 0);
-+
-+	/* Setup source address registers */
-+	atmel_mpopfb_update_sar(info, &info->var);
-+
-+	dev_dbg(info->device, "  * DONE\n");
-+
-+	return 0;
-+}
-+
-+static int atmel_mpopfb_pan_display(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	dev_dbg(info->device, "%s\n", __func__);
-+
-+	/* Change source address registers to reflect the panning. */
-+	atmel_mpopfb_update_sar(info, var);
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_put_overlay_info(struct fb_info *info,
-+		struct atmel_mpopfb_overlay_info overlay_info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	/* We can update the position now since it is double buffered. */
-+	switch (overlay_info.overlay) {
-+	case ATMEL_MPOPFB_OVERLAY1:
-+		mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_OVERLAY2:
-+		mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_CURSOR:
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+		break;
-+	default:
-+		dev_warn(info->device, "Unknown overlay type: %d\n",
-+				overlay_info.overlay);
-+		return;
-+	}
-+
-+	/* Copy the overlay info to the mpopfb info structure. */
-+	sinfo->overlay_info[overlay_info.overlay] = overlay_info;
-+}
-+
-+static int atmel_mpopfb_ioctl(struct fb_info *info,
-+		unsigned int cmd, unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct atmel_mpopfb_overlay_info overlay_info;
-+
-+	switch (cmd) {
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_overlay_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			atmel_mpopfb_get_overlay_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_cursor_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			atmel_mpopfb_get_cursor_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_INFO:
-+		if (copy_from_user(&overlay_info, argp, sizeof(overlay_info)))
-+			return -EFAULT;
-+		atmel_mpopfb_put_overlay_info(info, overlay_info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOPUT_BASEIMG_INFO:
-+		if (copy_from_user(&sinfo->baseimg_info, argp,
-+					sizeof(sinfo->baseimg_info)))
-+			return -EFAULT;
-+
-+		/* Check that new baseimg parameters are sane. */
-+		if (atmel_mpopfb_check_var(&info->var, info))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		atmel_mpopfb_set_par(info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_BASEIMG_INFO:
-+		return copy_to_user(argp, &sinfo->baseimg_info,
-+				sizeof(sinfo->baseimg_info)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS:
-+		if (copy_from_user(&sinfo->rgbconv_coeffs, argp,
-+					sizeof(sinfo->rgbconv_coeffs)))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		if (atmel_mpopfb_set_par(info))
-+			return -EFAULT;
-+
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS:
-+		return copy_to_user(argp, &sinfo->rgbconv_coeffs,
-+				sizeof(sinfo->rgbconv_coeffs)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIO_CONNECT_TO_LCDC:
-+		atmel_mpopfb_connect_to_lcdc(sinfo);
-+		return 0;
-+	case ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC:
-+		atmel_mpopfb_disconnect_from_lcdc(sinfo);
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* Force MPOP to be updated with any new parameters. */
-+	atmel_mpopfb_set_par(info);
-+}
-+
-+static int atmel_mpopfb_setcolreg(unsigned int regno, unsigned int red,
-+				  unsigned int green, unsigned int blue,
-+				  unsigned int transp, struct fb_info *info)
-+{
-+	return 0;
-+}
-+
-+static struct fb_ops atmel_mpopfb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_check_var	= atmel_mpopfb_check_var,
-+	.fb_set_par	= atmel_mpopfb_set_par,
-+	.fb_setcolreg	= atmel_mpopfb_setcolreg,
-+	.fb_pan_display	= atmel_mpopfb_pan_display,
-+	.fb_imageblit	= cfb_imageblit,
-+	.fb_ioctl	= atmel_mpopfb_ioctl,
-+	.fb_fillrect	= cfb_fillrect,
-+	.fb_copyarea	= cfb_copyarea,
-+};
-+
-+static irqreturn_t atmel_mpopfb_interrupt(int irq, void *dev_id)
-+{
-+	struct fb_info *info = dev_id;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	u32 status;
-+
-+	/* Check which interrupt we have. */
-+	status = mpop_readl(sinfo, ATMEL_MPOP_INTSTATUS);
-+
-+	/* Clear interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTCLEAR, status);
-+
-+	if (status & ATMEL_MPOP_EOP) {
-+		/* End Of Picture. Start new picture. */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+				ATMEL_MPOP_CR_START_MASK
-+				| mpop_readl(sinfo, ATMEL_MPOP_CR));
-+	} else if (status & ATMEL_MPOP_OUT) {
-+		dev_err(info->dev,
-+			"MPOP Output DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OUT_BEAR));
-+	} else if (status & ATMEL_MPOP_YUV) {
-+		dev_err(info->dev,
-+			"MPOP YUV Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_YUV_BEAR));
-+	} else if (status & ATMEL_MPOP_OVERLAY) {
-+		dev_err(info->dev,
-+			"MPOP Overlay Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OVERLAY_BEAR));
-+	}
-+
-+	dev_dbg(info->device, "%s\n", __func__);
-+	dev_dbg(info->device, "  * status: 0x%x \n", status);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init atmel_mpopfb_init_fbinfo(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	int ret = 0;
-+
-+	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
-+
-+	dev_info(info->device,
-+			"%luKiB frame buffer at %08lx (mapped at %p)\n",
-+			(unsigned long)info->fix.smem_len / 1024,
-+			(unsigned long)info->fix.smem_start, info->screen_base);
-+
-+	return ret;
-+}
-+
-+static void atmel_mpopfb_start_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_enable(sinfo->mpop_hclk);
-+	clk_enable(sinfo->mpop_pclk);
-+}
-+
-+static void atmel_mpopfb_stop_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_disable(sinfo->mpop_hclk);
-+	clk_disable(sinfo->mpop_pclk);
-+}
-+
-+static int __init atmel_mpopfb_probe(struct platform_device *pdev)
-+{
-+	struct device			*dev = &pdev->dev;
-+	struct fb_info			*info;
-+	struct fb_info			*lcdc_info;
-+	struct atmel_mpopfb_info	*sinfo;
-+	struct atmel_mpopfb_info	*pdata_sinfo;
-+	struct resource			*regs = NULL;
-+	struct resource			*slave = NULL;
-+	struct resource			*map = NULL;
-+	int				ret;
-+
-+	dev_dbg(dev, "%s BEGIN\n", __func__);
-+
-+	ret = -ENOMEM;
-+	info = framebuffer_alloc(sizeof(struct atmel_mpopfb_info), dev);
-+	if (!info) {
-+		dev_err(dev, "cannot allocate memory\n");
-+		goto out;
-+	}
-+
-+	sinfo = info->par;
-+
-+	if (dev->platform_data) {
-+		pdata_sinfo = dev->platform_data;
-+		sinfo->lcdc_pdev = pdata_sinfo->lcdc_pdev;
-+		if (!sinfo->lcdc_pdev) {
-+			dev_err(dev, "cannot get hold of lcdcfb device\n");
-+			goto free_info;
-+		}
-+	} else {
-+		dev_err(dev, "cannot get default configuration\n");
-+		goto free_info;
-+	}
-+
-+	sinfo->info = info;
-+	sinfo->pdev = pdev;
-+	sinfo->running = 0;
-+	sinfo->connected_to_lcdc = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled = 0;
-+
-+	/* Setup default info */
-+
-+	/* Set fb_var_screeninfo equal to that of the lcdcfb driver. */
-+	lcdc_info = (struct fb_info *)platform_get_drvdata(sinfo->lcdc_pdev);
-+	memcpy(&info->var, &lcdc_info->var, sizeof(struct fb_var_screeninfo));
-+
-+	/* Set default position of the image on the screen to (0,0) and
-+	   no scaling */
-+	sinfo->baseimg_info.xpos = 0;
-+	sinfo->baseimg_info.ypos = 0;
-+	sinfo->baseimg_info.xsize = info->var.xres;
-+	sinfo->baseimg_info.ysize = info->var.yres;
-+
-+	/* Use YCbCr --> RGB converion per default. */
-+	memcpy(&sinfo->rgbconv_coeffs, &atmel_mpop_ycrcb2rgb_coeffs,
-+	       sizeof(struct atmel_mpopfb_rgbconv_coeffs));
-+
-+	strcpy(info->fix.id, sinfo->pdev->name);
-+	info->flags = ATMEL_MPOPFB_FBINFO_DEFAULT;
-+	info->fbops = &atmel_mpopfb_ops;
-+
-+	//memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
-+	info->fix = atmel_mpopfb_fix;
-+
-+	/* Enable MPOP Clocks */
-+	sinfo->mpop_hclk = clk_get(dev, "hclk");
-+	sinfo->mpop_pclk = clk_get(dev, "pclk");
-+	if (IS_ERR(sinfo->mpop_hclk)) {
-+		ret = PTR_ERR(sinfo->mpop_hclk);
-+		goto put_bus_clk;
-+	}
-+	if (IS_ERR(sinfo->mpop_pclk)) {
-+		ret = PTR_ERR(sinfo->mpop_pclk);
-+		goto stop_clk;
-+	}
-+	atmel_mpopfb_start_clock(sinfo);
-+
-+	//ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
-+	//                   info->monspecs.modedb_len, info->monspecs.modedb,
-+	//                   sinfo->default_bpp);
-+	//if (!ret) {
-+	//      dev_err(dev, "no suitable video mode found\n");
-+	//      goto stop_clk;
-+	//}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(dev, "resources unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+
-+	slave = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (!slave) {
-+		dev_err(dev, "slave interface memory resource unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+	sinfo->slave_base = (void *)slave->start;
-+
-+	sinfo->irq_base = platform_get_irq(pdev, 0);
-+	if (sinfo->irq_base < 0) {
-+		dev_err(dev, "unable to get irq\n");
-+		ret = sinfo->irq_base;
-+		goto stop_clk;
-+	}
-+
-+	/* Initialize video memory */
-+	map = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-+	if (map) {
-+		/* use a pre-allocated memory buffer */
-+		info->fix.smem_start = map->start;
-+		info->fix.smem_len = map->end - map->start + 1;
-+		if (!request_mem_region(info->fix.smem_start,
-+					info->fix.smem_len, pdev->name)) {
-+			//ret = -EBUSY;
-+			//goto stop_clk;
-+			/* Probably in use by LCD controller. */
-+			info->screen_base = lcdc_info->screen_base;
-+		} else {
-+			info->screen_base =
-+			    ioremap(info->fix.smem_start, info->fix.smem_len);
-+			if (!info->screen_base)
-+				goto release_intmem;
-+		}
-+	} else {
-+		/* alocate memory buffer */
-+		ret = atmel_mpopfb_alloc_video_memory(sinfo);
-+		if (ret < 0) {
-+			dev_err(dev, "cannot allocate mpop framebuffer: %d\n",
-+				ret);
-+			goto stop_clk;
-+		}
-+	}
-+
-+	/* MPOP registers */
-+	info->fix.mmio_start = regs->start;
-+	info->fix.mmio_len = regs->end - regs->start + 1;
-+
-+	if (!request_mem_region(info->fix.mmio_start,
-+				info->fix.mmio_len, pdev->name)) {
-+		ret = -EBUSY;
-+		goto free_fb;
-+	}
-+
-+	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
-+	if (!sinfo->mmio) {
-+		dev_err(dev, "cannot map MPOP registers\n");
-+		goto release_mem;
-+	}
-+
-+	/* MPOP slave interface */
-+	if (!request_mem_region(slave->start,
-+				slave->end - slave->start + 1, pdev->name)) {
-+		dev_err(dev,
-+			"error requesting memory region for MPOP slave interface\n");
-+		ret = -EBUSY;
-+		goto unmap_mmio;
-+	}
-+
-+	/* interrupt */
-+	ret =
-+	    request_irq(sinfo->irq_base, atmel_mpopfb_interrupt, 0, pdev->name,
-+			info);
-+	if (ret) {
-+		dev_err(dev, "request_irq failed: %d\n", ret);
-+		goto release_mem_slave;
-+	}
-+
-+	ret = atmel_mpopfb_init_fbinfo(sinfo);
-+	if (ret < 0) {
-+		dev_err(dev, "init fbinfo failed: %d\n", ret);
-+		goto unregister_irqs;
-+	}
-+
-+	/*
-+	 * This makes sure that our colour bitfield
-+	 * descriptors are correctly initialised.
-+	 */
-+	atmel_mpopfb_check_var(&info->var, info);
-+
-+	ret = fb_set_var(info, &info->var);
-+	if (ret) {
-+		dev_warn(dev, "unable to set display parameters\n");
-+		goto free_cmap;
-+	}
-+
-+	dev_set_drvdata(dev, info);
-+
-+	/*
-+	 * Tell the world that we're ready to go
-+	 */
-+	ret = register_framebuffer(info);
-+	if (ret < 0) {
-+		dev_err(dev, "failed to register framebuffer device: %d\n",
-+			ret);
-+		goto free_cmap;
-+	}
-+
-+	dev_info(dev, "fb%d: Atmel MPOP at 0x%08lx (mapped at %p), irq %lu\n",
-+		 info->node, info->fix.mmio_start, sinfo->mmio,
-+		 sinfo->irq_base);
-+
-+	return 0;
-+
-+free_cmap:
-+	fb_dealloc_cmap(&info->cmap);
-+unregister_irqs:
-+	free_irq(sinfo->irq_base, info);
-+release_mem_slave:
-+	release_mem_region(slave->start, slave->end - slave->start + 1);
-+unmap_mmio:
-+	iounmap(sinfo->mmio);
-+release_mem:
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+free_fb:
-+	if (map)
-+		iounmap(info->screen_base);
-+	else
-+		atmel_mpopfb_free_video_memory(sinfo);
-+
-+release_intmem:
-+	if (map)
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+stop_clk:
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+put_bus_clk:
-+	if (sinfo->mpop_pclk)
-+		clk_put(sinfo->mpop_pclk);
-+free_info:
-+	framebuffer_release(info);
-+out:
-+	dev_dbg(dev, "%s FAILED\n", __func__);
-+	return ret;
-+}
-+
-+static int __exit atmel_mpopfb_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct fb_info *info = dev_get_drvdata(dev);
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	if (!sinfo)
-+		return 0;
-+
-+	unregister_framebuffer(info);
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+	clk_put(sinfo->mpop_pclk);
-+	fb_dealloc_cmap(&info->cmap);
-+	free_irq(sinfo->irq_base, info);
-+	iounmap(sinfo->mmio);
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
-+		iounmap(info->screen_base);
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+	} else {
-+		atmel_mpopfb_free_video_memory(sinfo);
-+	}
-+
-+	dev_set_drvdata(dev, NULL);
-+	framebuffer_release(info);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver atmel_mpopfb_driver = {
-+	.remove = __exit_p(atmel_mpopfb_remove),
-+	.driver.name = "atmel_mpopfb",
-+	.driver.owner = THIS_MODULE,
-+};
-+
-+static int __init atmel_mpopfb_init(void)
-+{
-+	return platform_driver_probe(&atmel_mpopfb_driver, atmel_mpopfb_probe);
-+}
-+
-+static void __exit atmel_mpopfb_exit(void)
-+{
-+	platform_driver_unregister(&atmel_mpopfb_driver);
-+}
-+
-+module_init(atmel_mpopfb_init);
-+module_exit(atmel_mpopfb_exit);
-+
-+MODULE_DESCRIPTION("AT32 MPOP framebuffer driver");
-+MODULE_AUTHOR("Ronny Pedersen <rpedersen at atmel.com>");
-+MODULE_LICENSE("GPL");
-diff -urN linux-2.6.28.2-0rig//drivers/video/Kconfig linux-2.6.28.2/drivers/video/Kconfig
---- linux-2.6.28.2-0rig//drivers/video/Kconfig	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/video/Kconfig	2009-01-29 08:52:50.000000000 +0100
-@@ -940,6 +940,15 @@
- 	help
- 	  This enables support for the AT91/AT32 LCD Controller.
- 
-+config FB_ATMEL_MPOP
-+	tristate "AT32 MPOP support"
-+	depends on FB && AVR32 && FB_ATMEL
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This enables support for the AT32 MPOP module.
-+
- config FB_INTSRAM
- 	bool "Frame Buffer in internal SRAM"
- 	depends on FB_ATMEL && ARCH_AT91SAM9261
-diff -urN linux-2.6.28.2-0rig//drivers/video/Makefile linux-2.6.28.2/drivers/video/Makefile
---- linux-2.6.28.2-0rig//drivers/video/Makefile	2009-01-29 08:39:31.000000000 +0100
-+++ linux-2.6.28.2/drivers/video/Makefile	2009-01-29 08:52:50.000000000 +0100
-@@ -89,6 +89,7 @@
- obj-$(CONFIG_FB_HIT)              += hitfb.o
- obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
- obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
-+obj-$(CONFIG_FB_ATMEL_MPOP)	  += atmel_mpopfb.o
- obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
- obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
- obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
-diff -urN linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h linux-2.6.28.2/include/linux/atmel_mpopfb.h
---- linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/include/linux/atmel_mpopfb.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,112 @@
-+/*
-+ *  Header file for AT32 MPOP FB Driver
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOPFB_H__
-+#define __ATMEL_MPOPFB_H__
-+
-+#include <linux/fb.h>
-+#include <linux/ioctl.h>
-+
-+/* Coefficients for conversion to rgb. */
-+struct atmel_mpopfb_rgbconv_coeffs {
-+	int r1, r2, r3, r4;
-+	int g1, g2, g3, g4;
-+	int b1, b2, b3, b4;
-+};
-+
-+struct atmel_mpopfb_baseimg_info {
-+	/* Position of the mpop base image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+
-+	/* The size of the base image after scaling. */
-+	unsigned xsize;
-+	unsigned ysize;
-+
-+	/* Signal that we should flip the video. */
-+	int flip;
-+
-+};
-+
-+enum atmel_mpopfb_overlay_type {
-+	ATMEL_MPOPFB_OVERLAY1 = 0,
-+	ATMEL_MPOPFB_OVERLAY2 = 1,
-+	ATMEL_MPOPFB_CURSOR = 2
-+};
-+
-+struct atmel_mpopfb_overlay_info {
-+	/* Position of the mpop overlay image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+	/* The size of the overlay image. */
-+	unsigned xsize;
-+	unsigned ysize;
-+	/* Signal which overlay this info is for. */
-+	enum atmel_mpopfb_overlay_type overlay;
-+	/* Signal if the overlay is enabled. */
-+	unsigned enabled;
-+};
-+
-+struct atmel_mpopfb_overlay_palette_entry {
-+	unsigned char alpha;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_cursor_palette_entry {
-+	unsigned char:6;
-+	unsigned char invert:1;
-+	unsigned char visible:1;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_overlay_palette {
-+	struct atmel_mpopfb_overlay_palette_entry entry[256];
-+};
-+
-+struct atmel_mpopfb_cursor_palette {
-+	struct atmel_mpopfb_cursor_palette_entry entry[4];
-+};
-+
-+#define ATMEL_MPOP_FBIOPUT_BASEIMG_INFO        _IOW('x',0,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOGET_BASEIMG_INFO        _IOR('x',1,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_INFO        _IOW('x',2,struct atmel_mpopfb_overlay_info)
-+#define ATMEL_MPOP_FBIO_CONNECT_TO_LCDC        _IO( 'x',4)
-+#define ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC   _IO( 'x',5)
-+#define ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS      _IOW('x',6,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS      _IOR('x',7,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE     _IOW('x',8,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE     _IOR('x',9,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE      _IOW('x',10,struct atmel_mpopfb_cursor_palette)
-+#define ATMEL_MPOP_FBIOGET_CURSOR_PALETTE      _IOR('x',11,struct atmel_mpopfb_cursor_palette)
-+
-+#define ATMEL_MPOP_RESIZE_FRAC_BITS 5
-+#define ATMEL_MPOP_SCALE_FRAC_DIV(a,b)  ((((a) << ATMEL_MPOP_RESIZE_FRAC_BITS))/(b))
-+#define ATMEL_MPOP_CALC_SCALE(from_res,to_res)  ATMEL_MPOP_SCALE_FRAC_DIV(from_res, to_res)
-+
-+#define ATMEL_MPOP_COEFF_FRAC_BITS 8
-+
-+#endif
-diff -urN linux-2.6.28.2-0rig//include/linux/atmel_pdca.h linux-2.6.28.2/include/linux/atmel_pdca.h
---- linux-2.6.28.2-0rig//include/linux/atmel_pdca.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/include/linux/atmel_pdca.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,120 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ATMEL_PDCA_H
-+#define __ATMEL_PDCA_H
-+
-+#include <linux/dmaengine.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+
-+struct pdca_pdata {
-+	unsigned int		nr_channels;
-+};
-+
-+struct pdca_slave {
-+	struct dma_slave	slave;
-+	u8			tx_periph_id;
-+	u8			rx_periph_id;
-+};
-+
-+struct pdca_desc {
-+	/* This controller does not support hardware descriptors */
-+	struct scatterlist	*sg;
-+	int			sg_len;
-+	u8			reg_width;
-+	u8			periph_id;
-+
-+	struct list_head	desc_node;
-+	struct dma_async_tx_descriptor txd;
-+};
-+
-+struct pdca_chan {
-+	struct list_head	freelist;
-+	struct list_head	queue;
-+
-+	spinlock_t		lock;
-+	void __iomem		*regs;
-+
-+	struct scatterlist	*cur_sg;
-+	struct scatterlist	*next_sg;
-+
-+	struct tasklet_struct	tasklet;
-+
-+	dma_cookie_t		completed;
-+	struct dma_chan		chan;
-+	struct pdca_slave	*pslave;
-+	unsigned int		descs_allocated;
-+	bool			enabled;
-+};
-+
-+struct pdca_dev {
-+	struct clk		*hclk;
-+	struct clk		*pclk;
-+	struct dma_device	dma;
-+	void __iomem		*regs;
-+
-+	struct pdca_chan	chan[];
-+};
-+
-+static inline struct pdca_slave *dma_to_pdca_slave(struct dma_slave *slave)
-+{
-+	return container_of(slave, struct pdca_slave, slave);
-+}
-+
-+static inline struct pdca_desc *txd_to_pdca_desc(
-+		struct dma_async_tx_descriptor *txd)
-+{
-+	return container_of(txd, struct pdca_desc, txd);
-+}
-+
-+static inline struct pdca_chan *dma_to_pdca_chan(struct dma_chan *chan)
-+{
-+	return container_of(chan, struct pdca_chan, chan);
-+}
-+
-+static inline struct pdca_dev *dma_to_pdca_dev(struct dma_device *dma)
-+{
-+	return container_of(dma, struct pdca_dev, dma);
-+}
-+
-+/* PDCA per-channel register definitions */
-+#define PDCA_MAR		0x0000	/* Memory Address */
-+#define PDCA_PSR		0x0004	/* Peripheral Select */
-+#define PDCA_TCR		0x0008	/* Transfer Counter */
-+#define PDCA_MARR		0x000c	/* Memory Address Reload */
-+#define PDCA_TCRR		0x0010	/* Transfer Counter Reload */
-+#define PDCA_CR			0x0014	/* Control */
-+# define PDCA_CR_TEN		(  1 <<  0)	/* Transfer Enable */
-+# define PDCA_CR_TDIS		(  1 <<  1)	/* Transfer Disable */
-+# define PDCA_CR_ECLR		(  1 <<  8)	/* Error Clear */
-+#define PDCA_MR			0x0018	/* Mode */
-+# define PDCA_SIZE_BYTE		(  0 <<  0)	/* 8 bits per transfer */
-+# define PDCA_SIZE_HWORD	(  1 <<  0)	/* 16 bits per transfer */
-+# define PDCA_SIZE_WORD		(  2 <<  0)	/* 32 bits per transfer */
-+#define PDCA_SR			0x001c	/* Status */
-+# define PDCA_SR_TEN		(  1 <<  0)	/* Transfer Enabled */
-+#define PDCA_IER		0x0020	/* Interrupt Enable */
-+#define PDCA_IDR		0x0024	/* Interrupt Disable */
-+#define PDCA_IMR		0x0028	/* Interrupt Mask */
-+#define PDCA_ISR		0x002c	/* Interrupt Status */
-+# define PDCA_RCZ		(  1 <<  0)	/* Reload Counter Zero */
-+# define PDCA_TRC		(  1 <<  1)	/* Transfer Complete */
-+# define PDCA_TERR		(  1 <<  2)	/* Transfer Error */
-+
-+/* Address space occupied by one channel */
-+#define PDCA_CHAN_SIZE		0x40
-+
-+#define pdca_readl(base, reg)				\
-+	__raw_readl((base) + PDCA_##reg)
-+#define pdca_writel(base, reg, value)			\
-+	__raw_writel((value), (base) + PDCA_##reg)
-+
-+#endif /* __ATMEL_PDCA_H */
-diff -urN linux-2.6.28.2-0rig//include/linux/Kbuild linux-2.6.28.2/include/linux/Kbuild
---- linux-2.6.28.2-0rig//include/linux/Kbuild	2009-01-29 08:39:39.000000000 +0100
-+++ linux-2.6.28.2/include/linux/Kbuild	2009-01-29 08:52:50.000000000 +0100
-@@ -23,6 +23,7 @@
- header-y += atmarp.h
- header-y += atmbr2684.h
- header-y += atmclip.h
-+header-y += atmel_mpopfb.h
- header-y += atm_eni.h
- header-y += atm_he.h
- header-y += atm_idt77105.h
-diff -urN linux-2.6.28.2-0rig//include/linux/spi/atmel_spi.h linux-2.6.28.2/include/linux/spi/atmel_spi.h
---- linux-2.6.28.2-0rig//include/linux/spi/atmel_spi.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/include/linux/spi/atmel_spi.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,20 @@
-+/*
-+ * Driver for Atmel AT32 and AT91 SPI Controllers
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __LINUX_SPI_ATMEL_SPI_H
-+#define __LINUX_SPI_ATMEL_SPI_H
-+
-+struct atmel_spi_pdata {
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct dma_slave	*rx_dma_slave;
-+	struct dma_slave	*tx_dma_slave;
-+#endif
-+};
-+
-+#endif /* __LINUX_SPI_ATMEL_SPI_H */
-diff -urN linux-2.6.28.2-0rig//include/video/atmel_mpop.h linux-2.6.28.2/include/video/atmel_mpop.h
---- linux-2.6.28.2-0rig//include/video/atmel_mpop.h	1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.28.2/include/video/atmel_mpop.h	2009-01-29 08:52:50.000000000 +0100
-@@ -0,0 +1,820 @@
-+/*
-+ *  Header file for AT32 MPOP Controller
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOP_H__
-+#define __ATMEL_MPOP_H__
-+
-+#include <linux/atmel_mpopfb.h>
-+
-+/* MPOP Controller info data structure */
-+struct atmel_mpopfb_info {
-+	spinlock_t lock;
-+	struct fb_info *info;
-+	void __iomem *mmio;
-+	unsigned long irq_base;
-+	void *slave_base;
-+
-+	struct platform_device *pdev;
-+	struct platform_device *lcdc_pdev;
-+	struct clk *mpop_hclk;
-+	struct clk *mpop_pclk;
-+	unsigned int running;
-+	unsigned int connected_to_lcdc;
-+	unsigned long lcdc_old_smem_start;
-+	unsigned long lcdc_old_bits_per_pixel;
-+	struct atmel_mpopfb_baseimg_info baseimg_info;
-+	struct atmel_mpopfb_overlay_info overlay_info[3];
-+	struct atmel_mpopfb_rgbconv_coeffs rgbconv_coeffs;
-+};
-+
-+/* TODO! Clean up these defines.... */
-+#define ATMEL_MPOP_B                                                 0
-+#define ATMEL_MPOP_B1                                                0
-+#define ATMEL_MPOP_B1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B1_OFFSET                                         0
-+#define ATMEL_MPOP_B1_SIZE                                          12
-+#define ATMEL_MPOP_B2                                               12
-+#define ATMEL_MPOP_B2B1                                     0x00000024
-+#define ATMEL_MPOP_B2B1_B1                                           0
-+#define ATMEL_MPOP_B2B1_B1_MASK                             0x00000fff
-+#define ATMEL_MPOP_B2B1_B1_OFFSET                                    0
-+#define ATMEL_MPOP_B2B1_B1_SIZE                                     12
-+#define ATMEL_MPOP_B2B1_B2                                          12
-+#define ATMEL_MPOP_B2B1_B2_MASK                             0x00fff000
-+#define ATMEL_MPOP_B2B1_B2_OFFSET                                   12
-+#define ATMEL_MPOP_B2B1_B2_SIZE                                     12
-+#define ATMEL_MPOP_B2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_B2_OFFSET                                        12
-+#define ATMEL_MPOP_B2_SIZE                                          12
-+#define ATMEL_MPOP_B3                                                0
-+#define ATMEL_MPOP_B3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B3_OFFSET                                         0
-+#define ATMEL_MPOP_B3_SIZE                                          12
-+#define ATMEL_MPOP_B4                                               12
-+#define ATMEL_MPOP_B4B3                                     0x00000028
-+#define ATMEL_MPOP_B4B3_B3                                           0
-+#define ATMEL_MPOP_B4B3_B3_MASK                             0x00000fff
-+#define ATMEL_MPOP_B4B3_B3_OFFSET                                    0
-+#define ATMEL_MPOP_B4B3_B3_SIZE                                     12
-+#define ATMEL_MPOP_B4B3_B4                                          12
-+#define ATMEL_MPOP_B4B3_B4_MASK                             0xfffff000
-+#define ATMEL_MPOP_B4B3_B4_OFFSET                                   12
-+#define ATMEL_MPOP_B4B3_B4_SIZE                                     20
-+#define ATMEL_MPOP_B4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_B4_OFFSET                                        12
-+#define ATMEL_MPOP_B4_SIZE                                          20
-+#define ATMEL_MPOP_BGCOLOR                                  0x00000090
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR                                   0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_MASK                     0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_OFFSET                            0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_SIZE                             32
-+#define ATMEL_MPOP_BGCOLOR_MASK                             0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_OFFSET                                    0
-+#define ATMEL_MPOP_BGCOLOR_SIZE                                     32
-+#define ATMEL_MPOP_BGR                                               6
-+#define ATMEL_MPOP_BGR_MASK                                 0x00000040
-+#define ATMEL_MPOP_BGR_OFFSET                                        6
-+#define ATMEL_MPOP_BGR_SIZE                                          1
-+#define ATMEL_MPOP_B_MASK                                   0x000000ff
-+#define ATMEL_MPOP_B_OFFSET                                          0
-+#define ATMEL_MPOP_B_SIZE                                            8
-+#define ATMEL_MPOP_CACHEDIS                                          8
-+#define ATMEL_MPOP_CACHEDIS_MASK                            0x00000100
-+#define ATMEL_MPOP_CACHEDIS_OFFSET                                   8
-+#define ATMEL_MPOP_CACHEDIS_SIZE                                     1
-+#define ATMEL_MPOP_CR                                       0x00000000
-+#define ATMEL_MPOP_CR_CACHEDIS                                       8
-+#define ATMEL_MPOP_CR_CACHEDIS_MASK                         0x00000100
-+#define ATMEL_MPOP_CR_CACHEDIS_OFFSET                                8
-+#define ATMEL_MPOP_CR_CACHEDIS_SIZE                                  1
-+#define ATMEL_MPOP_CR_EN                                             0
-+#define ATMEL_MPOP_CR_EN_MASK                               0x00000001
-+#define ATMEL_MPOP_CR_EN_OFFSET                                      0
-+#define ATMEL_MPOP_CR_EN_SIZE                                        1
-+#define ATMEL_MPOP_CR_OUT_BGR                                        3
-+#define ATMEL_MPOP_CR_OUT_BGR_MASK                          0x00000008
-+#define ATMEL_MPOP_CR_OUT_BGR_OFFSET                                 3
-+#define ATMEL_MPOP_CR_OUT_BGR_SIZE                                   1
-+#define ATMEL_MPOP_CR_OUT_CTRL                                       2
-+#define ATMEL_MPOP_CR_OUT_CTRL_MASK                         0x00000004
-+#define ATMEL_MPOP_CR_OUT_CTRL_OFFSET                                2
-+#define ATMEL_MPOP_CR_OUT_CTRL_SIZE                                  1
-+#define ATMEL_MPOP_CR_START                                          1
-+#define ATMEL_MPOP_CR_START_MASK                            0x00000002
-+#define ATMEL_MPOP_CR_START_OFFSET                                   1
-+#define ATMEL_MPOP_CR_START_SIZE                                     1
-+#define ATMEL_MPOP_CURSOREN                                          0
-+#define ATMEL_MPOP_CURSOREN_MASK                            0x00000001
-+#define ATMEL_MPOP_CURSOREN_OFFSET                                   0
-+#define ATMEL_MPOP_CURSOREN_SIZE                                     1
-+#define ATMEL_MPOP_CURSOR_P0                                0x00000080
-+#define ATMEL_MPOP_CURSOR_P0_B                                       0
-+#define ATMEL_MPOP_CURSOR_P0_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P0_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P0_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_G                                       8
-+#define ATMEL_MPOP_CURSOR_P0_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P0_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P0_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P0_R                                      16
-+#define ATMEL_MPOP_CURSOR_P0_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P0_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P0_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P1                                0x00000084
-+#define ATMEL_MPOP_CURSOR_P1_B                                       0
-+#define ATMEL_MPOP_CURSOR_P1_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P1_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P1_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_G                                       8
-+#define ATMEL_MPOP_CURSOR_P1_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P1_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P1_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P1_R                                      16
-+#define ATMEL_MPOP_CURSOR_P1_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P1_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P1_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P2                                0x00000088
-+#define ATMEL_MPOP_CURSOR_P2_B                                       0
-+#define ATMEL_MPOP_CURSOR_P2_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P2_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P2_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_G                                       8
-+#define ATMEL_MPOP_CURSOR_P2_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P2_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P2_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P2_R                                      16
-+#define ATMEL_MPOP_CURSOR_P2_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P2_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P2_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P3                                0x0000008c
-+#define ATMEL_MPOP_CURSOR_P3_B                                       0
-+#define ATMEL_MPOP_CURSOR_P3_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P3_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P3_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_G                                       8
-+#define ATMEL_MPOP_CURSOR_P3_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P3_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P3_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P3_R                                      16
-+#define ATMEL_MPOP_CURSOR_P3_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P3_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P3_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_POS                               0x00000058
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X                          11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_MASK             0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_OFFSET                   11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y                           0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_MASK             0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_OFFSET                    0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_X                                     11
-+#define ATMEL_MPOP_CURSOR_POS_X_MASK                        0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_X_OFFSET                              11
-+#define ATMEL_MPOP_CURSOR_POS_X_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_POS_Y                                      0
-+#define ATMEL_MPOP_CURSOR_POS_Y_MASK                        0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_Y_OFFSET                               0
-+#define ATMEL_MPOP_CURSOR_POS_Y_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_SAR                               0x00000048
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR                             0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_SAR_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_SAR_SIZE                                  32
-+#define ATMEL_MPOP_CURSOR_SIZE                              0x0000006c
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X                        11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_MASK           0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_OFFSET                 11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y                         0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_MASK           0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_OFFSET                  0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_X                                    11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_MASK                       0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_X_OFFSET                             11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_SIZE_Y                                     0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_MASK                       0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_OFFSET                              0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_WTC                               0x0000007c
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC                             0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_WTC_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_WTC_SIZE                                  32
-+#define ATMEL_MPOP_DISP_MAX_COORD                           0x00000010
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X                  11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_MASK     0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_OFFSET           11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y                   0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_MASK     0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_OFFSET            0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X                                 11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_MASK                    0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET                          11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_SIZE                            11
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y                                  0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_MASK                    0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET                           0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_SIZE                            11
-+#define ATMEL_MPOP_EN                                                0
-+#define ATMEL_MPOP_EN_MASK                                  0x00000001
-+#define ATMEL_MPOP_EN_OFFSET                                         0
-+#define ATMEL_MPOP_EN_SIZE                                           1
-+#define ATMEL_MPOP_EOP                                               3
-+#define ATMEL_MPOP_EOP_MASK                                 0x00000008
-+#define ATMEL_MPOP_EOP_OFFSET                                        3
-+#define ATMEL_MPOP_EOP_SIZE                                          1
-+#define ATMEL_MPOP_G                                                 8
-+#define ATMEL_MPOP_G1                                                0
-+#define ATMEL_MPOP_G1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G1_OFFSET                                         0
-+#define ATMEL_MPOP_G1_SIZE                                          12
-+#define ATMEL_MPOP_G2                                               12
-+#define ATMEL_MPOP_G2G1                                     0x0000001c
-+#define ATMEL_MPOP_G2G1_G1                                           0
-+#define ATMEL_MPOP_G2G1_G1_MASK                             0x00000fff
-+#define ATMEL_MPOP_G2G1_G1_OFFSET                                    0
-+#define ATMEL_MPOP_G2G1_G1_SIZE                                     12
-+#define ATMEL_MPOP_G2G1_G2                                          12
-+#define ATMEL_MPOP_G2G1_G2_MASK                             0x00fff000
-+#define ATMEL_MPOP_G2G1_G2_OFFSET                                   12
-+#define ATMEL_MPOP_G2G1_G2_SIZE                                     12
-+#define ATMEL_MPOP_G2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_G2_OFFSET                                        12
-+#define ATMEL_MPOP_G2_SIZE                                          12
-+#define ATMEL_MPOP_G3                                                0
-+#define ATMEL_MPOP_G3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G3_OFFSET                                         0
-+#define ATMEL_MPOP_G3_SIZE                                          12
-+#define ATMEL_MPOP_G4                                               12
-+#define ATMEL_MPOP_G4G3                                     0x00000020
-+#define ATMEL_MPOP_G4G3_G3                                           0
-+#define ATMEL_MPOP_G4G3_G3_MASK                             0x00000fff
-+#define ATMEL_MPOP_G4G3_G3_OFFSET                                    0
-+#define ATMEL_MPOP_G4G3_G3_SIZE                                     12
-+#define ATMEL_MPOP_G4G3_G4                                          12
-+#define ATMEL_MPOP_G4G3_G4_MASK                             0xfffff000
-+#define ATMEL_MPOP_G4G3_G4_OFFSET                                   12
-+#define ATMEL_MPOP_G4G3_G4_SIZE                                     20
-+#define ATMEL_MPOP_G4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_G4_OFFSET                                        12
-+#define ATMEL_MPOP_G4_SIZE                                          20
-+#define ATMEL_MPOP_G_MASK                                   0x0000ff00
-+#define ATMEL_MPOP_G_OFFSET                                          8
-+#define ATMEL_MPOP_G_SIZE                                            8
-+#define ATMEL_MPOP_INTCLEAR                                 0x000000b0
-+#define ATMEL_MPOP_INTCLEAR_EOP                                      3
-+#define ATMEL_MPOP_INTCLEAR_EOP_MASK                        0x00000008
-+#define ATMEL_MPOP_INTCLEAR_EOP_OFFSET                               3
-+#define ATMEL_MPOP_INTCLEAR_EOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OUT                                      2
-+#define ATMEL_MPOP_INTCLEAR_OUT_MASK                        0x00000004
-+#define ATMEL_MPOP_INTCLEAR_OUT_OFFSET                               2
-+#define ATMEL_MPOP_INTCLEAR_OUT_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY                                  1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_MASK                    0x00000002
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_OFFSET                           1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_SIZE                             1
-+#define ATMEL_MPOP_INTCLEAR_SOP                                      4
-+#define ATMEL_MPOP_INTCLEAR_SOP_MASK                        0x00000010
-+#define ATMEL_MPOP_INTCLEAR_SOP_OFFSET                               4
-+#define ATMEL_MPOP_INTCLEAR_SOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_YUV                                      0
-+#define ATMEL_MPOP_INTCLEAR_YUV_MASK                        0x00000001
-+#define ATMEL_MPOP_INTCLEAR_YUV_OFFSET                               0
-+#define ATMEL_MPOP_INTCLEAR_YUV_SIZE                                 1
-+#define ATMEL_MPOP_INTDIS                                   0x000000a4
-+#define ATMEL_MPOP_INTDIS_EOP                                        3
-+#define ATMEL_MPOP_INTDIS_EOP_MASK                          0x00000008
-+#define ATMEL_MPOP_INTDIS_EOP_OFFSET                                 3
-+#define ATMEL_MPOP_INTDIS_EOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OUT                                        2
-+#define ATMEL_MPOP_INTDIS_OUT_MASK                          0x00000004
-+#define ATMEL_MPOP_INTDIS_OUT_OFFSET                                 2
-+#define ATMEL_MPOP_INTDIS_OUT_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OVERLAY                                    1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_MASK                      0x00000002
-+#define ATMEL_MPOP_INTDIS_OVERLAY_OFFSET                             1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_SIZE                               1
-+#define ATMEL_MPOP_INTDIS_SOP                                        4
-+#define ATMEL_MPOP_INTDIS_SOP_MASK                          0x00000010
-+#define ATMEL_MPOP_INTDIS_SOP_OFFSET                                 4
-+#define ATMEL_MPOP_INTDIS_SOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_YUV                                        0
-+#define ATMEL_MPOP_INTDIS_YUV_MASK                          0x00000001
-+#define ATMEL_MPOP_INTDIS_YUV_OFFSET                                 0
-+#define ATMEL_MPOP_INTDIS_YUV_SIZE                                   1
-+#define ATMEL_MPOP_INTEN                                    0x000000a0
-+#define ATMEL_MPOP_INTEN_EOP                                         3
-+#define ATMEL_MPOP_INTEN_EOP_MASK                           0x00000008
-+#define ATMEL_MPOP_INTEN_EOP_OFFSET                                  3
-+#define ATMEL_MPOP_INTEN_EOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OUT                                         2
-+#define ATMEL_MPOP_INTEN_OUT_MASK                           0x00000004
-+#define ATMEL_MPOP_INTEN_OUT_OFFSET                                  2
-+#define ATMEL_MPOP_INTEN_OUT_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OVERLAY                                     1
-+#define ATMEL_MPOP_INTEN_OVERLAY_MASK                       0x00000002
-+#define ATMEL_MPOP_INTEN_OVERLAY_OFFSET                              1
-+#define ATMEL_MPOP_INTEN_OVERLAY_SIZE                                1
-+#define ATMEL_MPOP_INTEN_SOP                                         4
-+#define ATMEL_MPOP_INTEN_SOP_MASK                           0x00000010
-+#define ATMEL_MPOP_INTEN_SOP_OFFSET                                  4
-+#define ATMEL_MPOP_INTEN_SOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_YUV                                         0
-+#define ATMEL_MPOP_INTEN_YUV_MASK                           0x00000001
-+#define ATMEL_MPOP_INTEN_YUV_OFFSET                                  0
-+#define ATMEL_MPOP_INTEN_YUV_SIZE                                    1
-+#define ATMEL_MPOP_INTMASK                                  0x000000a8
-+#define ATMEL_MPOP_INTMASK_EOP                                       3
-+#define ATMEL_MPOP_INTMASK_EOP_MASK                         0x00000008
-+#define ATMEL_MPOP_INTMASK_EOP_OFFSET                                3
-+#define ATMEL_MPOP_INTMASK_EOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OUT                                       2
-+#define ATMEL_MPOP_INTMASK_OUT_MASK                         0x00000004
-+#define ATMEL_MPOP_INTMASK_OUT_OFFSET                                2
-+#define ATMEL_MPOP_INTMASK_OUT_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OVERLAY                                   1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_MASK                     0x00000002
-+#define ATMEL_MPOP_INTMASK_OVERLAY_OFFSET                            1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_SIZE                              1
-+#define ATMEL_MPOP_INTMASK_SOP                                       4
-+#define ATMEL_MPOP_INTMASK_SOP_MASK                         0x00000010
-+#define ATMEL_MPOP_INTMASK_SOP_OFFSET                                4
-+#define ATMEL_MPOP_INTMASK_SOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_YUV                                       0
-+#define ATMEL_MPOP_INTMASK_YUV_MASK                         0x00000001
-+#define ATMEL_MPOP_INTMASK_YUV_OFFSET                                0
-+#define ATMEL_MPOP_INTMASK_YUV_SIZE                                  1
-+#define ATMEL_MPOP_INTSTATUS                                0x000000ac
-+#define ATMEL_MPOP_INTSTATUS_EOP                                     3
-+#define ATMEL_MPOP_INTSTATUS_EOP_MASK                       0x00000008
-+#define ATMEL_MPOP_INTSTATUS_EOP_OFFSET                              3
-+#define ATMEL_MPOP_INTSTATUS_EOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OUT                                     2
-+#define ATMEL_MPOP_INTSTATUS_OUT_MASK                       0x00000004
-+#define ATMEL_MPOP_INTSTATUS_OUT_OFFSET                              2
-+#define ATMEL_MPOP_INTSTATUS_OUT_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY                                 1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_MASK                   0x00000002
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_OFFSET                          1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_SIZE                            1
-+#define ATMEL_MPOP_INTSTATUS_SOP                                     4
-+#define ATMEL_MPOP_INTSTATUS_SOP_MASK                       0x00000010
-+#define ATMEL_MPOP_INTSTATUS_SOP_OFFSET                              4
-+#define ATMEL_MPOP_INTSTATUS_SOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_YUV                                     0
-+#define ATMEL_MPOP_INTSTATUS_YUV_MASK                       0x00000001
-+#define ATMEL_MPOP_INTSTATUS_YUV_OFFSET                              0
-+#define ATMEL_MPOP_INTSTATUS_YUV_SIZE                                1
-+#define ATMEL_MPOP_INVERT                                           25
-+#define ATMEL_MPOP_INVERT_MASK                              0x02000000
-+#define ATMEL_MPOP_INVERT_OFFSET                                    25
-+#define ATMEL_MPOP_INVERT_SIZE                                       1
-+#define ATMEL_MPOP_MSTR_PTR                                 0x0000000c
-+#define ATMEL_MPOP_MSTR_PTR_MASK                            0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR                                 0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_MASK                   0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_OFFSET                          0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_SIZE                           32
-+#define ATMEL_MPOP_MSTR_PTR_OFFSET                                   0
-+#define ATMEL_MPOP_MSTR_PTR_SIZE                                    32
-+#define ATMEL_MPOP_O1EN                                              1
-+#define ATMEL_MPOP_O1EN_MASK                                0x00000002
-+#define ATMEL_MPOP_O1EN_OFFSET                                       1
-+#define ATMEL_MPOP_O1EN_SIZE                                         1
-+#define ATMEL_MPOP_O1_POS                                   0x00000050
-+#define ATMEL_MPOP_O1_POS_O1_POS_X                                  11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y                                   0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_X                                         11
-+#define ATMEL_MPOP_O1_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O1_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O1_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O1_POS_Y                                          0
-+#define ATMEL_MPOP_O1_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O1_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O1_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O1_SAR                                   0x00000040
-+#define ATMEL_MPOP_O1_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR                                     0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_SIZE                               32
-+#define ATMEL_MPOP_O1_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O1_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O1_SIZE                                  0x00000064
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X                                11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y                                 0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_X                                        11
-+#define ATMEL_MPOP_O1_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O1_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O1_SIZE_Y                                         0
-+#define ATMEL_MPOP_O1_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O1_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O1_WTC                                   0x00000074
-+#define ATMEL_MPOP_O1_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC                                     0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_SIZE                               32
-+#define ATMEL_MPOP_O1_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O1_WTC_SIZE                                      32
-+#define ATMEL_MPOP_O2EN                                              2
-+#define ATMEL_MPOP_O2EN_MASK                                0x00000004
-+#define ATMEL_MPOP_O2EN_OFFSET                                       2
-+#define ATMEL_MPOP_O2EN_SIZE                                         1
-+#define ATMEL_MPOP_O2_POS                                   0x00000054
-+#define ATMEL_MPOP_O2_POS_O2_POS_X                                  11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y                                   0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_X                                         11
-+#define ATMEL_MPOP_O2_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O2_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O2_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O2_POS_Y                                          0
-+#define ATMEL_MPOP_O2_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O2_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O2_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O2_SAR                                   0x00000044
-+#define ATMEL_MPOP_O2_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR                                     0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_SIZE                               32
-+#define ATMEL_MPOP_O2_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O2_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O2_SIZE                                  0x00000068
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X                                11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y                                 0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_X                                        11
-+#define ATMEL_MPOP_O2_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O2_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O2_SIZE_Y                                         0
-+#define ATMEL_MPOP_O2_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O2_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O2_WTC                                   0x00000078
-+#define ATMEL_MPOP_O2_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC                                     0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_SIZE                               32
-+#define ATMEL_MPOP_O2_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O2_WTC_SIZE                                      32
-+#define ATMEL_MPOP_OCR                                      0x00000008
-+#define ATMEL_MPOP_OCR_BGR                                           6
-+#define ATMEL_MPOP_OCR_BGR_MASK                             0x00000040
-+#define ATMEL_MPOP_OCR_BGR_OFFSET                                    6
-+#define ATMEL_MPOP_OCR_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OCR_CURSOREN                                      0
-+#define ATMEL_MPOP_OCR_CURSOREN_MASK                        0x00000001
-+#define ATMEL_MPOP_OCR_CURSOREN_OFFSET                               0
-+#define ATMEL_MPOP_OCR_CURSOREN_SIZE                                 1
-+#define ATMEL_MPOP_OCR_O1EN                                          1
-+#define ATMEL_MPOP_OCR_O1EN_MASK                            0x00000002
-+#define ATMEL_MPOP_OCR_O1EN_OFFSET                                   1
-+#define ATMEL_MPOP_OCR_O1EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_O2EN                                          2
-+#define ATMEL_MPOP_OCR_O2EN_MASK                            0x00000004
-+#define ATMEL_MPOP_OCR_O2EN_OFFSET                                   2
-+#define ATMEL_MPOP_OCR_O2EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_RGBEN                                         3
-+#define ATMEL_MPOP_OCR_RGBEN_MASK                           0x00000008
-+#define ATMEL_MPOP_OCR_RGBEN_OFFSET                                  3
-+#define ATMEL_MPOP_OCR_RGBEN_SIZE                                    1
-+#define ATMEL_MPOP_OCR_RGBFORM                                       5
-+#define ATMEL_MPOP_OCR_RGBFORM_MASK                         0x00000020
-+#define ATMEL_MPOP_OCR_RGBFORM_OFFSET                                5
-+#define ATMEL_MPOP_OCR_RGBFORM_SIZE                                  1
-+#define ATMEL_MPOP_OCR_RGBSRC                                        4
-+#define ATMEL_MPOP_OCR_RGBSRC_MASK                          0x00000010
-+#define ATMEL_MPOP_OCR_RGBSRC_OFFSET                                 4
-+#define ATMEL_MPOP_OCR_RGBSRC_SIZE                                   1
-+#define ATMEL_MPOP_OUT                                               2
-+#define ATMEL_MPOP_OUT_BEAR                                 0x0000009c
-+#define ATMEL_MPOP_OUT_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR                                 0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_SIZE                           32
-+#define ATMEL_MPOP_OUT_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_OUT_BGR                                           3
-+#define ATMEL_MPOP_OUT_BGR_MASK                             0x00000008
-+#define ATMEL_MPOP_OUT_BGR_OFFSET                                    3
-+#define ATMEL_MPOP_OUT_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OUT_CTRL                                          2
-+#define ATMEL_MPOP_OUT_CTRL_MASK                            0x00000004
-+#define ATMEL_MPOP_OUT_CTRL_OFFSET                                   2
-+#define ATMEL_MPOP_OUT_CTRL_SIZE                                     1
-+#define ATMEL_MPOP_OUT_MASK                                 0x00000004
-+#define ATMEL_MPOP_OUT_OFFSET                                        2
-+#define ATMEL_MPOP_OUT_SIZE                                          1
-+#define ATMEL_MPOP_OVERLAY                                           1
-+#define ATMEL_MPOP_OVERLAY_BEAR                             0x00000098
-+#define ATMEL_MPOP_OVERLAY_BEAR_MASK                        0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OFFSET                               0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR                         0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_MASK           0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_OFFSET                  0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_SIZE                   32
-+#define ATMEL_MPOP_OVERLAY_BEAR_SIZE                                32
-+#define ATMEL_MPOP_OVERLAY_MASK                             0x00000002
-+#define ATMEL_MPOP_OVERLAY_OFFSET                                    1
-+#define ATMEL_MPOP_OVERLAY_SIZE                                      1
-+#define ATMEL_MPOP_PALETTEDATA                              0x00000400
-+#define ATMEL_MPOP_R                                                16
-+#define ATMEL_MPOP_R1                                                0
-+#define ATMEL_MPOP_R1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R1_OFFSET                                         0
-+#define ATMEL_MPOP_R1_SIZE                                          12
-+#define ATMEL_MPOP_R2                                               12
-+#define ATMEL_MPOP_R2R1                                     0x00000014
-+#define ATMEL_MPOP_R2R1_R1                                           0
-+#define ATMEL_MPOP_R2R1_R1_MASK                             0x00000fff
-+#define ATMEL_MPOP_R2R1_R1_OFFSET                                    0
-+#define ATMEL_MPOP_R2R1_R1_SIZE                                     12
-+#define ATMEL_MPOP_R2R1_R2                                          12
-+#define ATMEL_MPOP_R2R1_R2_MASK                             0x00fff000
-+#define ATMEL_MPOP_R2R1_R2_OFFSET                                   12
-+#define ATMEL_MPOP_R2R1_R2_SIZE                                     12
-+#define ATMEL_MPOP_R2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_R2_OFFSET                                        12
-+#define ATMEL_MPOP_R2_SIZE                                          12
-+#define ATMEL_MPOP_R3                                                0
-+#define ATMEL_MPOP_R3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R3_OFFSET                                         0
-+#define ATMEL_MPOP_R3_SIZE                                          12
-+#define ATMEL_MPOP_R4                                               12
-+#define ATMEL_MPOP_R4R3                                     0x00000018
-+#define ATMEL_MPOP_R4R3_R3                                           0
-+#define ATMEL_MPOP_R4R3_R3_MASK                             0x00000fff
-+#define ATMEL_MPOP_R4R3_R3_OFFSET                                    0
-+#define ATMEL_MPOP_R4R3_R3_SIZE                                     12
-+#define ATMEL_MPOP_R4R3_R4                                          12
-+#define ATMEL_MPOP_R4R3_R4_MASK                             0xfffff000
-+#define ATMEL_MPOP_R4R3_R4_OFFSET                                   12
-+#define ATMEL_MPOP_R4R3_R4_SIZE                                     20
-+#define ATMEL_MPOP_R4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_R4_OFFSET                                        12
-+#define ATMEL_MPOP_R4_SIZE                                          20
-+#define ATMEL_MPOP_RGBEN                                             3
-+#define ATMEL_MPOP_RGBEN_MASK                               0x00000008
-+#define ATMEL_MPOP_RGBEN_OFFSET                                      3
-+#define ATMEL_MPOP_RGBEN_SIZE                                        1
-+#define ATMEL_MPOP_RGBFORM                                           5
-+#define ATMEL_MPOP_RGBFORM_MASK                             0x00000020
-+#define ATMEL_MPOP_RGBFORM_OFFSET                                    5
-+#define ATMEL_MPOP_RGBFORM_SIZE                                      1
-+#define ATMEL_MPOP_RGBSRC                                            4
-+#define ATMEL_MPOP_RGBSRC_MASK                              0x00000010
-+#define ATMEL_MPOP_RGBSRC_OFFSET                                     4
-+#define ATMEL_MPOP_RGBSRC_SIZE                                       1
-+#define ATMEL_MPOP_RGB_POS                                  0x0000004c
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X                                11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_OFFSET                         11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y                                 0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_OFFSET                          0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_X                                        11
-+#define ATMEL_MPOP_RGB_POS_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_RGB_POS_X_OFFSET                                 11
-+#define ATMEL_MPOP_RGB_POS_X_SIZE                                   11
-+#define ATMEL_MPOP_RGB_POS_Y                                         0
-+#define ATMEL_MPOP_RGB_POS_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_RGB_POS_Y_OFFSET                                  0
-+#define ATMEL_MPOP_RGB_POS_Y_SIZE                                   11
-+#define ATMEL_MPOP_RGB_SAR                                  0x0000003c
-+#define ATMEL_MPOP_RGB_SAR_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR                                   0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_OFFSET                            0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_SIZE                             32
-+#define ATMEL_MPOP_RGB_SAR_SIZE                                     32
-+#define ATMEL_MPOP_RGB_SIZE                                 0x00000060
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X                              11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_MASK                 0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_OFFSET                       11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y                               0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_MASK                 0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_OFFSET                        0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_X                                       11
-+#define ATMEL_MPOP_RGB_SIZE_X_MASK                          0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_X_OFFSET                                11
-+#define ATMEL_MPOP_RGB_SIZE_X_SIZE                                  11
-+#define ATMEL_MPOP_RGB_SIZE_Y                                        0
-+#define ATMEL_MPOP_RGB_SIZE_Y_MASK                          0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_Y_OFFSET                                 0
-+#define ATMEL_MPOP_RGB_SIZE_Y_SIZE                                  11
-+#define ATMEL_MPOP_RGB_WTC                                  0x00000070
-+#define ATMEL_MPOP_RGB_WTC_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC                                   0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_OFFSET                            0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_SIZE                             32
-+#define ATMEL_MPOP_RGB_WTC_SIZE                                     32
-+#define ATMEL_MPOP_R_MASK                                   0x00ff0000
-+#define ATMEL_MPOP_R_OFFSET                                         16
-+#define ATMEL_MPOP_R_SIZE                                            8
-+#define ATMEL_MPOP_SOP                                               4
-+#define ATMEL_MPOP_SOP_MASK                                 0x00000010
-+#define ATMEL_MPOP_SOP_OFFSET                                        4
-+#define ATMEL_MPOP_SOP_SIZE                                          1
-+#define ATMEL_MPOP_START                                             1
-+#define ATMEL_MPOP_START_MASK                               0x00000002
-+#define ATMEL_MPOP_START_OFFSET                                      1
-+#define ATMEL_MPOP_START_SIZE                                        1
-+#define ATMEL_MPOP_STRIDE                                   0x0000002c
-+#define ATMEL_MPOP_STRIDE_MASK                              0xffffffff
-+#define ATMEL_MPOP_STRIDE_OFFSET                                     0
-+#define ATMEL_MPOP_STRIDE_SIZE                                      32
-+#define ATMEL_MPOP_STRIDE_STRIDE                                     0
-+#define ATMEL_MPOP_STRIDE_STRIDE_MASK                       0xffffffff
-+#define ATMEL_MPOP_STRIDE_STRIDE_OFFSET                              0
-+#define ATMEL_MPOP_STRIDE_STRIDE_SIZE                               32
-+#define ATMEL_MPOP_U_SAR                                    0x00000034
-+#define ATMEL_MPOP_U_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_U_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_U_SAR_SIZE                                       32
-+#define ATMEL_MPOP_U_SAR_U_SAR                                       0
-+#define ATMEL_MPOP_U_SAR_U_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_U_SAR_U_SAR_OFFSET                                0
-+#define ATMEL_MPOP_U_SAR_U_SAR_SIZE                                 32
-+#define ATMEL_MPOP_VISIBLE                                          24
-+#define ATMEL_MPOP_VISIBLE_MASK                             0x01000000
-+#define ATMEL_MPOP_VISIBLE_OFFSET                                   24
-+#define ATMEL_MPOP_VISIBLE_SIZE                                      1
-+#define ATMEL_MPOP_V_SAR                                    0x00000038
-+#define ATMEL_MPOP_V_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_V_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_V_SAR_SIZE                                       32
-+#define ATMEL_MPOP_V_SAR_V_SAR                                       0
-+#define ATMEL_MPOP_V_SAR_V_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_V_SAR_V_SAR_OFFSET                                0
-+#define ATMEL_MPOP_V_SAR_V_SAR_SIZE                                 32
-+#define ATMEL_MPOP_XRESIZE                                          16
-+#define ATMEL_MPOP_XRESIZE_MASK                             0x00ff0000
-+#define ATMEL_MPOP_XRESIZE_OFFSET                                   16
-+#define ATMEL_MPOP_XRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YCR                                      0x00000004
-+#define ATMEL_MPOP_YCR_XRESIZE                                      16
-+#define ATMEL_MPOP_YCR_XRESIZE_MASK                         0x00ff0000
-+#define ATMEL_MPOP_YCR_XRESIZE_OFFSET                               16
-+#define ATMEL_MPOP_YCR_XRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YRESIZE                                       8
-+#define ATMEL_MPOP_YCR_YRESIZE_MASK                         0x0000ff00
-+#define ATMEL_MPOP_YCR_YRESIZE_OFFSET                                8
-+#define ATMEL_MPOP_YCR_YRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YUVFORMAT                                     0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_MASK                       0x00000003
-+#define ATMEL_MPOP_YCR_YUVFORMAT_OFFSET                              0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_SIZE                                2
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_420              0x00000002
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_422              0x00000001
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_444              0x00000000
-+#define ATMEL_MPOP_YRESIZE                                           8
-+#define ATMEL_MPOP_YRESIZE_MASK                             0x0000ff00
-+#define ATMEL_MPOP_YRESIZE_OFFSET                                    8
-+#define ATMEL_MPOP_YRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YUV                                               0
-+#define ATMEL_MPOP_YUVFORMAT                                         0
-+#define ATMEL_MPOP_YUVFORMAT_420                            0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_422                            0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_444                            0x00000000
-+#define ATMEL_MPOP_YUVFORMAT_MASK                           0x00000003
-+#define ATMEL_MPOP_YUVFORMAT_OFFSET                                  0
-+#define ATMEL_MPOP_YUVFORMAT_SIZE                                    2
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_420                  0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_422                  0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_444                  0x00000000
-+#define ATMEL_MPOP_YUV_BEAR                                 0x00000094
-+#define ATMEL_MPOP_YUV_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_YUV_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR                                 0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_SIZE                           32
-+#define ATMEL_MPOP_YUV_MASK                                 0x00000001
-+#define ATMEL_MPOP_YUV_MAX_COORD                            0x0000005c
-+#define ATMEL_MPOP_YUV_MAX_COORD_X                                  11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET                           11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_SIZE                             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y                                   0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X                    11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_MASK       0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_OFFSET             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y                     0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_MASK       0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_OFFSET              0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET                            0
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_SIZE                             11
-+#define ATMEL_MPOP_YUV_OFFSET                                        0
-+#define ATMEL_MPOP_YUV_SIZE                                          1
-+#define ATMEL_MPOP_Y_SAR                                    0x00000030
-+#define ATMEL_MPOP_Y_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_Y_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_Y_SAR_SIZE                                       32
-+#define ATMEL_MPOP_Y_SAR_Y_SAR                                       0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_OFFSET                                0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_SIZE                                 32
-+
-+#endif /* __ATMEL_MPOP_H__ */
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/clock.c linux-2.6.28.2/arch/avr32/mach-at32ap/clock.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/clock.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/clock.c	2009-01-29 10:16:11.000000000 +0100
-@@ -178,7 +178,11 @@
- #include <linux/io.h>
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
--#include "pm.h"
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# include "pm-v1.h"
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include "pm-v3.h"
-+#endif
- 
- 
- #define	NEST_DELTA	2
-@@ -234,19 +238,40 @@
- 	struct clk 	*clk;
- 
- 	/* show all the power manager registers */
--	seq_printf(s, "MCCTRL  = %8x\n", pm_readl(MCCTRL));
--	seq_printf(s, "CKSEL   = %8x\n", pm_readl(CKSEL));
--	seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
--	seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
--	seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
--	seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
--	seq_printf(s, "PLL0    = %8x\n", pm_readl(PLL0));
--	seq_printf(s, "PLL1    = %8x\n", pm_readl(PLL1));
--	seq_printf(s, "IMR     = %8x\n", pm_readl(IMR));
-+	seq_printf(s, "MCCTRL     = %8x\n", pm_readl(MCCTRL));
-+	seq_printf(s, "CKSEL      = %8x\n", pm_readl(CKSEL));
-+#ifdef CONFIG_CPU_AT32AP700X
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPU_MASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSB_MASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBA_MASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBB_MASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL0));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL1));
-+#else
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPUMASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSBMASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBAMASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBBMASK));
-+	seq_printf(s, "PBADIVMASK = %8x\n", pm_readl(PBADIVMASK));
-+	seq_printf(s, "PBBDIVMASK = %8x\n", pm_readl(PBBDIVMASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL[0]));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL[1]));
-+	seq_printf(s, "PLL2       = %8x\n", pm_readl(PLL[2]));
-+	seq_printf(s, "OSCCTRL0   = %8x\n", pm_readl(OSCCTRL[0]));
-+	seq_printf(s, "OSCCTRL1   = %8x\n", pm_readl(OSCCTRL[1]));
-+	seq_printf(s, "OSCCTRL2   = %8x\n", pm_readl(OSCCTRL[2]));
-+	seq_printf(s, "POSCSR     = %8x\n", pm_readl(POSCSR));
-+	seq_printf(s, "PPCR       = %8x\n", pm_readl(PPCR));
-+#endif
-+	seq_printf(s, "IMR        = %8x\n", pm_readl(IMR));
- 	for (i = 0; i < 8; i++) {
- 		if (i == 5)
- 			continue;
--		seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
-+#ifdef CONFIG_CPU_AT32AP700X
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL(i)));
-+#else
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL[i]));
-+#endif
- 	}
- 
- 	seq_printf(s, "\n");
-@@ -269,6 +294,16 @@
- 	dump_clock(clk, &r);
- 	clk_put(clk);
- 
-+#ifdef CONFIG_CPU_AT32AP720X
-+	clk = clk_get(NULL, "osc2");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "rcosc");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+#endif
-+
- 	spin_unlock(&clk_list_lock);
- 
- 	return 0;
-
diff --git a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-201-avr32-atmel_mpopfb-disable-debug.patch b/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-201-avr32-atmel_mpopfb-disable-debug.patch
deleted file mode 100644
index 6cc4b67..0000000
--- a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-201-avr32-atmel_mpopfb-disable-debug.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From f26e2224d46430ac4f6c0ddeb518f5766ba62b16 Mon Sep 17 00:00:00 2001
-From: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-Date: Wed, 26 Nov 2008 14:10:45 +0100
-Subject: [PATCH 2/3] atmel_mpopfb: remove define DEBUG to disable debug output
-
-Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-
-diff --git a/drivers/video/atmel_mpopfb.c b/drivers/video/atmel_mpopfb.c
-index 0a07f7b..3b4b668 100644
---- a/drivers/video/atmel_mpopfb.c
-+++ b/drivers/video/atmel_mpopfb.c
-@@ -8,8 +8,6 @@
-  * more details.
-  */
- 
--#define DEBUG
--
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
--- 
-1.5.6.3
-
diff --git a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch b/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
deleted file mode 100644
index 2163c92..0000000
--- a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-diff -urN linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c linux-2.6.28.2/drivers/video/atmel_mpopfb.c
---- linux-2.6.28.2-0rig//drivers/video/atmel_mpopfb.c	2009-01-29 09:41:04.000000000 +0100
-+++ linux-2.6.28.2/drivers/video/atmel_mpopfb.c	2009-01-29 09:43:46.000000000 +0100
-@@ -315,6 +315,10 @@
- static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
- {
- 	if (!sinfo->running) {
-+		unsigned int line_cache_disable =
-+			sinfo->baseimg_info.line_cache_disable ?
-+			ATMEL_MPOP_CR_CACHEDIS_MASK : 0;
-+
- 		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
- 
- 		/* Enable all error interrupts. */
-@@ -325,9 +329,9 @@
- 		 * reading from the slave interface it will start
- 		 * generating a frame.
- 		 */
--		mpop_writel(sinfo, ATMEL_MPOP_CR,
--			    ATMEL_MPOP_CR_EN_MASK
--			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
-+		mpop_writel(sinfo, ATMEL_MPOP_CR, ATMEL_MPOP_CR_EN_MASK
-+				| line_cache_disable
-+				| ATMEL_MPOP_CR_OUT_BGR_MASK);
- 
- 		sinfo->running = 1;
- 	}
-diff -urN linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h linux-2.6.28.2/include/linux/atmel_mpopfb.h
---- linux-2.6.28.2-0rig//include/linux/atmel_mpopfb.h	2009-01-29 09:41:04.000000000 +0100
-+++ linux-2.6.28.2/include/linux/atmel_mpopfb.h	2009-01-29 09:43:46.000000000 +0100
-@@ -42,9 +42,11 @@
- 	unsigned xsize;
- 	unsigned ysize;
- 
--	/* Signal that we should flip the video. */
-+	/* Signal for flipping the video. */
- 	int flip;
- 
-+	/* Signal for disabling the line cache. */
-+	int line_cache_disable;
- };
- 
- enum atmel_mpopfb_overlay_type {
diff --git a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-203-avr32-fix-arch-header-byteorder.patch b/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-203-avr32-fix-arch-header-byteorder.patch
deleted file mode 100644
index ac990f9..0000000
--- a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-203-avr32-fix-arch-header-byteorder.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-Index: linux-2.6.27.6/arch/avr32/include/asm/byteorder.h
-===================================================================
---- linux-2.6.27.6.orig/arch/avr32/include/asm/byteorder.h	2008-11-28 16:47:15.000000000 +0100
-+++ linux-2.6.27.6/arch/avr32/include/asm/byteorder.h	2008-11-28 16:47:31.000000000 +0100
-@@ -7,8 +7,9 @@
- #include <asm/types.h>
- #include <linux/compiler.h>
- 
--#define __BIG_ENDIAN
-+#define __BIG_ENDIAN 4321
- #define __SWAB_64_THRU_32__
-+#define __BYTEORDER_HAS_U64__
- 
- #ifdef __CHECKER__
- extern unsigned long __builtin_bswap_32(unsigned long x);
-@@ -33,5 +34,5 @@
- #define __arch_swab32 __arch_swab32
- #endif
- 
--#include <linux/byteorder.h>
-+#include <linux/byteorder/big_endian.h>
- #endif /* __ASM_AVR32_BYTEORDER_H */
-Index: linux-2.6.27.6/arch/avr32/mach-at32ap/include/mach/io.h
-===================================================================
---- linux-2.6.27.6.orig/arch/avr32/mach-at32ap/include/mach/io.h	2008-11-28 16:47:58.000000000 +0100
-+++ linux-2.6.27.6/arch/avr32/mach-at32ap/include/mach/io.h	2008-11-28 16:48:15.000000000 +0100
-@@ -1,7 +1,7 @@
- #ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
- #define __ASM_AVR32_ARCH_AT32AP_IO_H
- 
--#include <linux/swab.h>
-+#include <linux/byteorder/swabb.h>
- 
- #if defined(CONFIG_AP700X_32_BIT_SMC)
- # define __swizzle_addr_b(addr)	(addr ^ 3UL)
diff --git a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch b/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
deleted file mode 100644
index 05522da..0000000
--- a/target/device/Atmel/arch-avr32/kernel-headers-2.6.28.2/linux-2.6.28.7-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-diff -urN linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1002.c linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1002.c
---- linux-2.6.28.2-0rig//arch/avr32/boards/atstk1000/atstk1002.c	2009-01-29 08:39:35.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/boards/atstk1000/atstk1002.c	2009-01-29 09:50:56.000000000 +0100
-@@ -99,6 +99,7 @@
- static struct atmel_nand_data atstk1006_nand_data __initdata = {
- 	.cle		= 21,
- 	.ale		= 22,
-+	.det_pin	= GPIO_PIN_NONE,
- 	.rdy_pin	= GPIO_PIN_PB(30),
- 	.enable_pin	= GPIO_PIN_PB(29),
- 	.partition_info	= nand_part_info,
-diff -urN linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c
---- linux-2.6.28.2-0rig//arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 09:41:04.000000000 +0100
-+++ linux-2.6.28.2/arch/avr32/mach-at32ap/at32ap700x.c	2009-01-29 09:50:56.000000000 +0100
-@@ -1972,13 +1972,14 @@
- 		goto fail;
- 
- 	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
--	if (data->enable_pin)
-+
-+	if (gpio_is_valid(data->enable_pin))
- 		at32_select_gpio(data->enable_pin,
- 				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
--	if (data->rdy_pin)
--		at32_select_gpio(data->rdy_pin, 0);
--	if (data->det_pin)
-+	if (gpio_is_valid(data->det_pin))
- 		at32_select_gpio(data->det_pin, 0);
-+	if (gpio_is_valid(data->rdy_pin))
-+		at32_select_gpio(data->rdy_pin, 0);
- 
- 	platform_device_add(pdev);
- 	return pdev;
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch
deleted file mode 100644
index 11bcdae..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-100-avr32-atmel.1.patch
+++ /dev/null
@@ -1,26786 +0,0 @@
-diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
-index dbfd9f7..b2a96fe 100644
---- a/arch/arm/mach-at91/include/mach/cpu.h
-+++ b/arch/arm/mach-at91/include/mach/cpu.h
-@@ -99,5 +99,6 @@ static inline unsigned long at91_arch_identify(void)
-  * definitions may reduce clutter in common drivers.
-  */
- #define cpu_is_at32ap7000()	(0)
-+#define cpu_is_at32ap7200()	(0)
- 
- #endif
-diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
-index 7c239a9..6cef643 100644
---- a/arch/avr32/Kconfig
-+++ b/arch/avr32/Kconfig
-@@ -83,6 +83,18 @@ config MMU
- config PERFORMANCE_COUNTERS
- 	bool
- 
-+# The old "PIO" portmux/GPIO module used on AT32AP700x
-+config PORTMUX_PIO
-+	bool
-+
-+# The new "GPIO" portmux/GPIO module, version 2
-+config PORTMUX_GPIO_V2
-+	bool
-+
-+# Asynchronous Timer clocksource/clockevent driver
-+config TIMER_AST
-+	bool
-+
- config PLATFORM_AT32AP
- 	bool
- 	select SUBARCH_AVR32B
-@@ -99,6 +111,7 @@ config PLATFORM_AT32AP
- config CPU_AT32AP700X
- 	bool
- 	select PLATFORM_AT32AP
-+	select PORTMUX_PIO
- config CPU_AT32AP7000
- 	bool
- 	select CPU_AT32AP700X
-@@ -109,6 +122,16 @@ config CPU_AT32AP7002
- 	bool
- 	select CPU_AT32AP700X
- 
-+# AP7200 derivatives
-+config CPU_AT32AP720X
-+	bool
-+	select PLATFORM_AT32AP
-+	select TIMER_AST
-+	select PORTMUX_GPIO_V2
-+config CPU_AT32AP7200
-+	bool
-+	select CPU_AT32AP720X
-+
- choice
- 	prompt "AVR32 board type"
- 	default BOARD_ATSTK1000
-@@ -119,11 +142,19 @@ config BOARD_ATSTK1000
- config BOARD_ATNGW100
- 	bool "ATNGW100 Network Gateway"
- 	select CPU_AT32AP7000
-+
-+config BOARD_FAVR_32
-+	bool "Favr-32 LCD-board"
-+	select CPU_AT32AP7000
-+
-+config BOARD_MIMC200
-+	bool "MIMC200 CPU board"
-+	select CPU_AT32AP7000
- endchoice
- 
--if BOARD_ATSTK1000
- source "arch/avr32/boards/atstk1000/Kconfig"
--endif
-+source "arch/avr32/boards/atngw100/Kconfig"
-+source "arch/avr32/boards/favr-32/Kconfig"
- 
- choice
- 	prompt "Boot loader type"
-@@ -138,14 +169,17 @@ source "arch/avr32/mach-at32ap/Kconfig"
- config LOAD_ADDRESS
- 	hex
- 	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config ENTRY_ADDRESS
- 	hex
- 	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-+	default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP720X=y
- 
- config PHYS_OFFSET
- 	hex
- 	default 0x10000000 if CPU_AT32AP700X=y
-+	default 0x10000000 if CPU_AT32AP720X=y
- 
- source "kernel/Kconfig.preempt"
- 
-diff --git a/arch/avr32/Makefile b/arch/avr32/Makefile
-index c9e1f0b..b088e10 100644
---- a/arch/avr32/Makefile
-+++ b/arch/avr32/Makefile
-@@ -33,6 +33,8 @@ head-y					+= arch/avr32/kernel/head.o
- core-y					+= $(machdirs)
- core-$(CONFIG_BOARD_ATSTK1000)		+= arch/avr32/boards/atstk1000/
- core-$(CONFIG_BOARD_ATNGW100)		+= arch/avr32/boards/atngw100/
-+core-$(CONFIG_BOARD_FAVR_32)		+= arch/avr32/boards/favr-32/
-+core-$(CONFIG_BOARD_MIMC200)		+= arch/avr32/boards/mimc200/
- core-$(CONFIG_LOADER_U_BOOT)		+= arch/avr32/boot/u-boot/
- core-y					+= arch/avr32/kernel/
- core-y					+= arch/avr32/mm/
-diff --git a/arch/avr32/boards/atngw100/Kconfig b/arch/avr32/boards/atngw100/Kconfig
-new file mode 100644
-index 0000000..b3f9947
---- /dev/null
-+++ b/arch/avr32/boards/atngw100/Kconfig
-@@ -0,0 +1,35 @@
-+# NGW100 customization
-+
-+if BOARD_ATNGW100
-+
-+config BOARD_ATNGW100_EVKLCD10X
-+	bool "Add support for EVKLCD10X addon board"
-+	help
-+	  This enables support for the EVKLCD100 (QVGA) or EVKLCD101 (VGA)
-+	  addon board for the NGW100. By enabling this the LCD controller and
-+	  AC97 controller is added as platform devices.
-+
-+	  This choice disables the detect pin and the write-protect pin for the
-+	  MCI platform device, since it conflicts with the LCD platform device.
-+	  The MCI pins can be reenabled by editing the "add device function" but
-+	  this may break the setup for other displays that use these pins.
-+
-+	  Choose 'Y' here if you have a EVKLCD100/101 connected to the NGW100.
-+
-+choice
-+	prompt "LCD panel resolution on EVKLCD10X"
-+	depends on BOARD_ATNGW100_EVKLCD10X
-+	default BOARD_ATNGW100_EVKLCD10X_VGA
-+
-+config BOARD_ATNGW100_EVKLCD10X_QVGA
-+	bool "QVGA (320x240)"
-+
-+config BOARD_ATNGW100_EVKLCD10X_VGA
-+	bool "VGA (640x480)"
-+
-+config BOARD_ATNGW100_EVKLCD10X_POW_QVGA
-+	bool "Powertip QVGA (320x240)"
-+
-+endchoice
-+
-+endif	# BOARD_ATNGW100
-diff --git a/arch/avr32/boards/atngw100/Makefile b/arch/avr32/boards/atngw100/Makefile
-index c740aa1..6376f53 100644
---- a/arch/avr32/boards/atngw100/Makefile
-+++ b/arch/avr32/boards/atngw100/Makefile
-@@ -1 +1,2 @@
--obj-y				+= setup.o flash.o
-+obj-y					+= setup.o flash.o
-+obj-$(CONFIG_BOARD_ATNGW100_EVKLCD10X)	+= evklcd10x.o
-diff --git a/arch/avr32/boards/atngw100/evklcd10x.c b/arch/avr32/boards/atngw100/evklcd10x.c
-new file mode 100644
-index 0000000..8140b22
---- /dev/null
-+++ b/arch/avr32/boards/atngw100/evklcd10x.c
-@@ -0,0 +1,155 @@
-+/*
-+ * Board-specific setup code for the ATEVKLCD10X addon board to the ATNGW100
-+ * Network Gateway
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published by
-+ * the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/linkage.h>
-+#include <linux/fb.h>
-+#include <linux/platform_device.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/board.h>
-+
-+static struct ac97c_platform_data __initdata ac97c0_data = {
-+	.dma_rx_periph_id	= 3,
-+	.dma_tx_periph_id	= 4,
-+	.dma_controller_id	= 0,
-+	.reset_pin		= GPIO_PIN_PB(19),
-+};
-+
-+#ifdef CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA
-+static struct fb_videomode __initdata tcg057vglad_modes[] = {
-+	{
-+		.name		= "640x480 @ 60",
-+		.refresh	= 60,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(25180),
-+
-+		.left_margin	= 64,		.right_margin	= 31,
-+		.upper_margin	= 34,		.lower_margin	= 2,
-+		.hsync_len	= 96,		.vsync_len	= 4,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "KYO",
-+	.monitor		= "TCG057VGLAD",
-+	.modedb			= tcg057vglad_modes,
-+	.modedb_len		= ARRAY_SIZE(tcg057vglad_modes),
-+	.hfmin			= 19948,
-+	.hfmax			= 31478,
-+	.vfmin			= 50,
-+	.vfmax			= 67,
-+	.dclkmax		= 28330000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#elif CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA
-+static struct fb_videomode __initdata tcg057qvlad_modes[] = {
-+	{
-+		.name		= "320x240 @ 60",
-+		.refresh	= 60,
-+		.xres		= 320,		.yres		= 240,
-+		.pixclock	= KHZ2PICOS(6300),
-+
-+		.left_margin	= 52,		.right_margin	= 28,
-+		.upper_margin	= 7,		.lower_margin	= 2,
-+		.hsync_len	= 96,		.vsync_len	= 4,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "KYO",
-+	.monitor		= "TCG057QVLAD",
-+	.modedb			= tcg057qvlad_modes,
-+	.modedb_len		= ARRAY_SIZE(tcg057qvlad_modes),
-+	.hfmin			= 19948,
-+	.hfmax			= 31478,
-+	.vfmin			= 50,
-+	.vfmax			= 67,
-+	.dclkmax		= 7000000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#elif CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA
-+static struct fb_videomode __initdata ph320240t_modes[] = {
-+	{
-+		.name		= "320x240 @ 60",
-+		.refresh	= 60,
-+		.xres		= 320,		.yres		= 240,
-+		.pixclock	= KHZ2PICOS(6300),
-+
-+		.left_margin	= 38,		.right_margin	= 20,
-+		.upper_margin	= 15,		.lower_margin	= 5,
-+		.hsync_len	= 30,		.vsync_len	= 3,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata atevklcd10x_default_monspecs = {
-+	.manufacturer		= "POW",
-+	.monitor		= "PH320240T",
-+	.modedb			= ph320240t_modes,
-+	.modedb_len		= ARRAY_SIZE(ph320240t_modes),
-+	.hfmin			= 14400,
-+	.hfmax			= 21600,
-+	.vfmin			= 50,
-+	.vfmax			= 90,
-+	.dclkmax		= 6400000,
-+};
-+
-+static struct atmel_lcdfb_info __initdata atevklcd10x_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &atevklcd10x_default_monspecs,
-+	.guard_time		= 2,
-+};
-+#endif
-+
-+static int __init atevklcd10x_init(void)
-+{
-+	at32_add_device_ac97c(0, &ac97c0_data);
-+
-+	at32_add_device_lcdc(0, &atevklcd10x_lcdc_data,
-+			fbmem_start, fbmem_size, 1);
-+	return 0;
-+}
-+postcore_initcall(atevklcd10x_init);
-diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
-index b8286f1..32fb9ba 100644
---- a/arch/avr32/boards/atngw100/setup.c
-+++ b/arch/avr32/boards/atngw100/setup.c
-@@ -9,6 +9,7 @@
-  */
- #include <linux/clk.h>
- #include <linux/etherdevice.h>
-+#include <linux/gpio.h>
- #include <linux/irq.h>
- #include <linux/i2c.h>
- #include <linux/i2c-gpio.h>
-@@ -53,8 +54,16 @@ static struct spi_board_info spi0_board_info[] __initdata = {
- };
- 
- static struct mci_platform_data __initdata mci0_data = {
--	.detect_pin	= GPIO_PIN_PC(25),
--	.wp_pin		= GPIO_PIN_PE(0),
-+	.slot[0] = {
-+		.bus_width	= 4,
-+#ifndef CONFIG_BOARD_ATNGW100_EVKLCD10X
-+		.detect_pin	= GPIO_PIN_PC(25),
-+		.wp_pin		= GPIO_PIN_PE(0),
-+#else
-+		.detect_pin	= GPIO_PIN_NONE,
-+		.wp_pin		= GPIO_PIN_NONE,
-+#endif
-+	},
- };
- 
- /*
-@@ -168,8 +177,6 @@ static int __init atngw100_init(void)
- 	 * reserve any pins for it.
- 	 */
- 
--	at32_add_system_devices();
--
- 	at32_add_device_usart(0);
- 
- 	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-@@ -190,7 +197,7 @@ static int __init atngw100_init(void)
- 	 * PB28/EXTINT3 doesn't; it should be SMBALERT# (for PMBus),
- 	 * but it's not available off-board.
- 	 */
--	at32_select_periph(GPIO_PIN_PB(28), 0, AT32_GPIOF_PULLUP);
-+	at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
- 	at32_select_gpio(i2c_gpio_data.sda_pin,
- 		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
- 	at32_select_gpio(i2c_gpio_data.scl_pin,
-@@ -204,6 +211,15 @@ postcore_initcall(atngw100_init);
- 
- static int __init atngw100_arch_init(void)
- {
-+	/* PB30 is the otherwise unused jumper on the mainboard, with an
-+	 * external pullup; the jumper grounds it.  Use it however you
-+	 * like, including letting U-Boot or Linux tweak boot sequences.
-+	 */
-+	at32_select_gpio(GPIO_PIN_PB(30), 0);
-+	gpio_request(GPIO_PIN_PB(30), "j15");
-+	gpio_direction_input(GPIO_PIN_PB(30));
-+	gpio_export(GPIO_PIN_PB(30), false);
-+
- 	/* set_irq_type() after the arch_initcall for EIC has run, and
- 	 * before the I2C subsystem could try using this IRQ.
- 	 */
-diff --git a/arch/avr32/boards/atstk1000/Kconfig b/arch/avr32/boards/atstk1000/Kconfig
-index 8dc4821..0884884 100644
---- a/arch/avr32/boards/atstk1000/Kconfig
-+++ b/arch/avr32/boards/atstk1000/Kconfig
-@@ -18,6 +18,10 @@ config BOARD_ATSTK1004
- 	bool "ATSTK1004"
- 	select CPU_AT32AP7002
- 
-+config BOARD_ATSTK1005
-+	bool "ATSTK1005"
-+	select CPU_AT32AP7200
-+
- config BOARD_ATSTK1006
- 	bool "ATSTK1006"
- 	select CPU_AT32AP7000
-diff --git a/arch/avr32/boards/atstk1000/Makefile b/arch/avr32/boards/atstk1000/Makefile
-index edecee0..d0f248d 100644
---- a/arch/avr32/boards/atstk1000/Makefile
-+++ b/arch/avr32/boards/atstk1000/Makefile
-@@ -2,4 +2,5 @@ obj-y				+= setup.o flash.o
- obj-$(CONFIG_BOARD_ATSTK1002)	+= atstk1002.o
- obj-$(CONFIG_BOARD_ATSTK1003)	+= atstk1003.o
- obj-$(CONFIG_BOARD_ATSTK1004)	+= atstk1004.o
-+obj-$(CONFIG_BOARD_ATSTK1005)	+= atstk1005.o
- obj-$(CONFIG_BOARD_ATSTK1006)	+= atstk1002.o
-diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
-index dfc3443..11e7800 100644
---- a/arch/avr32/boards/atstk1000/atstk1002.c
-+++ b/arch/avr32/boards/atstk1000/atstk1002.c
-@@ -232,7 +232,7 @@ static void __init atstk1002_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -264,16 +264,20 @@ void __init setup_board(void)
- 
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+
- /* MMC card detect requires MACB0 *NOT* be used */
- #ifdef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
--static struct mci_platform_data __initdata mci0_data = {
--	.detect_pin	= GPIO_PIN_PC(14),	/* gpio30/sdcd */
--	.wp_pin		= GPIO_PIN_PC(15),	/* gpio31/sdwp */
--};
--#define MCI_PDATA	&mci0_data
-+		.detect_pin	= GPIO_PIN_PC(14), /* gpio30/sdcd */
-+		.wp_pin		= GPIO_PIN_PC(15), /* gpio31/sdwp */
- #else
--#define MCI_PDATA	NULL
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
- #endif	/* SW6 for sd{cd,wp} routing */
-+	},
-+};
- 
- #endif	/* SW2 for MMC signal routing */
- 
-@@ -283,25 +287,7 @@ static int __init atstk1002_init(void)
- 	 * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
- 	 * SDRAM-specific pins so that nobody messes with them.
- 	 */
--	at32_reserve_pin(GPIO_PIN_PE(0));	/* DATA[16]	*/
--	at32_reserve_pin(GPIO_PIN_PE(1));	/* DATA[17]	*/
--	at32_reserve_pin(GPIO_PIN_PE(2));	/* DATA[18]	*/
--	at32_reserve_pin(GPIO_PIN_PE(3));	/* DATA[19]	*/
--	at32_reserve_pin(GPIO_PIN_PE(4));	/* DATA[20]	*/
--	at32_reserve_pin(GPIO_PIN_PE(5));	/* DATA[21]	*/
--	at32_reserve_pin(GPIO_PIN_PE(6));	/* DATA[22]	*/
--	at32_reserve_pin(GPIO_PIN_PE(7));	/* DATA[23]	*/
--	at32_reserve_pin(GPIO_PIN_PE(8));	/* DATA[24]	*/
--	at32_reserve_pin(GPIO_PIN_PE(9));	/* DATA[25]	*/
--	at32_reserve_pin(GPIO_PIN_PE(10));	/* DATA[26]	*/
--	at32_reserve_pin(GPIO_PIN_PE(11));	/* DATA[27]	*/
--	at32_reserve_pin(GPIO_PIN_PE(12));	/* DATA[28]	*/
--	at32_reserve_pin(GPIO_PIN_PE(13));	/* DATA[29]	*/
--	at32_reserve_pin(GPIO_PIN_PE(14));	/* DATA[30]	*/
--	at32_reserve_pin(GPIO_PIN_PE(15));	/* DATA[31]	*/
--	at32_reserve_pin(GPIO_PIN_PE(26));	/* SDCS		*/
--
--	at32_add_system_devices();
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
- 
- #ifdef CONFIG_BOARD_ATSTK1006
- 	smc_set_timing(&nand_config, &nand_timing);
-@@ -326,13 +312,14 @@ static int __init atstk1002_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, MCI_PDATA);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- #ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
- 	set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
- #else
- 	at32_add_device_lcdc(0, &atstk1000_lcdc_data,
--			     fbmem_start, fbmem_size, 0);
-+			     fbmem_start, fbmem_size,
-+			     ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
- #endif
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-diff --git a/arch/avr32/boards/atstk1000/atstk1003.c b/arch/avr32/boards/atstk1000/atstk1003.c
-index 0cf6641..ac31666 100644
---- a/arch/avr32/boards/atstk1000/atstk1003.c
-+++ b/arch/avr32/boards/atstk1000/atstk1003.c
-@@ -19,6 +19,7 @@
- #include <linux/spi/spi.h>
- 
- #include <asm/setup.h>
-+#include <asm/atmel-mci.h>
- 
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
-@@ -66,6 +67,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
- } };
- #endif
- 
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
-+	},
-+};
-+#endif
-+
- #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- static void __init atstk1003_setup_extdac(void)
- {
-@@ -84,7 +95,7 @@ static void __init atstk1003_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -120,25 +131,7 @@ static int __init atstk1003_init(void)
- 	 * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
- 	 * SDRAM-specific pins so that nobody messes with them.
- 	 */
--	at32_reserve_pin(GPIO_PIN_PE(0));	/* DATA[16]	*/
--	at32_reserve_pin(GPIO_PIN_PE(1));	/* DATA[17]	*/
--	at32_reserve_pin(GPIO_PIN_PE(2));	/* DATA[18]	*/
--	at32_reserve_pin(GPIO_PIN_PE(3));	/* DATA[19]	*/
--	at32_reserve_pin(GPIO_PIN_PE(4));	/* DATA[20]	*/
--	at32_reserve_pin(GPIO_PIN_PE(5));	/* DATA[21]	*/
--	at32_reserve_pin(GPIO_PIN_PE(6));	/* DATA[22]	*/
--	at32_reserve_pin(GPIO_PIN_PE(7));	/* DATA[23]	*/
--	at32_reserve_pin(GPIO_PIN_PE(8));	/* DATA[24]	*/
--	at32_reserve_pin(GPIO_PIN_PE(9));	/* DATA[25]	*/
--	at32_reserve_pin(GPIO_PIN_PE(10));	/* DATA[26]	*/
--	at32_reserve_pin(GPIO_PIN_PE(11));	/* DATA[27]	*/
--	at32_reserve_pin(GPIO_PIN_PE(12));	/* DATA[28]	*/
--	at32_reserve_pin(GPIO_PIN_PE(13));	/* DATA[29]	*/
--	at32_reserve_pin(GPIO_PIN_PE(14));	/* DATA[30]	*/
--	at32_reserve_pin(GPIO_PIN_PE(15));	/* DATA[31]	*/
--	at32_reserve_pin(GPIO_PIN_PE(26));	/* SDCS		*/
--
--	at32_add_system_devices();
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
- 
- #ifdef	CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 	at32_add_device_usart(1);
-@@ -154,7 +147,7 @@ static int __init atstk1003_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, NULL);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-diff --git a/arch/avr32/boards/atstk1000/atstk1004.c b/arch/avr32/boards/atstk1000/atstk1004.c
-index 50a5273..cb32eb8 100644
---- a/arch/avr32/boards/atstk1000/atstk1004.c
-+++ b/arch/avr32/boards/atstk1000/atstk1004.c
-@@ -21,6 +21,7 @@
- #include <video/atmel_lcdc.h>
- 
- #include <asm/setup.h>
-+#include <asm/atmel-mci.h>
- 
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
-@@ -71,6 +72,16 @@ static struct spi_board_info spi1_board_info[] __initdata = { {
- } };
- #endif
- 
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= -ENODEV,
-+		.wp_pin		= -ENODEV,
-+	},
-+};
-+#endif
-+
- #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- static void __init atstk1004_setup_extdac(void)
- {
-@@ -89,7 +100,7 @@ static void __init atstk1004_setup_extdac(void)
- 		goto err_set_clk;
- 	}
- 
--	at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+	at32_select_periph(GPIO_PIOA_BASE, (1 << 30), GPIO_PERIPH_A, 0);
- 	at73c213_data.dac_clk = gclk;
- 
- err_set_clk:
-@@ -121,8 +132,6 @@ void __init setup_board(void)
- 
- static int __init atstk1004_init(void)
- {
--	at32_add_system_devices();
--
- #ifdef	CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- 	at32_add_device_usart(1);
- #else
-@@ -137,10 +146,11 @@ static int __init atstk1004_init(void)
- 	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
- #endif
- #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
--	at32_add_device_mci(0, NULL);
-+	at32_add_device_mci(0, &mci0_data);
- #endif
- 	at32_add_device_lcdc(0, &atstk1000_lcdc_data,
--			     fbmem_start, fbmem_size, 0);
-+			     fbmem_start, fbmem_size,
-+			     ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL);
- 	at32_add_device_usba(0, NULL);
- #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
- 	at32_add_device_ssc(0, ATMEL_SSC_TX);
-diff --git a/arch/avr32/boards/atstk1000/atstk1005.c b/arch/avr32/boards/atstk1000/atstk1005.c
-new file mode 100644
-index 0000000..f5a9baa
---- /dev/null
-+++ b/arch/avr32/boards/atstk1000/atstk1005.c
-@@ -0,0 +1,225 @@
-+/*
-+ * ATSTK1005 daughterboard-specific init code
-+ *
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/string.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/spi/spi.h>
-+
-+#include <asm/atmel-mci.h>
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/init.h>
-+#include <mach/portmux.h>
-+#include <mach/smc.h>
-+
-+#include "atstk1000.h"
-+
-+/* Oscillator frequencies. These are board specific */
-+unsigned long at32_board_osc_rates[4] = {
-+	[0] = 20000000,	/* 20 MHz on osc0 */
-+	[1] = 0,	/* Nothing on osc1 */
-+	[2] = 12000000,	/* 12 MHz on osc2 */
-+	[3] = 32768,	/* 32.768 kHz on RTC osc */
-+};
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+
-+static struct eth_addr __initdata hw_addr;
-+static struct eth_platform_data __initdata eth_data;
-+
-+static struct mci_platform_data mci_data __initdata = {
-+	.slot[0]	= {
-+		.detect_pin		= GPIO_PIN_NONE,
-+		.wp_pin			= GPIO_PIN_NONE,
-+		.bus_width		= 4,
-+	},
-+	.slot[1]	= {
-+		.detect_pin		= GPIO_PIN_PA(30),
-+		.wp_pin			= GPIO_PIN_PA(31),
-+		.bus_width		= 8,
-+	},
-+};
-+
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+	{
-+		/* AT45DB642D: 8MB DataFlash */
-+		.modalias	= "mtd_dataflash",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 0,
-+		.mode		= SPI_MODE_0,
-+	}, {
-+		/* QVGA display */
-+		.modalias	= "ltv350qv",
-+		.max_speed_hz	= 8000000,
-+		.chip_select	= 2,
-+		.mode		= SPI_MODE_3,
-+	},
-+};
-+
-+static struct smc_timing nand_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 10,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 10,
-+
-+	.ncs_read_pulse		= 30,
-+	.nrd_pulse		= 15,
-+	.ncs_write_pulse	= 30,
-+	.nwe_pulse		= 15,
-+
-+	.read_cycle		= 30,
-+	.write_cycle		= 30,
-+
-+	.ncs_read_recover	= 0,
-+	.nrd_recover		= 15,
-+	.ncs_write_recover	= 0,
-+	.nwe_recover		= 50,
-+};
-+
-+static struct smc_config nand_config __initdata = {
-+	.bus_width		= 1,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.nwait_mode		= 0,
-+	.byte_write		= 0,
-+	.tdf_cycles		= 3,
-+	.tdf_mode		= 0,
-+};
-+
-+static struct mtd_partition nand_partitions[] = {
-+	{
-+		.name	= "u-boot",
-+		.offset	= 0,
-+		.size	= 131072,
-+	}, {
-+		.name	= "kernel",
-+		.offset	= 262144,
-+		.size	= 2097152,
-+	}, {
-+		.name	= "user",
-+		.offset	= 2359296,
-+		.size	= MTDPART_SIZ_FULL,
-+	},
-+};
-+
-+/* Isn't this rather more complicated than necessary? */
-+static struct mtd_partition *nand_part_info(int size, int *num_partitions)
-+{
-+	*num_partitions = ARRAY_SIZE(nand_partitions);
-+	return nand_partitions;
-+}
-+
-+static struct atmel_nand_data nand_data __initdata = {
-+	.cle		= 21,
-+	.ale		= 22,
-+	.rdy_pin	= GPIO_PIN_PE(31),
-+	.enable_pin	= GPIO_PIN_PF(2),
-+	.det_pin	= GPIO_PIN_NONE,
-+	.partition_info	= nand_part_info,
-+};
-+
-+
-+/*
-+ * Grab ethernet address and PHY address provided by the boot loader.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	struct tag_ethernet *etag = &tag->u.ethernet;
-+
-+	if (etag->mac_index == 0) {
-+		eth_data.phy_mask = ~(1U << etag->mii_phy_addr);
-+		memcpy(&hw_addr.addr, etag->hw_address, sizeof(hw_addr.addr));
-+	}
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+/*
-+ * We need to get rid of this crap and pass the mac address to the
-+ * driver explicitly.
-+ */
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id != 0)
-+		return;
-+
-+	addr = hw_addr.addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(4, 0);	/* USART4: /dev/ttyS0, DB9 */
-+	at32_setup_serial_console(0);
-+}
-+
-+static int __init atstk1005_init(void)
-+{
-+	struct platform_device	*lcdc_pdev;
-+
-+	at32_add_device_usart(0);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data));
-+	lcdc_pdev = at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-+			fbmem_start, fbmem_size, 0);
-+	at32_add_device_mpop(0, lcdc_pdev, fbmem_start, fbmem_size);
-+	at32_add_device_mci(0, &mci_data);
-+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+
-+	/* NAND Flash */
-+	smc_set_timing(&nand_config, &nand_timing);
-+	smc_set_configuration(3, &nand_config);
-+	at32_add_device_nand(0, &nand_data);
-+
-+	/* USB OHCI/EHCI host */
-+	at32_add_device_ohci(0);
-+	at32_add_device_ehci(0);
-+
-+	return 0;
-+}
-+postcore_initcall(atstk1005_init);
-diff --git a/arch/avr32/boards/favr-32/Kconfig b/arch/avr32/boards/favr-32/Kconfig
-new file mode 100644
-index 0000000..2c83d1d
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/Kconfig
-@@ -0,0 +1,22 @@
-+# Favr-32 customization
-+
-+if BOARD_FAVR_32
-+
-+config BOARD_FAVR32_ABDAC_RATE
-+	int "DAC target rate"
-+	default 44100
-+	range 32000 50000
-+	help
-+	  Specify the target rate the internal DAC should try to match. This
-+	  will use PLL1 to generate a frequency as close as possible to this
-+	  rate.
-+
-+	  Must be within the range 32000 to 50000, which should be suitable to
-+	  generate most other frequencies in power of 2 steps.
-+
-+	  Ex:
-+		48000 will also suit 24000 and 12000
-+		44100 will also suit 22050 and 11025
-+		32000 will also suit 16000 and 8000
-+
-+endif # BOARD_FAVR_32
-diff --git a/arch/avr32/boards/favr-32/Makefile b/arch/avr32/boards/favr-32/Makefile
-new file mode 100644
-index 0000000..234f215
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/Makefile
-@@ -0,0 +1 @@
-+obj-y	+= setup.o flash.o
-diff --git a/arch/avr32/boards/favr-32/flash.c b/arch/avr32/boards/favr-32/flash.c
-new file mode 100644
-index 0000000..604bbd5
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/flash.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Favr-32 board-specific flash initialization
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <mach/smc.h>
-+
-+static struct smc_timing flash_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 40,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 10,
-+
-+	.ncs_read_pulse		= 80,
-+	.nrd_pulse		= 40,
-+	.ncs_write_pulse	= 65,
-+	.nwe_pulse		= 55,
-+
-+	.read_cycle		= 120,
-+	.write_cycle		= 120,
-+};
-+
-+static struct smc_config flash_config __initdata = {
-+	.bus_width		= 2,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.byte_write		= 1,
-+};
-+
-+static struct mtd_partition flash_parts[] = {
-+	{
-+		.name           = "u-boot",
-+		.offset         = 0x00000000,
-+		.size           = 0x00020000,           /* 128 KiB */
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+	{
-+		.name           = "root",
-+		.offset         = 0x00020000,
-+		.size           = 0x007d0000,
-+	},
-+	{
-+		.name           = "env",
-+		.offset         = 0x007f0000,
-+		.size           = 0x00010000,
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_data = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts),
-+	.parts		= flash_parts,
-+};
-+
-+static struct resource flash_resource = {
-+	.start		= 0x00000000,
-+	.end		= 0x007fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device = {
-+	.name		= "physmap-flash",
-+	.id		= 0,
-+	.resource	= &flash_resource,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_data,
-+	},
-+};
-+
-+/* This needs to be called after the SMC has been initialized */
-+static int __init favr32_flash_init(void)
-+{
-+	int ret;
-+
-+	smc_set_timing(&flash_config, &flash_timing);
-+	ret = smc_set_configuration(0, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "Favr-32: failed to set NOR flash timing\n");
-+		return ret;
-+	}
-+
-+	platform_device_register(&flash_device);
-+
-+	return 0;
-+}
-+device_initcall(favr32_flash_init);
-diff --git a/arch/avr32/boards/favr-32/setup.c b/arch/avr32/boards/favr-32/setup.c
-new file mode 100644
-index 0000000..1a12930
---- /dev/null
-+++ b/arch/avr32/boards/favr-32/setup.c
-@@ -0,0 +1,334 @@
-+/*
-+ * Favr-32 board-specific setup code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/bootmem.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/types.h>
-+#include <linux/linkage.h>
-+#include <linux/gpio.h>
-+#include <linux/leds.h>
-+#include <linux/atmel-pwm-bl.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/ads7846.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/init.h>
-+#include <mach/board.h>
-+#include <mach/portmux.h>
-+
-+/* Oscillator frequencies. These are board-specific */
-+unsigned long at32_board_osc_rates[3] = {
-+	[0] = 32768,	/* 32.768 kHz on RTC osc */
-+	[1] = 20000000,	/* 20 MHz on osc0 */
-+	[2] = 12000000,	/* 12 MHz on osc1 */
-+};
-+
-+/* Initialized by bootloader-specific startup code. */
-+struct tag *bootloader_tags __initdata;
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+static struct eth_addr __initdata hw_addr[1];
-+static struct eth_platform_data __initdata eth_data[1] = {
-+	{
-+		.phy_mask	= ~(1U << 1),
-+	},
-+};
-+
-+static int ads7843_get_pendown_state(void)
-+{
-+	return !gpio_get_value(GPIO_PIN_PB(3));
-+}
-+
-+static struct ads7846_platform_data ads7843_data = {
-+	.model			= 7843,
-+	.get_pendown_state	= ads7843_get_pendown_state,
-+	.pressure_max		= 255,
-+	/*
-+	 * Values below are for debounce filtering, these can be experimented
-+	 * with further.
-+	 */
-+	.debounce_max		= 20,
-+	.debounce_rep		= 4,
-+	.debounce_tol		= 5,
-+};
-+
-+static struct spi_board_info __initdata spi1_board_info[] = {
-+	{
-+		/* ADS7843 touch controller */
-+		.modalias	= "ads7846",
-+		.max_speed_hz	= 2000000,
-+		.chip_select	= 0,
-+		.bus_num	= 1,
-+		.platform_data	= &ads7843_data,
-+	},
-+};
-+
-+static struct fb_videomode __initdata lb104v03_modes[] = {
-+	{
-+		.name		= "640x480 @ 50",
-+		.refresh	= 50,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(25100),
-+
-+		.left_margin	= 90,		.right_margin	= 70,
-+		.upper_margin	= 30,		.lower_margin	= 15,
-+		.hsync_len	= 12,		.vsync_len	= 2,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata favr32_default_monspecs = {
-+	.manufacturer		= "LG",
-+	.monitor		= "LB104V03",
-+	.modedb			= lb104v03_modes,
-+	.modedb_len		= ARRAY_SIZE(lb104v03_modes),
-+	.hfmin			= 27273,
-+	.hfmax			= 31111,
-+	.vfmin			= 45,
-+	.vfmax			= 60,
-+	.dclkmax		= 28000000,
-+};
-+
-+struct atmel_lcdfb_info __initdata favr32_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &favr32_default_monspecs,
-+	.guard_time		= 2,
-+};
-+
-+static struct gpio_led favr32_leds[] = {
-+	{
-+		.name		 = "green",
-+		.gpio		 = GPIO_PIN_PE(19),
-+		.default_trigger = "heartbeat",
-+		.active_low	 = 1,
-+	},
-+	{
-+		.name		 = "red",
-+		.gpio		 = GPIO_PIN_PE(20),
-+		.active_low	 = 1,
-+	},
-+};
-+
-+static struct gpio_led_platform_data favr32_led_data = {
-+	.num_leds	= ARRAY_SIZE(favr32_leds),
-+	.leds		= favr32_leds,
-+};
-+
-+static struct platform_device favr32_led_dev = {
-+	.name		= "leds-gpio",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data	= &favr32_led_data,
-+	},
-+};
-+
-+/*
-+ * The next two functions should go away as the boot loader is
-+ * supposed to initialize the macb address registers with a valid
-+ * ethernet address. But we need to keep it around for a while until
-+ * we can be reasonably sure the boot loader does this.
-+ *
-+ * The phy_id is ignored as the driver will probe for it.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	int i;
-+
-+	i = tag->u.ethernet.mac_index;
-+	if (i < ARRAY_SIZE(hw_addr))
-+		memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
-+		       sizeof(hw_addr[i].addr));
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id >= ARRAY_SIZE(hw_addr))
-+		return;
-+
-+	addr = hw_addr[pdev->id].addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init favr32_setup_leds(void)
-+{
-+	unsigned i;
-+
-+	for (i = 0; i < ARRAY_SIZE(favr32_leds); i++)
-+		at32_select_gpio(favr32_leds[i].gpio, AT32_GPIOF_OUTPUT);
-+
-+	platform_device_register(&favr32_led_dev);
-+}
-+
-+static struct atmel_pwm_bl_platform_data atmel_pwm_bl_pdata = {
-+	.pwm_channel		= 2,
-+	.pwm_frequency		= 200000,
-+	.pwm_compare_max	= 345,
-+	.pwm_duty_max		= 345,
-+	.pwm_duty_min		= 90,
-+	.pwm_active_low		= 1,
-+	.gpio_on		= GPIO_PIN_PA(28),
-+	.on_active_low		= 0,
-+};
-+
-+static struct platform_device atmel_pwm_bl_dev = {
-+	.name		= "atmel-pwm-bl",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data = &atmel_pwm_bl_pdata,
-+	},
-+};
-+
-+static void __init favr32_setup_atmel_pwm_bl(void)
-+{
-+	platform_device_register(&atmel_pwm_bl_dev);
-+	at32_select_gpio(atmel_pwm_bl_pdata.gpio_on, 0);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(3, 0);	/* USART 3 => /dev/ttyS0 */
-+	at32_setup_serial_console(0);
-+}
-+
-+static int __init set_abdac_rate(struct platform_device *pdev)
-+{
-+	int retval;
-+	struct clk *osc1;
-+	struct clk *pll1;
-+	struct clk *abdac;
-+
-+	if (pdev == NULL)
-+		return -ENXIO;
-+
-+	osc1 = clk_get(NULL, "osc1");
-+	if (IS_ERR(osc1)) {
-+		retval = PTR_ERR(osc1);
-+		goto out;
-+	}
-+
-+	pll1 = clk_get(NULL, "pll1");
-+	if (IS_ERR(pll1)) {
-+		retval = PTR_ERR(pll1);
-+		goto out_osc1;
-+	}
-+
-+	abdac = clk_get(&pdev->dev, "sample_clk");
-+	if (IS_ERR(abdac)) {
-+		retval = PTR_ERR(abdac);
-+		goto out_pll1;
-+	}
-+
-+	retval = clk_set_parent(pll1, osc1);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+	/*
-+	 * Rate is 32000 to 50000 and ABDAC oversamples 256x. Multiply, in
-+	 * power of 2, to a value above 80 MHz. Power of 2 so it is possible
-+	 * for the generic clock to divide it down again and 80 MHz is the
-+	 * lowest frequency for the PLL.
-+	 */
-+	retval = clk_round_rate(pll1,
-+			CONFIG_BOARD_FAVR32_ABDAC_RATE * 256 * 16);
-+	if (retval < 0)
-+		goto out_abdac;
-+
-+	retval = clk_set_rate(pll1, retval);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+	retval = clk_set_parent(abdac, pll1);
-+	if (retval != 0)
-+		goto out_abdac;
-+
-+out_abdac:
-+	clk_put(abdac);
-+out_pll1:
-+	clk_put(pll1);
-+out_osc1:
-+	clk_put(osc1);
-+out:
-+	return retval;
-+}
-+
-+static int __init favr32_init(void)
-+{
-+	/*
-+	 * Favr-32 uses 32-bit SDRAM interface. Reserve the SDRAM-specific
-+	 * pins so that nobody messes with them.
-+	 */
-+	at32_reserve_pin(GPIO_PIOE_BASE, ATMEL_EBI_PE_DATA_ALL);
-+
-+	at32_select_gpio(GPIO_PIN_PB(3), 0);	/* IRQ from ADS7843 */
-+
-+	at32_add_device_usart(0);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-+
-+	spi1_board_info[0].irq = gpio_to_irq(GPIO_PIN_PB(3));
-+
-+	set_abdac_rate(at32_add_device_abdac(0));
-+
-+	at32_add_device_pwm(1 << atmel_pwm_bl_pdata.pwm_channel);
-+	at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
-+	at32_add_device_mci(0, NULL);
-+	at32_add_device_usba(0, NULL);
-+	at32_add_device_lcdc(0, &favr32_lcdc_data, fbmem_start, fbmem_size, 0);
-+
-+	favr32_setup_leds();
-+
-+	favr32_setup_atmel_pwm_bl();
-+
-+	return 0;
-+}
-+postcore_initcall(favr32_init);
-diff --git a/arch/avr32/boards/mimc200/Makefile b/arch/avr32/boards/mimc200/Makefile
-new file mode 100644
-index 0000000..79c076e
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/Makefile
-@@ -0,0 +1 @@
-+obj-y				+= setup.o flash.o fram.o
-diff --git a/arch/avr32/boards/mimc200/flash.c b/arch/avr32/boards/mimc200/flash.c
-new file mode 100644
-index 0000000..d83d650
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/flash.c
-@@ -0,0 +1,143 @@
-+/*
-+ * MIMC200 board-specific flash initialization
-+ *
-+ * Copyright (C) 2008 Mercury IMC Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include <mach/smc.h>
-+
-+static struct smc_timing flash_timing __initdata = {
-+	.ncs_read_setup		= 0,
-+	.nrd_setup		= 15,
-+	.ncs_write_setup	= 0,
-+	.nwe_setup		= 0,
-+
-+	.ncs_read_pulse		= 115,
-+	.nrd_pulse		= 110,
-+	.ncs_write_pulse	= 60,
-+	.nwe_pulse		= 60,
-+
-+	.read_cycle		= 115,
-+	.write_cycle		= 100,
-+};
-+
-+static struct smc_config flash_config __initdata = {
-+	.bus_width		= 2,
-+	.nrd_controlled		= 1,
-+	.nwe_controlled		= 1,
-+	.byte_write		= 1,
-+};
-+
-+/* system flash definition */
-+
-+static struct mtd_partition flash_parts_system[] = {
-+	{
-+		.name           = "u-boot",
-+		.offset         = 0x00000000,
-+		.size           = 0x00020000,           /* 128 KiB */
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+	{
-+		.name           = "root",
-+		.offset         = 0x00020000,
-+		.size           = 0x007c0000,
-+	},
-+	{
-+		.name		= "splash",
-+		.offset		= 0x007e0000,
-+		.size		= 0x00010000,		/* 64KiB */
-+	},
-+	{
-+		.name           = "env",
-+		.offset         = 0x007f0000,
-+		.size           = 0x00010000,
-+		.mask_flags     = MTD_WRITEABLE,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_system = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts_system),
-+	.parts		= flash_parts_system,
-+};
-+
-+static struct resource flash_resource_system = {
-+	.start		= 0x00000000,
-+	.end		= 0x007fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device_system = {
-+	.name		= "physmap-flash",
-+	.id		= 0,
-+	.resource	= &flash_resource_system,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_system,
-+	},
-+};
-+
-+/* data flash definition */
-+
-+static struct mtd_partition flash_parts_data[] = {
-+	{
-+		.name		= "data",
-+		.offset		= 0x00000000,
-+		.size		= 0x00800000,
-+	},
-+};
-+
-+static struct physmap_flash_data flash_data = {
-+	.width		= 2,
-+	.nr_parts	= ARRAY_SIZE(flash_parts_data),
-+	.parts		= flash_parts_data,
-+};
-+
-+static struct resource flash_resource_data = {
-+	.start		= 0x08000000,
-+	.end		= 0x087fffff,
-+	.flags		= IORESOURCE_MEM,
-+};
-+
-+static struct platform_device flash_device_data = {
-+	.name		= "physmap-flash",
-+	.id		= 1,
-+	.resource	= &flash_resource_data,
-+	.num_resources	= 1,
-+	.dev		= {
-+		.platform_data = &flash_data,
-+	},
-+};
-+
-+/* This needs to be called after the SMC has been initialized */
-+static int __init mimc200_flash_init(void)
-+{
-+	int ret;
-+
-+	smc_set_timing(&flash_config, &flash_timing);
-+	ret = smc_set_configuration(0, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "mimc200: failed to set 'System' NOR flash timing\n");
-+		return ret;
-+	}
-+	ret = smc_set_configuration(1, &flash_config);
-+	if (ret < 0) {
-+		printk(KERN_ERR "mimc200: failed to set 'Data' NOR flash timing\n");
-+		return ret;
-+	}
-+
-+	platform_device_register(&flash_device_system);
-+	platform_device_register(&flash_device_data);
-+
-+	return 0;
-+}
-+device_initcall(mimc200_flash_init);
-diff --git a/arch/avr32/boards/mimc200/fram.c b/arch/avr32/boards/mimc200/fram.c
-new file mode 100644
-index 0000000..54fbd95
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/fram.c
-@@ -0,0 +1,80 @@
-+/*
-+ * FRAM driver for MIMC200 board
-+ *
-+ * Copyright 2008 Mark Jackson <mpfj at mimc.co.uk>
-+ *
-+ * This module adds *very* simply support for the system's FRAM device.
-+ * At the moment, this is hard-coded to the MIMC200 platform, and only
-+ * supports mmap().
-+ */
-+
-+#define FRAM_VERSION	"1.0"
-+
-+#include <linux/miscdevice.h>
-+#include <linux/proc_fs.h>
-+#include <linux/mm.h>
-+#include <linux/io.h>
-+
-+#define FRAM_BASE	0xac000000
-+#define FRAM_SIZE	0x20000
-+
-+/*
-+ * The are the file operation function for user access to /dev/fram
-+ */
-+
-+static int fram_mmap(struct file *filp, struct vm_area_struct *vma)
-+{
-+	int ret;
-+
-+	ret = remap_pfn_range(vma,
-+		vma->vm_start,
-+		virt_to_phys((void *)((unsigned long)FRAM_BASE)) >> PAGE_SHIFT,
-+		vma->vm_end-vma->vm_start,
-+		PAGE_SHARED);
-+
-+	if (ret != 0)
-+		return -EAGAIN;
-+
-+	return 0;
-+}
-+
-+static const struct file_operations fram_fops = {
-+	.owner			= THIS_MODULE,
-+	.mmap			= fram_mmap,
-+};
-+
-+#define FRAM_MINOR	0
-+
-+static struct miscdevice fram_dev = {
-+	FRAM_MINOR,
-+	"fram",
-+	&fram_fops
-+};
-+
-+static int __init
-+fram_init(void)
-+{
-+	int ret;
-+
-+	ret = misc_register(&fram_dev);
-+	if (ret) {
-+		printk(KERN_ERR "fram: can't misc_register on minor=%d\n",
-+		    FRAM_MINOR);
-+		return ret;
-+	}
-+	printk(KERN_INFO "FRAM memory driver v" FRAM_VERSION "\n");
-+	return 0;
-+}
-+
-+static void __exit
-+fram_cleanup_module(void)
-+{
-+	misc_deregister(&fram_dev);
-+}
-+
-+module_init(fram_init);
-+module_exit(fram_cleanup_module);
-+
-+MODULE_LICENSE("GPL");
-+
-+MODULE_ALIAS_MISCDEV(FRAM_MINOR);
-diff --git a/arch/avr32/boards/mimc200/setup.c b/arch/avr32/boards/mimc200/setup.c
-new file mode 100644
-index 0000000..c060d4d
---- /dev/null
-+++ b/arch/avr32/boards/mimc200/setup.c
-@@ -0,0 +1,235 @@
-+/*
-+ * Board-specific setup code for the MIMC200
-+ *
-+ * Copyright (C) 2008 Mercury IMC Ltd
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+extern struct atmel_lcdfb_info mimc200_lcdc_data;
-+
-+#include <linux/clk.h>
-+#include <linux/etherdevice.h>
-+#include <linux/i2c-gpio.h>
-+#include <linux/init.h>
-+#include <linux/linkage.h>
-+#include <linux/platform_device.h>
-+#include <linux/types.h>
-+#include <linux/leds.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/eeprom.h>
-+
-+#include <video/atmel_lcdc.h>
-+#include <linux/fb.h>
-+
-+#include <asm/atmel-mci.h>
-+#include <linux/io.h>
-+#include <asm/setup.h>
-+
-+#include <mach/at32ap700x.h>
-+#include <mach/board.h>
-+#include <mach/init.h>
-+#include <mach/portmux.h>
-+
-+/* Oscillator frequencies. These are board-specific */
-+unsigned long at32_board_osc_rates[3] = {
-+	[0] = 32768,	/* 32.768 kHz on RTC osc */
-+	[1] = 10000000,	/* 10 MHz on osc0 */
-+	[2] = 12000000,	/* 12 MHz on osc1 */
-+};
-+
-+/* Initialized by bootloader-specific startup code. */
-+struct tag *bootloader_tags __initdata;
-+
-+static struct fb_videomode __initdata tx14d14_modes[] = {
-+	{
-+		.name		= "640x480 @ 60",
-+		.refresh	= 60,
-+		.xres		= 640,		.yres		= 480,
-+		.pixclock	= KHZ2PICOS(11666),
-+
-+		.left_margin	= 80,		.right_margin	= 1,
-+		.upper_margin	= 13,		.lower_margin	= 2,
-+		.hsync_len	= 64,		.vsync_len	= 1,
-+
-+		.sync		= 0,
-+		.vmode		= FB_VMODE_NONINTERLACED,
-+	},
-+};
-+
-+static struct fb_monspecs __initdata mimc200_default_monspecs = {
-+	.manufacturer		= "HIT",
-+	.monitor		= "TX14D14VM1BAB",
-+	.modedb			= tx14d14_modes,
-+	.modedb_len		= ARRAY_SIZE(tx14d14_modes),
-+	.hfmin			= 14820,
-+	.hfmax			= 22230,
-+	.vfmin			= 60,
-+	.vfmax			= 73.3,
-+	.dclkmax		= 25200000,
-+};
-+
-+struct atmel_lcdfb_info __initdata mimc200_lcdc_data = {
-+	.default_bpp		= 16,
-+	.default_dmacon		= ATMEL_LCDC_DMAEN | ATMEL_LCDC_DMA2DEN,
-+	.default_lcdcon2	= (ATMEL_LCDC_DISTYPE_TFT
-+				   | ATMEL_LCDC_INVCLK
-+				   | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE
-+				   | ATMEL_LCDC_MEMOR_BIG),
-+	.default_monspecs	= &mimc200_default_monspecs,
-+	.guard_time		= 2,
-+};
-+
-+struct eth_addr {
-+	u8 addr[6];
-+};
-+static struct eth_addr __initdata hw_addr[2];
-+static struct eth_platform_data __initdata eth_data[2];
-+
-+static struct spi_eeprom eeprom_25lc010 = {
-+		.name = "25lc010",
-+		.byte_len = 128,
-+		.page_size = 16,
-+		.flags = EE_ADDR1,
-+};
-+
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+	{
-+		.modalias	= "rtc-ds1390",
-+		.max_speed_hz	= 4000000,
-+		.chip_select	= 2,
-+	},
-+	{
-+		.modalias	= "at25",
-+		.max_speed_hz	= 1000000,
-+		.chip_select	= 1,
-+		.mode		= SPI_MODE_3,
-+		.platform_data	= &eeprom_25lc010,
-+	},
-+};
-+
-+static struct mci_platform_data __initdata mci0_data = {
-+	.slot[0] = {
-+		.bus_width	= 4,
-+		.detect_pin	= GPIO_PIN_PA(26),
-+		.wp_pin		= GPIO_PIN_PA(27),
-+	},
-+};
-+
-+/*
-+ * The next two functions should go away as the boot loader is
-+ * supposed to initialize the macb address registers with a valid
-+ * ethernet address. But we need to keep it around for a while until
-+ * we can be reasonably sure the boot loader does this.
-+ *
-+ * The phy_id is ignored as the driver will probe for it.
-+ */
-+static int __init parse_tag_ethernet(struct tag *tag)
-+{
-+	int i;
-+
-+	i = tag->u.ethernet.mac_index;
-+	if (i < ARRAY_SIZE(hw_addr))
-+		memcpy(hw_addr[i].addr, tag->u.ethernet.hw_address,
-+		       sizeof(hw_addr[i].addr));
-+
-+	return 0;
-+}
-+__tagtable(ATAG_ETHERNET, parse_tag_ethernet);
-+
-+static void __init set_hw_addr(struct platform_device *pdev)
-+{
-+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	const u8 *addr;
-+	void __iomem *regs;
-+	struct clk *pclk;
-+
-+	if (!res)
-+		return;
-+	if (pdev->id >= ARRAY_SIZE(hw_addr))
-+		return;
-+
-+	addr = hw_addr[pdev->id].addr;
-+	if (!is_valid_ether_addr(addr))
-+		return;
-+
-+	/*
-+	 * Since this is board-specific code, we'll cheat and use the
-+	 * physical address directly as we happen to know that it's
-+	 * the same as the virtual address.
-+	 */
-+	regs = (void __iomem __force *)res->start;
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk)
-+		return;
-+
-+	clk_enable(pclk);
-+	__raw_writel((addr[3] << 24) | (addr[2] << 16)
-+		     | (addr[1] << 8) | addr[0], regs + 0x98);
-+	__raw_writel((addr[5] << 8) | addr[4], regs + 0x9c);
-+	clk_disable(pclk);
-+	clk_put(pclk);
-+}
-+
-+void __init setup_board(void)
-+{
-+	at32_map_usart(0, 0);	/* USART 0: /dev/ttyS0 (TTL --> Altera) */
-+	at32_map_usart(1, 1);	/* USART 1: /dev/ttyS1 (RS232) */
-+	at32_map_usart(2, 2);	/* USART 2: /dev/ttyS2 (RS485) */
-+	at32_map_usart(3, 3);	/* USART 3: /dev/ttyS3 (RS422 Multidrop) */
-+}
-+
-+static struct i2c_gpio_platform_data i2c_gpio_data = {
-+	.sda_pin		= GPIO_PIN_PA(6),
-+	.scl_pin		= GPIO_PIN_PA(7),
-+	.sda_is_open_drain	= 1,
-+	.scl_is_open_drain	= 1,
-+	.udelay			= 2,	/* close to 100 kHz */
-+};
-+
-+static struct platform_device i2c_gpio_device = {
-+	.name		= "i2c-gpio",
-+	.id		= 0,
-+	.dev		= {
-+	.platform_data	= &i2c_gpio_data,
-+	},
-+};
-+
-+static struct i2c_board_info __initdata i2c_info[] = {
-+};
-+
-+static int __init mimc200_init(void)
-+{
-+	/*
-+	 * MIMC200 uses 16-bit SDRAM interface, so we don't need to
-+	 * reserve any pins for it.
-+	 */
-+
-+	at32_add_device_usart(0);
-+	at32_add_device_usart(1);
-+	at32_add_device_usart(2);
-+	at32_add_device_usart(3);
-+
-+	set_hw_addr(at32_add_device_eth(0, &eth_data[0]));
-+	set_hw_addr(at32_add_device_eth(1, &eth_data[1]));
-+
-+	at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+	at32_add_device_mci(0, &mci0_data);
-+	at32_add_device_usba(0, NULL);
-+
-+	at32_select_periph(GPIO_PIOB_BASE, 1 << 28, 0, AT32_GPIOF_PULLUP);
-+	at32_select_gpio(i2c_gpio_data.sda_pin,
-+		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	at32_select_gpio(i2c_gpio_data.scl_pin,
-+		AT32_GPIOF_MULTIDRV | AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	platform_device_register(&i2c_gpio_device);
-+	i2c_register_board_info(0, i2c_info, ARRAY_SIZE(i2c_info));
-+
-+	at32_add_device_lcdc(0, &mimc200_lcdc_data,
-+			     fbmem_start, fbmem_size, 1);
-+
-+	return 0;
-+}
-+postcore_initcall(mimc200_init);
-diff --git a/arch/avr32/configs/atngw100_defconfig b/arch/avr32/configs/atngw100_defconfig
-index 5415209..58fe9f3 100644
---- a/arch/avr32/configs/atngw100_defconfig
-+++ b/arch/avr32/configs/atngw100_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 16:00:47 2008
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -130,11 +130,15 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- # CONFIG_BOARD_ATSTK1000 is not set
- CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X is not set
- CONFIG_LOADER_U_BOOT=y
- 
- #
-@@ -177,7 +181,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -615,6 +619,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -664,6 +669,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -706,7 +712,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -720,6 +726,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -751,11 +758,14 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_DISPLAY_SUPPORT is not set
- # CONFIG_SOUND is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -806,6 +816,7 @@ CONFIG_MMC_TEST=m
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -880,11 +891,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -898,13 +911,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
- # CONFIG_FS_POSIX_ACL is not set
-@@ -944,7 +957,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-diff --git a/arch/avr32/configs/atngw100_evklcd100_defconfig b/arch/avr32/configs/atngw100_evklcd100_defconfig
-new file mode 100644
-index 0000000..24f57fa
---- /dev/null
-+++ b/arch/avr32/configs/atngw100_evklcd100_defconfig
-@@ -0,0 +1,1323 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:10:50 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
-+CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA is not set
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IP_VS is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+# CONFIG_NETFILTER_ADVANCED is not set
-+
-+#
-+# Core Netfilter Configuration
-+#
-+CONFIG_NETFILTER_NETLINK=m
-+CONFIG_NETFILTER_NETLINK_LOG=m
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XTABLES=y
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_TARGET_LOG=m
-+# CONFIG_IP_NF_TARGET_ULOG is not set
-+CONFIG_NF_NAT=m
-+CONFIG_NF_NAT_NEEDED=y
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_NF_NAT_FTP=m
-+CONFIG_NF_NAT_IRC=m
-+# CONFIG_NF_NAT_TFTP is not set
-+# CONFIG_NF_NAT_AMANDA is not set
-+# CONFIG_NF_NAT_PPTP is not set
-+# CONFIG_NF_NAT_H323 is not set
-+CONFIG_NF_NAT_SIP=m
-+CONFIG_IP_NF_MANGLE=m
-+
-+#
-+# IPv6: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_LOG=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+# CONFIG_VLAN_8021Q_GVRP is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_SPI=y
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+# CONFIG_DMADEVICES is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+CONFIG_SMB_FS=m
-+# CONFIG_SMB_NLS_DEFAULT is not set
-+CONFIG_CIFS=m
-+# CONFIG_CIFS_STATS is not set
-+# CONFIG_CIFS_WEAK_PW_HASH is not set
-+# CONFIG_CIFS_XATTR is not set
-+# CONFIG_CIFS_DEBUG2 is not set
-+# CONFIG_CIFS_EXPERIMENTAL is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=m
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atngw100_evklcd101_defconfig b/arch/avr32/configs/atngw100_evklcd101_defconfig
-new file mode 100644
-index 0000000..253b4b9
---- /dev/null
-+++ b/arch/avr32/configs/atngw100_evklcd101_defconfig
-@@ -0,0 +1,1323 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Thu Nov 13 14:11:19 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+CONFIG_MODULE_FORCE_UNLOAD=y
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+CONFIG_BOARD_ATNGW100=y
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_QVGA is not set
-+CONFIG_BOARD_ATNGW100_EVKLCD10X_VGA=y
-+# CONFIG_BOARD_ATNGW100_EVKLCD10X_POW_QVGA is not set
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IP_VS is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+CONFIG_NETFILTER=y
-+# CONFIG_NETFILTER_DEBUG is not set
-+# CONFIG_NETFILTER_ADVANCED is not set
-+
-+#
-+# Core Netfilter Configuration
-+#
-+CONFIG_NETFILTER_NETLINK=m
-+CONFIG_NETFILTER_NETLINK_LOG=m
-+CONFIG_NF_CONNTRACK=m
-+CONFIG_NF_CONNTRACK_FTP=m
-+CONFIG_NF_CONNTRACK_IRC=m
-+CONFIG_NF_CONNTRACK_SIP=m
-+CONFIG_NF_CT_NETLINK=m
-+CONFIG_NETFILTER_XTABLES=y
-+CONFIG_NETFILTER_XT_TARGET_MARK=m
-+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-+CONFIG_NETFILTER_XT_MATCH_MARK=m
-+CONFIG_NETFILTER_XT_MATCH_POLICY=m
-+CONFIG_NETFILTER_XT_MATCH_STATE=m
-+
-+#
-+# IP: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV4=m
-+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-+CONFIG_IP_NF_IPTABLES=m
-+CONFIG_IP_NF_FILTER=m
-+CONFIG_IP_NF_TARGET_REJECT=m
-+CONFIG_IP_NF_TARGET_LOG=m
-+# CONFIG_IP_NF_TARGET_ULOG is not set
-+CONFIG_NF_NAT=m
-+CONFIG_NF_NAT_NEEDED=y
-+CONFIG_IP_NF_TARGET_MASQUERADE=m
-+CONFIG_NF_NAT_FTP=m
-+CONFIG_NF_NAT_IRC=m
-+# CONFIG_NF_NAT_TFTP is not set
-+# CONFIG_NF_NAT_AMANDA is not set
-+# CONFIG_NF_NAT_PPTP is not set
-+# CONFIG_NF_NAT_H323 is not set
-+CONFIG_NF_NAT_SIP=m
-+CONFIG_IP_NF_MANGLE=m
-+
-+#
-+# IPv6: Netfilter Configuration
-+#
-+CONFIG_NF_CONNTRACK_IPV6=m
-+CONFIG_IP6_NF_IPTABLES=m
-+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-+CONFIG_IP6_NF_FILTER=m
-+CONFIG_IP6_NF_TARGET_LOG=m
-+CONFIG_IP6_NF_TARGET_REJECT=m
-+CONFIG_IP6_NF_MANGLE=m
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+CONFIG_VLAN_8021Q=m
-+# CONFIG_VLAN_8021Q_GVRP is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+CONFIG_PPP_FILTER=y
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+CONFIG_PPP_MPPE=m
-+CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+# CONFIG_INPUT_POLLDEV is not set
-+
-+#
-+# Userland interfaces
-+#
-+# CONFIG_INPUT_MOUSEDEV is not set
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+# CONFIG_INPUT_KEYBOARD is not set
-+# CONFIG_INPUT_MOUSE is not set
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+# CONFIG_TOUCHSCREEN_ADS7846 is not set
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+# CONFIG_GPIO_SYSFS is not set
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=y
-+CONFIG_SND=y
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+CONFIG_SND_DRIVERS=y
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+CONFIG_SND_SPI=y
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+# CONFIG_DMADEVICES is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+# CONFIG_UBIFS_FS_XATTR is not set
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+CONFIG_SMB_FS=m
-+# CONFIG_SMB_NLS_DEFAULT is not set
-+CONFIG_CIFS=m
-+# CONFIG_CIFS_STATS is not set
-+# CONFIG_CIFS_WEAK_PW_HASH is not set
-+# CONFIG_CIFS_XATTR is not set
-+# CONFIG_CIFS_DEBUG2 is not set
-+# CONFIG_CIFS_EXPERIMENTAL is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=m
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=m
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=m
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1002_defconfig b/arch/avr32/configs/atstk1002_defconfig
-index 69fce6b..42829bb 100644
---- a/arch/avr32/configs/atstk1002_defconfig
-+++ b/arch/avr32/configs/atstk1002_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Mon Aug  4 16:02:27 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:28:45 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -129,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- CONFIG_BOARD_ATSTK1002=y
- # CONFIG_BOARD_ATSTK1003 is not set
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -186,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -360,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -421,12 +426,23 @@ CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_DOC2001 is not set
- # CONFIG_MTD_DOC2001PLUS is not set
- # CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
- # CONFIG_MTD_ONENAND is not set
- 
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -502,7 +518,7 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -561,7 +577,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -590,6 +606,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -606,8 +624,12 @@ CONFIG_MOUSE_GPIO=m
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -634,6 +656,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -663,7 +686,7 @@ CONFIG_I2C_GPIO=m
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -683,6 +706,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -725,7 +749,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -739,6 +763,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -784,6 +809,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -797,6 +823,12 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SND=m
-@@ -820,11 +852,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -876,6 +911,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -952,11 +988,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -1017,7 +1055,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -1031,7 +1069,8 @@ CONFIG_TMPFS=y
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -1039,6 +1078,12 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
- CONFIG_MINIX_FS=m
-@@ -1173,7 +1218,7 @@ CONFIG_CRYPTO=y
- #
- # Crypto core or helper
- #
--CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_ALGAPI=y
- CONFIG_CRYPTO_AEAD=m
- CONFIG_CRYPTO_BLKCIPHER=m
- CONFIG_CRYPTO_HASH=m
-@@ -1247,8 +1292,8 @@ CONFIG_CRYPTO_DES=m
- #
- # Compression
- #
--CONFIG_CRYPTO_DEFLATE=m
--# CONFIG_CRYPTO_LZO is not set
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
- # CONFIG_CRYPTO_HW is not set
- 
- #
-@@ -1258,7 +1303,7 @@ CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
-@@ -1266,6 +1311,8 @@ CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff --git a/arch/avr32/configs/atstk1003_defconfig b/arch/avr32/configs/atstk1003_defconfig
-index 5477ed3..9eb129b 100644
---- a/arch/avr32/configs/atstk1003_defconfig
-+++ b/arch/avr32/configs/atstk1003_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:34:44 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:33:33 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -34,12 +34,9 @@ CONFIG_SWAP=y
- CONFIG_SYSVIPC=y
- CONFIG_SYSVIPC_SYSCTL=y
- CONFIG_POSIX_MQUEUE=y
--CONFIG_BSD_PROCESS_ACCT=y
--CONFIG_BSD_PROCESS_ACCT_V3=y
--CONFIG_TASKSTATS=y
--CONFIG_TASK_DELAY_ACCT=y
--# CONFIG_TASK_XACCT is not set
--CONFIG_AUDIT=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
- # CONFIG_IKCONFIG is not set
- CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_CGROUPS is not set
-@@ -71,7 +68,7 @@ CONFIG_TIMERFD=y
- CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
--# CONFIG_SLUB_DEBUG is not set
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
- CONFIG_SLUB=y
- # CONFIG_SLOB is not set
-@@ -90,6 +87,7 @@ CONFIG_HAVE_KPROBES=y
- CONFIG_HAVE_CLK=y
- CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
- CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
-@@ -131,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7001=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- CONFIG_BOARD_ATSTK1003=y
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -188,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -239,40 +241,71 @@ CONFIG_NET=y
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -331,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -397,7 +431,15 @@ CONFIG_M25PXX_USE_FAST_READ=y
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
- CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
-@@ -458,9 +500,7 @@ CONFIG_SCSI_WAIT_SCAN=m
- # CONFIG_SCSI_ISCSI_ATTRS is not set
- # CONFIG_SCSI_SAS_LIBSAS is not set
- # CONFIG_SCSI_SRP_ATTRS is not set
--CONFIG_SCSI_LOWLEVEL=y
--# CONFIG_ISCSI_TCP is not set
--# CONFIG_SCSI_DEBUG is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
- # CONFIG_SCSI_DH is not set
- CONFIG_ATA=m
- # CONFIG_ATA_NONSTANDARD is not set
-@@ -477,7 +517,32 @@ CONFIG_NETDEVICES=y
- # CONFIG_EQUALIZER is not set
- # CONFIG_TUN is not set
- # CONFIG_VETH is not set
--# CONFIG_NET_ETHERNET is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
- # CONFIG_NETDEV_1000 is not set
- # CONFIG_NETDEV_10000 is not set
- 
-@@ -509,7 +574,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -521,7 +586,7 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
- CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
- CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
- # CONFIG_INPUT_JOYDEV is not set
--# CONFIG_INPUT_EVDEV is not set
-+CONFIG_INPUT_EVDEV=m
- # CONFIG_INPUT_EVBUG is not set
- 
- #
-@@ -538,6 +603,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -555,7 +622,7 @@ CONFIG_MOUSE_GPIO=m
- # Character devices
- #
- # CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -582,6 +649,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -611,7 +679,7 @@ CONFIG_I2C_GPIO=m
- # Miscellaneous I2C Chip support
- #
- # CONFIG_DS1682 is not set
--CONFIG_AT24=m
-+# CONFIG_AT24 is not set
- # CONFIG_SENSORS_EEPROM is not set
- # CONFIG_SENSORS_PCF8574 is not set
- # CONFIG_PCF8575 is not set
-@@ -631,6 +699,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -673,7 +742,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -687,6 +756,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -726,8 +796,8 @@ CONFIG_SND_MIXER_OSS=m
- CONFIG_SND_PCM_OSS=m
- CONFIG_SND_PCM_OSS_PLUGINS=y
- # CONFIG_SND_DYNAMIC_MINORS is not set
--CONFIG_SND_SUPPORT_OLD_API=y
--CONFIG_SND_VERBOSE_PROCFS=y
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
- # CONFIG_SND_DRIVERS is not set
-@@ -738,11 +808,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -750,7 +823,7 @@ CONFIG_USB_SUPPORT=y
- CONFIG_USB_GADGET=y
- # CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
--CONFIG_USB_GADGET_DEBUG_FS=y
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -787,33 +860,34 @@ CONFIG_MMC=y
- CONFIG_MMC_BLOCK=y
- CONFIG_MMC_BLOCK_BOUNCE=y
- # CONFIG_SDIO_UART is not set
--CONFIG_MMC_TEST=m
-+# CONFIG_MMC_TEST is not set
- 
- #
- # MMC/SD Host Controller Drivers
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
--CONFIG_LEDS_CLASS=y
-+CONFIG_LEDS_CLASS=m
- 
- #
- # LED drivers
- #
- CONFIG_LEDS_ATMEL_PWM=m
- # CONFIG_LEDS_PCA9532 is not set
--CONFIG_LEDS_GPIO=y
-+CONFIG_LEDS_GPIO=m
- # CONFIG_LEDS_PCA955X is not set
- 
- #
- # LED Triggers
- #
- CONFIG_LEDS_TRIGGERS=y
--CONFIG_LEDS_TRIGGER_TIMER=y
--CONFIG_LEDS_TRIGGER_HEARTBEAT=y
--CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -870,11 +944,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -888,13 +964,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -935,7 +1011,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--CONFIG_CONFIGFS_FS=m
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -958,16 +1034,39 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
- # CONFIG_CRAMFS is not set
- # CONFIG_VXFS_FS is not set
--# CONFIG_MINIX_FS is not set
-+CONFIG_MINIX_FS=m
- # CONFIG_OMFS_FS is not set
- # CONFIG_HPFS_FS is not set
- # CONFIG_QNX4FS_FS is not set
- # CONFIG_ROMFS_FS is not set
- # CONFIG_SYSV_FS is not set
- # CONFIG_UFS_FS is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
- 
- #
- # Partition Types
-@@ -1036,6 +1135,8 @@ CONFIG_SCHED_DEBUG=y
- # CONFIG_SCHEDSTATS is not set
- # CONFIG_TIMER_STATS is not set
- # CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
- # CONFIG_DEBUG_RT_MUTEXES is not set
- # CONFIG_RT_MUTEX_TESTER is not set
- # CONFIG_DEBUG_SPINLOCK is not set
-@@ -1068,7 +1169,88 @@ CONFIG_FRAME_POINTER=y
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -1077,15 +1259,16 @@ CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
- CONFIG_CRC_CCITT=m
--# CONFIG_CRC16 is not set
-+CONFIG_CRC16=y
- CONFIG_CRC_T10DIF=m
- CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
- CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
--CONFIG_AUDIT_GENERIC=y
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
- CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
-diff --git a/arch/avr32/configs/atstk1004_defconfig b/arch/avr32/configs/atstk1004_defconfig
-index 69e6c0d..9f76e2a 100644
---- a/arch/avr32/configs/atstk1004_defconfig
-+++ b/arch/avr32/configs/atstk1004_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:38:56 2008
-+# Linux kernel version: 2.6.27.4
-+# Wed Nov 12 10:35:14 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -30,8 +30,10 @@ CONFIG_BROKEN_ON_SMP=y
- CONFIG_INIT_ENV_ARG_LIMIT=32
- CONFIG_LOCALVERSION=""
- # CONFIG_LOCALVERSION_AUTO is not set
--# CONFIG_SYSVIPC is not set
--# CONFIG_POSIX_MQUEUE is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
- # CONFIG_BSD_PROCESS_ACCT is not set
- # CONFIG_TASKSTATS is not set
- # CONFIG_AUDIT is not set
-@@ -41,14 +43,16 @@ CONFIG_LOG_BUF_SHIFT=14
- # CONFIG_GROUP_SCHED is not set
- CONFIG_SYSFS_DEPRECATED=y
- CONFIG_SYSFS_DEPRECATED_V2=y
--# CONFIG_RELAY is not set
-+CONFIG_RELAY=y
- # CONFIG_NAMESPACES is not set
--# CONFIG_BLK_DEV_INITRD is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
- CONFIG_CC_OPTIMIZE_FOR_SIZE=y
- CONFIG_SYSCTL=y
- CONFIG_EMBEDDED=y
- # CONFIG_SYSCTL_SYSCALL is not set
- CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
- # CONFIG_KALLSYMS_EXTRA_PASS is not set
- CONFIG_HOTPLUG=y
- CONFIG_PRINTK=y
-@@ -56,19 +60,23 @@ CONFIG_BUG=y
- CONFIG_ELF_CORE=y
- # CONFIG_COMPAT_BRK is not set
- # CONFIG_BASE_FULL is not set
--# CONFIG_FUTEX is not set
--# CONFIG_EPOLL is not set
--# CONFIG_SIGNALFD is not set
--# CONFIG_TIMERFD is not set
--# CONFIG_EVENTFD is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
- CONFIG_SHMEM=y
- CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
- # CONFIG_SLAB is not set
--# CONFIG_SLUB is not set
--CONFIG_SLOB=y
--# CONFIG_PROFILING is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
- # CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
- CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
- # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
- # CONFIG_HAVE_IOREMAP_PROT is not set
- CONFIG_HAVE_KPROBES=y
-@@ -77,36 +85,68 @@ CONFIG_HAVE_KPROBES=y
- # CONFIG_HAVE_DMA_ATTRS is not set
- # CONFIG_USE_GENERIC_SMP_HELPERS is not set
- CONFIG_HAVE_CLK=y
--# CONFIG_PROC_PAGE_MONITOR is not set
-+CONFIG_PROC_PAGE_MONITOR=y
- # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
- # CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
--# CONFIG_MODULES is not set
--# CONFIG_BLOCK is not set
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
- CONFIG_CLASSIC_RCU=y
- 
- #
- # System Type and features
- #
--# CONFIG_TICK_ONESHOT is not set
--# CONFIG_NO_HZ is not set
--# CONFIG_HIGH_RES_TIMERS is not set
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
- CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7002=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- # CONFIG_BOARD_ATSTK1003 is not set
- CONFIG_BOARD_ATSTK1004=y
-+# CONFIG_BOARD_ATSTK1005 is not set
- # CONFIG_BOARD_ATSTK1006 is not set
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -144,25 +184,43 @@ CONFIG_ZONE_DMA_FLAG=0
- CONFIG_NR_QUICK=2
- CONFIG_VIRT_TO_BUS=y
- # CONFIG_OWNERSHIP_TRACE is not set
--# CONFIG_NMI_DEBUGGING is not set
-+CONFIG_NMI_DEBUGGING=y
- # CONFIG_HZ_100 is not set
- CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
- # Power management options
- #
--# CONFIG_PM is not set
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
- CONFIG_ARCH_SUSPEND_POSSIBLE=y
- 
- #
- # CPU Frequency scaling
- #
--# CONFIG_CPU_FREQ is not set
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
- 
- #
- # Bus options
-@@ -183,40 +241,71 @@ CONFIG_NET=y
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
- CONFIG_IP_FIB_HASH=y
--# CONFIG_IP_PNP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
- # CONFIG_INET_LRO is not set
--# CONFIG_INET_DIAG is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -230,6 +319,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
- # Network testing
- #
- # CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
- # CONFIG_HAMRADIO is not set
- # CONFIG_CAN is not set
- # CONFIG_IRDA is not set
-@@ -257,6 +347,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
- CONFIG_STANDALONE=y
- # CONFIG_PREVENT_FIRMWARE_BUILD is not set
- # CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
- # CONFIG_SYS_HYPERVISOR is not set
- # CONFIG_CONNECTOR is not set
- CONFIG_MTD=y
-@@ -271,6 +363,14 @@ CONFIG_MTD_CMDLINE_PARTS=y
- # User Modules And Translation Layers
- #
- CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
- # CONFIG_MTD_OOPS is not set
- 
- #
-@@ -311,11 +411,13 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # Self-contained MTD device drivers
- #
--# CONFIG_MTD_DATAFLASH is not set
--# CONFIG_MTD_M25P80 is not set
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_SLRAM is not set
- # CONFIG_MTD_PHRAM is not set
- # CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
- 
- #
- # Disk-On-Chip Device Drivers
-@@ -329,24 +431,186 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # UBI - Unsorted block images
- #
--# CONFIG_MTD_UBI is not set
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
- # CONFIG_PARPORT is not set
--# CONFIG_MISC_DEVICES is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
- # CONFIG_HAVE_IDE is not set
- 
- #
- # SCSI device support
- #
--# CONFIG_SCSI_DMA is not set
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
- # CONFIG_SCSI_NETLINK is not set
--# CONFIG_NETDEVICES is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
- # CONFIG_ISDN is not set
- # CONFIG_PHONE is not set
- 
- #
- # Input device support
- #
--# CONFIG_INPUT is not set
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
- 
- #
- # Hardware I/O ports
-@@ -357,8 +621,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -371,7 +639,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
- #
- CONFIG_SERIAL_ATMEL=y
- CONFIG_SERIAL_ATMEL_CONSOLE=y
--# CONFIG_SERIAL_ATMEL_PDC is not set
-+CONFIG_SERIAL_ATMEL_PDC=y
- # CONFIG_SERIAL_ATMEL_TTYAT is not set
- CONFIG_SERIAL_CORE=y
- CONFIG_SERIAL_CORE_CONSOLE=y
-@@ -380,14 +648,62 @@ CONFIG_UNIX98_PTYS=y
- # CONFIG_IPMI_HANDLER is not set
- # CONFIG_HW_RANDOM is not set
- # CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
- # CONFIG_TCG_TPM is not set
--# CONFIG_I2C is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
- CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
- CONFIG_SPI_MASTER=y
- 
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -395,15 +711,19 @@ CONFIG_SPI_ATMEL=y
- # SPI Protocol Masters
- #
- # CONFIG_SPI_AT25 is not set
--# CONFIG_SPI_SPIDEV is not set
-+CONFIG_SPI_SPIDEV=m
- # CONFIG_SPI_TLE62X0 is not set
- CONFIG_ARCH_REQUIRE_GPIOLIB=y
- CONFIG_GPIOLIB=y
--# CONFIG_GPIO_SYSFS is not set
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
- 
- #
- # I2C GPIO expanders:
- #
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
- 
- #
- # PCI GPIO expanders:
-@@ -426,7 +746,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -440,6 +760,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -485,6 +806,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -498,20 +820,51 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
--# CONFIG_SOUND is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+# CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
- #
- CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
- # CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
- CONFIG_USB_GADGET_SELECTED=y
- # CONFIG_USB_GADGET_AMD5536UDC is not set
- CONFIG_USB_GADGET_ATMEL_USBA=y
-@@ -528,18 +881,54 @@ CONFIG_USB_ATMEL_USBA=y
- # CONFIG_USB_GADGET_AT91 is not set
- # CONFIG_USB_GADGET_DUMMY_HCD is not set
- CONFIG_USB_GADGET_DUALSPEED=y
--# CONFIG_USB_ZERO is not set
--CONFIG_USB_ETH=y
--# CONFIG_USB_ETH_RNDIS is not set
--# CONFIG_USB_GADGETFS is not set
--# CONFIG_USB_FILE_STORAGE is not set
--# CONFIG_USB_G_SERIAL is not set
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
--# CONFIG_MMC is not set
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
--# CONFIG_NEW_LEDS is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
- # CONFIG_ACCESSIBILITY is not set
- CONFIG_RTC_LIB=y
- CONFIG_RTC_CLASS=y
-@@ -551,12 +940,28 @@ CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
- # RTC interfaces
- #
- CONFIG_RTC_INTF_SYSFS=y
--# CONFIG_RTC_INTF_PROC is not set
-+CONFIG_RTC_INTF_PROC=y
- CONFIG_RTC_INTF_DEV=y
- # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
- # CONFIG_RTC_DRV_TEST is not set
- 
- #
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
- # SPI RTC drivers
- #
- # CONFIG_RTC_DRV_M41T94 is not set
-@@ -580,18 +985,62 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
--# CONFIG_DMADEVICES is not set
-+# CONFIG_RTC_DRV_AVR32_AST is not set
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+# CONFIG_ATMEL_PDCA is not set
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
- # CONFIG_UIO is not set
- 
- #
- # File systems
- #
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
- # CONFIG_DNOTIFY is not set
--# CONFIG_INOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
- # CONFIG_QUOTA is not set
- # CONFIG_AUTOFS_FS is not set
- # CONFIG_AUTOFS4_FS is not set
--# CONFIG_FUSE_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
- 
- #
- # Pseudo filesystems
-@@ -603,14 +1052,22 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
- #
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-@@ -618,8 +1075,85 @@ CONFIG_JFFS2_ZLIB=y
- # CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
- # CONFIG_JFFS2_RUBIN is not set
--# CONFIG_NETWORK_FILESYSTEMS is not set
--# CONFIG_NLS is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
- # CONFIG_DLM is not set
- 
- #
-@@ -631,11 +1165,43 @@ CONFIG_ENABLE_MUST_CHECK=y
- CONFIG_FRAME_WARN=1024
- CONFIG_MAGIC_SYSRQ=y
- # CONFIG_UNUSED_SYMBOLS is not set
--# CONFIG_DEBUG_FS is not set
-+CONFIG_DEBUG_FS=y
- # CONFIG_HEADERS_CHECK is not set
--# CONFIG_DEBUG_KERNEL is not set
--# CONFIG_DEBUG_BUGVERBOSE is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
- # CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
- # CONFIG_SAMPLES is not set
- 
- #
-@@ -644,7 +1210,88 @@ CONFIG_MAGIC_SYSRQ=y
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
- # CONFIG_SECURITY_FILE_CAPABILITIES is not set
--# CONFIG_CRYPTO is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
- 
- #
- # Library routines
-@@ -652,16 +1299,19 @@ CONFIG_MAGIC_SYSRQ=y
- CONFIG_BITREVERSE=y
- # CONFIG_GENERIC_FIND_FIRST_BIT is not set
- # CONFIG_GENERIC_FIND_NEXT_BIT is not set
--# CONFIG_CRC_CCITT is not set
--# CONFIG_CRC16 is not set
--# CONFIG_CRC_T10DIF is not set
--# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+CONFIG_CRC_T10DIF=m
-+CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
--# CONFIG_CRC7 is not set
-+CONFIG_CRC7=m
- # CONFIG_LIBCRC32C is not set
- CONFIG_ZLIB_INFLATE=y
- CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
- CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
- CONFIG_HAS_IOMEM=y
- CONFIG_HAS_IOPORT=y
- CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1005_defconfig b/arch/avr32/configs/atstk1005_defconfig
-new file mode 100644
-index 0000000..e36b73d
---- /dev/null
-+++ b/arch/avr32/configs/atstk1005_defconfig
-@@ -0,0 +1,1505 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27.4
-+# Fri Nov  7 10:22:27 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+CONFIG_RELAY=y
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_GPIO_V2=y
-+CONFIG_TIMER_AST=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP720X=y
-+CONFIG_CPU_AT32AP7200=y
-+CONFIG_BOARD_ATSTK1000=y
-+# CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
-+# CONFIG_BOARD_ATSTK1002 is not set
-+# CONFIG_BOARD_ATSTK1003 is not set
-+# CONFIG_BOARD_ATSTK1004 is not set
-+CONFIG_BOARD_ATSTK1005=y
-+# CONFIG_BOARD_ATSTK1006 is not set
-+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
-+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
-+CONFIG_BOARD_ATSTK1000_EXTDAC=y
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
-+CONFIG_M25PXX_USE_FAST_READ=y
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+CONFIG_MTD_NAND=y
-+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
-+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-+CONFIG_MTD_NAND_IDS=y
-+# CONFIG_MTD_NAND_DISKONCHIP is not set
-+CONFIG_MTD_NAND_ATMEL=y
-+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
-+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
-+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
-+# CONFIG_MTD_NAND_NANDSIM is not set
-+# CONFIG_MTD_NAND_PLATFORM is not set
-+# CONFIG_MTD_ALAUDA is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+CONFIG_MTD_UBI=y
-+CONFIG_MTD_UBI_WL_THRESHOLD=4096
-+CONFIG_MTD_UBI_BEB_RESERVE=1
-+# CONFIG_MTD_UBI_GLUEBI is not set
-+
-+#
-+# UBI debugging options
-+#
-+# CONFIG_MTD_UBI_DEBUG is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+# CONFIG_BLK_DEV_UB is not set
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+# CONFIG_ATMEL_TCLIB is not set
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_SCSI_PROC_FS is not set
-+
-+#
-+# SCSI support type (disk, tape, CD-ROM)
-+#
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-+
-+#
-+# SCSI Transports
-+#
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+# CONFIG_SCSI_DH is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+# CONFIG_SATA_PMP is not set
-+CONFIG_ATA_SFF=y
-+# CONFIG_SATA_MV is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+CONFIG_MII=m
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+
-+#
-+# USB Network Adapters
-+#
-+CONFIG_USB_CATC=m
-+# CONFIG_USB_KAWETH is not set
-+# CONFIG_USB_PEGASUS is not set
-+# CONFIG_USB_RTL8150 is not set
-+CONFIG_USB_USBNET=m
-+# CONFIG_USB_NET_AX8817X is not set
-+CONFIG_USB_NET_CDCETHER=m
-+# CONFIG_USB_NET_DM9601 is not set
-+# CONFIG_USB_NET_GL620A is not set
-+# CONFIG_USB_NET_NET1080 is not set
-+# CONFIG_USB_NET_PLUSB is not set
-+# CONFIG_USB_NET_MCS7830 is not set
-+# CONFIG_USB_NET_RNDIS_HOST is not set
-+CONFIG_USB_NET_CDC_SUBSET=m
-+# CONFIG_USB_ALI_M5632 is not set
-+# CONFIG_USB_AN2720 is not set
-+CONFIG_USB_BELKIN=y
-+CONFIG_USB_ARMLINUX=y
-+# CONFIG_USB_EPSON2888 is not set
-+# CONFIG_USB_KC2190 is not set
-+# CONFIG_USB_NET_ZAURUS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+CONFIG_I2C_TINY_USB=m
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32_WDT=y
-+
-+#
-+# USB-based Watchdog Cards
-+#
-+# CONFIG_USBPCWATCHDOG is not set
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_LCD_LTV350QV=y
-+# CONFIG_LCD_ILI9320 is not set
-+# CONFIG_LCD_VGG2432A4 is not set
-+# CONFIG_LCD_PLATFORM is not set
-+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=m
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+CONFIG_SND_HWDEP=m
-+CONFIG_SND_RAWMIDI=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+# CONFIG_SND_DRIVERS is not set
-+CONFIG_SND_SPI=y
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+CONFIG_SND_USB=y
-+CONFIG_SND_USB_AUDIO=m
-+# CONFIG_SND_USB_CAIAQ is not set
-+# CONFIG_SND_SOC is not set
-+# CONFIG_SOUND_PRIME is not set
-+CONFIG_HID_SUPPORT=y
-+CONFIG_HID=y
-+# CONFIG_HID_DEBUG is not set
-+# CONFIG_HIDRAW is not set
-+
-+#
-+# USB Input Devices
-+#
-+CONFIG_USB_HID=y
-+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-+# CONFIG_HID_FF is not set
-+# CONFIG_USB_HIDDEV is not set
-+CONFIG_USB_SUPPORT=y
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+CONFIG_USB=y
-+# CONFIG_USB_DEBUG is not set
-+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-+
-+#
-+# Miscellaneous USB options
-+#
-+CONFIG_USB_DEVICEFS=y
-+# CONFIG_USB_DEVICE_CLASS is not set
-+CONFIG_USB_DYNAMIC_MINORS=y
-+CONFIG_USB_SUSPEND=y
-+# CONFIG_USB_OTG is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+CONFIG_USB_MON=y
-+
-+#
-+# USB Host Controller Drivers
-+#
-+# CONFIG_USB_C67X00_HCD is not set
-+CONFIG_USB_EHCI_HCD=y
-+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
-+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-+# CONFIG_USB_ISP116X_HCD is not set
-+# CONFIG_USB_ISP1760_HCD is not set
-+CONFIG_USB_OHCI_HCD=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y
-+CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
-+# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set
-+# CONFIG_USB_SL811_HCD is not set
-+# CONFIG_USB_R8A66597_HCD is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# USB Device Class drivers
-+#
-+CONFIG_USB_ACM=m
-+CONFIG_USB_PRINTER=m
-+CONFIG_USB_WDM=m
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+
-+#
-+# may also be needed; see USB_STORAGE Help for more information
-+#
-+CONFIG_USB_STORAGE=m
-+# CONFIG_USB_STORAGE_DEBUG is not set
-+# CONFIG_USB_STORAGE_DATAFAB is not set
-+# CONFIG_USB_STORAGE_FREECOM is not set
-+# CONFIG_USB_STORAGE_ISD200 is not set
-+# CONFIG_USB_STORAGE_DPCM is not set
-+# CONFIG_USB_STORAGE_USBAT is not set
-+# CONFIG_USB_STORAGE_SDDR09 is not set
-+# CONFIG_USB_STORAGE_SDDR55 is not set
-+# CONFIG_USB_STORAGE_JUMPSHOT is not set
-+# CONFIG_USB_STORAGE_ALAUDA is not set
-+# CONFIG_USB_STORAGE_ONETOUCH is not set
-+# CONFIG_USB_STORAGE_KARMA is not set
-+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-+# CONFIG_USB_LIBUSUAL is not set
-+
-+#
-+# USB Imaging devices
-+#
-+# CONFIG_USB_MDC800 is not set
-+# CONFIG_USB_MICROTEK is not set
-+
-+#
-+# USB port drivers
-+#
-+CONFIG_USB_SERIAL=m
-+# CONFIG_USB_EZUSB is not set
-+CONFIG_USB_SERIAL_GENERIC=y
-+# CONFIG_USB_SERIAL_AIRCABLE is not set
-+# CONFIG_USB_SERIAL_ARK3116 is not set
-+# CONFIG_USB_SERIAL_BELKIN is not set
-+# CONFIG_USB_SERIAL_CH341 is not set
-+# CONFIG_USB_SERIAL_WHITEHEAT is not set
-+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-+# CONFIG_USB_SERIAL_CP2101 is not set
-+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-+# CONFIG_USB_SERIAL_EMPEG is not set
-+# CONFIG_USB_SERIAL_FTDI_SIO is not set
-+# CONFIG_USB_SERIAL_FUNSOFT is not set
-+# CONFIG_USB_SERIAL_VISOR is not set
-+# CONFIG_USB_SERIAL_IPAQ is not set
-+# CONFIG_USB_SERIAL_IR is not set
-+# CONFIG_USB_SERIAL_EDGEPORT is not set
-+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-+# CONFIG_USB_SERIAL_GARMIN is not set
-+# CONFIG_USB_SERIAL_IPW is not set
-+# CONFIG_USB_SERIAL_IUU is not set
-+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-+# CONFIG_USB_SERIAL_KEYSPAN is not set
-+# CONFIG_USB_SERIAL_KLSI is not set
-+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-+# CONFIG_USB_SERIAL_MCT_U232 is not set
-+# CONFIG_USB_SERIAL_MOS7720 is not set
-+# CONFIG_USB_SERIAL_MOS7840 is not set
-+# CONFIG_USB_SERIAL_MOTOROLA is not set
-+# CONFIG_USB_SERIAL_NAVMAN is not set
-+CONFIG_USB_SERIAL_PL2303=m
-+# CONFIG_USB_SERIAL_OTI6858 is not set
-+# CONFIG_USB_SERIAL_SPCP8X5 is not set
-+# CONFIG_USB_SERIAL_HP4X is not set
-+# CONFIG_USB_SERIAL_SAFE is not set
-+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-+# CONFIG_USB_SERIAL_TI is not set
-+# CONFIG_USB_SERIAL_CYBERJACK is not set
-+# CONFIG_USB_SERIAL_XIRCOM is not set
-+# CONFIG_USB_SERIAL_OPTION is not set
-+# CONFIG_USB_SERIAL_OMNINET is not set
-+# CONFIG_USB_SERIAL_DEBUG is not set
-+
-+#
-+# USB Miscellaneous drivers
-+#
-+# CONFIG_USB_EMI62 is not set
-+# CONFIG_USB_EMI26 is not set
-+# CONFIG_USB_ADUTUX is not set
-+# CONFIG_USB_RIO500 is not set
-+# CONFIG_USB_LEGOTOWER is not set
-+# CONFIG_USB_LCD is not set
-+# CONFIG_USB_BERRY_CHARGE is not set
-+# CONFIG_USB_LED is not set
-+# CONFIG_USB_CYPRESS_CY7C63 is not set
-+# CONFIG_USB_CYTHERM is not set
-+# CONFIG_USB_PHIDGET is not set
-+# CONFIG_USB_IDMOUSE is not set
-+# CONFIG_USB_FTDI_ELAN is not set
-+# CONFIG_USB_APPLEDISPLAY is not set
-+# CONFIG_USB_SISUSBVGA is not set
-+# CONFIG_USB_LD is not set
-+# CONFIG_USB_TRANCEVIBRATOR is not set
-+# CONFIG_USB_IOWARRIOR is not set
-+CONFIG_USB_TEST=m
-+# CONFIG_USB_ISIGHTFW is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+CONFIG_MMC_TEST=m
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=m
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=m
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_RTC_DRV_AT32AP700X is not set
-+CONFIG_RTC_DRV_AVR32_AST=y
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_ATMEL_PDCA=y
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+CONFIG_DMATEST=m
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+CONFIG_UBIFS_FS=y
-+CONFIG_UBIFS_FS_XATTR=y
-+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-+CONFIG_UBIFS_FS_LZO=y
-+CONFIG_UBIFS_FS_ZLIB=y
-+# CONFIG_UBIFS_FS_DEBUG is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+CONFIG_MINIX_FS=m
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+CONFIG_CRYPTO_LZO=y
-+# CONFIG_CRYPTO_HW is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+CONFIG_CRC16=y
-+# CONFIG_CRC_T10DIF is not set
-+CONFIG_CRC_ITU_T=m
-+CONFIG_CRC32=y
-+CONFIG_CRC7=m
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_LZO_COMPRESS=y
-+CONFIG_LZO_DECOMPRESS=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/atstk1006_defconfig b/arch/avr32/configs/atstk1006_defconfig
-index 8b6e54c..cee2884 100644
---- a/arch/avr32/configs/atstk1006_defconfig
-+++ b/arch/avr32/configs/atstk1006_defconfig
-@@ -1,7 +1,7 @@
- #
- # Automatically generated make config: don't edit
--# Linux kernel version: 2.6.27-rc1
--# Tue Aug  5 15:40:26 2008
-+# Linux kernel version: 2.6.27.4
-+# Fri Nov  7 10:25:15 2008
- #
- CONFIG_AVR32=y
- CONFIG_GENERIC_GPIO=y
-@@ -129,20 +129,24 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
- CONFIG_SUBARCH_AVR32B=y
- CONFIG_MMU=y
- CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PORTMUX_PIO=y
- CONFIG_PLATFORM_AT32AP=y
- CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_FAVR_32 is not set
-+# CONFIG_BOARD_MIMC200 is not set
- # CONFIG_BOARD_ATSTK1002 is not set
- # CONFIG_BOARD_ATSTK1003 is not set
- # CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK1005 is not set
- CONFIG_BOARD_ATSTK1006=y
- # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
- # CONFIG_BOARD_ATSTK100X_SPI1 is not set
--# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_J2_LED=y
- # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
--# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_J2_RGB=y
- CONFIG_BOARD_ATSTK1000_EXTDAC=y
- CONFIG_LOADER_U_BOOT=y
- 
-@@ -186,7 +190,7 @@ CONFIG_HZ_250=y
- # CONFIG_HZ_300 is not set
- # CONFIG_HZ_1000 is not set
- CONFIG_HZ=250
--# CONFIG_SCHED_HRTICK is not set
-+CONFIG_SCHED_HRTICK=y
- CONFIG_CMDLINE=""
- 
- #
-@@ -360,7 +364,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
- #
- CONFIG_MTD_CHAR=y
- CONFIG_MTD_BLKDEVS=y
--CONFIG_MTD_BLOCK=y
-+# CONFIG_MTD_BLOCK is not set
-+# CONFIG_MTD_BLOCK_RO is not set
- # CONFIG_FTL is not set
- # CONFIG_NFTL is not set
- # CONFIG_INFTL is not set
-@@ -422,7 +427,7 @@ CONFIG_M25PXX_USE_FAST_READ=y
- # CONFIG_MTD_DOC2001PLUS is not set
- CONFIG_MTD_NAND=y
- # CONFIG_MTD_NAND_VERIFY_WRITE is not set
--# CONFIG_MTD_NAND_ECC_SMC is not set
-+CONFIG_MTD_NAND_ECC_SMC=y
- # CONFIG_MTD_NAND_MUSEUM_IDS is not set
- CONFIG_MTD_NAND_IDS=y
- # CONFIG_MTD_NAND_DISKONCHIP is not set
-@@ -521,7 +526,7 @@ CONFIG_NETDEVICES=y
- # CONFIG_BONDING is not set
- # CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
--CONFIG_TUN=m
-+# CONFIG_TUN is not set
- # CONFIG_VETH is not set
- CONFIG_PHYLIB=y
- 
-@@ -580,7 +585,7 @@ CONFIG_SLHC=m
- #
- # Input device support
- #
--CONFIG_INPUT=m
-+CONFIG_INPUT=y
- # CONFIG_INPUT_FF_MEMLESS is not set
- CONFIG_INPUT_POLLDEV=m
- 
-@@ -609,6 +614,8 @@ CONFIG_KEYBOARD_GPIO=m
- CONFIG_INPUT_MOUSE=y
- # CONFIG_MOUSE_PS2 is not set
- # CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_APPLETOUCH is not set
-+# CONFIG_MOUSE_BCM5974 is not set
- # CONFIG_MOUSE_VSXXXAA is not set
- CONFIG_MOUSE_GPIO=m
- # CONFIG_INPUT_JOYSTICK is not set
-@@ -625,8 +632,12 @@ CONFIG_MOUSE_GPIO=m
- #
- # Character devices
- #
--# CONFIG_VT is not set
--# CONFIG_DEVKMEM is not set
-+CONFIG_VT=y
-+CONFIG_CONSOLE_TRANSLATIONS=y
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+CONFIG_DEVKMEM=y
- # CONFIG_SERIAL_NONSTANDARD is not set
- 
- #
-@@ -653,6 +664,7 @@ CONFIG_UNIX98_PTYS=y
- CONFIG_I2C=m
- CONFIG_I2C_BOARDINFO=y
- CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
- CONFIG_I2C_ALGOBIT=m
- 
- #
-@@ -702,6 +714,7 @@ CONFIG_SPI_MASTER=y
- #
- # SPI Master Controller Drivers
- #
-+CONFIG_SPI_ATMEL_HAVE_PDC=y
- CONFIG_SPI_ATMEL=y
- # CONFIG_SPI_BITBANG is not set
- 
-@@ -744,7 +757,7 @@ CONFIG_WATCHDOG=y
- # Watchdog Device Drivers
- #
- # CONFIG_SOFT_WATCHDOG is not set
--CONFIG_AT32AP700X_WDT=y
-+CONFIG_AT32_WDT=y
- 
- #
- # Sonics Silicon Backplane
-@@ -758,6 +771,7 @@ CONFIG_SSB_POSSIBLE=y
- # CONFIG_MFD_CORE is not set
- # CONFIG_MFD_SM501 is not set
- # CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
- 
- #
- # Multimedia devices
-@@ -803,6 +817,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y
- #
- # CONFIG_FB_S1D13XXX is not set
- CONFIG_FB_ATMEL=y
-+# CONFIG_FB_ATMEL_MPOP is not set
- # CONFIG_FB_VIRTUAL is not set
- CONFIG_BACKLIGHT_LCD_SUPPORT=y
- CONFIG_LCD_CLASS_DEVICE=y
-@@ -816,6 +831,12 @@ CONFIG_LCD_LTV350QV=y
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
- # CONFIG_LOGO is not set
- CONFIG_SOUND=m
- CONFIG_SND=m
-@@ -831,11 +852,7 @@ CONFIG_SND_PCM_OSS_PLUGINS=y
- # CONFIG_SND_VERBOSE_PROCFS is not set
- # CONFIG_SND_VERBOSE_PRINTK is not set
- # CONFIG_SND_DEBUG is not set
--CONFIG_SND_DRIVERS=y
--# CONFIG_SND_DUMMY is not set
--# CONFIG_SND_MTPAV is not set
--# CONFIG_SND_SERIAL_U16550 is not set
--# CONFIG_SND_MPU401 is not set
-+# CONFIG_SND_DRIVERS is not set
- CONFIG_SND_SPI=y
- CONFIG_SND_AT73C213=m
- CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-@@ -843,11 +860,14 @@ CONFIG_SND_AT73C213_TARGET_BITRATE=48000
- # CONFIG_SOUND_PRIME is not set
- # CONFIG_HID_SUPPORT is not set
- CONFIG_USB_SUPPORT=y
--# CONFIG_USB_ARCH_HAS_HCD is not set
--# CONFIG_USB_ARCH_HAS_OHCI is not set
--# CONFIG_USB_ARCH_HAS_EHCI is not set
-+CONFIG_USB_ARCH_HAS_HCD=y
-+CONFIG_USB_ARCH_HAS_OHCI=y
-+CONFIG_USB_ARCH_HAS_EHCI=y
-+# CONFIG_USB is not set
- # CONFIG_USB_OTG_WHITELIST is not set
- # CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
- 
- #
- # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-@@ -881,7 +901,7 @@ CONFIG_USB_FILE_STORAGE=m
- CONFIG_USB_G_SERIAL=m
- # CONFIG_USB_MIDI_GADGET is not set
- # CONFIG_USB_G_PRINTER is not set
--# CONFIG_USB_CDC_COMPOSITE is not set
-+CONFIG_USB_CDC_COMPOSITE=m
- CONFIG_MMC=y
- # CONFIG_MMC_DEBUG is not set
- # CONFIG_MMC_UNSAFE_RESUME is not set
-@@ -899,6 +919,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
- #
- # CONFIG_MMC_SDHCI is not set
- CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
- CONFIG_MMC_SPI=m
- # CONFIG_MEMSTICK is not set
- CONFIG_NEW_LEDS=y
-@@ -975,11 +996,13 @@ CONFIG_RTC_INTF_DEV=y
- # on-CPU RTC drivers
- #
- CONFIG_RTC_DRV_AT32AP700X=y
-+# CONFIG_RTC_DRV_AVR32_AST is not set
- CONFIG_DMADEVICES=y
- 
- #
- # DMA Devices
- #
-+# CONFIG_ATMEL_PDCA is not set
- CONFIG_DW_DMAC=y
- CONFIG_DMA_ENGINE=y
- 
-@@ -993,13 +1016,13 @@ CONFIG_DMATEST=m
- #
- # File systems
- #
--CONFIG_EXT2_FS=m
-+CONFIG_EXT2_FS=y
- # CONFIG_EXT2_FS_XATTR is not set
- # CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=m
-+CONFIG_EXT3_FS=y
- # CONFIG_EXT3_FS_XATTR is not set
- # CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=m
-+CONFIG_JBD=y
- # CONFIG_JBD_DEBUG is not set
- # CONFIG_REISERFS_FS is not set
- # CONFIG_JFS_FS is not set
-@@ -1040,7 +1063,7 @@ CONFIG_SYSFS=y
- CONFIG_TMPFS=y
- # CONFIG_TMPFS_POSIX_ACL is not set
- # CONFIG_HUGETLB_PAGE is not set
--# CONFIG_CONFIGFS_FS is not set
-+CONFIG_CONFIGFS_FS=y
- 
- #
- # Miscellaneous filesystems
-@@ -1054,7 +1077,8 @@ CONFIG_TMPFS=y
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-diff --git a/arch/avr32/configs/favr-32_defconfig b/arch/avr32/configs/favr-32_defconfig
-new file mode 100644
-index 0000000..e2bd998
---- /dev/null
-+++ b/arch/avr32/configs/favr-32_defconfig
-@@ -0,0 +1,1235 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27-rc8
-+# Tue Oct 14 13:20:41 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+CONFIG_RELAY=y
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+CONFIG_OPROFILE=m
-+CONFIG_HAVE_OPROFILE=y
-+CONFIG_KPROBES=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+CONFIG_MODULES=y
-+# CONFIG_MODULE_FORCE_LOAD is not set
-+CONFIG_MODULE_UNLOAD=y
-+# CONFIG_MODULE_FORCE_UNLOAD is not set
-+# CONFIG_MODVERSIONS is not set
-+# CONFIG_MODULE_SRCVERSION_ALL is not set
-+CONFIG_KMOD=y
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+# CONFIG_BOARD_ATNGW100 is not set
-+CONFIG_BOARD_FAVR_32=y
-+# CONFIG_BOARD_MIMC200 is not set
-+CONFIG_BOARD_FAVR32_ABDAC_RATE=44100
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=m
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+CONFIG_STP=m
-+CONFIG_BRIDGE=m
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+CONFIG_LLC=m
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+CONFIG_BLK_DEV_LOOP=m
-+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-+CONFIG_BLK_DEV_NBD=m
-+CONFIG_BLK_DEV_RAM=m
-+CONFIG_BLK_DEV_RAM_COUNT=16
-+CONFIG_BLK_DEV_RAM_SIZE=4096
-+# CONFIG_BLK_DEV_XIP is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+CONFIG_ATMEL_PWM=m
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+CONFIG_PPP=m
-+# CONFIG_PPP_MULTILINK is not set
-+# CONFIG_PPP_FILTER is not set
-+CONFIG_PPP_ASYNC=m
-+# CONFIG_PPP_SYNC_TTY is not set
-+CONFIG_PPP_DEFLATE=m
-+CONFIG_PPP_BSDCOMP=m
-+# CONFIG_PPP_MPPE is not set
-+# CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
-+# CONFIG_SLIP is not set
-+CONFIG_SLHC=m
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+CONFIG_INPUT=y
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+CONFIG_INPUT_TOUCHSCREEN=y
-+CONFIG_TOUCHSCREEN_ADS7846=m
-+# CONFIG_TOUCHSCREEN_FUJITSU is not set
-+# CONFIG_TOUCHSCREEN_GUNZE is not set
-+# CONFIG_TOUCHSCREEN_ELO is not set
-+# CONFIG_TOUCHSCREEN_MTOUCH is not set
-+# CONFIG_TOUCHSCREEN_INEXIO is not set
-+# CONFIG_TOUCHSCREEN_MK712 is not set
-+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-+# CONFIG_TOUCHSCREEN_UCB1400 is not set
-+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-+# CONFIG_INPUT_MISC is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+CONFIG_VT=y
-+# CONFIG_CONSOLE_TRANSLATIONS is not set
-+CONFIG_VT_CONSOLE=y
-+CONFIG_HW_CONSOLE=y
-+# CONFIG_VT_HW_CONSOLE_BINDING is not set
-+# CONFIG_DEVKMEM is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=m
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+# CONFIG_I2C_STUB is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+# CONFIG_AT24 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+# CONFIG_LCD_CLASS_DEVICE is not set
-+CONFIG_BACKLIGHT_CLASS_DEVICE=m
-+# CONFIG_BACKLIGHT_ATMEL_LCDC is not set
-+CONFIG_BACKLIGHT_ATMEL_PWM=m
-+# CONFIG_BACKLIGHT_CORGI is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Console display driver support
-+#
-+CONFIG_DUMMY_CONSOLE=y
-+# CONFIG_FRAMEBUFFER_CONSOLE is not set
-+# CONFIG_LOGO is not set
-+CONFIG_SOUND=m
-+# CONFIG_SND is not set
-+CONFIG_SOUND_PRIME=m
-+# CONFIG_HID_SUPPORT is not set
-+CONFIG_USB_SUPPORT=y
-+# CONFIG_USB_ARCH_HAS_HCD is not set
-+# CONFIG_USB_ARCH_HAS_OHCI is not set
-+# CONFIG_USB_ARCH_HAS_EHCI is not set
-+# CONFIG_USB_OTG_WHITELIST is not set
-+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-+# CONFIG_USB_MUSB_HDRC is not set
-+# CONFIG_USB_GADGET_MUSB_HDRC is not set
-+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA25X is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_PXA27X is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_USB_G_PRINTER is not set
-+CONFIG_USB_CDC_COMPOSITE=m
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+# CONFIG_MMC_TEST is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+CONFIG_MMC_ATMELMCI_DMA=y
-+# CONFIG_MMC_SPI is not set
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_ATMEL_PWM=m
-+# CONFIG_LEDS_PCA9532 is not set
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+CONFIG_FUSE_FS=m
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=m
-+CONFIG_MSDOS_FS=m
-+CONFIG_VFAT_FS=m
-+CONFIG_FAT_DEFAULT_CODEPAGE=437
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=m
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=m
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+# CONFIG_NLS_CODEPAGE_850 is not set
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=m
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=m
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+CONFIG_DEBUG_FS=y
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_KPROBES_SANITY_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_LKDTM is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_AEAD=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=m
-+# CONFIG_CRYPTO_TEST is not set
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+# CONFIG_CRYPTO_ECB is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_LZO is not set
-+# CONFIG_CRYPTO_HW is not set
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=m
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/configs/mimc200_defconfig b/arch/avr32/configs/mimc200_defconfig
-new file mode 100644
-index 0000000..981e4f8
---- /dev/null
-+++ b/arch/avr32/configs/mimc200_defconfig
-@@ -0,0 +1,1109 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.27-rc8
-+# Mon Oct 13 15:46:53 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+CONFIG_SWAP=y
-+CONFIG_SYSVIPC=y
-+CONFIG_SYSVIPC_SYSCTL=y
-+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+CONFIG_SYSFS_DEPRECATED_V2=y
-+# CONFIG_RELAY is not set
-+# CONFIG_NAMESPACES is not set
-+CONFIG_BLK_DEV_INITRD=y
-+CONFIG_INITRAMFS_SOURCE=""
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_ALL is not set
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_COMPAT_BRK is not set
-+# CONFIG_BASE_FULL is not set
-+CONFIG_FUTEX=y
-+CONFIG_ANON_INODES=y
-+CONFIG_EPOLL=y
-+CONFIG_SIGNALFD=y
-+CONFIG_TIMERFD=y
-+CONFIG_EVENTFD=y
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+CONFIG_SLUB_DEBUG=y
-+# CONFIG_SLAB is not set
-+CONFIG_SLUB=y
-+# CONFIG_SLOB is not set
-+CONFIG_PROFILING=y
-+# CONFIG_MARKERS is not set
-+# CONFIG_OPROFILE is not set
-+CONFIG_HAVE_OPROFILE=y
-+# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-+# CONFIG_HAVE_IOREMAP_PROT is not set
-+CONFIG_HAVE_KPROBES=y
-+# CONFIG_HAVE_KRETPROBES is not set
-+# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-+# CONFIG_HAVE_DMA_ATTRS is not set
-+# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-+CONFIG_HAVE_CLK=y
-+CONFIG_PROC_PAGE_MONITOR=y
-+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
-+CONFIG_SLABINFO=y
-+CONFIG_RT_MUTEXES=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+# CONFIG_MODULES is not set
-+CONFIG_BLOCK=y
-+# CONFIG_LBD is not set
-+# CONFIG_BLK_DEV_IO_TRACE is not set
-+# CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-+# CONFIG_BLK_DEV_INTEGRITY is not set
-+
-+#
-+# IO Schedulers
-+#
-+CONFIG_IOSCHED_NOOP=y
-+# CONFIG_IOSCHED_AS is not set
-+# CONFIG_IOSCHED_DEADLINE is not set
-+CONFIG_IOSCHED_CFQ=y
-+# CONFIG_DEFAULT_AS is not set
-+# CONFIG_DEFAULT_DEADLINE is not set
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
-+CONFIG_CLASSIC_RCU=y
-+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7000=y
-+# CONFIG_BOARD_ATSTK1000 is not set
-+# CONFIG_BOARD_ATNGW100 is not set
-+CONFIG_BOARD_MIMC200=y
-+CONFIG_LOADER_U_BOOT=y
-+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+CONFIG_QUICKLIST=y
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_PAGEFLAGS_EXTENDED=y
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_NR_QUICK=2
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+CONFIG_NMI_DEBUGGING=y
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_SCHED_HRTICK=y
-+CONFIG_CMDLINE=""
-+
-+#
-+# Power management options
-+#
-+CONFIG_PM=y
-+# CONFIG_PM_DEBUG is not set
-+CONFIG_PM_SLEEP=y
-+CONFIG_SUSPEND=y
-+CONFIG_SUSPEND_FREEZER=y
-+CONFIG_ARCH_SUSPEND_POSSIBLE=y
-+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
-+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
-+CONFIG_NET=y
-+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=y
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+# CONFIG_XFRM_STATISTICS is not set
-+CONFIG_XFRM_IPCOMP=y
-+CONFIG_NET_KEY=y
-+# CONFIG_NET_KEY_MIGRATE is not set
-+CONFIG_INET=y
-+CONFIG_IP_MULTICAST=y
-+CONFIG_IP_ADVANCED_ROUTER=y
-+CONFIG_ASK_IP_FIB_HASH=y
-+# CONFIG_IP_FIB_TRIE is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_MULTIPLE_TABLES is not set
-+# CONFIG_IP_ROUTE_MULTIPATH is not set
-+# CONFIG_IP_ROUTE_VERBOSE is not set
-+CONFIG_IP_PNP=y
-+CONFIG_IP_PNP_DHCP=y
-+# CONFIG_IP_PNP_BOOTP is not set
-+# CONFIG_IP_PNP_RARP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+CONFIG_IP_MROUTE=y
-+CONFIG_IP_PIMSM_V1=y
-+# CONFIG_IP_PIMSM_V2 is not set
-+# CONFIG_ARPD is not set
-+CONFIG_SYN_COOKIES=y
-+CONFIG_INET_AH=y
-+CONFIG_INET_ESP=y
-+CONFIG_INET_IPCOMP=y
-+CONFIG_INET_XFRM_TUNNEL=y
-+CONFIG_INET_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET_XFRM_MODE_TUNNEL=y
-+CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
-+CONFIG_INET_DIAG=y
-+CONFIG_INET_TCP_DIAG=y
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+CONFIG_IPV6=y
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=y
-+CONFIG_INET6_ESP=y
-+CONFIG_INET6_IPCOMP=y
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=y
-+CONFIG_INET6_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-+CONFIG_INET6_XFRM_MODE_TUNNEL=y
-+CONFIG_INET6_XFRM_MODE_BEET=y
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=y
-+CONFIG_IPV6_NDISC_NODETYPE=y
-+# CONFIG_IPV6_TUNNEL is not set
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
-+# CONFIG_IPV6_MROUTE is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
-+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_CAN is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
-+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-+
-+#
-+# Device Drivers
-+#
-+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_DEBUG_DRIVER is not set
-+# CONFIG_DEBUG_DEVRES is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
-+# CONFIG_MTD_AR7_PARTS is not set
-+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+CONFIG_MTD_BLKDEVS=y
-+CONFIG_MTD_BLOCK=y
-+# CONFIG_FTL is not set
-+# CONFIG_NFTL is not set
-+# CONFIG_INFTL is not set
-+# CONFIG_RFD_FTL is not set
-+# CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
-+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x80000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
-+
-+#
-+# Self-contained MTD device drivers
-+#
-+CONFIG_MTD_DATAFLASH=y
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
-+# CONFIG_MTD_BLOCK2MTD is not set
-+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
-+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_BLK_DEV=y
-+# CONFIG_BLK_DEV_COW_COMMON is not set
-+# CONFIG_BLK_DEV_LOOP is not set
-+# CONFIG_BLK_DEV_NBD is not set
-+# CONFIG_BLK_DEV_RAM is not set
-+# CONFIG_CDROM_PKTCDVD is not set
-+# CONFIG_ATA_OVER_ETH is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
-+# CONFIG_ENCLOSURE_SERVICES is not set
-+# CONFIG_HAVE_IDE is not set
-+
-+#
-+# SCSI device support
-+#
-+# CONFIG_RAID_ATTRS is not set
-+# CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_ATA is not set
-+# CONFIG_MD is not set
-+CONFIG_NETDEVICES=y
-+# CONFIG_DUMMY is not set
-+# CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
-+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-+
-+#
-+# MII PHY device drivers
-+#
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_REALTEK_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
-+CONFIG_NET_ETHERNET=y
-+# CONFIG_MII is not set
-+CONFIG_MACB=y
-+# CONFIG_ENC28J60 is not set
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
-+# CONFIG_NETDEV_1000 is not set
-+# CONFIG_NETDEV_10000 is not set
-+
-+#
-+# Wireless LAN
-+#
-+# CONFIG_WLAN_PRE80211 is not set
-+# CONFIG_WLAN_80211 is not set
-+# CONFIG_IWLWIFI_LEDS is not set
-+# CONFIG_WAN is not set
-+# CONFIG_PPP is not set
-+# CONFIG_SLIP is not set
-+# CONFIG_NETCONSOLE is not set
-+# CONFIG_NETPOLL is not set
-+# CONFIG_NET_POLL_CONTROLLER is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
-+
-+#
-+# Input device support
-+#
-+# CONFIG_INPUT is not set
-+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
-+
-+#
-+# Character devices
-+#
-+# CONFIG_VT is not set
-+# CONFIG_DEVKMEM is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
-+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
-+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+CONFIG_SERIAL_ATMEL_PDC=y
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=y
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=y
-+CONFIG_I2C_HELPER_AUTO=y
-+CONFIG_I2C_ALGOBIT=y
-+
-+#
-+# I2C Hardware Bus support
-+#
-+
-+#
-+# I2C system bus drivers (mostly embedded / system-on-chip)
-+#
-+CONFIG_I2C_GPIO=y
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_SIMTEC is not set
-+
-+#
-+# External I2C/SMBus adapter drivers
-+#
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+
-+#
-+# Other I2C/SMBus bus drivers
-+#
-+# CONFIG_I2C_PCA_PLATFORM is not set
-+
-+#
-+# Miscellaneous I2C Chip support
-+#
-+# CONFIG_DS1682 is not set
-+CONFIG_AT24=y
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_PCF8575 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_TPS65010 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_DS28CM00 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
-+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
-+
-+#
-+# SPI Protocol Masters
-+#
-+CONFIG_SPI_AT25=y
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+CONFIG_ARCH_REQUIRE_GPIOLIB=y
-+CONFIG_GPIOLIB=y
-+# CONFIG_DEBUG_GPIO is not set
-+CONFIG_GPIO_SYSFS=y
-+
-+#
-+# I2C GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX732X is not set
-+# CONFIG_GPIO_PCA953X is not set
-+# CONFIG_GPIO_PCF857X is not set
-+
-+#
-+# PCI GPIO expanders:
-+#
-+
-+#
-+# SPI GPIO expanders:
-+#
-+# CONFIG_GPIO_MAX7301 is not set
-+# CONFIG_GPIO_MCP23S08 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+# CONFIG_THERMAL is not set
-+# CONFIG_THERMAL_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_CORE is not set
-+# CONFIG_MFD_SM501 is not set
-+# CONFIG_HTC_PASIC3 is not set
-+# CONFIG_MFD_TMIO is not set
-+
-+#
-+# Multimedia devices
-+#
-+
-+#
-+# Multimedia core support
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_VIDEO_MEDIA is not set
-+
-+#
-+# Multimedia drivers
-+#
-+# CONFIG_DAB is not set
-+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_FOREIGN_ENDIAN is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+# CONFIG_LOGO is not set
-+# CONFIG_SOUND is not set
-+# CONFIG_USB_SUPPORT is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+CONFIG_MMC_BLOCK_BOUNCE=y
-+# CONFIG_SDIO_UART is not set
-+CONFIG_MMC_TEST=y
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+# CONFIG_MMC_SDHCI is not set
-+CONFIG_MMC_ATMELMCI=y
-+# CONFIG_MMC_ATMELMCI_DMA is not set
-+CONFIG_MMC_SPI=y
-+# CONFIG_MEMSTICK is not set
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
-+
-+#
-+# LED drivers
-+#
-+CONFIG_LEDS_GPIO=y
-+# CONFIG_LEDS_PCA955X is not set
-+
-+#
-+# LED Triggers
-+#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-+# CONFIG_ACCESSIBILITY is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-+
-+#
-+# I2C RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-+# CONFIG_RTC_DRV_S35390A is not set
-+# CONFIG_RTC_DRV_FM3130 is not set
-+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_M41T94 is not set
-+# CONFIG_RTC_DRV_DS1305 is not set
-+CONFIG_RTC_DRV_DS1390=y
-+# CONFIG_RTC_DRV_MAX6902 is not set
-+# CONFIG_RTC_DRV_R9701 is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1511 is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-+
-+#
-+# on-CPU RTC drivers
-+#
-+# CONFIG_RTC_DRV_AT32AP700X is not set
-+CONFIG_DMADEVICES=y
-+
-+#
-+# DMA Devices
-+#
-+CONFIG_DW_DMAC=y
-+CONFIG_DMA_ENGINE=y
-+
-+#
-+# DMA Clients
-+#
-+# CONFIG_NET_DMA is not set
-+# CONFIG_DMATEST is not set
-+# CONFIG_UIO is not set
-+
-+#
-+# File systems
-+#
-+CONFIG_EXT2_FS=y
-+# CONFIG_EXT2_FS_XATTR is not set
-+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
-+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=y
-+# CONFIG_REISERFS_FS is not set
-+# CONFIG_JFS_FS is not set
-+# CONFIG_FS_POSIX_ACL is not set
-+# CONFIG_XFS_FS is not set
-+# CONFIG_OCFS2_FS is not set
-+# CONFIG_DNOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
-+# CONFIG_QUOTA is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
-+
-+#
-+# CD-ROM/DVD Filesystems
-+#
-+# CONFIG_ISO9660_FS is not set
-+# CONFIG_UDF_FS is not set
-+
-+#
-+# DOS/FAT/NT Filesystems
-+#
-+CONFIG_FAT_FS=y
-+CONFIG_MSDOS_FS=y
-+CONFIG_VFAT_FS=y
-+CONFIG_FAT_DEFAULT_CODEPAGE=850
-+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-+# CONFIG_NTFS_FS is not set
-+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+# CONFIG_PROC_KCORE is not set
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+CONFIG_CONFIGFS_FS=y
-+
-+#
-+# Miscellaneous filesystems
-+#
-+# CONFIG_ADFS_FS is not set
-+# CONFIG_AFFS_FS is not set
-+# CONFIG_HFS_FS is not set
-+# CONFIG_HFSPLUS_FS is not set
-+# CONFIG_BEFS_FS is not set
-+# CONFIG_BFS_FS is not set
-+# CONFIG_EFS_FS is not set
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_CRAMFS is not set
-+# CONFIG_VXFS_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_OMFS_FS is not set
-+# CONFIG_HPFS_FS is not set
-+# CONFIG_QNX4FS_FS is not set
-+# CONFIG_ROMFS_FS is not set
-+# CONFIG_SYSV_FS is not set
-+# CONFIG_UFS_FS is not set
-+CONFIG_NETWORK_FILESYSTEMS=y
-+CONFIG_NFS_FS=y
-+CONFIG_NFS_V3=y
-+# CONFIG_NFS_V3_ACL is not set
-+# CONFIG_NFS_V4 is not set
-+CONFIG_ROOT_NFS=y
-+# CONFIG_NFSD is not set
-+CONFIG_LOCKD=y
-+CONFIG_LOCKD_V4=y
-+CONFIG_NFS_COMMON=y
-+CONFIG_SUNRPC=y
-+# CONFIG_RPCSEC_GSS_KRB5 is not set
-+# CONFIG_RPCSEC_GSS_SPKM3 is not set
-+# CONFIG_SMB_FS is not set
-+# CONFIG_CIFS is not set
-+# CONFIG_NCP_FS is not set
-+# CONFIG_CODA_FS is not set
-+# CONFIG_AFS_FS is not set
-+
-+#
-+# Partition Types
-+#
-+# CONFIG_PARTITION_ADVANCED is not set
-+CONFIG_MSDOS_PARTITION=y
-+CONFIG_NLS=y
-+CONFIG_NLS_DEFAULT="iso8859-1"
-+CONFIG_NLS_CODEPAGE_437=y
-+# CONFIG_NLS_CODEPAGE_737 is not set
-+# CONFIG_NLS_CODEPAGE_775 is not set
-+CONFIG_NLS_CODEPAGE_850=y
-+# CONFIG_NLS_CODEPAGE_852 is not set
-+# CONFIG_NLS_CODEPAGE_855 is not set
-+# CONFIG_NLS_CODEPAGE_857 is not set
-+# CONFIG_NLS_CODEPAGE_860 is not set
-+# CONFIG_NLS_CODEPAGE_861 is not set
-+# CONFIG_NLS_CODEPAGE_862 is not set
-+# CONFIG_NLS_CODEPAGE_863 is not set
-+# CONFIG_NLS_CODEPAGE_864 is not set
-+# CONFIG_NLS_CODEPAGE_865 is not set
-+# CONFIG_NLS_CODEPAGE_866 is not set
-+# CONFIG_NLS_CODEPAGE_869 is not set
-+# CONFIG_NLS_CODEPAGE_936 is not set
-+# CONFIG_NLS_CODEPAGE_950 is not set
-+# CONFIG_NLS_CODEPAGE_932 is not set
-+# CONFIG_NLS_CODEPAGE_949 is not set
-+# CONFIG_NLS_CODEPAGE_874 is not set
-+# CONFIG_NLS_ISO8859_8 is not set
-+# CONFIG_NLS_CODEPAGE_1250 is not set
-+# CONFIG_NLS_CODEPAGE_1251 is not set
-+# CONFIG_NLS_ASCII is not set
-+CONFIG_NLS_ISO8859_1=y
-+# CONFIG_NLS_ISO8859_2 is not set
-+# CONFIG_NLS_ISO8859_3 is not set
-+# CONFIG_NLS_ISO8859_4 is not set
-+# CONFIG_NLS_ISO8859_5 is not set
-+# CONFIG_NLS_ISO8859_6 is not set
-+# CONFIG_NLS_ISO8859_7 is not set
-+# CONFIG_NLS_ISO8859_9 is not set
-+# CONFIG_NLS_ISO8859_13 is not set
-+# CONFIG_NLS_ISO8859_14 is not set
-+# CONFIG_NLS_ISO8859_15 is not set
-+# CONFIG_NLS_KOI8_R is not set
-+# CONFIG_NLS_KOI8_U is not set
-+CONFIG_NLS_UTF8=y
-+# CONFIG_DLM is not set
-+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_FRAME_WARN=1024
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+CONFIG_DEBUG_KERNEL=y
-+# CONFIG_DEBUG_SHIRQ is not set
-+CONFIG_DETECT_SOFTLOCKUP=y
-+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-+CONFIG_SCHED_DEBUG=y
-+# CONFIG_SCHEDSTATS is not set
-+# CONFIG_TIMER_STATS is not set
-+# CONFIG_DEBUG_OBJECTS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
-+# CONFIG_SLUB_STATS is not set
-+# CONFIG_DEBUG_RT_MUTEXES is not set
-+# CONFIG_RT_MUTEX_TESTER is not set
-+# CONFIG_DEBUG_SPINLOCK is not set
-+# CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
-+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-+# CONFIG_DEBUG_KOBJECT is not set
-+CONFIG_DEBUG_BUGVERBOSE=y
-+# CONFIG_DEBUG_INFO is not set
-+# CONFIG_DEBUG_VM is not set
-+# CONFIG_DEBUG_WRITECOUNT is not set
-+# CONFIG_DEBUG_MEMORY_INIT is not set
-+# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
-+CONFIG_FRAME_POINTER=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
-+# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_BACKTRACE_SELF_TEST is not set
-+# CONFIG_FAULT_INJECTION is not set
-+# CONFIG_SAMPLES is not set
-+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+
-+#
-+# Crypto core or helper
-+#
-+CONFIG_CRYPTO_ALGAPI=y
-+CONFIG_CRYPTO_AEAD=y
-+CONFIG_CRYPTO_BLKCIPHER=y
-+CONFIG_CRYPTO_HASH=y
-+CONFIG_CRYPTO_MANAGER=y
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_AUTHENC=y
-+
-+#
-+# Authenticated Encryption with Associated Data
-+#
-+# CONFIG_CRYPTO_CCM is not set
-+# CONFIG_CRYPTO_GCM is not set
-+# CONFIG_CRYPTO_SEQIV is not set
-+
-+#
-+# Block modes
-+#
-+CONFIG_CRYPTO_CBC=y
-+# CONFIG_CRYPTO_CTR is not set
-+# CONFIG_CRYPTO_CTS is not set
-+CONFIG_CRYPTO_ECB=y
-+# CONFIG_CRYPTO_LRW is not set
-+CONFIG_CRYPTO_PCBC=y
-+# CONFIG_CRYPTO_XTS is not set
-+
-+#
-+# Hash modes
-+#
-+CONFIG_CRYPTO_HMAC=y
-+# CONFIG_CRYPTO_XCBC is not set
-+
-+#
-+# Digest
-+#
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=y
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_RMD128 is not set
-+# CONFIG_CRYPTO_RMD160 is not set
-+# CONFIG_CRYPTO_RMD256 is not set
-+# CONFIG_CRYPTO_RMD320 is not set
-+CONFIG_CRYPTO_SHA1=y
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+
-+#
-+# Ciphers
-+#
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+CONFIG_CRYPTO_ARC4=y
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+CONFIG_CRYPTO_DES=y
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_SALSA20 is not set
-+# CONFIG_CRYPTO_SEED is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+
-+#
-+# Compression
-+#
-+CONFIG_CRYPTO_DEFLATE=y
-+# CONFIG_CRYPTO_LZO is not set
-+CONFIG_CRYPTO_HW=y
-+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-+# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-+CONFIG_CRC_CCITT=y
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_T10DIF is not set
-+CONFIG_CRC_ITU_T=y
-+CONFIG_CRC32=y
-+CONFIG_CRC7=y
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_GENERIC_ALLOCATOR=y
-+CONFIG_PLIST=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
-diff --git a/arch/avr32/include/asm/ast_regs.h b/arch/avr32/include/asm/ast_regs.h
-new file mode 100644
-index 0000000..2e2cfb9
---- /dev/null
-+++ b/arch/avr32/include/asm/ast_regs.h
-@@ -0,0 +1,88 @@
-+/*
-+ * Register definitions for the Asynchronous Timer (AST)
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __AST_REGS_H__
-+#define __AST_REGS_H__
-+
-+/* Control Register */
-+#define AST_CR				0x0000
-+# define AST_CR_EN_BIT			0	/* Enable */
-+# define AST_CR_PCLR_BIT		1	/* Prescaler Clear */
-+# define AST_CR_CA0_BIT			8	/* Clear on Alarm */
-+# define AST_CR_CA1_BIT			9
-+# define AST_CR_PSEL_START		16	/* Prescale Select */
-+# define AST_CR_PSEL_SIZE		4
-+
-+/* Counter Value */
-+#define AST_CV				0x0004
-+
-+/* Status, Status Clear, Interrupt Enable/Disable/Mask, Wake Enable */
-+#define AST_SR				0x0008
-+#define AST_SCR				0x000c
-+#define AST_IER				0x0010
-+#define AST_IDR				0x0014
-+#define AST_IMR				0x0018
-+#define AST_WER				0x001c
-+# define AST_OVF_BIT			0	/* Overflow */
-+# define AST_ALARM0_BIT			8	/* Alarm event */
-+# define AST_ALARM1_BIT			9
-+# define AST_PER0_BIT			16	/* Periodic event */
-+# define AST_PER1_BIT			17
-+# define AST_BUSY_BIT			24	/* AST busy */
-+# define AST_READY_BIT			25	/* BUSY 1 -> 0 event */
-+# define AST_CLK_BUSY_BIT		28	/* CLOCK busy */
-+# define AST_CLK_READY_BIT		29	/* CKL_BUSY 1 -> 0 event */
-+
-+/* Alarm registers */
-+#define AST_AR0				0x0020
-+#define AST_AR1				0x0024
-+
-+/* Periodic Interval registers */
-+#define AST_PIR0			0x0030
-+#define AST_PIR1			0x0034
-+# define AST_PIRx_INSEL_START		0	/* Interval select */
-+# define AST_PIRx_INSEL_SIZE		4
-+
-+/* Clock Select register */
-+#define AST_CLOCK			0x0040
-+# define AST_CLOCK_CEN_BIT		0	/* Clock Enable */
-+# define AST_CLOCK_CSSEL_START		8	/* Clock Source */
-+# define AST_CLOCK_CSSEL_SIZE		2
-+#  define AST_CLOCK_SLOW		0	/* RC oscillator */
-+#  define AST_CLOCK_OSC32		1	/* 32 kHz oscillator */
-+#  define AST_CLOCK_PB			2	/* Peripheral Bus clock */
-+#  define AST_CLOCK_GC			3	/* Generic clock */
-+
-+/* Version register */
-+#define AST_VERSION			0x00fc
-+
-+/* Bit manipulation macros */
-+#define AST_BIT(name)						\
-+	(1 << AST_##name##_BIT)
-+#define AST_BF(name,value)					\
-+	(((value) & ((1 << AST_##name##_SIZE) - 1))		\
-+	 << AST_##name##_START)
-+#define AST_BFEXT(name,value)					\
-+	(((value) >> AST_##name##_START)			\
-+	 & ((1 << AST_##name##_SIZE) - 1))
-+#define AST_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << AST_##name##_SIZE) - 1)		\
-+		    << AST_##name##_START))			\
-+	 | AST_BF(name,value))
-+
-+/* Register access macros */
-+#define ast_readl(base, reg)					\
-+	__raw_readl(base + AST_##reg)
-+#define ast_writel(base, reg, value)				\
-+	__raw_writel(value, base + AST_##reg)
-+
-+struct platform_device;
-+void ast_time_init(struct platform_device *pdev, unsigned int clksel);
-+
-+#endif /* __AST_REGS_H__ */
-diff --git a/arch/avr32/include/asm/atmel-mci.h b/arch/avr32/include/asm/atmel-mci.h
-index c2ea6e1..59f3fad 100644
---- a/arch/avr32/include/asm/atmel-mci.h
-+++ b/arch/avr32/include/asm/atmel-mci.h
-@@ -1,9 +1,39 @@
- #ifndef __ASM_AVR32_ATMEL_MCI_H
- #define __ASM_AVR32_ATMEL_MCI_H
- 
--struct mci_platform_data {
-+#define ATMEL_MCI_MAX_NR_SLOTS	2
-+
-+struct dma_slave;
-+
-+/**
-+ * struct mci_slot_pdata - board-specific per-slot configuration
-+ * @bus_width: Number of data lines wired up the slot
-+ * @detect_pin: GPIO pin wired to the card detect switch
-+ * @wp_pin: GPIO pin wired to the write protect sensor
-+ *
-+ * If a given slot is not present on the board, @bus_width should be
-+ * set to 0. The other fields are ignored in this case.
-+ *
-+ * Any pins that aren't available should be set to a negative value.
-+ *
-+ * Note that support for multiple slots is experimental -- some cards
-+ * might get upset if we don't get the clock management exactly right.
-+ * But in most cases, it should work just fine.
-+ */
-+struct mci_slot_pdata {
-+	unsigned int		bus_width;
- 	int			detect_pin;
- 	int			wp_pin;
- };
- 
-+/**
-+ * struct mci_platform_data - board-specific MMC/SDcard configuration
-+ * @dma_slave: DMA slave interface to use in data transfers, or NULL.
-+ * @slot: Per-slot configuration data.
-+ */
-+struct mci_platform_data {
-+	struct dma_slave	*dma_slave;
-+	struct mci_slot_pdata	slot[ATMEL_MCI_MAX_NR_SLOTS];
-+};
-+
- #endif /* __ASM_AVR32_ATMEL_MCI_H */
-diff --git a/arch/avr32/include/asm/byteorder.h b/arch/avr32/include/asm/byteorder.h
-index d77b48b..8e3af02 100644
---- a/arch/avr32/include/asm/byteorder.h
-+++ b/arch/avr32/include/asm/byteorder.h
-@@ -7,6 +7,9 @@
- #include <asm/types.h>
- #include <linux/compiler.h>
- 
-+#define __BIG_ENDIAN
-+#define __SWAB_64_THRU_32__
-+
- #ifdef __CHECKER__
- extern unsigned long __builtin_bswap_32(unsigned long x);
- extern unsigned short __builtin_bswap_16(unsigned short x);
-@@ -17,15 +20,18 @@ extern unsigned short __builtin_bswap_16(unsigned short x);
-  * the result.
-  */
- #if !(__GNUC__ == 4 && __GNUC_MINOR__ < 2)
--#define __arch__swab32(x) __builtin_bswap_32(x)
--#define __arch__swab16(x) __builtin_bswap_16(x)
--#endif
-+static inline __attribute_const__ __u16 __arch_swab16(__u16 val)
-+{
-+	return __builtin_bswap_16(val);
-+}
-+#define __arch_swab16 __arch_swab16
- 
--#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
--# define __BYTEORDER_HAS_U64__
--# define __SWAB_64_THRU_32__
-+static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
-+{
-+	return __builtin_bswap_32(val);
-+}
-+#define __arch_swab32 __arch_swab32
- #endif
- 
--#include <linux/byteorder/big_endian.h>
--
-+#include <linux/byteorder.h>
- #endif /* __ASM_AVR32_BYTEORDER_H */
-diff --git a/arch/avr32/include/asm/io.h b/arch/avr32/include/asm/io.h
-index a520f77..22c97ef 100644
---- a/arch/avr32/include/asm/io.h
-+++ b/arch/avr32/include/asm/io.h
-@@ -160,6 +160,14 @@ BUILDIO_IOPORT(l, u32)
- #define readw_relaxed			readw
- #define readl_relaxed			readl
- 
-+#define readb_be			__raw_readb
-+#define readw_be			__raw_readw
-+#define readl_be			__raw_readl
-+
-+#define writeb_be			__raw_writeb
-+#define writew_be			__raw_writew
-+#define writel_be			__raw_writel
-+
- #define __BUILD_MEMORY_STRING(bwl, type)				\
- static inline void writes##bwl(volatile void __iomem *addr,		\
- 			       const void *data, unsigned int count)	\
-diff --git a/arch/avr32/kernel/cpu.c b/arch/avr32/kernel/cpu.c
-index e84faff..f2c0cb1 100644
---- a/arch/avr32/kernel/cpu.c
-+++ b/arch/avr32/kernel/cpu.c
-@@ -208,6 +208,7 @@ struct chip_id_map {
- 
- static const struct chip_id_map chip_names[] = {
- 	{ .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
-+	{ .mid = 0x1f, .pn = 0x1e83, .name = "AT32AP720x" },
- };
- #define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
- 
-diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
-index 33d4937..921da60 100644
---- a/arch/avr32/kernel/entry-avr32b.S
-+++ b/arch/avr32/kernel/entry-avr32b.S
-@@ -112,7 +112,9 @@ pgtbl_lookup:
- 
- 	/* Second level lookup */
- 	ld.w	r2, r3[r1 << 2]
-+#ifdef CONFIG_CPU_AT32AP700X
- 	mfsr	r0, SYSREG_TLBARLO
-+#endif
- 	bld	r2, _PAGE_BIT_PRESENT
- 	brcc	page_not_present
- 
-@@ -124,6 +126,8 @@ pgtbl_lookup:
- 	andl	r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
- 	mtsr	SYSREG_TLBELO, r2
- 
-+	/* Later CPUs do this algorithm in hardware */
-+#ifdef CONFIG_CPU_AT32AP700X
- 	/* Figure out which entry we want to replace */
- 	mfsr	r1, SYSREG_MMUCR
- 	clz	r2, r0
-@@ -134,6 +138,7 @@ pgtbl_lookup:
- 
- 1:	bfins	r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
- 	mtsr	SYSREG_MMUCR, r1
-+#endif /* CONFIG_CPU_AT32AP700X */
- 	tlbw
- 
- 	tlbmiss_restore
-@@ -751,8 +756,10 @@ irq_level\level:
- 
- 	lddsp	r4, sp[REG_SR]
- 	bfextu	r4, r4, SYSREG_M0_OFFSET, 3
-+#ifdef CONFIG_CPU_AT32AP700X
- 	cp.w	r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
- 	breq	2f
-+#endif
- 	cp.w	r4, MODE_USER >> SYSREG_M0_OFFSET
- #ifdef CONFIG_PREEMPT
- 	brne	3f
-@@ -786,6 +793,7 @@ irq_level\level:
- 	rete
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP700X
- 2:	get_thread_info	r0
- 	ld.w	r1, r0[TI_flags]
- 	bld	r1, TIF_CPU_GOING_TO_SLEEP
-@@ -796,6 +804,7 @@ irq_level\level:
- #endif
- 	sub	r1, pc, . - cpu_idle_skip_sleep
- 	stdsp	sp[REG_PC], r1
-+#endif
- #ifdef CONFIG_PREEMPT
- 3:	get_thread_info r0
- 	ld.w	r2, r0[TI_preempt_count]
-diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
-index 2c08ac9..134d530 100644
---- a/arch/avr32/kernel/process.c
-+++ b/arch/avr32/kernel/process.c
-@@ -9,6 +9,7 @@
- #include <linux/module.h>
- #include <linux/kallsyms.h>
- #include <linux/fs.h>
-+#include <linux/pm.h>
- #include <linux/ptrace.h>
- #include <linux/reboot.h>
- #include <linux/tick.h>
-@@ -20,7 +21,7 @@
- 
- #include <mach/pm.h>
- 
--void (*pm_power_off)(void) = NULL;
-+void (*pm_power_off)(void);
- EXPORT_SYMBOL(pm_power_off);
- 
- /*
-diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
-index d8e623c..5c70839 100644
---- a/arch/avr32/kernel/setup.c
-+++ b/arch/avr32/kernel/setup.c
-@@ -283,6 +283,25 @@ static int __init early_parse_fbmem(char *p)
- }
- early_param("fbmem", early_parse_fbmem);
- 
-+/*
-+ * Pick out the memory size.  We look for mem=size at start,
-+ * where start and size are "size[KkMmGg]"
-+ */
-+static int __init early_mem(char *p)
-+{
-+	resource_size_t size, start;
-+
-+	start = system_ram->start;
-+	size  = memparse(p, &p);
-+	if (*p == '@')
-+		start = memparse(p + 1, &p);
-+
-+	system_ram->start = start;
-+	system_ram->end = system_ram->start + size - 1;
-+	return 0;
-+}
-+early_param("mem", early_mem);
-+
- static int __init parse_tag_core(struct tag *tag)
- {
- 	if (tag->hdr.size > 2) {
-diff --git a/arch/avr32/kernel/time.c b/arch/avr32/kernel/time.c
-index 283481d..09dfab9 100644
---- a/arch/avr32/kernel/time.c
-+++ b/arch/avr32/kernel/time.c
-@@ -15,6 +15,8 @@
- 
- #include <asm/sysreg.h>
- 
-+#include <mach/cpu.h>
-+#include <mach/init.h>
- #include <mach/pm.h>
- 
- 
-@@ -116,6 +118,9 @@ void __init time_init(void)
- 	unsigned long counter_hz;
- 	int ret;
- 
-+	/* Make sure we don't get any interrupts until we ask for it. */
-+	sysreg_write(COMPARE, 0);
-+
- 	xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
- 	xtime.tv_nsec = 0;
- 
-@@ -130,12 +135,16 @@ void __init time_init(void)
- 	if (ret)
- 		pr_debug("timer: could not register clocksource: %d\n", ret);
- 
-+	if (!cpu_has_working_compare()) {
-+		platform_time_init();
-+		return;
-+	}
-+
- 	/* setup COMPARE clockevent */
- 	comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
- 	comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
- 	comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
- 
--	sysreg_write(COMPARE, 0);
- 	timer_irqaction.dev_id = &comparator;
- 
- 	ret = setup_irq(0, &timer_irqaction);
-diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
-index 514c9a9..79ef59b 100644
---- a/arch/avr32/mach-at32ap/Makefile
-+++ b/arch/avr32/mach-at32ap/Makefile
-@@ -1,9 +1,14 @@
--obj-y				+= pdc.o clock.o intc.o extint.o pio.o hsmc.o
-+obj-y				+= pdc.o clock.o intc.o extint.o hsmc.o
- obj-y				+= hmatrix.o
--obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_PORTMUX_PIO)	+= pio.o
-+obj-$(CONFIG_PORTMUX_GPIO_V2)	+= gpio-v2.o
-+obj-$(CONFIG_TIMER_AST)		+= timer-ast.o
- obj-$(CONFIG_CPU_FREQ_AT32AP)	+= cpufreq.o
- obj-$(CONFIG_PM)		+= pm.o
- 
-+obj-$(CONFIG_CPU_AT32AP700X)	+= at32ap700x.o pm-at32ap700x.o
-+obj-$(CONFIG_CPU_AT32AP720X)	+= at32ap720x.o pm-at32ap720x.o
-+
- ifeq ($(CONFIG_PM_DEBUG),y)
- CFLAGS_pm.o	+= -DDEBUG
- endif
-diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
-index e01dbe4..7e83326 100644
---- a/arch/avr32/mach-at32ap/at32ap700x.c
-+++ b/arch/avr32/mach-at32ap/at32ap700x.c
-@@ -23,6 +23,7 @@
- #include <mach/at32ap700x.h>
- #include <mach/board.h>
- #include <mach/hmatrix.h>
-+#include <mach/pm.h>
- #include <mach/portmux.h>
- #include <mach/sram.h>
- 
-@@ -30,7 +31,7 @@
- 
- #include "clock.h"
- #include "pio.h"
--#include "pm.h"
-+#include "pm-v1.h"
- 
- 
- #define PBMEM(base)					\
-@@ -82,8 +83,9 @@ static struct platform_device _name##_id##_device = {		\
- 	.num_resources	= ARRAY_SIZE(_name##_id##_resource),	\
- }
- 
--#define select_peripheral(pin, periph, flags)			\
--	at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
-+#define select_peripheral(port, pin_mask, periph, flags)	\
-+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
-+			   GPIO_##periph, flags)
- 
- #define DEV_CLK(_name, devname, bus, _index)			\
- static struct clk devname##_##_name = {				\
-@@ -812,7 +814,7 @@ static struct resource pio4_resource[] = {
- DEFINE_DEV(pio, 4);
- DEV_CLK(mck, pio4, pba, 14);
- 
--void __init at32_add_system_devices(void)
-+static int __init system_device_init(void)
- {
- 	platform_device_register(&at32_pm0_device);
- 	platform_device_register(&at32_intc0_device);
-@@ -831,7 +833,10 @@ void __init at32_add_system_devices(void)
- 	platform_device_register(&pio2_device);
- 	platform_device_register(&pio3_device);
- 	platform_device_register(&pio4_device);
-+
-+	return 0;
- }
-+core_initcall(system_device_init);
- 
- /* --------------------------------------------------------------------
-  *  PSIF
-@@ -871,6 +876,7 @@ static struct clk atmel_psif1_pclk = {
- struct platform_device *__init at32_add_device_psif(unsigned int id)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (!(id == 0 || id == 1))
- 		return NULL;
-@@ -881,20 +887,22 @@ struct platform_device *__init at32_add_device_psif(unsigned int id)
- 
- 	switch (id) {
- 	case 0:
-+		pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
-+
- 		if (platform_device_add_resources(pdev, atmel_psif0_resource,
- 					ARRAY_SIZE(atmel_psif0_resource)))
- 			goto err_add_resources;
- 		atmel_psif0_pclk.dev = &pdev->dev;
--		select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
--		select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
- 		break;
- 	case 1:
-+		pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
-+
- 		if (platform_device_add_resources(pdev, atmel_psif1_resource,
- 					ARRAY_SIZE(atmel_psif1_resource)))
- 			goto err_add_resources;
- 		atmel_psif1_pclk.dev = &pdev->dev;
--		select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
--		select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
-+		select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
- 		break;
- 	default:
- 		return NULL;
-@@ -958,26 +966,30 @@ DEV_CLK(usart, atmel_usart3, pba, 6);
- 
- static inline void configure_usart0_pins(void)
- {
--	select_peripheral(PA(8),  PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PA(9),  PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart1_pins(void)
- {
--	select_peripheral(PA(17), PERIPH_A, 0);	/* RXD	*/
--	select_peripheral(PA(18), PERIPH_A, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart2_pins(void)
- {
--	select_peripheral(PB(26), PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PB(27), PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static inline void configure_usart3_pins(void)
- {
--	select_peripheral(PB(18), PERIPH_B, 0);	/* RXD	*/
--	select_peripheral(PB(17), PERIPH_B, 0);	/* TXD	*/
-+	u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
- }
- 
- static struct platform_device *__initdata at32_usarts[4];
-@@ -1057,59 +1069,73 @@ struct platform_device *__init
- at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &macb0_device;
- 
--		select_peripheral(PC(3),  PERIPH_A, 0);	/* TXD0	*/
--		select_peripheral(PC(4),  PERIPH_A, 0);	/* TXD1	*/
--		select_peripheral(PC(7),  PERIPH_A, 0);	/* TXEN	*/
--		select_peripheral(PC(8),  PERIPH_A, 0);	/* TXCK */
--		select_peripheral(PC(9),  PERIPH_A, 0);	/* RXD0	*/
--		select_peripheral(PC(10), PERIPH_A, 0);	/* RXD1	*/
--		select_peripheral(PC(13), PERIPH_A, 0);	/* RXER	*/
--		select_peripheral(PC(15), PERIPH_A, 0);	/* RXDV	*/
--		select_peripheral(PC(16), PERIPH_A, 0);	/* MDC	*/
--		select_peripheral(PC(17), PERIPH_A, 0);	/* MDIO	*/
-+		pin_mask  = (1 << 3);	/* TXD0 */
-+		pin_mask |= (1 << 4);	/* TXD1 */
-+		pin_mask |= (1 << 7);	/* TXEN */
-+		pin_mask |= (1 << 8);	/* TXCK */
-+		pin_mask |= (1 << 9);	/* RXD0 */
-+		pin_mask |= (1 << 10);	/* RXD1 */
-+		pin_mask |= (1 << 13);	/* RXER */
-+		pin_mask |= (1 << 15);	/* RXDV */
-+		pin_mask |= (1 << 16);	/* MDC  */
-+		pin_mask |= (1 << 17);	/* MDIO */
- 
- 		if (!data->is_rmii) {
--			select_peripheral(PC(0),  PERIPH_A, 0);	/* COL	*/
--			select_peripheral(PC(1),  PERIPH_A, 0);	/* CRS	*/
--			select_peripheral(PC(2),  PERIPH_A, 0);	/* TXER	*/
--			select_peripheral(PC(5),  PERIPH_A, 0);	/* TXD2	*/
--			select_peripheral(PC(6),  PERIPH_A, 0);	/* TXD3 */
--			select_peripheral(PC(11), PERIPH_A, 0);	/* RXD2	*/
--			select_peripheral(PC(12), PERIPH_A, 0);	/* RXD3	*/
--			select_peripheral(PC(14), PERIPH_A, 0);	/* RXCK	*/
--			select_peripheral(PC(18), PERIPH_A, 0);	/* SPD	*/
-+			pin_mask |= (1 << 0);	/* COL  */
-+			pin_mask |= (1 << 1);	/* CRS  */
-+			pin_mask |= (1 << 2);	/* TXER */
-+			pin_mask |= (1 << 5);	/* TXD2 */
-+			pin_mask |= (1 << 6);	/* TXD3 */
-+			pin_mask |= (1 << 11);	/* RXD2 */
-+			pin_mask |= (1 << 12);	/* RXD3 */
-+			pin_mask |= (1 << 14);	/* RXCK */
-+#ifndef CONFIG_BOARD_MIMC200
-+			pin_mask |= (1 << 18);	/* SPD  */
-+#endif
- 		}
-+
-+		select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 
- 	case 1:
- 		pdev = &macb1_device;
- 
--		select_peripheral(PD(13), PERIPH_B, 0);		/* TXD0	*/
--		select_peripheral(PD(14), PERIPH_B, 0);		/* TXD1	*/
--		select_peripheral(PD(11), PERIPH_B, 0);		/* TXEN	*/
--		select_peripheral(PD(12), PERIPH_B, 0);		/* TXCK */
--		select_peripheral(PD(10), PERIPH_B, 0);		/* RXD0	*/
--		select_peripheral(PD(6),  PERIPH_B, 0);		/* RXD1	*/
--		select_peripheral(PD(5),  PERIPH_B, 0);		/* RXER	*/
--		select_peripheral(PD(4),  PERIPH_B, 0);		/* RXDV	*/
--		select_peripheral(PD(3),  PERIPH_B, 0);		/* MDC	*/
--		select_peripheral(PD(2),  PERIPH_B, 0);		/* MDIO	*/
-+		pin_mask  = (1 << 13);	/* TXD0 */
-+		pin_mask |= (1 << 14);	/* TXD1 */
-+		pin_mask |= (1 << 11);	/* TXEN */
-+		pin_mask |= (1 << 12);	/* TXCK */
-+		pin_mask |= (1 << 10);	/* RXD0 */
-+		pin_mask |= (1 << 6);	/* RXD1 */
-+		pin_mask |= (1 << 5);	/* RXER */
-+		pin_mask |= (1 << 4);	/* RXDV */
-+		pin_mask |= (1 << 3);	/* MDC  */
-+		pin_mask |= (1 << 2);	/* MDIO */
-+
-+#ifndef CONFIG_BOARD_MIMC200
-+		if (!data->is_rmii)
-+			pin_mask |= (1 << 15);	/* SPD  */
-+#endif
-+
-+		select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
- 
- 		if (!data->is_rmii) {
--			select_peripheral(PC(19), PERIPH_B, 0);	/* COL	*/
--			select_peripheral(PC(23), PERIPH_B, 0);	/* CRS	*/
--			select_peripheral(PC(26), PERIPH_B, 0);	/* TXER	*/
--			select_peripheral(PC(27), PERIPH_B, 0);	/* TXD2	*/
--			select_peripheral(PC(28), PERIPH_B, 0);	/* TXD3 */
--			select_peripheral(PC(29), PERIPH_B, 0);	/* RXD2	*/
--			select_peripheral(PC(30), PERIPH_B, 0);	/* RXD3	*/
--			select_peripheral(PC(24), PERIPH_B, 0);	/* RXCK	*/
--			select_peripheral(PD(15), PERIPH_B, 0);	/* SPD	*/
-+			pin_mask  = (1 << 19);	/* COL  */
-+			pin_mask |= (1 << 23);	/* CRS  */
-+			pin_mask |= (1 << 26);	/* TXER */
-+			pin_mask |= (1 << 27);	/* TXD2 */
-+			pin_mask |= (1 << 28);	/* TXD3 */
-+			pin_mask |= (1 << 29);	/* RXD2 */
-+			pin_mask |= (1 << 30);	/* RXD3 */
-+			pin_mask |= (1 << 24);	/* RXCK */
-+
-+			select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
- 		}
- 		break;
- 
-@@ -1130,6 +1156,7 @@ at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
- static struct resource atmel_spi0_resource[] = {
- 	PBMEM(0xffe00000),
- 	IRQ(3),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 0);
- DEV_CLK(spi_clk, atmel_spi0, pba, 0);
-@@ -1137,6 +1164,7 @@ DEV_CLK(spi_clk, atmel_spi0, pba, 0);
- static struct resource atmel_spi1_resource[] = {
- 	PBMEM(0xffe00400),
- 	IRQ(4),
-+	{ 0 },	/* SRAM buffer, if available */
- };
- DEFINE_DEV(atmel_spi, 1);
- DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-@@ -1166,6 +1194,8 @@ at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
- struct platform_device *__init
- at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- {
-+	unsigned long sram_buf;
-+
- 	/*
- 	 * Manage the chipselects as GPIOs, normally using the same pins
- 	 * the SPI controller expects; but boards can use other pins.
-@@ -1177,23 +1207,28 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- 		{ GPIO_PIN_PB(2), GPIO_PIN_PB(3),
- 		  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &atmel_spi0_device;
-+		pin_mask  = (1 << 1) | (1 << 2);	/* MOSI & SCK */
-+
- 		/* pullup MISO so a level is always defined */
--		select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
--		select_peripheral(PA(1),  PERIPH_A, 0);	/* MOSI	 */
--		select_peripheral(PA(2),  PERIPH_A, 0);	/* SCK	 */
-+		select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
- 		at32_spi_setup_slaves(0, b, n, spi0_pins);
- 		break;
- 
- 	case 1:
- 		pdev = &atmel_spi1_device;
-+		pin_mask  = (1 << 1) | (1 << 5);	/* MOSI */
-+
- 		/* pullup MISO so a level is always defined */
--		select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
--		select_peripheral(PB(1),  PERIPH_B, 0);	/* MOSI  */
--		select_peripheral(PB(5),  PERIPH_B, 0);	/* SCK   */
-+		select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
-+		select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
-+
- 		at32_spi_setup_slaves(1, b, n, spi1_pins);
- 		break;
- 
-@@ -1201,6 +1236,13 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
- 		return NULL;
- 	}
- 
-+	sram_buf = sram_alloc(4096);
-+	if (sram_buf) {
-+		pdev->resource[2].start = sram_buf;
-+		pdev->resource[2].end = sram_buf + 4096 - 1;
-+		pdev->resource[2].flags = IORESOURCE_MEM;
-+	}
-+
- 	spi_register_board_info(b, n);
- 	platform_device_register(pdev);
- 	return pdev;
-@@ -1226,6 +1268,7 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
- 						    unsigned int n)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -1238,8 +1281,9 @@ struct platform_device *__init at32_add_device_twi(unsigned int id,
- 				ARRAY_SIZE(atmel_twi0_resource)))
- 		goto err_add_resources;
- 
--	select_peripheral(PA(6),  PERIPH_A, 0);	/* SDA	*/
--	select_peripheral(PA(7),  PERIPH_A, 0);	/* SDL	*/
-+	pin_mask  = (1 << 6) | (1 << 7);	/* SDA & SDL */
-+
-+	select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
- 
- 	atmel_twi0_pclk.dev = &pdev->dev;
- 
-@@ -1272,10 +1316,16 @@ static struct clk atmel_mci0_pclk = {
- struct platform_device *__init
- at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
- {
--	struct mci_platform_data	_data;
- 	struct platform_device		*pdev;
-+	struct dw_dma_slave		*dws;
-+	u32				pioa_mask;
-+	u32				piob_mask;
- 
--	if (id != 0)
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	/* Must have at least one usable slot */
-+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
- 		return NULL;
- 
- 	pdev = platform_device_alloc("atmel_mci", id);
-@@ -1286,28 +1336,80 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
- 				ARRAY_SIZE(atmel_mci0_resource)))
- 		goto fail;
- 
--	if (!data) {
--		data = &_data;
--		memset(data, -1, sizeof(struct mci_platform_data));
--		data->detect_pin = GPIO_PIN_NONE;
--		data->wp_pin = GPIO_PIN_NONE;
--	}
-+	if (data->dma_slave)
-+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	dws->slave.dev = &pdev->dev;
-+	dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
-+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
-+				| DWC_CFGH_DST_PER(1));
-+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	data->dma_slave = &dws->slave;
- 
- 	if (platform_device_add_data(pdev, data,
- 				sizeof(struct mci_platform_data)))
- 		goto fail;
- 
--	select_peripheral(PA(10), PERIPH_A, 0);	/* CLK	 */
--	select_peripheral(PA(11), PERIPH_A, 0);	/* CMD	 */
--	select_peripheral(PA(12), PERIPH_A, 0);	/* DATA0 */
--	select_peripheral(PA(13), PERIPH_A, 0);	/* DATA1 */
--	select_peripheral(PA(14), PERIPH_A, 0);	/* DATA2 */
--	select_peripheral(PA(15), PERIPH_A, 0);	/* DATA3 */
-+	/* CLK line is common to both slots */
-+	pioa_mask = 1 << 10;
- 
--	if (gpio_is_valid(data->detect_pin))
--		at32_select_gpio(data->detect_pin, 0);
--	if (gpio_is_valid(data->wp_pin))
--		at32_select_gpio(data->wp_pin, 0);
-+	switch (data->slot[0].bus_width) {
-+	case 4:
-+		pioa_mask |= 1 << 13;		/* DATA1 */
-+		pioa_mask |= 1 << 14;		/* DATA2 */
-+		pioa_mask |= 1 << 15;		/* DATA3 */
-+		/* fall through */
-+	case 1:
-+		pioa_mask |= 1 << 11;		/* CMD	 */
-+		pioa_mask |= 1 << 12;		/* DATA0 */
-+
-+		if (gpio_is_valid(data->slot[0].detect_pin))
-+			at32_select_gpio(data->slot[0].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[0].wp_pin))
-+			at32_select_gpio(data->slot[0].wp_pin, 0);
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
-+	piob_mask = 0;
-+
-+	switch (data->slot[1].bus_width) {
-+	case 4:
-+		piob_mask |= 1 <<  8;		/* DATA1 */
-+		piob_mask |= 1 <<  9;		/* DATA2 */
-+		piob_mask |= 1 << 10;		/* DATA3 */
-+		/* fall through */
-+	case 1:
-+		piob_mask |= 1 <<  6;		/* CMD	 */
-+		piob_mask |= 1 <<  7;		/* DATA0 */
-+		select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
-+
-+		if (gpio_is_valid(data->slot[1].detect_pin))
-+			at32_select_gpio(data->slot[1].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[1].wp_pin))
-+			at32_select_gpio(data->slot[1].wp_pin, 0);
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		if (!data->slot[0].bus_width)
-+			goto fail;
-+
-+		data->slot[1].bus_width = 0;
-+		break;
-+	}
- 
- 	atmel_mci0_pclk.dev = &pdev->dev;
- 
-@@ -1353,13 +1455,14 @@ static struct clk atmel_lcdfb0_pixclk = {
- struct platform_device *__init
- at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 		     unsigned long fbmem_start, unsigned long fbmem_len,
--		     unsigned int pin_config)
-+		     u64 pin_mask)
- {
- 	struct platform_device *pdev;
- 	struct atmel_lcdfb_info *info;
- 	struct fb_monspecs *monspecs;
- 	struct fb_videomode *modedb;
- 	unsigned int modedb_size;
-+	u32 portc_mask, portd_mask, porte_mask;
- 
- 	/*
- 	 * Do a deep copy of the fb data, monspecs and modedb. Make
-@@ -1381,76 +1484,21 @@ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 	case 0:
- 		pdev = &atmel_lcdfb0_device;
- 
--		switch (pin_config) {
--		case 0:
--			select_peripheral(PC(19), PERIPH_A, 0);	/* CC	  */
--			select_peripheral(PC(20), PERIPH_A, 0);	/* HSYNC  */
--			select_peripheral(PC(21), PERIPH_A, 0);	/* PCLK	  */
--			select_peripheral(PC(22), PERIPH_A, 0);	/* VSYNC  */
--			select_peripheral(PC(23), PERIPH_A, 0);	/* DVAL	  */
--			select_peripheral(PC(24), PERIPH_A, 0);	/* MODE	  */
--			select_peripheral(PC(25), PERIPH_A, 0);	/* PWR	  */
--			select_peripheral(PC(26), PERIPH_A, 0);	/* DATA0  */
--			select_peripheral(PC(27), PERIPH_A, 0);	/* DATA1  */
--			select_peripheral(PC(28), PERIPH_A, 0);	/* DATA2  */
--			select_peripheral(PC(29), PERIPH_A, 0);	/* DATA3  */
--			select_peripheral(PC(30), PERIPH_A, 0);	/* DATA4  */
--			select_peripheral(PC(31), PERIPH_A, 0);	/* DATA5  */
--			select_peripheral(PD(0),  PERIPH_A, 0);	/* DATA6  */
--			select_peripheral(PD(1),  PERIPH_A, 0);	/* DATA7  */
--			select_peripheral(PD(2),  PERIPH_A, 0);	/* DATA8  */
--			select_peripheral(PD(3),  PERIPH_A, 0);	/* DATA9  */
--			select_peripheral(PD(4),  PERIPH_A, 0);	/* DATA10 */
--			select_peripheral(PD(5),  PERIPH_A, 0);	/* DATA11 */
--			select_peripheral(PD(6),  PERIPH_A, 0);	/* DATA12 */
--			select_peripheral(PD(7),  PERIPH_A, 0);	/* DATA13 */
--			select_peripheral(PD(8),  PERIPH_A, 0);	/* DATA14 */
--			select_peripheral(PD(9),  PERIPH_A, 0);	/* DATA15 */
--			select_peripheral(PD(10), PERIPH_A, 0);	/* DATA16 */
--			select_peripheral(PD(11), PERIPH_A, 0);	/* DATA17 */
--			select_peripheral(PD(12), PERIPH_A, 0);	/* DATA18 */
--			select_peripheral(PD(13), PERIPH_A, 0);	/* DATA19 */
--			select_peripheral(PD(14), PERIPH_A, 0);	/* DATA20 */
--			select_peripheral(PD(15), PERIPH_A, 0);	/* DATA21 */
--			select_peripheral(PD(16), PERIPH_A, 0);	/* DATA22 */
--			select_peripheral(PD(17), PERIPH_A, 0);	/* DATA23 */
--			break;
--		case 1:
--			select_peripheral(PE(0),  PERIPH_B, 0);	/* CC	  */
--			select_peripheral(PC(20), PERIPH_A, 0);	/* HSYNC  */
--			select_peripheral(PC(21), PERIPH_A, 0);	/* PCLK	  */
--			select_peripheral(PC(22), PERIPH_A, 0);	/* VSYNC  */
--			select_peripheral(PE(1),  PERIPH_B, 0);	/* DVAL	  */
--			select_peripheral(PE(2),  PERIPH_B, 0);	/* MODE	  */
--			select_peripheral(PC(25), PERIPH_A, 0);	/* PWR	  */
--			select_peripheral(PE(3),  PERIPH_B, 0);	/* DATA0  */
--			select_peripheral(PE(4),  PERIPH_B, 0);	/* DATA1  */
--			select_peripheral(PE(5),  PERIPH_B, 0);	/* DATA2  */
--			select_peripheral(PE(6),  PERIPH_B, 0);	/* DATA3  */
--			select_peripheral(PE(7),  PERIPH_B, 0);	/* DATA4  */
--			select_peripheral(PC(31), PERIPH_A, 0);	/* DATA5  */
--			select_peripheral(PD(0),  PERIPH_A, 0);	/* DATA6  */
--			select_peripheral(PD(1),  PERIPH_A, 0);	/* DATA7  */
--			select_peripheral(PE(8),  PERIPH_B, 0);	/* DATA8  */
--			select_peripheral(PE(9),  PERIPH_B, 0);	/* DATA9  */
--			select_peripheral(PE(10), PERIPH_B, 0);	/* DATA10 */
--			select_peripheral(PE(11), PERIPH_B, 0);	/* DATA11 */
--			select_peripheral(PE(12), PERIPH_B, 0);	/* DATA12 */
--			select_peripheral(PD(7),  PERIPH_A, 0);	/* DATA13 */
--			select_peripheral(PD(8),  PERIPH_A, 0);	/* DATA14 */
--			select_peripheral(PD(9),  PERIPH_A, 0);	/* DATA15 */
--			select_peripheral(PE(13), PERIPH_B, 0);	/* DATA16 */
--			select_peripheral(PE(14), PERIPH_B, 0);	/* DATA17 */
--			select_peripheral(PE(15), PERIPH_B, 0);	/* DATA18 */
--			select_peripheral(PE(16), PERIPH_B, 0);	/* DATA19 */
--			select_peripheral(PE(17), PERIPH_B, 0);	/* DATA20 */
--			select_peripheral(PE(18), PERIPH_B, 0);	/* DATA21 */
--			select_peripheral(PD(16), PERIPH_A, 0);	/* DATA22 */
--			select_peripheral(PD(17), PERIPH_A, 0);	/* DATA23 */
--			break;
--		default:
--			goto err_invalid_id;
--		}
-+		if (pin_mask == 0ULL)
-+			/* Default to "full" lcdc control signals and 24bit */
-+			pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
-+
-+		/* LCDC on port C */
-+		portc_mask = pin_mask & 0xfff80000;
-+		select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
-+
-+		/* LCDC on port D */
-+		portd_mask = pin_mask & 0x0003ffff;
-+		select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
-+
-+		/* LCDC on port E */
-+		porte_mask = (pin_mask >> 32) & 0x0007ffff;
-+		select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
- 
- 		clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
- 		clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-@@ -1499,6 +1547,7 @@ static struct clk atmel_pwm0_mck = {
- struct platform_device *__init at32_add_device_pwm(u32 mask)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (!mask)
- 		return NULL;
-@@ -1514,14 +1563,21 @@ struct platform_device *__init at32_add_device_pwm(u32 mask)
- 	if (platform_device_add_data(pdev, &mask, sizeof(mask)))
- 		goto out_free_pdev;
- 
-+	pin_mask = 0;
- 	if (mask & (1 << 0))
--		select_peripheral(PA(28), PERIPH_A, 0);
-+		pin_mask |= (1 << 28);
- 	if (mask & (1 << 1))
--		select_peripheral(PA(29), PERIPH_A, 0);
-+		pin_mask |= (1 << 29);
-+	if (pin_mask > 0)
-+		select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
-+	pin_mask = 0;
- 	if (mask & (1 << 2))
--		select_peripheral(PA(21), PERIPH_B, 0);
-+		pin_mask |= (1 << 21);
- 	if (mask & (1 << 3))
--		select_peripheral(PA(22), PERIPH_B, 0);
-+		pin_mask |= (1 << 22);
-+	if (pin_mask > 0)
-+		select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
- 
- 	atmel_pwm0_mck.dev = &pdev->dev;
- 
-@@ -1562,52 +1618,65 @@ struct platform_device *__init
- at32_add_device_ssc(unsigned int id, unsigned int flags)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask = 0;
- 
- 	switch (id) {
- 	case 0:
- 		pdev = &ssc0_device;
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PA(21), PERIPH_A, 0);	/* RF */
-+			pin_mask |= (1 << 21);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PA(22), PERIPH_A, 0);	/* RK */
-+			pin_mask |= (1 << 22);	/* RK */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PA(23), PERIPH_A, 0);	/* TK */
-+			pin_mask |= (1 << 23);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PA(24), PERIPH_A, 0);	/* TF */
-+			pin_mask |= (1 << 24);	/* TF */
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PA(25), PERIPH_A, 0);	/* TD */
-+			pin_mask |= (1 << 25);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PA(26), PERIPH_A, 0);	/* RD */
-+			pin_mask |= (1 << 26);	/* RD */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 	case 1:
- 		pdev = &ssc1_device;
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PA(0), PERIPH_B, 0);	/* RF */
-+			pin_mask |= (1 << 0);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PA(1), PERIPH_B, 0);	/* RK */
-+			pin_mask |= (1 << 1);	/* RK */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PA(2), PERIPH_B, 0);	/* TK */
-+			pin_mask |= (1 << 2);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PA(3), PERIPH_B, 0);	/* TF */
-+			pin_mask |= (1 << 3);	/* TF */
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PA(4), PERIPH_B, 0);	/* TD */
-+			pin_mask |= (1 << 4);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PA(5), PERIPH_B, 0);	/* RD */
-+			pin_mask |= (1 << 5);	/* RD */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
-+
- 		break;
- 	case 2:
- 		pdev = &ssc2_device;
- 		if (flags & ATMEL_SSC_TD)
--			select_peripheral(PB(13), PERIPH_A, 0);	/* TD */
-+			pin_mask |= (1 << 13);	/* TD */
- 		if (flags & ATMEL_SSC_RD)
--			select_peripheral(PB(14), PERIPH_A, 0);	/* RD */
-+			pin_mask |= (1 << 14);	/* RD */
- 		if (flags & ATMEL_SSC_TK)
--			select_peripheral(PB(15), PERIPH_A, 0);	/* TK */
-+			pin_mask |= (1 << 15);	/* TK */
- 		if (flags & ATMEL_SSC_TF)
--			select_peripheral(PB(16), PERIPH_A, 0);	/* TF */
-+			pin_mask |= (1 << 16);	/* TF */
- 		if (flags & ATMEL_SSC_RF)
--			select_peripheral(PB(17), PERIPH_A, 0);	/* RF */
-+			pin_mask |= (1 << 17);	/* RF */
- 		if (flags & ATMEL_SSC_RK)
--			select_peripheral(PB(18), PERIPH_A, 0);	/* RK */
-+			pin_mask |= (1 << 18);	/* RK */
-+
-+		if (pin_mask > 0)
-+			select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
-+
- 		break;
- 	default:
- 		return NULL;
-@@ -1745,14 +1814,15 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		unsigned int cs, unsigned int extint)
- {
- 	static unsigned int extint_pin_map[4] __initdata = {
--		GPIO_PIN_PB(25),
--		GPIO_PIN_PB(26),
--		GPIO_PIN_PB(27),
--		GPIO_PIN_PB(28),
-+		(1 << 25),
-+		(1 << 26),
-+		(1 << 27),
-+		(1 << 28),
- 	};
- 	static bool common_pins_initialized __initdata = false;
- 	unsigned int extint_pin;
- 	int ret;
-+	u32 pin_mask;
- 
- 	if (extint >= ARRAY_SIZE(extint_pin_map))
- 		return -EINVAL;
-@@ -1766,7 +1836,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		if (ret)
- 			return ret;
- 
--		select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
-+		/* NCS4   -> OE_N  */
-+		select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
- 		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
- 		break;
- 	case 5:
-@@ -1776,7 +1847,8 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 		if (ret)
- 			return ret;
- 
--		select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
-+		/* NCS5   -> OE_N  */
-+		select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
- 		hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
- 		break;
- 	default:
-@@ -1784,14 +1856,17 @@ static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- 	}
- 
- 	if (!common_pins_initialized) {
--		select_peripheral(PE(19), PERIPH_A, 0);	/* CFCE1  -> CS0_N */
--		select_peripheral(PE(20), PERIPH_A, 0);	/* CFCE2  -> CS1_N */
--		select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
--		select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
-+		pin_mask  = (1 << 19);	/* CFCE1  -> CS0_N */
-+		pin_mask |= (1 << 20);	/* CFCE2  -> CS1_N */
-+		pin_mask |= (1 << 23);	/* CFRNW  -> DIR   */
-+		pin_mask |= (1 << 24);	/* NWAIT  <- IORDY */
-+
-+		select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
-+
- 		common_pins_initialized = true;
- 	}
- 
--	at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
-+	select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
- 
- 	pdev->resource[1].start = EIM_IRQ_BASE + extint;
- 	pdev->resource[1].end = pdev->resource[1].start;
-@@ -1930,6 +2005,7 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
- {
- 	struct platform_device *pdev;
- 	struct ac97c_platform_data _data;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -1956,10 +2032,10 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
- 				sizeof(struct ac97c_platform_data)))
- 		goto fail;
- 
--	select_peripheral(PB(20), PERIPH_B, 0);	/* SDO	*/
--	select_peripheral(PB(21), PERIPH_B, 0);	/* SYNC	*/
--	select_peripheral(PB(22), PERIPH_B, 0);	/* SCLK	*/
--	select_peripheral(PB(23), PERIPH_B, 0);	/* SDI	*/
-+	pin_mask  = (1 << 20) | (1 << 21);	/* SDO & SYNC */
-+	pin_mask |= (1 << 22) | (1 << 23);	/* SCLK & SDI */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
- 
- 	/* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
- 	if (data->reset_pin != GPIO_PIN_NONE)
-@@ -2001,6 +2077,7 @@ static struct clk abdac0_sample_clk = {
- struct platform_device *__init at32_add_device_abdac(unsigned int id)
- {
- 	struct platform_device *pdev;
-+	u32 pin_mask;
- 
- 	if (id != 0)
- 		return NULL;
-@@ -2013,10 +2090,10 @@ struct platform_device *__init at32_add_device_abdac(unsigned int id)
- 				ARRAY_SIZE(abdac0_resource)))
- 		goto err_add_resources;
- 
--	select_peripheral(PB(20), PERIPH_A, 0);	/* DATA1	*/
--	select_peripheral(PB(21), PERIPH_A, 0);	/* DATA0	*/
--	select_peripheral(PB(22), PERIPH_A, 0);	/* DATAN1	*/
--	select_peripheral(PB(23), PERIPH_A, 0);	/* DATAN0	*/
-+	pin_mask  = (1 << 20) | (1 << 22);	/* DATA1 & DATAN1 */
-+	pin_mask |= (1 << 21) | (1 << 23);	/* DATA0 & DATAN0 */
-+
-+	select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
- 
- 	abdac0_pclk.dev = &pdev->dev;
- 	abdac0_sample_clk.dev = &pdev->dev;
-@@ -2073,7 +2150,7 @@ static struct clk gclk4 = {
- 	.index		= 4,
- };
- 
--struct clk *at32_clock_list[] = {
-+static __initdata struct clk *init_clocks[] = {
- 	&osc32k,
- 	&osc0,
- 	&osc1,
-@@ -2137,7 +2214,6 @@ struct clk *at32_clock_list[] = {
- 	&gclk3,
- 	&gclk4,
- };
--unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
- 
- void __init setup_platform(void)
- {
-@@ -2168,14 +2244,19 @@ void __init setup_platform(void)
- 	genclk_init_parent(&abdac0_sample_clk);
- 
- 	/*
--	 * Turn on all clocks that have at least one user already, and
--	 * turn off everything else. We only do this for module
--	 * clocks, and even though it isn't particularly pretty to
--	 * check the address of the mode function, it should do the
--	 * trick...
-+	 * Build initial dynamic clock list by registering all clocks
-+	 * from the array.
-+	 * At the same time, turn on all clocks that have at least one
-+	 * user already, and turn off everything else. We only do this
-+	 * for module clocks, and even though it isn't particularly
-+	 * pretty to  check the address of the mode function, it should
-+	 * do the trick...
- 	 */
--	for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
--		struct clk *clk = at32_clock_list[i];
-+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
-+		struct clk *clk = init_clocks[i];
-+
-+		/* first, register clock */
-+		at32_clk_register(clk);
- 
- 		if (clk->users == 0)
- 			continue;
-@@ -2203,6 +2284,11 @@ void __init setup_platform(void)
- 	at32_init_pio(&pio4_device);
- }
- 
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
- struct gen_pool *sram_pool;
- 
- static int __init sram_init(void)
-diff --git a/arch/avr32/mach-at32ap/at32ap720x.c b/arch/avr32/mach-at32ap/at32ap720x.c
-new file mode 100644
-index 0000000..0cb675a
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/at32ap720x.c
-@@ -0,0 +1,2303 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dw_dmac.h>
-+#include <linux/errno.h>
-+#include <linux/fb.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm.h>
-+#include <linux/spinlock.h>
-+#include <linux/spi/atmel_spi.h>
-+#include <linux/spi/spi.h>
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#include <asm/ast_regs.h>
-+#include <asm/atmel-mci.h>
-+
-+#include <mach/at32ap720x.h>
-+#include <mach/board.h>
-+#include <mach/hmatrix.h>
-+#include <mach/init.h>
-+#include <mach/pm.h>
-+#include <mach/portmux.h>
-+#include <mach/sram.h>
-+
-+#include "clock.h"
-+#include "gpio-v2.h"
-+#include "pm-v3.h"
-+#include "sdc.h"
-+
-+#define PBMEM(base)					\
-+	{						\
-+		.start		= base,			\
-+		.end		= base + 0x3ff,		\
-+		.flags		= IORESOURCE_MEM,	\
-+	}
-+#define IRQ(num)					\
-+	{						\
-+		.start		= num,			\
-+		.end		= num,			\
-+		.flags		= IORESOURCE_IRQ,	\
-+	}
-+
-+#define select_peripheral(port, pin_mask, periph, flags)	\
-+	at32_select_periph(GPIO_##port##_BASE, pin_mask,	\
-+			   GPIO_##periph, flags)
-+
-+#define DEV_CLK(_name, devname, bus, _index)			\
-+static struct clk devname##_##_name = {				\
-+	.name		= #_name,				\
-+	.dev		= &devname##_device.dev,		\
-+	.parent		= &bus##_clk,				\
-+	.mode		= bus##_clk_mode,			\
-+	.get_rate	= bus##_clk_get_rate,			\
-+	.index		= _index,				\
-+}
-+
-+static DEFINE_SPINLOCK(pm_lock);
-+
-+static unsigned long rcosc_get_rate(struct clk *clk)
-+{
-+	return 32768;
-+}
-+
-+static unsigned long osc_get_rate(struct clk *clk)
-+{
-+	return at32_board_osc_rates[clk->index];
-+}
-+
-+static void osc32_mode(struct clk *clk, int enabled)
-+{
-+	/* We never disable the 32 kHz oscillator */
-+	if (!enabled)
-+		return;
-+
-+	/* If it's already running, we're done. */
-+	if (pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY))
-+		return;
-+
-+	/* Enable it, unless someone did it for us already */
-+	if (!(sdc_readl(OSCCTRL32) & SDC_BIT(OSCCTRL32_OSC32EN))) {
-+		u32 value;
-+
-+		value = SDC_BF(OSCCTRL32_STARTUP, 5)
-+			| SDC_BF(OSCCTRL32_MODE, 0xd)
-+			| SDC_BIT(OSCCTRL32_OSC32EN);
-+
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0x55));
-+		sdc_writel(OSCCTRL32, value | SDC_BF(OSCCTRL32_KEY, 0xaa));
-+	}
-+
-+	pr_info("Waiting for 32 kHz crystal oscillator to start...\n");
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_OSC32RDY)))
-+		cpu_relax();
-+}
-+
-+static void oscn_mode(struct clk *clk, int enabled)
-+{
-+	unsigned int	i = clk->index;
-+	u32		mcctrl;
-+
-+	BUG_ON(i > 2);
-+
-+	/* Let's keep oscillators running for now... */
-+	if (!enabled)
-+		goto out;
-+
-+	/* If it's already running, we're done */
-+	if (pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i))
-+		goto out;
-+
-+	/* Enable it, unless someone did it for us already */
-+	mcctrl = pm_readl(MCCTRL);
-+	if (!(mcctrl & (PM_BIT(MCCTRL_OSC0EN) << i))) {
-+		/* TODO: Make OSC startup parameters configurable */
-+		pm_writel(OSCCTRL[i], PM_BF(OSCCTRLx_STARTUP, 5)
-+				| PM_BF(OSCCTRLx_MODE, 0xa));
-+		pm_writel(MCCTRL, mcctrl | (PM_BIT(MCCTRL_OSC0EN) << i));
-+	}
-+
-+	pr_debug("clk %s: waiting for clock to become ready...\n", clk->name);
-+	pr_debug("clk %s: MCCTRL=%08x OSCCTRL%u=%08x\n", clk->name,
-+			pm_readl(MCCTRL), i, pm_readl(OSCCTRL[i]));
-+
-+	while (!(pm_readl(POSCSR) & (PM_BIT(POSCSR_OSC0RDY) << i)))
-+		cpu_relax();
-+
-+out:
-+	pr_debug("clk %s: running\n", clk->name);
-+}
-+
-+static struct clk rcosc = {
-+	.name		= "rcosc",
-+	.get_rate	= rcosc_get_rate,
-+	.users		= 1,
-+};
-+static struct clk osc0 = {
-+	.name		= "osc0",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk osc1 = {
-+	.name		= "osc1",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 1,
-+};
-+static struct clk osc2 = {
-+	.name		= "osc2",
-+	.get_rate	= osc_get_rate,
-+	.mode		= oscn_mode,
-+	.index		= 2,
-+};
-+static struct clk osc32 = {
-+	.name		= "osc32k",
-+	.get_rate	= osc_get_rate,
-+	.mode		= osc32_mode,
-+	.index		= 3,
-+};
-+
-+static void pll_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long timeout;
-+	unsigned int index = clk->index;
-+	u32 status;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[index]);
-+
-+	if (enabled) {
-+		if (PM_BFEXT(PLLx_PLLMUL, ctrl) <= 1) {
-+			pr_debug("clk %s: failed to enable, rate not set\n",
-+					clk->name);
-+			return;
-+		}
-+
-+		ctrl |= PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+
-+		pr_debug("clk %s: waiting for lock...\n", clk->name);
-+		for (timeout = 10000; timeout; timeout--) {
-+			status = pm_readl(POSCSR);
-+			if (status & (PM_BIT(POSCSR_LOCK0) << index))
-+				break;
-+			udelay(10);
-+		}
-+
-+		if (!(status & (PM_BIT(POSCSR_LOCK0) << index)))
-+			pr_err("clk %s: timeout waiting for lock\n",
-+					clk->name);
-+		else
-+			pr_debug("clk %s: running\n", clk->name);
-+	} else {
-+		ctrl &= ~PM_BIT(PLLx_PLLEN);
-+		pm_writel(PLL[index], ctrl);
-+		pr_debug("clk %s: stopped\n", clk->name);
-+	}
-+}
-+
-+
-+static unsigned long pll_get_rate(struct clk *clk)
-+{
-+	unsigned long rate;
-+	unsigned int div;
-+	unsigned int mul;
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[clk->index]);
-+
-+	div = PM_BFEXT(PLLx_PLLDIV, ctrl);
-+	mul = PM_BFEXT(PLLx_PLLMUL, ctrl);
-+
-+	rate = clk->parent->get_rate(clk->parent);
-+	if (div != 0)
-+		rate = (rate + div / 2) / div;
-+	else
-+		rate = rate * 2;
-+	rate *= mul;
-+
-+	if (ctrl & PM_BF(PLLx_PLLOPT, 4))
-+		rate = (rate + 1) / 2;
-+
-+	return rate;
-+}
-+
-+static long pll_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long mul_best_fit = 0;
-+	unsigned long div;
-+	unsigned long div_min;
-+	unsigned long div_max;
-+	unsigned long div_best_fit = 0;
-+	unsigned long base;
-+	unsigned long fvco;
-+	unsigned long actual = 0;
-+	unsigned long rate_error_prev = ~0UL;
-+	u32 ctrl;
-+
-+	/* Rate must be between 25 MHz and 400 Mhz. */
-+	if (rate < 25000000UL || rate > 400000000UL)
-+		return -EINVAL;
-+
-+	base = clk->parent->get_rate(clk->parent);
-+
-+	/* PLL input frequency must be between 10 MHz and 200 MHz. */
-+	div_min = DIV_ROUND_UP(base, 200000000UL);
-+	div_max = base / 10000000UL;
-+
-+	if (div_max < div_min)
-+		return -EINVAL;
-+
-+	for (div = div_min; div <= div_max; div++) {
-+		unsigned long mul;
-+		unsigned long pll_in;
-+		unsigned long rate_error;
-+
-+		pll_in = (base + div / 2) / div;
-+		mul = (rate + pll_in / 2) / pll_in;
-+
-+		if (mul < 1)
-+			continue;
-+
-+		actual = pll_in * mul;
-+		rate_error = abs(actual - rate);
-+
-+		if (rate_error < rate_error_prev) {
-+			mul_best_fit = mul;
-+			div_best_fit = div;
-+			rate_error_prev = rate_error;
-+		}
-+
-+		if (rate_error == 0)
-+			break;
-+	}
-+
-+	if (div_best_fit == 0)
-+		return -EINVAL;
-+
-+	ctrl = 0;
-+	fvco = actual;
-+
-+	/*
-+	 * MUL=1 is not allowed. So we must double it and set the
-+	 * divide-by-two bit.
-+	 */
-+	if (mul_best_fit == 1) {
-+		ctrl |= PM_BF(PLLx_PLLOPT, 4);
-+		mul_best_fit *= 2;
-+		fvco = actual * 2;
-+	}
-+
-+	if (fvco > 200000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 3);
-+	else if (fvco > 100000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 2);
-+	else if (fvco > 50000000)
-+		ctrl |= PM_BF(PLLx_PLLOPT, 1);
-+
-+	ctrl |= PM_BF(PLLx_PLLCOUNT, 31);
-+	ctrl |= PM_BF(PLLx_PLLMUL, mul_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLDIV, div_best_fit);
-+	ctrl |= PM_BF(PLLx_PLLOSC, clk->parent->index);
-+
-+	if (apply) {
-+		if (actual != rate)
-+			return -EINVAL;
-+		if (clk->users > 0)
-+			return -EBUSY;
-+		pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
-+				clk->name, rate, actual);
-+		pm_writel(PLL[clk->index], ctrl);
-+	}
-+
-+	return actual;
-+}
-+
-+static int pll_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int index = clk->index;
-+	u32 ctrl;
-+
-+	if (clk->users > 0)
-+		return -EBUSY;
-+
-+	ctrl = pm_readl(PLL[index]);
-+	BUG_ON(ctrl & PM_BIT(PLLx_PLLEN));
-+
-+	ctrl = PM_BFINS(PLLx_PLLOSC, parent->index, ctrl);
-+	pm_writel(PLL[index], ctrl);
-+
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+static struct clk pll0 = {
-+	.name		= "pll0",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 1,
-+	.index		= 0,
-+};
-+static struct clk pll1 = {
-+	.name		= "pll1",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 1,
-+};
-+static struct clk pll2 = {
-+	.name		= "pll2",
-+	.mode		= pll_mode,
-+	.get_rate	= pll_get_rate,
-+	.set_rate	= pll_set_rate,
-+	.set_parent	= pll_set_parent,
-+	.users		= 0,
-+	.index		= 2,
-+};
-+
-+/*
-+ * The main clock can be either rcosc, osc0 or pll0.  The boot loader
-+ * may have chosen one for us, so we don't really know which one until
-+ * we have a look at the PM registers.
-+ */
-+static struct clk *main_clock;
-+
-+/*
-+ * Synchronous clocks are generated from the main clock. The clocks
-+ * must satisfy the constraint
-+ *   fCPU >= fHSB >= fPB
-+ * i.e. each clock must not be faster than its parent.
-+ */
-+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
-+{
-+	return main_clock->get_rate(main_clock) >> shift;
-+};
-+
-+static void cpu_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(CPUMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(CPUMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long cpu_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_CPUDIV))
-+		shift = PM_BFEXT(CKSEL_CPUSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	u32 control;
-+	unsigned long parent_rate, child_div, actual_rate, div;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(CKSEL);
-+
-+	if (control & PM_BIT(CKSEL_HSBDIV))
-+		child_div = 1 << (PM_BFEXT(CKSEL_HSBSEL, control) + 1);
-+	else
-+		child_div = 1;
-+
-+	if (rate > 3 * (parent_rate / 4) || child_div == 1) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(CKSEL_CPUDIV);
-+	} else {
-+		unsigned int cpusel;
-+		div = (parent_rate + rate / 2) / rate;
-+		if (div > child_div)
-+			div = child_div;
-+		cpusel = (div > 1) ? (fls(div) - 2) : 0;
-+		control = PM_BIT(CKSEL_CPUDIV)
-+			| PM_BFINS(CKSEL_CPUSEL, cpusel, control);
-+		actual_rate = parent_rate / (1 << (cpusel + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply) {
-+		while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_CKRDY)))
-+			cpu_relax();
-+
-+		pm_writel(CKSEL, control);
-+	}
-+
-+	return actual_rate;
-+}
-+
-+static void hsb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(HSBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(HSBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long hsb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_HSBDIV))
-+		shift = PM_BFEXT(CKSEL_HSBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pba_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBAMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBAMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pba_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBADIV))
-+		shift = PM_BFEXT(CKSEL_PBASEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pbb_clk_mode(struct clk *clk, int enabled)
-+{
-+	unsigned long flags;
-+	u32 mask;
-+
-+	spin_lock_irqsave(&pm_lock, flags);
-+
-+	while (!(pm_readl(POSCSR) & PM_BIT(POSCSR_MSKRDY)))
-+		cpu_relax();
-+
-+	mask = pm_readl(PBBMASK);
-+	if (enabled)
-+		mask |= 1 << clk->index;
-+	else
-+		mask &= ~(1 << clk->index);
-+	pm_writel(PBBMASK, mask);
-+	spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pbb_clk_get_rate(struct clk *clk)
-+{
-+	unsigned long cksel, shift = 0;
-+
-+	cksel = pm_readl(CKSEL);
-+	if (cksel & PM_BIT(CKSEL_PBBDIV))
-+		shift = PM_BFEXT(CKSEL_PBBSEL, cksel) + 1;
-+
-+	return bus_clk_get_rate(clk, shift);
-+}
-+
-+static struct clk cpu_clk = {
-+	.name		= "cpu",
-+	.get_rate	= cpu_clk_get_rate,
-+	.set_rate	= cpu_clk_set_rate,
-+	.users		= 1,
-+};
-+static struct clk hsb_clk = {
-+	.name		= "hsb",
-+	.parent		= &cpu_clk,
-+	.get_rate	= hsb_clk_get_rate,
-+};
-+static struct clk pba_clk = {
-+	.name		= "pba",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pba_clk_get_rate,
-+	.users		= 1,
-+	.index		= 1,
-+};
-+static struct clk pbb_clk = {
-+	.name		= "pbb",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 2,
-+};
-+static struct clk pbc_clk = {
-+	.name		= "pbc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 3,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  Generic Clocks
-+ * -------------------------------------------------------------------- */
-+
-+/* Mapping from GCCTRL:OSCSEL values to parent clocks */
-+static struct clk *const genclk_parent[] = {
-+	&rcosc,
-+	&osc32,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+};
-+
-+#define NR_GENERIC_CLOCKS	8
-+
-+static void genclk_mode(struct clk *clk, int enabled)
-+{
-+	u32 control;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (enabled)
-+		control |= PM_BIT(GCCTRL_CEN);
-+	else
-+		control &= PM_BIT(GCCTRL_CEN);
-+	pm_writel(GCCTRL[clk->index], control);
-+}
-+
-+static unsigned long genclk_get_rate(struct clk *clk)
-+{
-+	u32 control;
-+	unsigned long div = 1;
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	if (control & PM_BIT(GCCTRL_DIVEN))
-+		div = 2 * (PM_BFEXT(GCCTRL_DIV, control) + 1);
-+
-+	return clk->parent->get_rate(clk->parent) / div;
-+}
-+
-+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+	unsigned long	parent_rate;
-+	unsigned long	actual_rate;
-+	unsigned long	div;
-+	u32		control;
-+
-+	parent_rate = clk->parent->get_rate(clk->parent);
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	if (rate > 3 * parent_rate / 4) {
-+		actual_rate = parent_rate;
-+		control &= ~PM_BIT(GCCTRL_DIVEN);
-+	} else {
-+		div = (parent_rate + rate) / (2 * rate) - 1;
-+		control = PM_BFINS(GCCTRL_DIV, div, control)
-+				| PM_BIT(GCCTRL_DIVEN);
-+		actual_rate = parent_rate / (2 * (div + 1));
-+	}
-+
-+	pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+			clk->name, rate, actual_rate);
-+
-+	if (apply)
-+		pm_writel(GCCTRL[clk->index], control);
-+
-+	return actual_rate;
-+}
-+
-+static int genclk_set_parent(struct clk *clk, struct clk *parent)
-+{
-+	unsigned int	i;
-+	u32		control;
-+
-+	pr_debug("clk %s: new parent %s (was %s)\n",
-+			clk->name, parent->name,
-+			clk->parent ? clk->parent->name : "<none>");
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+
-+	for (i = 0; i < ARRAY_SIZE(genclk_parent); i++) {
-+		if (parent == genclk_parent[i]) {
-+			control = PM_BFINS(GCCTRL_OSCSEL, i, control);
-+			break;
-+		}
-+	}
-+
-+	if (i >= ARRAY_SIZE(genclk_parent))
-+		return -EINVAL;
-+
-+	pm_writel(GCCTRL[clk->index], control);
-+	clk->parent = parent;
-+
-+	return 0;
-+}
-+
-+#define DEFINE_GCLK(_name, i)				\
-+	static struct clk _name = {			\
-+		.name		= #_name,		\
-+		.mode		= genclk_mode,		\
-+		.get_rate	= genclk_get_rate,	\
-+		.set_rate	= genclk_set_rate,	\
-+		.set_parent	= genclk_set_parent,	\
-+		.index		= i,			\
-+	}
-+
-+DEFINE_GCLK(gclk0, 0);
-+DEFINE_GCLK(gclk1, 1);
-+DEFINE_GCLK(gclk2, 2);
-+DEFINE_GCLK(gclk3, 3);
-+DEFINE_GCLK(gclk4, 4);
-+DEFINE_GCLK(gclk5, 5);
-+
-+static void __init genclk_init_parent(struct clk *clk)
-+{
-+	unsigned int	parent;
-+	u32		control;
-+
-+	BUG_ON(clk->index > NR_GENERIC_CLOCKS);
-+
-+	control = pm_readl(GCCTRL[clk->index]);
-+	parent = PM_BFEXT(GCCTRL_OSCSEL, control);
-+	if (parent >= ARRAY_SIZE(genclk_parent)) {
-+		/* Current parent is invalid. Reset to a sane value */
-+		parent = 0;
-+		control = PM_BF(GCCTRL_OSCSEL, parent);
-+	}
-+
-+	clk->parent = genclk_parent[parent];
-+}
-+
-+
-+/* --------------------------------------------------------------------
-+ *  System peripherals
-+ * -------------------------------------------------------------------- */
-+static struct dw_dma_platform_data dw_dmac0_data = {
-+	.nr_channels	= 4,
-+};
-+static struct pdca_pdata pdca_data = {
-+	.nr_channels	= 20,
-+};
-+
-+static struct resource intc_resource[] = {
-+	PBMEM(0xffd00000),
-+};
-+static struct resource pm_resource[] = {
-+	PBMEM(0xffd00400),
-+	IRQ(10),
-+};
-+static struct resource sdc_resource[] = {
-+	PBMEM(0xffd00800),
-+	IRQ(45),
-+};
-+static struct resource ast0_resource[] = {
-+	PBMEM(0xffd00c00),
-+	IRQ(11),
-+};
-+static struct resource ast1_resource[] = {
-+	PBMEM(0xffd01000),
-+	IRQ(12),
-+};
-+static struct resource wdt_resource[] = {
-+	PBMEM(0xffd01400),
-+};
-+static struct resource gpio_resource[] = {
-+	PBMEM(0xffd02000),
-+	{
-+		.start	= 16,
-+		.end	= 19,
-+		.flags	= IORESOURCE_IRQ,
-+	},
-+};
-+static struct resource pdca_resource[] = {
-+	{
-+		.start	= 0xffe00000,
-+		.end	= 0xffe01fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(1),
-+};
-+static struct resource smc_resource[] = {
-+	PBMEM(0xffe04400),
-+};
-+static struct resource dw_dmac0_resource[] = {
-+	{
-+		.start	= 0xff100000,
-+		.end	= 0xff1003ff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(5),
-+};
-+
-+struct platform_device at32_intc0_device = {
-+	.name		= "intc",
-+	.resource	= intc_resource,
-+	.num_resources	= ARRAY_SIZE(intc_resource),
-+};
-+static struct platform_device pm_device = {
-+	.name		= "pm",
-+	.resource	= pm_resource,
-+	.num_resources	= ARRAY_SIZE(pm_resource),
-+};
-+static struct platform_device sdc_device = {
-+	.name		= "sdc",
-+	.resource	= sdc_resource,
-+	.num_resources	= ARRAY_SIZE(sdc_resource),
-+};
-+static struct platform_device ast0_device = {
-+	.name		= "rtc-ast",
-+	.id		= 0,
-+	.resource	= ast0_resource,
-+	.num_resources	= ARRAY_SIZE(ast0_resource),
-+};
-+static struct platform_device ast1_device = {
-+	.name		= "timer-ast",
-+	.id		= 1,
-+	.resource	= ast1_resource,
-+	.num_resources	= ARRAY_SIZE(ast1_resource),
-+};
-+static struct platform_device wdt_device = {
-+	.name		= "at32_wdt",
-+	.id		= 0,
-+	.resource	= wdt_resource,
-+	.num_resources	= ARRAY_SIZE(wdt_resource),
-+};
-+static struct platform_device gpio_device = {
-+	.name		= "gpio",
-+	.id		= 0,
-+	.resource	= gpio_resource,
-+	.num_resources	= ARRAY_SIZE(gpio_resource),
-+};
-+static struct platform_device pdca_device = {
-+	.dev.platform_data = &pdca_data,
-+	.name		= "atmel_pdca",
-+	.id		= 0,
-+	.resource	= pdca_resource,
-+	.num_resources	= ARRAY_SIZE(pdca_resource),
-+};
-+static struct platform_device smc_device = {
-+	.name		= "smc",
-+	.id		= 0,
-+	.resource	= smc_resource,
-+	.num_resources	= ARRAY_SIZE(smc_resource),
-+};
-+static struct platform_device dw_dmac0_device = {
-+	.dev.platform_data = &dw_dmac0_data,
-+	.name		= "dw_dmac",
-+	.id		= 0,
-+	.resource	= dw_dmac0_resource,
-+	.num_resources	= ARRAY_SIZE(dw_dmac0_resource),
-+};
-+
-+DEV_CLK(pclk, at32_intc0, pba, 0);
-+DEV_CLK(pclk, pm, pba, 1);
-+DEV_CLK(pclk, sdc, pba, 2);
-+DEV_CLK(pclk, ast0, pba, 3);
-+DEV_CLK(pclk, ast1, pba, 4);
-+DEV_CLK(pclk, wdt, pba, 5);
-+DEV_CLK(pclk, gpio, pba, 8);
-+DEV_CLK(hclk, pdca, hsb, 9);
-+DEV_CLK(pclk, pdca, pbb, 0);
-+DEV_CLK(pclk, smc, pbb, 5);
-+DEV_CLK(hclk, dw_dmac0, hsb, 10);
-+
-+static struct clk ebi_hclk = {
-+	.name		= "ebi_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+};
-+static struct clk hramc_clk = {
-+	.name		= "hramc",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 4,
-+};
-+static struct clk sdramc_clk = {
-+	.name		= "sdramc_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.users		= 1,
-+	.index		= 6,
-+};
-+
-+static int __init system_device_init(void)
-+{
-+	platform_device_register(&at32_intc0_device);
-+	platform_device_register(&pm_device);
-+	platform_device_register(&sdc_device);
-+	platform_device_register(&ast0_device);
-+	platform_device_register(&ast1_device);
-+	platform_device_register(&wdt_device);
-+	platform_device_register(&gpio_device);
-+	platform_device_register(&pdca_device);
-+	platform_device_register(&smc_device);
-+	platform_device_register(&dw_dmac0_device);
-+
-+	return 0;
-+}
-+core_initcall(system_device_init);
-+
-+/* --------------------------------------------------------------------
-+ * HMATRIX
-+ * -------------------------------------------------------------------- */
-+
-+struct clk at32_hmatrix_clk = {
-+	.name		= "hmatrix_clk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 8,
-+	.users		= 0,
-+};
-+
-+/* --------------------------------------------------------------------
-+ *  USART
-+ * -------------------------------------------------------------------- */
-+
-+static struct atmel_uart_data atmel_usart0_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart0_resource[] = {
-+	PBMEM(0xffd03000),
-+	IRQ(24),
-+};
-+static struct platform_device atmel_usart0_device = {
-+	.name		= "atmel_usart",
-+	.id		= 0,
-+	.dev		= {
-+		.platform_data	= &atmel_usart0_data,
-+	},
-+	.resource	= atmel_usart0_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart0_resource),
-+};
-+DEV_CLK(usart, atmel_usart0, pba, 9);
-+
-+static struct atmel_uart_data atmel_usart1_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart1_resource[] = {
-+	PBMEM(0xffd03400),
-+	IRQ(25),
-+};
-+static struct platform_device atmel_usart1_device = {
-+	.name		= "atmel_usart",
-+	.id		= 1,
-+	.dev		= {
-+		.platform_data	= &atmel_usart1_data,
-+	},
-+	.resource	= atmel_usart1_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart1_resource),
-+};
-+DEV_CLK(usart, atmel_usart1, pba, 10);
-+
-+static struct atmel_uart_data atmel_usart2_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart2_resource[] = {
-+	PBMEM(0xffd03800),
-+	IRQ(26),
-+};
-+static struct platform_device atmel_usart2_device = {
-+	.name		= "atmel_usart",
-+	.id		= 2,
-+	.dev		= {
-+		.platform_data	= &atmel_usart2_data,
-+	},
-+	.resource	= atmel_usart2_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart2_resource),
-+};
-+DEV_CLK(usart, atmel_usart2, pba, 11);
-+
-+static struct atmel_uart_data atmel_usart3_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart3_resource[] = {
-+	PBMEM(0xffd03c00),
-+	IRQ(27),
-+};
-+static struct platform_device atmel_usart3_device = {
-+	.name		= "atmel_usart",
-+	.id		= 3,
-+	.dev		= {
-+		.platform_data	= &atmel_usart3_data,
-+	},
-+	.resource	= atmel_usart3_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart3_resource),
-+};
-+DEV_CLK(usart, atmel_usart3, pba, 12);
-+
-+static struct atmel_uart_data atmel_usart4_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart4_resource[] = {
-+	PBMEM(0xffd04000),
-+	IRQ(28),
-+};
-+static struct platform_device atmel_usart4_device = {
-+	.name		= "atmel_usart",
-+	.id		= 4,
-+	.dev		= {
-+		.platform_data	= &atmel_usart4_data,
-+	},
-+	.resource	= atmel_usart4_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart4_resource),
-+};
-+DEV_CLK(usart, atmel_usart4, pba, 13);
-+
-+static struct atmel_uart_data atmel_usart5_data = {
-+	.use_dma_tx	= 0,
-+	.use_dma_rx	= 0,
-+};
-+static struct resource atmel_usart5_resource[] = {
-+	PBMEM(0xffd04400),
-+	IRQ(29),
-+};
-+static struct platform_device atmel_usart5_device = {
-+	.name		= "atmel_usart",
-+	.id		= 5,
-+	.dev		= {
-+		.platform_data	= &atmel_usart5_data,
-+	},
-+	.resource	= atmel_usart5_resource,
-+	.num_resources	= ARRAY_SIZE(atmel_usart5_resource),
-+};
-+DEV_CLK(usart, atmel_usart5, pba, 14);
-+
-+static void __init configure_usart0_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PB, (1 << 14) | (1 << 15), PERIPH_B, 0);
-+}
-+
-+static void __init configure_usart1_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 8) | (1 << 9), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart2_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 16) | (1 << 17), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart3_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PC, (1 << 10) | (1 << 11), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart4_pins(void)
-+{
-+	/* TXD | RXD */
-+	select_peripheral(PA, (1 << 14) | (1 << 15), PERIPH_A, 0);
-+}
-+
-+static void __init configure_usart5_pins(void)
-+{
-+	/* RXD | TXD */
-+	select_peripheral(PA, (1 << 22) | (1 << 23), PERIPH_A, 0);
-+}
-+
-+static struct platform_device *__initdata at32_usarts[6];
-+
-+void __init at32_map_usart(unsigned int hw_id, unsigned int line)
-+{
-+	struct platform_device *pdev;
-+
-+	switch (hw_id) {
-+	case 0:
-+		pdev = &atmel_usart0_device;
-+		configure_usart0_pins();
-+		break;
-+	case 1:
-+		pdev = &atmel_usart1_device;
-+		configure_usart1_pins();
-+		break;
-+	case 2:
-+		pdev = &atmel_usart2_device;
-+		configure_usart2_pins();
-+		break;
-+	case 3:
-+		pdev = &atmel_usart3_device;
-+		configure_usart3_pins();
-+		break;
-+	case 4:
-+		pdev = &atmel_usart4_device;
-+		configure_usart4_pins();
-+		break;
-+	case 5:
-+		pdev = &atmel_usart5_device;
-+		configure_usart5_pins();
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	if (PXSEG(pdev->resource[0].start) == P4SEG) {
-+		/* Addresses in the P4 segment are permanently mapped 1:1 */
-+		struct atmel_uart_data *data = pdev->dev.platform_data;
-+		data->regs = (void __iomem __force *)pdev->resource[0].start;
-+	}
-+
-+	pdev->id = line;
-+	at32_usarts[line] = pdev;
-+}
-+
-+struct platform_device *__init at32_add_device_usart(unsigned int id)
-+{
-+	platform_device_register(at32_usarts[id]);
-+	return at32_usarts[id];
-+}
-+
-+struct platform_device *atmel_default_console_device;
-+
-+void __init at32_setup_serial_console(unsigned int usart_id)
-+{
-+	atmel_default_console_device = at32_usarts[usart_id];
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Ethernet
-+ * -------------------------------------------------------------------- */
-+
-+static u64 macb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource macb0_resource[] __initdata = {
-+	PBMEM(0xffe04000),
-+	IRQ(8),
-+};
-+static struct clk macb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 8,
-+};
-+static struct clk macb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 4,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
-+{
-+	struct platform_device *pdev;
-+	u32 pin_mask_a;
-+	u32 pin_mask_c;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("macb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	if (platform_device_add_resources(pdev, macb0_resource,
-+				ARRAY_SIZE(macb0_resource)))
-+		goto out_free_pdev;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct eth_platform_data)))
-+		goto out_free_pdev;
-+
-+	pin_mask_a  = (1 << 4);  /* RXDV */
-+	pin_mask_c  = (1 << 10); /* MDC  */
-+	pin_mask_c |= (1 << 11); /* MDIO */
-+	pin_mask_c |= (1 << 12); /* TXCK */
-+	pin_mask_c |= (1 << 14); /* RXD0 */
-+	pin_mask_c |= (1 << 15); /* RXD1 */
-+	pin_mask_c |= (1 << 16); /* RXER */
-+	pin_mask_c |= (1 << 18); /* TXEN */
-+	pin_mask_c |= (1 << 19); /* TXD0 */
-+	pin_mask_c |= (1 << 20); /* TXD1 */
-+
-+	if (!data->is_rmii) {
-+		pin_mask_a |= (1<<0);  /* COL  */
-+		pin_mask_a |= (1<<1);  /* RXD2 */
-+		pin_mask_a |= (1<<2);  /* RXD3 */
-+		pin_mask_a |= (1<<3);  /* RXCK */
-+		pin_mask_a |= (1<<5);  /* TXER */
-+		pin_mask_a |= (1<<6);  /* TXD2 */
-+		pin_mask_a |= (1<<7);  /* TXD3 */
-+		pin_mask_c |= (1<<13); /* CRS  */
-+		pin_mask_c |= (1<<17); /* SPD  */
-+	}
-+
-+	select_peripheral(PA, pin_mask_a, PERIPH_B, 0);
-+	select_peripheral(PC, pin_mask_c, PERIPH_C, 0);
-+
-+	pdev->dev.dma_mask = &macb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	macb0_hclk.dev = &pdev->dev;
-+	macb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+out_free_pdev:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * SPI
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_spi_resource[][2] __initdata = {
-+	{
-+		PBMEM(0xffe05400),
-+		IRQ(36),
-+	}, {
-+		PBMEM(0xffe05800),
-+		IRQ(37),
-+	}, {
-+		PBMEM(0xffe05c00),
-+		IRQ(38),
-+	}, {
-+		PBMEM(0xffe06000),
-+		IRQ(39),
-+	}
-+};
-+static struct clk atmel_spi_clk[] = {
-+	{
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 9,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 10,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 11,
-+	}, {
-+		.name		= "spi_clk",
-+		.parent		= &pbb_clk,
-+		.mode		= pbb_clk_mode,
-+		.get_rate	= pbb_clk_get_rate,
-+		.index		= 12,
-+	}
-+};
-+static int __initdata atmel_spi_pins[][4] = {
-+	{
-+		/* SPI0 */
-+		GPIO_PIN_PB(3), GPIO_PIN_PB(4),
-+		GPIO_PIN_PB(5), GPIO_PIN_PB(6),
-+	}, {
-+		/* SPI1 */
-+		GPIO_PIN_PB(4), -1, -1, -1,
-+	}, {
-+		/* SPI2 */
-+		GPIO_PIN_PA(28), -1, -1, -1,
-+	}, {
-+		/* SPI3 */
-+		GPIO_PIN_PA(27), GPIO_PIN_PA(20),
-+		GPIO_PIN_PA(29), GPIO_PIN_PA(30),
-+	}
-+};
-+
-+
-+static void __init at32_spi_setup_dw_dma(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct dw_dma_slave	*rx_dws;
-+	struct dw_dma_slave	*tx_dws;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_dws = kmemdup(to_dw_dma_slave(pdata->rx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		rx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_dws = kmemdup(to_dw_dma_slave(pdata->tx_dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		tx_dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	rx_dws->slave.dma_dev = tx_dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	rx_dws->slave.reg_width = tx_dws->slave.reg_width
-+		= DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_dws->cfg_hi = DWC_CFGH_SRC_PER(2);
-+	tx_dws->cfg_hi = DWC_CFGH_DST_PER(3);
-+	rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+	tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	pdata->rx_dma_slave = &rx_dws->slave;
-+	pdata->tx_dma_slave = &tx_dws->slave;
-+}
-+
-+static void __init at32_spi_setup_pdca(unsigned int id,
-+		struct atmel_spi_pdata *pdata)
-+{
-+	struct pdca_slave	*rx_pslave;
-+	struct pdca_slave	*tx_pslave;
-+
-+	if (pdata->rx_dma_slave)
-+		rx_pslave = kmemdup(dma_to_pdca_slave(pdata->rx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		rx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+	if (pdata->tx_dma_slave)
-+		tx_pslave = kmemdup(dma_to_pdca_slave(pdata->tx_dma_slave),
-+				sizeof(struct pdca_slave), GFP_KERNEL);
-+	else
-+		tx_pslave = kzalloc(sizeof(struct pdca_slave), GFP_KERNEL);
-+
-+	rx_pslave->slave.dma_dev = &pdca_device.dev;
-+	tx_pslave->slave.dma_dev = &pdca_device.dev;
-+	rx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+	tx_pslave->slave.reg_width = DMA_SLAVE_WIDTH_8BIT;
-+
-+	rx_pslave->tx_periph_id = -1;
-+	tx_pslave->rx_periph_id = -1;
-+
-+	switch (id) {
-+	case 1:
-+		rx_pslave->rx_periph_id = 6;
-+		tx_pslave->tx_periph_id = 17;
-+		break;
-+	case 2:
-+		rx_pslave->rx_periph_id = 7;
-+		tx_pslave->tx_periph_id = 18;
-+		break;
-+	case 3:
-+		rx_pslave->rx_periph_id = 8;
-+		tx_pslave->tx_periph_id = 19;
-+		break;
-+	}
-+
-+	pdata->rx_dma_slave = &rx_pslave->slave;
-+	pdata->tx_dma_slave = &tx_pslave->slave;
-+}
-+
-+static void __init
-+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-+		unsigned int n, const int *pins)
-+{
-+	unsigned int	mode;
-+	unsigned int	cs;
-+	int		pin;
-+
-+	for (; n; n--, b++) {
-+		b->bus_num = bus_num;
-+		cs = b->chip_select;
-+		if (cs >= 4 || !gpio_is_valid(pins[cs]))
-+			continue;
-+
-+		pin = (int)b->controller_data;
-+		if (!pin || !gpio_is_valid(pin)) {
-+			pin = pins[cs];
-+			b->controller_data = (void *)pin;
-+		}
-+
-+		mode = AT32_GPIOF_OUTPUT;
-+		if (!(b->mode & SPI_CS_HIGH))
-+			mode |= AT32_GPIOF_HIGH;
-+		at32_select_gpio(pin, mode);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_spi(unsigned int id,
-+		struct spi_board_info *b, unsigned int n)
-+{
-+	struct atmel_spi_pdata	pdata;
-+	struct platform_device	*pdev;
-+
-+	BUILD_BUG_ON(ARRAY_SIZE(atmel_spi_resource)
-+			!= ARRAY_SIZE(atmel_spi_clk));
-+
-+	if (id >= ARRAY_SIZE(atmel_spi_resource))
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_spi", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_spi_resource[id],
-+				ARRAY_SIZE(atmel_spi_resource[id])))
-+		goto fail;
-+
-+	memset(&pdata, 0, sizeof(struct atmel_spi_pdata));
-+
-+	if (id == 0)
-+		at32_spi_setup_dw_dma(id, &pdata);
-+	else
-+		at32_spi_setup_pdca(id, &pdata);
-+	pdata.rx_dma_slave->dev = pdata.tx_dma_slave->dev = &pdev->dev;
-+
-+	if (platform_device_add_data(pdev, &pdata,
-+				sizeof(struct atmel_spi_pdata)))
-+		goto fail;
-+
-+	switch (id) {
-+	case 0:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 1), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 0) | (1 << 2), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(0, b, n, atmel_spi_pins[0]);
-+		break;
-+
-+	case 1:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PB, (1 << 7), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PB, (1 << 6) | (1 << 5), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(1, b, n, atmel_spi_pins[1]);
-+		break;
-+
-+	case 2:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 30), PERIPH_B, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 31) || (1 << 29), PERIPH_B, 0);
-+
-+		at32_spi_setup_slaves(2, b, n, atmel_spi_pins[2]);
-+		break;
-+
-+	case 3:
-+		/* pullup MISO so a level is always defined */
-+		select_peripheral(PA, (1 << 25), PERIPH_A, AT32_GPIOF_PULLUP);
-+		/* MOSI | SCK */
-+		select_peripheral(PA, (1 << 24) | (1 << 26), PERIPH_A, 0);
-+
-+		at32_spi_setup_slaves(3, b, n, atmel_spi_pins[3]);
-+		break;
-+
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_spi_clk[id].dev = &pdev->dev;
-+	spi_register_board_info(b, n);
-+	platform_device_add(pdev);
-+
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * MMC
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_mci0_resource[] __initdata = {
-+	PBMEM(0xfff00000),
-+	IRQ(43),
-+};
-+/* MCI is on the PBC bus, but it is controlled by the PBBMASK register */
-+static struct clk atmel_mci0_pclk = {
-+	.name		= "mci_clk",
-+	.parent		= &pbc_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 16,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
-+{
-+	struct platform_device		*pdev;
-+	struct dw_dma_slave		*dws;
-+	u32 pin_mask_1 = 0;
-+	u32 pin_mask_2 = 0;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	/* Must have at least one usable slot */
-+	if (!data->slot[0].bus_width && !data->slot[1].bus_width)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mci", id);
-+	if (!pdev)
-+		goto fail;
-+
-+	if (platform_device_add_resources(pdev, atmel_mci0_resource,
-+				ARRAY_SIZE(atmel_mci0_resource)))
-+		goto fail;
-+
-+	if (data->dma_slave)
-+		dws = kmemdup(to_dw_dma_slave(data->dma_slave),
-+				sizeof(struct dw_dma_slave), GFP_KERNEL);
-+	else
-+		dws = kzalloc(sizeof(struct dw_dma_slave), GFP_KERNEL);
-+
-+	dws->slave.dev = &pdev->dev;
-+	dws->slave.dma_dev = &dw_dmac0_device.dev;
-+	dws->slave.reg_width = DMA_SLAVE_WIDTH_32BIT;
-+	dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
-+				| DWC_CFGH_DST_PER(1));
-+	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
-+				| DWC_CFGL_HS_SRC_POL);
-+
-+	data->dma_slave = &dws->slave;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct mci_platform_data)))
-+		goto fail;
-+
-+	switch (data->slot[0].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 20); /* DATA4 */
-+		pin_mask_1 |= (1 << 21); /* DATA5 */
-+		pin_mask_1 |= (1 << 22); /* DATA6 */
-+		pin_mask_1 |= (1 << 23); /* DATA7 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_2 |= (1 << 19); /* DATA1 */
-+		pin_mask_2 |= (1 << 20); /* DATA2 */
-+		pin_mask_2 |= (1 << 21); /* DATA3 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_2 |= (1 << 18); /* DATA0 */
-+		pin_mask_2 |= (1 << 17); /* CMD   */
-+
-+		select_peripheral(PA, pin_mask_1, PERIPH_D, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, pin_mask_2, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PB, (1 << 16),  PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[0].detect_pin))
-+			at32_select_gpio(data->slot[0].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[0].wp_pin))
-+			at32_select_gpio(data->slot[0].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	pin_mask_1 = 0;
-+
-+	switch (data->slot[1].bus_width) {
-+	case 8:
-+		pin_mask_1 |= (1 << 9); /* DATA7 */
-+		pin_mask_1 |= (1 << 8); /* DATA6 */
-+		pin_mask_1 |= (1 << 7); /* DATA5 */
-+		pin_mask_1 |= (1 << 6); /* DATA4 */
-+		/* fall through */
-+	case 4:
-+		pin_mask_1 |= (1 << 5); /* DATA3 */
-+		pin_mask_1 |= (1 << 4); /* DATA2 */
-+		pin_mask_1 |= (1 << 3); /* DATA1 */
-+		/* fall through */
-+	case 1:
-+		pin_mask_1 |= (1 << 2); /* DATA0 */
-+		pin_mask_1 |= (1 << 1); /* CMD   */
-+
-+		select_peripheral(PC, pin_mask_1, PERIPH_A, AT32_GPIOF_PULLUP);
-+		select_peripheral(PC, (1 << 0),   PERIPH_A, 0);	/* CLK */
-+
-+		if (gpio_is_valid(data->slot[1].detect_pin))
-+			at32_select_gpio(data->slot[1].detect_pin, 0);
-+		if (gpio_is_valid(data->slot[1].wp_pin))
-+			at32_select_gpio(data->slot[1].wp_pin, 0);
-+
-+		break;
-+	case 0:
-+		/* Slot is unused */
-+		break;
-+	default:
-+		goto fail;
-+	}
-+
-+	atmel_mci0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+fail:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  LCDC
-+ * -------------------------------------------------------------------- */
-+static u64 atmel_lcdfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_lcdfb0_resource[] __initdata = {
-+	{
-+		.start	= 0xff000000,
-+		.end	= 0xff000fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(3),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_lcdfb0_hck1 = {
-+	.name		= "hck1",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 7,
-+};
-+static struct clk atmel_lcdfb0_pixclk = {
-+	.name		= "lcdc_clk",
-+	.mode		= genclk_mode,
-+	.get_rate	= genclk_get_rate,
-+	.set_rate	= genclk_set_rate,
-+	.set_parent	= genclk_set_parent,
-+	.index		= 6,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-+		unsigned long fbmem_start, unsigned long fbmem_len,
-+		u64 pin_mask)
-+{
-+	struct {
-+		struct atmel_lcdfb_info	info;
-+		struct fb_monspecs	monspecs;
-+		struct fb_videomode	modedb[0];
-+	} *all_data;
-+	struct platform_device	*pdev;
-+	unsigned int		data_size;
-+	unsigned int		modedb_size;
-+	unsigned int		num_resources;
-+	int			ret;
-+
-+	if (id > 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_lcdfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_lcdfb0_resource);
-+	if (fbmem_len) {
-+		atmel_lcdfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_lcdfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+
-+	if (platform_device_add_resources(pdev, atmel_lcdfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	/*
-+	 * Allocate all data -- info struct, monspecs and modedb -- in
-+	 * a single chunk.
-+	 */
-+	modedb_size = data->default_monspecs->modedb_len
-+			* sizeof(struct fb_videomode);
-+	data_size = sizeof(*all_data) + modedb_size;
-+	all_data = kmalloc(data_size, GFP_KERNEL);
-+	if (!all_data)
-+		goto error;
-+
-+	memcpy(&all_data->info, data, sizeof(struct atmel_lcdfb_info));
-+	memcpy(&all_data->monspecs, data->default_monspecs,
-+			sizeof(struct fb_monspecs));
-+	memcpy(&all_data->modedb, data->default_monspecs->modedb, modedb_size);
-+
-+	ret = platform_device_add_data(pdev, all_data, data_size);
-+	kfree(all_data);
-+	if (ret)
-+		goto error;
-+
-+	/*
-+	 * Update internal pointers to use memory allocated by
-+	 * platform_device_add_data().
-+	 */
-+	all_data = pdev->dev.platform_data;
-+	all_data->info.default_monspecs = &all_data->monspecs;
-+	all_data->monspecs.modedb = all_data->modedb;
-+
-+	select_peripheral(PD, 0x7fffffff,  PERIPH_A, 0);
-+
-+	pdev->dev.dma_mask = &atmel_lcdfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_lcdfb0_hck1.dev = &pdev->dev;
-+	atmel_lcdfb0_pixclk.dev = &pdev->dev;
-+
-+	clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
-+	clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ *  Media Post-Processor (MPOP)
-+ * -------------------------------------------------------------------- */
-+
-+static u64 atmel_mpopfb0_dma_mask = DMA_32BIT_MASK;
-+static struct resource atmel_mpopfb0_resource[] = {
-+	{
-+		/* Configuration interface */
-+		.start	= 0xffe02000,
-+		.end	= 0xffe02fff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		/* Data interface (output) */
-+		.start	= 0xf0000000,
-+		.end	= 0xf0ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(4),
-+	{
-+		/* Placeholder for pre-allocated fb memory */
-+		.start	= 0x00000000,
-+		.end	= 0x00000000,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+static struct clk atmel_mpopfb0_hclk = {
-+	.name		= "hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 12,
-+};
-+static struct clk atmel_mpopfb0_pclk = {
-+	.name		= "pclk",
-+	.parent		= &pbb_clk,
-+	.mode		= pbb_clk_mode,
-+	.get_rate	= pbb_clk_get_rate,
-+	.index		= 2,
-+};
-+
-+struct platform_device *__init at32_add_device_mpop(unsigned int id,
-+		struct platform_device *lcdc_pdev,
-+		unsigned long fbmem_start, unsigned long fbmem_len)
-+{
-+	struct platform_device		*pdev;
-+	struct atmel_mpopfb_info	info;
-+	unsigned int			num_resources;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_mpopfb", id);
-+	if (!pdev)
-+		return NULL;
-+
-+	num_resources = ARRAY_SIZE(atmel_mpopfb0_resource);
-+	if (fbmem_len) {
-+		atmel_mpopfb0_resource[num_resources - 1].start = fbmem_start;
-+		atmel_mpopfb0_resource[num_resources - 1].end
-+			= fbmem_start + fbmem_len - 1;
-+	} else {
-+		num_resources--;
-+	}
-+	if (platform_device_add_resources(pdev, atmel_mpopfb0_resource,
-+				num_resources))
-+		goto error;
-+
-+	info.lcdc_pdev = lcdc_pdev;
-+	if (platform_device_add_data(pdev, &info, sizeof(info)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &atmel_mpopfb0_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	atmel_mpopfb0_hclk.dev = &pdev->dev;
-+	atmel_mpopfb0_pclk.dev = &pdev->dev;
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  USB Host (OHCI/EHCI)
-+ * ------------------------------------------------------------------- */
-+
-+static u64 usbh_dma_mask = DMA_32BIT_MASK;
-+
-+static unsigned long parent_clk_get_rate(struct clk *clk)
-+{
-+	return clk->parent->get_rate(clk->parent);
-+}
-+
-+static void parent_clk_mode(struct clk *clk, int enabled)
-+{
-+	/* Parent clk enabled by clk core */
-+}
-+
-+/*
-+ * The UTMI clock is an internally controlled PLL. It is hardwired to
-+ * OSC2 and will run at 30 MHz or 60 MHz depending on the internal
-+ * UTMI <-> host controller data bus width.
-+ *
-+ * We can turn it on and off through the Power Manager. That's all.
-+ */
-+static void utmi_clk_mode(struct clk *clk, int enabled)
-+{
-+	u32 ppcr = pm_readl(PPCR);
-+
-+	if (enabled)
-+		/* Clear UTMI suspend signal */
-+		ppcr |= PM_BIT(PPCR_UTMI_CTRL);
-+	else
-+		/* Set UTMI suspend signal */
-+		ppcr &= ~PM_BIT(PPCR_UTMI_CTRL);
-+
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0x55));
-+	pm_writel(PPCR, ppcr | PM_BF(PPCR_KEY, 0xaa));
-+
-+	if (enabled)
-+		/* PLL startup time is 2.5 ms */
-+		udelay(2500);
-+}
-+
-+static unsigned long utmi_clk_get_rate(struct clk *clk)
-+{
-+	/*
-+	 * Not sure about this, but I think the UTMI interface on
-+	 * AP7200 is 16 bits wide, which means 30 MHz PHY clock.
-+	 */
-+	return 30000000;
-+}
-+
-+static struct clk usbh_utmi_clk = {
-+	.name		= "usbh_utmi_clk",
-+	.parent		= &osc2,
-+	.mode		= utmi_clk_mode,
-+	.get_rate	= utmi_clk_get_rate,
-+};
-+
-+static struct clk usbh_hclk = {
-+	.name		= "usbh_hclk",
-+	.parent		= &hsb_clk,
-+	.mode		= hsb_clk_mode,
-+	.get_rate	= hsb_clk_get_rate,
-+	.index		= 6,
-+};
-+
-+/*
-+ * UTMI and HSB clocks are shared between OHCI and EHCI. These wrappers
-+ * make sure both can use the clocks as if they had their own.
-+ */
-+static struct clk ohci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ohci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct clk ehci_utmi_clk = {
-+	.name		= "utmi_clk",
-+	.parent		= &usbh_utmi_clk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+static struct clk ehci_hclk = {
-+	.name		= "hclk",
-+	.parent		= &usbh_hclk,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+/*
-+ * The USBH needs both a 48 MHz and a 12 MHz clock, and the 12 MHz
-+ * must be generated by dividing the 48 MHz clock. There's only one
-+ * generic clock hooked up to the USBH which we must use to generate
-+ * both.
-+ *
-+ * This can be done because GCLK0 generates an additional "divided
-+ * clock", which is the normal clock output further divided by four
-+ * (this is hardcoded, but not surprisingly, exactly what we need.)
-+ *
-+ * So we generate the clocks as follows:
-+ *    OSC2 (12 MHz) -> PLL2 (48 MHz) --> GCLK0 undivided (48 MHz)
-+ *                                   |-> GCLK0 divided (12 MHz)
-+ *
-+ * This clock is only used by the OHCI part of the controller, not the
-+ * EHCI part.
-+ */
-+static struct clk ohci_gclk = {
-+	.name		= "ohci_clk",
-+	.parent		= &gclk0,
-+	.mode		= parent_clk_mode,
-+	.get_rate	= parent_clk_get_rate,
-+};
-+
-+static struct resource usbh_ohci_resource[] __initdata = {
-+	{
-+		.start	= 0xff400000,
-+		.end	= 0xff400400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static struct resource usbh_ehci_resource[] __initdata = {
-+	{
-+		.start	= 0xff300000,
-+		.end	= 0xff300400,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+	IRQ(7),
-+};
-+
-+static void __init usbh_setup_pins(void)
-+{
-+	static bool already_done __initdata;
-+
-+	if (!already_done) {
-+		already_done = true;
-+		/* OC_EN_N | OC_FLAG_N */
-+		select_peripheral(PA, (1 << 18) | (1 << 19), PERIPH_D, 0);
-+	}
-+}
-+
-+struct platform_device *__init at32_add_device_ohci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ohci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ohci_resource,
-+				ARRAY_SIZE(usbh_ohci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	clk_set_parent(&pll2, &osc2);
-+	if (clk_round_rate(&pll2, 48000000) != 48000000) {
-+		pr_debug("USBH OHCI: Cannot generate 48 MHz clock\n");
-+		goto error;
-+	}
-+	clk_set_rate(&pll2, 48000000);
-+
-+	clk_set_parent(&gclk0, &pll2);
-+	clk_set_rate(&gclk0, 48000000);
-+
-+	ohci_utmi_clk.dev = &pdev->dev;
-+	ohci_hclk.dev = &pdev->dev;
-+	ohci_gclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+struct platform_device *__init at32_add_device_ehci(unsigned int id)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("ehci", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, usbh_ehci_resource,
-+				ARRAY_SIZE(usbh_ehci_resource)))
-+		goto error;
-+
-+	pdev->dev.dma_mask = &usbh_dma_mask;
-+	pdev->dev.coherent_dma_mask = DMA_32BIT_MASK;
-+
-+	ehci_utmi_clk.dev = &pdev->dev;
-+	ehci_hclk.dev = &pdev->dev;
-+
-+	usbh_setup_pins();
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ *  NAND Flash / SmartMedia
-+ * ------------------------------------------------------------------- */
-+static struct resource smc_cs3_resource[] __initdata = {
-+	{
-+		.start	= 0x24000000,
-+		.end	= 0x27ffffff,
-+		.flags	= IORESOURCE_MEM,
-+	}, {
-+		.start	= 0xffe04c00,
-+		.end	= 0xffe04fff,
-+		.flags	= IORESOURCE_MEM,
-+	},
-+};
-+
-+struct platform_device *__init
-+at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
-+{
-+	struct platform_device *pdev;
-+
-+	if (id != 0 || !data)
-+		return NULL;
-+
-+	pdev = platform_device_alloc("atmel_nand", id);
-+	if (!pdev)
-+		goto error;
-+
-+	if (platform_device_add_resources(pdev, smc_cs3_resource,
-+				ARRAY_SIZE(smc_cs3_resource)))
-+		goto error;
-+
-+	if (platform_device_add_data(pdev, data,
-+				sizeof(struct atmel_nand_data)))
-+		goto error;
-+
-+	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
-+
-+	/* NANDOE | NANDWE */
-+	select_peripheral(PF, (1 << 0) | (1 << 1), PERIPH_A, 0);
-+
-+	if (gpio_is_valid(data->enable_pin))
-+		at32_select_gpio(data->enable_pin,
-+				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
-+	if (gpio_is_valid(data->det_pin))
-+		at32_select_gpio(data->det_pin, 0);
-+	if (gpio_is_valid(data->rdy_pin))
-+		at32_select_gpio(data->rdy_pin, 0);
-+
-+	platform_device_add(pdev);
-+	return pdev;
-+
-+error:
-+	platform_device_put(pdev);
-+	return NULL;
-+}
-+
-+/* -------------------------------------------------------------------
-+ * Clock list
-+ * ------------------------------------------------------------------- */
-+static __initdata struct clk *init_clocks[] = {
-+	&rcosc,
-+	&osc0,
-+	&osc1,
-+	&osc2,
-+	&osc32,
-+	&pll0,
-+	&pll1,
-+	&pll2,
-+	&cpu_clk,
-+	&hsb_clk,
-+	&pba_clk,
-+	&pbb_clk,
-+	&pbc_clk,
-+	&gclk0,
-+	&gclk1,
-+	&gclk2,
-+	&gclk3,
-+	&gclk4,
-+	&gclk5,
-+	&at32_intc0_pclk,
-+	&pm_pclk,
-+	&sdc_pclk,
-+	&ast0_pclk,
-+	&ast1_pclk,
-+	&wdt_pclk,
-+	&gpio_pclk,
-+	&pdca_hclk,
-+	&pdca_pclk,
-+	&ebi_hclk,
-+	&hramc_clk,
-+	&smc_pclk,
-+	&sdramc_clk,
-+	&dw_dmac0_hclk,
-+	&atmel_usart0_usart,
-+	&atmel_usart1_usart,
-+	&atmel_usart2_usart,
-+	&atmel_usart3_usart,
-+	&atmel_usart4_usart,
-+	&atmel_usart5_usart,
-+	&atmel_spi_clk[0],
-+	&atmel_spi_clk[1],
-+	&atmel_spi_clk[2],
-+	&atmel_spi_clk[3],
-+	&macb0_hclk,
-+	&macb0_pclk,
-+	&atmel_mci0_pclk,
-+	&atmel_lcdfb0_hck1,
-+	&atmel_lcdfb0_pixclk,
-+	&atmel_mpopfb0_hclk,
-+	&atmel_mpopfb0_pclk,
-+	&usbh_utmi_clk,
-+	&usbh_hclk,
-+	&ohci_utmi_clk,
-+	&ohci_hclk,
-+	&ohci_gclk,
-+	&ehci_utmi_clk,
-+	&ehci_hclk,
-+};
-+
-+static void pll_init_parent(struct clk *pll)
-+{
-+	u32 ctrl;
-+
-+	ctrl = pm_readl(PLL[pll->index]);
-+	switch (PM_BFEXT(PLLx_PLLOSC, ctrl)) {
-+	case 0:
-+		pll->parent = &osc0;
-+		break;
-+	case 1:
-+		pll->parent = &osc1;
-+		break;
-+	case 2:
-+		pll->parent = &osc2;
-+		break;
-+	}
-+}
-+
-+static void ap7200_power_off(void)
-+{
-+	/*
-+	 * Clear all wakeup events so that we don't wake up
-+	 * immediately after we shut down.
-+	 */
-+	sdc_writel(ECR, ~0UL);
-+	sdc_readl(STATUS);
-+	asm volatile("sleep %0; sub pc, -2"
-+			:: "i"(CPU_SLEEP_SHUTDOWN)
-+			: "memory");
-+}
-+
-+void __init setup_platform(void)
-+{
-+	unsigned int	i;
-+	u32		cpu_mask;
-+	u32		hsb_mask;
-+	u32		pba_mask;
-+	u32		pbb_mask;
-+
-+	switch (PM_BFEXT(MCCTRL_MCSEL, pm_readl(MCCTRL))) {
-+	case 0:
-+		main_clock = &rcosc;
-+		break;
-+	case 1:
-+		main_clock = &osc0;
-+		break;
-+	case 2:
-+		main_clock = &pll0;
-+		break;
-+	}
-+
-+	cpu_clk.parent = main_clock;
-+
-+	pll_init_parent(&pll0);
-+	pll_init_parent(&pll1);
-+	pll_init_parent(&pll2);
-+
-+	genclk_init_parent(&gclk0);
-+	genclk_init_parent(&gclk1);
-+	genclk_init_parent(&gclk2);
-+	genclk_init_parent(&gclk3);
-+	genclk_init_parent(&gclk4);
-+	genclk_init_parent(&gclk5);
-+	genclk_init_parent(&atmel_lcdfb0_pixclk);
-+
-+	/*
-+	 * Turn on all clocks that have at least one user already, and
-+	 * turn off everything else. We only do this for module
-+	 * clocks, and even though it isn't particularly pretty to
-+	 * check the address of the mode function, it should do the
-+	 * trick...
-+	 */
-+	cpu_mask = 0x10003;
-+	hsb_mask = pba_mask = pbb_mask = 0;
-+
-+	/* Make sure we don't disable the power manager or the SDRAM */
-+	pm_pclk.users = 1;
-+	pm_pclk.parent->users = 1;
-+	ebi_hclk.users = 1;
-+
-+	/* Can't recursively call clk_enable() from any of the clk ops */
-+	sdc_pclk.users = 1;
-+
-+	for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
-+		struct clk *clk = init_clocks[i];
-+
-+		/* first, register clock */
-+		at32_clk_register(clk);
-+
-+		if (clk->users == 0)
-+			continue;
-+
-+		if (clk->mode == &cpu_clk_mode)
-+			cpu_mask |= 1 << clk->index;
-+		else if (clk->mode == &hsb_clk_mode)
-+			hsb_mask |= 1 << clk->index;
-+		else if (clk->mode == &pba_clk_mode)
-+			pba_mask |= 1 << clk->index;
-+		else if (clk->mode == &pbb_clk_mode)
-+			pbb_mask |= 1 << clk->index;
-+	}
-+
-+	pm_writel(CPUMASK, cpu_mask);
-+	pm_writel(HSBMASK, hsb_mask);
-+	pm_writel(PBAMASK, pba_mask);
-+	pm_writel(PBBMASK, pbb_mask);
-+
-+	at32_gpio_init(&gpio_device);
-+
-+	/* Enter shutdown mode when powering off. This happens very
-+	 * early, so board code may still override this. */
-+	pm_power_off = ap7200_power_off;
-+
-+	/* Enable WAKE pin */
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0x55));
-+	sdc_writel(CTRL, SDC_BIT(CTRL_PIN_EN) | SDC_BIT(CTRL_AST_EN)
-+			| SDC_BIT(CTRL_OCD_EN) | SDC_BIT(CTRL_JTAG_EN)
-+			| SDC_BF(CTRL_KEY, 0xaa));
-+}
-+
-+void __init platform_time_init(void)
-+{
-+	ast_time_init(&ast1_device, AST_CLOCK_PB);
-+}
-+
-+unsigned long at32_get_reset_cause(void)
-+{
-+	return pm_readl(RCAUSE);
-+}
-+
-+struct gen_pool *sram_pool;
-+
-+static int __init sram_init(void)
-+{
-+	struct gen_pool *pool;
-+
-+	/* 1KiB granularity */
-+	pool = gen_pool_create(10, -1);
-+	if (!pool)
-+		goto fail;
-+
-+	if (gen_pool_add(pool, 0x08000000, 0x10000, -1))
-+		goto err_pool_add;
-+
-+	sram_pool = pool;
-+	return 0;
-+
-+err_pool_add:
-+	gen_pool_destroy(pool);
-+fail:
-+	pr_err("Failed to create SRAM pool\n");
-+	return -ENOMEM;
-+}
-+core_initcall(sram_init);
-diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
-index 6c27dda..05877d6 100644
---- a/arch/avr32/mach-at32ap/clock.c
-+++ b/arch/avr32/mach-at32ap/clock.c
-@@ -15,24 +15,40 @@
- #include <linux/err.h>
- #include <linux/device.h>
- #include <linux/string.h>
-+#include <linux/list.h>
- 
- #include <mach/chip.h>
- 
- #include "clock.h"
- 
-+/* at32 clock list */
-+static LIST_HEAD(at32_clock_list);
-+
- static DEFINE_SPINLOCK(clk_lock);
-+static DEFINE_SPINLOCK(clk_list_lock);
-+
-+void at32_clk_register(struct clk *clk)
-+{
-+	spin_lock(&clk_list_lock);
-+	/* add the new item to the end of the list */
-+	list_add_tail(&clk->list, &at32_clock_list);
-+	spin_unlock(&clk_list_lock);
-+}
- 
- struct clk *clk_get(struct device *dev, const char *id)
- {
--	int i;
-+	struct clk *clk;
- 
--	for (i = 0; i < at32_nr_clocks; i++) {
--		struct clk *clk = at32_clock_list[i];
-+	spin_lock(&clk_list_lock);
- 
--		if (clk->dev == dev && strcmp(id, clk->name) == 0)
-+	list_for_each_entry(clk, &at32_clock_list, list) {
-+		if (clk->dev == dev && strcmp(id, clk->name) == 0) {
-+			spin_unlock(&clk_list_lock);
- 			return clk;
-+		}
- 	}
- 
-+	spin_unlock(&clk_list_lock);
- 	return ERR_PTR(-ENOENT);
- }
- EXPORT_SYMBOL(clk_get);
-@@ -162,7 +178,11 @@ EXPORT_SYMBOL(clk_get_parent);
- #include <linux/io.h>
- #include <linux/debugfs.h>
- #include <linux/seq_file.h>
--#include "pm.h"
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# include "pm-v1.h"
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include "pm-v3.h"
-+#endif
- 
- 
- #define	NEST_DELTA	2
-@@ -203,8 +223,8 @@ dump_clock(struct clk *parent, struct clkinf *r)
- 
- 	/* cost of this scan is small, but not linear... */
- 	r->nest = nest + NEST_DELTA;
--	for (i = 3; i < at32_nr_clocks; i++) {
--		clk = at32_clock_list[i];
-+
-+	list_for_each_entry(clk, &at32_clock_list, list) {
- 		if (clk->parent == parent)
- 			dump_clock(clk, r);
- 	}
-@@ -215,33 +235,76 @@ static int clk_show(struct seq_file *s, void *unused)
- {
- 	struct clkinf	r;
- 	int		i;
-+	struct clk 	*clk;
- 
- 	/* show all the power manager registers */
--	seq_printf(s, "MCCTRL  = %8x\n", pm_readl(MCCTRL));
--	seq_printf(s, "CKSEL   = %8x\n", pm_readl(CKSEL));
--	seq_printf(s, "CPUMASK = %8x\n", pm_readl(CPU_MASK));
--	seq_printf(s, "HSBMASK = %8x\n", pm_readl(HSB_MASK));
--	seq_printf(s, "PBAMASK = %8x\n", pm_readl(PBA_MASK));
--	seq_printf(s, "PBBMASK = %8x\n", pm_readl(PBB_MASK));
--	seq_printf(s, "PLL0    = %8x\n", pm_readl(PLL0));
--	seq_printf(s, "PLL1    = %8x\n", pm_readl(PLL1));
--	seq_printf(s, "IMR     = %8x\n", pm_readl(IMR));
-+	seq_printf(s, "MCCTRL     = %8x\n", pm_readl(MCCTRL));
-+	seq_printf(s, "CKSEL      = %8x\n", pm_readl(CKSEL));
-+#ifdef CONFIG_CPU_AT32AP700X
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPU_MASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSB_MASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBA_MASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBB_MASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL0));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL1));
-+#else
-+	seq_printf(s, "CPUMASK    = %8x\n", pm_readl(CPUMASK));
-+	seq_printf(s, "HSBMASK    = %8x\n", pm_readl(HSBMASK));
-+	seq_printf(s, "PBAMASK    = %8x\n", pm_readl(PBAMASK));
-+	seq_printf(s, "PBBMASK    = %8x\n", pm_readl(PBBMASK));
-+	seq_printf(s, "PBADIVMASK = %8x\n", pm_readl(PBADIVMASK));
-+	seq_printf(s, "PBBDIVMASK = %8x\n", pm_readl(PBBDIVMASK));
-+	seq_printf(s, "PLL0       = %8x\n", pm_readl(PLL[0]));
-+	seq_printf(s, "PLL1       = %8x\n", pm_readl(PLL[1]));
-+	seq_printf(s, "PLL2       = %8x\n", pm_readl(PLL[2]));
-+	seq_printf(s, "OSCCTRL0   = %8x\n", pm_readl(OSCCTRL[0]));
-+	seq_printf(s, "OSCCTRL1   = %8x\n", pm_readl(OSCCTRL[1]));
-+	seq_printf(s, "OSCCTRL2   = %8x\n", pm_readl(OSCCTRL[2]));
-+	seq_printf(s, "POSCSR     = %8x\n", pm_readl(POSCSR));
-+	seq_printf(s, "PPCR       = %8x\n", pm_readl(PPCR));
-+#endif
-+	seq_printf(s, "IMR        = %8x\n", pm_readl(IMR));
- 	for (i = 0; i < 8; i++) {
- 		if (i == 5)
- 			continue;
--		seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
-+#ifdef CONFIG_CPU_AT32AP700X
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL(i)));
-+#else
-+		seq_printf(s, "GCCTRL%d    = %8x\n", i, pm_readl(GCCTRL[i]));
-+#endif
- 	}
- 
- 	seq_printf(s, "\n");
- 
--	/* show clock tree as derived from the three oscillators
--	 * we "know" are at the head of the list
--	 */
- 	r.s = s;
- 	r.nest = 0;
--	dump_clock(at32_clock_list[0], &r);
--	dump_clock(at32_clock_list[1], &r);
--	dump_clock(at32_clock_list[2], &r);
-+	/* protected from changes on the list while dumping */
-+	spin_lock(&clk_list_lock);
-+
-+	/* show clock tree as derived from the three oscillators */
-+	clk = clk_get(NULL, "osc32k");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "osc0");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "osc1");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+#ifdef CONFIG_CPU_AT32AP720X
-+	clk = clk_get(NULL, "osc2");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+
-+	clk = clk_get(NULL, "rcosc");
-+	dump_clock(clk, &r);
-+	clk_put(clk);
-+#endif
-+
-+	spin_unlock(&clk_list_lock);
- 
- 	return 0;
- }
-diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
-index bb8e1f2..623bf0e 100644
---- a/arch/avr32/mach-at32ap/clock.h
-+++ b/arch/avr32/mach-at32ap/clock.h
-@@ -12,8 +12,13 @@
-  * published by the Free Software Foundation.
-  */
- #include <linux/clk.h>
-+#include <linux/list.h>
-+
-+
-+void at32_clk_register(struct clk *clk);
- 
- struct clk {
-+	struct list_head list;		/* linking element */
- 	const char	*name;		/* Clock name/function */
- 	struct device	*dev;		/* Device the clock is used by */
- 	struct clk	*parent;	/* Parent clock, if any */
-@@ -25,6 +30,3 @@ struct clk {
- 	u16		users;		/* Enabled if non-zero */
- 	u16		index;		/* Sibling index */
- };
--
--extern struct clk *at32_clock_list[];
--extern unsigned int at32_nr_clocks;
-diff --git a/arch/avr32/mach-at32ap/cpufreq.c b/arch/avr32/mach-at32ap/cpufreq.c
-index 5dd8d25..4cabc76 100644
---- a/arch/avr32/mach-at32ap/cpufreq.c
-+++ b/arch/avr32/mach-at32ap/cpufreq.c
-@@ -40,6 +40,9 @@ static unsigned int at32_get_speed(unsigned int cpu)
- 	return (unsigned int)((clk_get_rate(cpuclk) + 500) / 1000);
- }
- 
-+static unsigned int	ref_freq;
-+static unsigned long	loops_per_jiffy_ref;
-+
- static int at32_set_target(struct cpufreq_policy *policy,
- 			  unsigned int target_freq,
- 			  unsigned int relation)
-@@ -61,8 +64,19 @@ static int at32_set_target(struct cpufreq_policy *policy,
- 	freqs.cpu = 0;
- 	freqs.flags = 0;
- 
-+	if (!ref_freq) {
-+		ref_freq = freqs.old;
-+		loops_per_jiffy_ref = boot_cpu_data.loops_per_jiffy;
-+	}
-+
- 	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-+	if (freqs.old < freqs.new)
-+		boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-+				loops_per_jiffy_ref, ref_freq, freqs.new);
- 	clk_set_rate(cpuclk, freq);
-+	if (freqs.new < freqs.old)
-+		boot_cpu_data.loops_per_jiffy = cpufreq_scale(
-+				loops_per_jiffy_ref, ref_freq, freqs.new);
- 	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
- 
- 	pr_debug("cpufreq: set frequency %lu Hz\n", freq);
-diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
-index c36a6d5..b6870b5 100644
---- a/arch/avr32/mach-at32ap/extint.c
-+++ b/arch/avr32/mach-at32ap/extint.c
-@@ -17,6 +17,8 @@
- 
- #include <asm/io.h>
- 
-+#include <mach/cpu.h>
-+
- /* EIC register offsets */
- #define EIC_IER					0x0000
- #define EIC_IDR					0x0004
-@@ -26,24 +28,18 @@
- #define EIC_MODE				0x0014
- #define EIC_EDGE				0x0018
- #define EIC_LEVEL				0x001c
-+
-+/* This is only valid on v1 (AP700x) */
- #define EIC_NMIC				0x0024
-+# define EIC_NMIC_ENABLE			(1 << 0)
- 
--/* Bitfields in NMIC */
--#define EIC_NMIC_ENABLE				(1 << 0)
--
--/* Bit manipulation macros */
--#define EIC_BIT(name)					\
--	(1 << EIC_##name##_OFFSET)
--#define EIC_BF(name,value)				\
--	(((value) & ((1 << EIC_##name##_SIZE) - 1))	\
--	 << EIC_##name##_OFFSET)
--#define EIC_BFEXT(name,value)				\
--	(((value) >> EIC_##name##_OFFSET)		\
--	 & ((1 << EIC_##name##_SIZE) - 1))
--#define EIC_BFINS(name,value,old)			\
--	(((old) & ~(((1 << EIC_##name##_SIZE) - 1)	\
--		    << EIC_##name##_OFFSET))		\
--	 | EIC_BF(name,value))
-+/* These are only valid on v3 (AP720x) */
-+#define EIC_FILTER				0x0020
-+#define EIC_TEST				0x0024
-+#define EIC_ASYNC				0x0028
-+#define EIC_EN					0x0030
-+#define EIC_DIS					0x0034
-+#define EIC_CTRL				0x0038
- 
- /* Register access macros */
- #define eic_readl(port,reg)				\
-@@ -60,36 +56,68 @@ struct eic {
- static struct eic *nmi_eic;
- static bool nmi_enabled;
- 
-+static inline int eic_version(struct eic *eic)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static inline int eic_irq_bitmask(struct eic *eic, unsigned int irq)
-+{
-+	irq -= eic->first_irq;
-+
-+	if (eic_version(eic) > 2)
-+		irq++;
-+	return 1 << irq;
-+}
-+
- static void eic_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_mask_ack_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, ICR, 1 << (irq - eic->first_irq));
--	eic_writel(eic, IDR, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, ICR, eic_irq_bitmask(eic, irq));
-+	eic_writel(eic, IDR, eic_irq_bitmask(eic, irq));
- }
- 
- static void eic_unmask_irq(unsigned int irq)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
--	eic_writel(eic, IER, 1 << (irq - eic->first_irq));
-+	eic_writel(eic, IER, eic_irq_bitmask(eic, irq));
-+}
-+
-+/* The following two hooks are only used on v2+ controllers */
-+static void eic_enable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, EN, eic_irq_bitmask(eic, irq));
-+}
-+
-+static void eic_disable_irq(unsigned int irq)
-+{
-+	struct eic *eic = get_irq_chip_data(irq);
-+	eic_writel(eic, DIS, eic_irq_bitmask(eic, irq));
- }
- 
- static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
- {
- 	struct eic *eic = get_irq_chip_data(irq);
- 	struct irq_desc *desc;
--	unsigned int i = irq - eic->first_irq;
-+	unsigned int irq_bitmask = eic_irq_bitmask(eic, irq);
- 	u32 mode, edge, level;
- 	int ret = 0;
- 
-@@ -105,20 +133,20 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
- 
- 	switch (flow_type) {
- 	case IRQ_TYPE_LEVEL_LOW:
--		mode |= 1 << i;
--		level &= ~(1 << i);
-+		mode |= irq_bitmask;
-+		level &= ~irq_bitmask;
- 		break;
- 	case IRQ_TYPE_LEVEL_HIGH:
--		mode |= 1 << i;
--		level |= 1 << i;
-+		mode |= irq_bitmask;
-+		level |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_RISING:
--		mode &= ~(1 << i);
--		edge |= 1 << i;
-+		mode &= ~irq_bitmask;
-+		edge |= irq_bitmask;
- 		break;
- 	case IRQ_TYPE_EDGE_FALLING:
--		mode &= ~(1 << i);
--		edge &= ~(1 << i);
-+		mode &= ~irq_bitmask;
-+		edge &= ~irq_bitmask;
- 		break;
- 	default:
- 		ret = -EINVAL;
-@@ -160,6 +188,11 @@ static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
- 	status = eic_readl(eic, ISR);
- 	pending = status & eic_readl(eic, IMR);
- 
-+	if (eic_version(eic) > 1) {
-+		status >>= 1;
-+		pending >>= 1;
-+	}
-+
- 	while (pending) {
- 		i = fls(pending) - 1;
- 		pending &= ~(1 << i);
-@@ -172,16 +205,34 @@ int nmi_enable(void)
- {
- 	nmi_enabled = true;
- 
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, EN, 1 << 0);
-+			eic_writel(nmi_eic, IER, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, EN, 1 << 8);
-+			eic_writel(nmi_eic, IER, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+		}
-+	}
- 
- 	return 0;
- }
- 
- void nmi_disable(void)
- {
--	if (nmi_eic)
--		eic_writel(nmi_eic, NMIC, 0);
-+	if (nmi_eic) {
-+		if (eic_version(nmi_eic) > 2) {
-+			eic_writel(nmi_eic, IDR, 1 << 0);
-+			eic_writel(nmi_eic, DIS, 1 << 0);
-+		} else if (eic_version(nmi_eic) > 1) {
-+			eic_writel(nmi_eic, IDR, 1 << 8);
-+			eic_writel(nmi_eic, DIS, 1 << 8);
-+		} else {
-+			eic_writel(nmi_eic, NMIC, 0);
-+		}
-+	}
- 
- 	nmi_enabled = false;
- }
-@@ -230,6 +281,15 @@ static int __init eic_probe(struct platform_device *pdev)
- 	eic_writel(eic, EDGE, 0UL);
- 	eic_writel(eic, LEVEL, 0UL);
- 
-+	/*
-+	 * v2+ controllers have an extra enable/disable/mask set of
-+	 * registers.
-+	 */
-+	if (eic_version(eic) >= 2) {
-+		eic_chip.enable = eic_enable_irq;
-+		eic_chip.disable = eic_disable_irq;
-+	}
-+
- 	eic->chip = &eic_chip;
- 
- 	for (i = 0; i < nr_irqs; i++) {
-diff --git a/arch/avr32/mach-at32ap/gpio-v2.c b/arch/avr32/mach-at32ap/gpio-v2.c
-new file mode 100644
-index 0000000..63b8943
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/gpio-v2.c
-@@ -0,0 +1,534 @@
-+/*
-+ * Atmel GPIO Port Multiplexer support
-+ *
-+ * Copyright (C) 2004-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/debugfs.h>
-+#include <linux/fs.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <mach/portmux.h>
-+#include <mach/chip.h>
-+
-+#include "gpio-v2.h"
-+
-+/*
-+ * One chip corresponds with one bank of I/O registers. They're really
-+ * all on the same controller.
-+ */
-+struct atmel_gpio_chip {
-+	void __iomem	*regs;
-+	u32		pinmux_mask;
-+	struct		gpio_chip chip;
-+	char		name[8];
-+	unsigned int	bank;
-+	int		irq;
-+};
-+
-+/* ...which means we only have one clock and one platform device */
-+static struct clk *gpio_clk;
-+static struct atmel_gpio_chip gpio_dev[NR_GPIO_BANKS];
-+
-+/* Pin multiplexing API */
-+static DEFINE_SPINLOCK(gpio_lock);
-+
-+static struct atmel_gpio_chip *to_atmel_gpio_chip(struct gpio_chip *chip)
-+{
-+	return container_of(chip, struct atmel_gpio_chip, chip);
-+}
-+
-+static struct atmel_gpio_chip *pin_to_chip(unsigned int gpio)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int index;
-+
-+	index = gpio >> 5;
-+	if (index >= NR_GPIO_BANKS)
-+		return NULL;
-+	chip = &gpio_dev[index];
-+	if (!chip->regs)
-+		return NULL;
-+
-+	return chip;
-+}
-+
-+/* Pin multiplexing API */
-+
-+void __init at32_select_periph(unsigned int port, u32 pin_mask,
-+		unsigned int periph, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(gpiochip_is_requested(&chip->chip, port)
-+			|| unlikely(pin_mask & chip->pinmux_mask))) {
-+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
-+		       chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	switch (periph) {
-+	case GPIO_PERIPH_A:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_B:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1C, pin_mask);
-+		break;
-+	case GPIO_PERIPH_C:
-+		gpio_writel(chip, PMR0C, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	case GPIO_PERIPH_D:
-+		gpio_writel(chip, PMR0S, pin_mask);
-+		gpio_writel(chip, PMR1S, pin_mask);
-+		break;
-+	default:
-+		printk("%s: unknown function for pin mask %u\n",
-+				chip->name, pin_mask);
-+		goto fail;
-+	}
-+
-+	gpio_writel(chip, PUERS, pin_mask);
-+
-+	gpio_writel(chip, GPERC, pin_mask);
-+	if (!(flags & AT32_GPIOF_PULLUP))
-+		gpio_writel(chip, PUERC, pin_mask);
-+
-+	spin_unlock(&gpio_lock);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+void __init at32_select_gpio(unsigned int pin, unsigned long flags)
-+{
-+	struct atmel_gpio_chip *chip;
-+	unsigned int pin_index = pin & 0x1f;
-+	u32 mask = 1 << pin_index;
-+
-+	chip = pin_to_chip(pin);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid pin %u\n", pin);
-+		goto fail;
-+	}
-+
-+	if (unlikely(test_and_set_bit(pin_index, &chip->pinmux_mask))) {
-+		printk("%s: pin %u is busy\n", chip->name, pin_index);
-+		goto fail;
-+	}
-+
-+	if (flags & AT32_GPIOF_PULLUP)
-+		gpio_writel(chip, PUERS, mask);
-+	else
-+		gpio_writel(chip, PUERC, mask);
-+	if (flags & AT32_GPIOF_MULTIDRV)
-+		gpio_writel(chip, ODMERS, mask);
-+	else
-+		gpio_writel(chip, ODMERC, mask);
-+	if (flags & AT32_GPIOF_DEGLITCH)
-+		gpio_writel(chip, GFERS, mask);
-+	else
-+		gpio_writel(chip, GFERC, mask);
-+
-+	if (flags & AT32_GPIOF_OUTPUT) {
-+		if (flags & AT32_GPIOF_HIGH)
-+			gpio_writel(chip, OVRS, mask);
-+		else
-+			gpio_writel(chip, OVRC, mask);
-+		gpio_writel(chip, ODERS, mask);
-+	} else {
-+		gpio_writel(chip, ODERC, mask);
-+	}
-+
-+	gpio_writel(chip, GPERS, mask);
-+
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/* Reserve a pin, preventing anyone else from changing its configuration. */
-+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-+{
-+	struct atmel_gpio_chip *chip;
-+
-+	chip = pin_to_chip(port);
-+	if (unlikely(!chip)) {
-+		printk("GPIO: invalid port %u\n", port);
-+		goto fail;
-+	}
-+
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&gpio_lock);
-+	if (unlikely(pin_mask & chip->pinmux_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
-+			chip->name, pin_mask, chip->pinmux_mask & pin_mask);
-+		spin_unlock(&gpio_lock);
-+		goto fail;
-+	}
-+
-+	/* Reserve pins */
-+	chip->pinmux_mask |= pin_mask;
-+	spin_unlock(&gpio_lock);
-+	return;
-+
-+fail:
-+	dump_stack();
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO API */
-+
-+static int get_pin_state(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+
-+	return (gpio_readl(gpio, PVR) >> offset) & 1;
-+}
-+
-+static void set_pin_state(struct gpio_chip *chip, unsigned int offset, int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (high)
-+		gpio_writel(gpio, OVRS, mask);
-+	else
-+		gpio_writel(gpio, OVRC, mask);
-+}
-+
-+static int direction_input(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	gpio_writel(gpio, ODERC, mask);
-+	return 0;
-+}
-+
-+static int direction_output(struct gpio_chip *chip, unsigned int offset,
-+		int high)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32 mask = 1 << offset;
-+
-+	if (!(gpio_readl(gpio, GPER) & mask))
-+		return -EINVAL;
-+
-+	set_pin_state(chip, offset, high);
-+	gpio_writel(gpio, ODERS, mask);
-+	return 0;
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+/* GPIO IRQ support */
-+
-+static void gpio_irq_mask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERC, 1 << (pin & 0x1f));
-+}
-+
-+static void gpio_irq_unmask(unsigned irq)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+
-+	gpio_writel(chip, IERS, 1 << (pin & 0x1f));
-+}
-+
-+static int gpio_irq_type(unsigned irq, unsigned type)
-+{
-+	unsigned int		pin = irq_to_gpio(irq);
-+	struct atmel_gpio_chip	*chip = &gpio_dev[pin >> 5];
-+	u32			mask = 1 << (pin & 0x1f);
-+
-+	switch (type) {
-+	case IRQ_TYPE_EDGE_FALLING:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1S, mask);
-+		break;
-+	case IRQ_TYPE_EDGE_RISING:
-+		gpio_writel(chip, IMR0S, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	case IRQ_TYPE_NONE:
-+		/* fall through */
-+	case IRQ_TYPE_EDGE_BOTH:
-+		gpio_writel(chip, IMR0C, mask);
-+		gpio_writel(chip, IMR1C, mask);
-+		break;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct irq_chip gpio_irqchip = {
-+	.name		= "gpio",
-+	.mask		= gpio_irq_mask,
-+	.unmask		= gpio_irq_unmask,
-+	.set_type	= gpio_irq_type,
-+};
-+
-+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+	struct atmel_gpio_chip	*chip = get_irq_chip_data(irq);
-+	unsigned int		gpio_irq;
-+
-+	gpio_irq = (unsigned int) get_irq_data(irq);
-+	for (;;) {
-+		u32		ifr;
-+		struct irq_desc	*d;
-+
-+		/* ack pending GPIO interrupts */
-+		ifr = gpio_readl(chip, IFR);
-+		if (!ifr)
-+			break;
-+		do {
-+			int pin;
-+
-+			pin = ffs(ifr) - 1;
-+			ifr &= ~(1 << pin);
-+			gpio_writel(chip, IFRC, (1 << pin));
-+
-+			pin += gpio_irq;
-+			d = &irq_desc[pin];
-+
-+			d->handle_irq(pin, d);
-+		} while (ifr);
-+	}
-+}
-+
-+static void __init
-+gpio_irq_setup(struct atmel_gpio_chip *chip, int irq, int gpio_irq)
-+{
-+	unsigned	i;
-+
-+	set_irq_chip_data(irq, chip);
-+	set_irq_data(irq, (void *) gpio_irq);
-+
-+	for (i = 0; i < 32; i++, gpio_irq++) {
-+		set_irq_chip_data(gpio_irq, chip);
-+		set_irq_chip_and_handler(gpio_irq, &gpio_irqchip,
-+				handle_simple_irq);
-+	}
-+
-+	set_irq_chained_handler(irq, gpio_irq_handler);
-+}
-+
-+/*--------------------------------------------------------------------------*/
-+
-+#ifdef CONFIG_DEBUG_FS
-+
-+#include <linux/seq_file.h>
-+
-+/*
-+ * This shows more info than the generic gpio dump code:
-+ * pullups, deglitching, open drain drive.
-+ */
-+static void gpio_bank_show(struct seq_file *s, struct gpio_chip *chip)
-+{
-+	struct atmel_gpio_chip *gpio = to_atmel_gpio_chip(chip);
-+	u32		oder, ovr, puer, pder, gfer, odmer, ier, imr0, imr1;
-+	unsigned int	i;
-+	u32		mask;
-+
-+	oder = gpio_readl(gpio, ODER);
-+	ovr = gpio_readl(gpio, OVR);
-+	puer = gpio_readl(gpio, PUER);
-+	pder = gpio_readl(gpio, PDER);
-+	gfer = gpio_readl(gpio, GFER);
-+	odmer = gpio_readl(gpio, ODMER);
-+	ier = gpio_readl(gpio, IER);
-+	imr0 = gpio_readl(gpio, IMR0);
-+	imr1 = gpio_readl(gpio, IMR1);
-+
-+	for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
-+		const char *label;
-+
-+		label = gpiochip_is_requested(chip, i);
-+		if (!label)
-+			continue;
-+
-+		seq_printf(s, " gpio-%-3d ", chip->base + i);
-+		gpio_decode_pin(s, gpio->bank, i);
-+		seq_printf(s, " (%-12s) %s %s", label,
-+				(oder & mask) ? "out" : "in",
-+				(ovr & mask) ? "hi" : "lo");
-+		if ((puer & mask) && !(pder & mask))
-+			seq_printf(s, " pull-up");
-+		else if (!(puer & mask) && (pder & mask))
-+			seq_printf(s, " pull-down");
-+		else if ((puer & mask) && (pder & mask))
-+			seq_printf(s, " buskeeper");
-+		if (gfer & mask)
-+			seq_printf(s, " deglitch");
-+		if (odmer & mask)
-+			seq_printf(s, " open-drain");
-+		if ((gpio->irq >= 0) && (ier & mask)) {
-+			seq_printf(s, " irq-%d edge-",
-+					gpio_to_irq(chip->base + i));
-+			if (!(imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "both");
-+			else if ((imr0 & mask) && !(imr1 & mask))
-+				seq_printf(s, "rising");
-+			else if (!(imr0 & mask) && (imr1 & mask))
-+				seq_printf(s, "falling");
-+			else
-+				seq_printf(s, "INVALID");
-+		}
-+		seq_printf(s, "\n");
-+	}
-+}
-+
-+#else
-+#define gpio_bank_show	NULL
-+#endif
-+
-+static int __init gpio_probe(struct platform_device *pdev)
-+{
-+	struct resource *regs;
-+	struct resource *irqs;
-+	int irq = -1;
-+	unsigned int i;
-+
-+	BUG_ON(pdev->id >= 1);
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return -ENXIO;
-+	}
-+	irqs = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+	if (irqs)
-+		irq = irqs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		unsigned int gpio_irq_base;
-+		struct atmel_gpio_chip *chip;
-+
-+		chip = &gpio_dev[i];
-+		BUG_ON(!chip->regs);
-+
-+		chip->chip.label = chip->name;
-+		chip->chip.base = i * 32;
-+		chip->chip.ngpio = 32;
-+
-+		chip->chip.direction_input = direction_input;
-+		chip->chip.get = get_pin_state;
-+		chip->chip.direction_output = direction_output;
-+		chip->chip.set = set_pin_state;
-+		chip->chip.dbg_show = gpio_bank_show;
-+
-+		gpiochip_add(&chip->chip);
-+
-+		gpio_irq_base = GPIO_IRQ_BASE + (i * 32);
-+		if (irqs && irq <= irqs->end) {
-+			gpio_irq_setup(chip, irq, gpio_irq_base);
-+			chip->irq = irq;
-+			irq++;
-+		} else {
-+			chip->irq = -1;
-+		}
-+
-+		platform_set_drvdata(pdev, chip);
-+
-+		printk(KERN_DEBUG "%s: base 0x%p", chip->name, chip->regs);
-+		if (chip->irq >= 0)
-+			printk(" irq %d chains %d..%d", irq,
-+					gpio_irq_base, gpio_irq_base + 31);
-+		printk("\n");
-+	}
-+
-+	return 0;
-+}
-+
-+static struct platform_driver gpio_driver = {
-+	.probe		= gpio_probe,
-+	.driver		= {
-+		.name		= "gpio",
-+	},
-+};
-+
-+static int __init gpio_init(void)
-+{
-+	return platform_driver_register(&gpio_driver);
-+}
-+postcore_initcall(gpio_init);
-+
-+void __init at32_gpio_init(struct platform_device *pdev)
-+{
-+	int i;
-+	struct clk *clk;
-+	struct resource *regs;
-+	void __iomem *iomem_base;
-+	struct atmel_gpio_chip *chip;
-+
-+	if (pdev->id > 0) {
-+		dev_err(&pdev->dev, "only one GPIO controller supported\n");
-+		return;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(&pdev->dev, "no mmio resource defined\n");
-+		return;
-+	}
-+
-+	clk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(clk)) {
-+		dev_err(&pdev->dev, "no mck clock defined\n");
-+		return;
-+	}
-+	clk_enable(clk);
-+
-+	gpio_clk = clk;
-+
-+	/*
-+	 * We may get called too early for ioremap() to work. But we
-+	 * know that the GPIO registers are permanently mapped 1:1
-+	 */
-+	iomem_base = (void __iomem __force *)regs->start;
-+
-+	for (i = 0; i < NR_GPIO_BANKS; i++) {
-+		chip = &gpio_dev[i];
-+		snprintf(chip->name, sizeof(chip->name), "gpio%d", i);
-+		chip->regs = iomem_base + (i * 0x200);
-+		chip->bank = i;
-+
-+		/* start with irqs disabled and acked */
-+		gpio_writel(chip, IERC, ~0UL);
-+		gpio_writel(chip, IFRC, ~0UL);
-+	}
-+}
-diff --git a/arch/avr32/mach-at32ap/gpio-v2.h b/arch/avr32/mach-at32ap/gpio-v2.h
-new file mode 100644
-index 0000000..77e4105
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/gpio-v2.h
-@@ -0,0 +1,116 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+#ifndef __GPIO_REGS_H__
-+#define __GPIO_REGS_H__
-+
-+/* Register offsets */
-+struct gpio_regs {
-+	u32	GPER;
-+	u32	GPERS;
-+	u32	GPERC;
-+	u32	GPERT;
-+	u32	PMR0;
-+	u32	PMR0S;
-+	u32	PMR0C;
-+	u32	PMR0T;
-+	u32	PMR1;
-+	u32	PMR1S;
-+	u32	PMR1C;
-+	u32	PMR1T;
-+	u32	__reserved0[4];
-+	u32	ODER;
-+	u32	ODERS;
-+	u32	ODERC;
-+	u32	ODERT;
-+	u32	OVR;
-+	u32	OVRS;
-+	u32	OVRC;
-+	u32	OVRT;
-+	u32	PVR;
-+	u32	__reserved_PVRS;
-+	u32	__reserved_PVRC;
-+	u32	__reserved_PVRT;
-+	u32	PUER;
-+	u32	PUERS;
-+	u32	PUERC;
-+	u32	PUERT;
-+	u32	PDER;
-+	u32	PDERS;
-+	u32	PDERC;
-+	u32	PDERT;
-+	u32	IER;
-+	u32	IERS;
-+	u32	IERC;
-+	u32	IERT;
-+	u32	IMR0;
-+	u32	IMR0S;
-+	u32	IMR0C;
-+	u32	IMR0T;
-+	u32	IMR1;
-+	u32	IMR1S;
-+	u32	IMR1C;
-+	u32	IMR1T;
-+	u32	GFER;
-+	u32	GFERS;
-+	u32	GFERC;
-+	u32	GFERT;
-+	u32	IFR;
-+	u32	__reserved_IFRS;
-+	u32	IFRC;
-+	u32	__reserved_IFRT;
-+	u32	ODMER;
-+	u32	ODMERS;
-+	u32	ODMERC;
-+	u32	ODMERT;
-+	u32	__reserved1[4];
-+	u32	ODCR0;
-+	u32	ODCR0S;
-+	u32	ODCR0C;
-+	u32	ODCR0T;
-+	u32	ODCR1;
-+	u32	ODCR1S;
-+	u32	ODCR1C;
-+	u32	ODCR1T;
-+	u32	__reserved2[4];
-+	u32	OSRR0;
-+	u32	OSRR0S;
-+	u32	OSRR0C;
-+	u32	OSRR0T;
-+	u32	__reserved3[8];
-+	u32	STER;
-+	u32	STERS;
-+	u32	STERC;
-+	u32	STERT;
-+	u32	__reserved4[35];
-+	u32	VERSION;
-+};
-+
-+/* Register access macros */
-+#define __gpio_regs(bank) ((struct gpio_regs __iomem *)(bank)->regs)
-+#define gpio_readl(bank, reg)						\
-+	__raw_readl(&__gpio_regs(bank)->reg)
-+#define gpio_writel(bank, reg, value)					\
-+	__raw_writel(value, &__gpio_regs(bank)->reg)
-+
-+void at32_gpio_init(struct platform_device *pdev);
-+
-+#endif /* __GPIO_REGS_H__ */
-diff --git a/arch/avr32/mach-at32ap/hmatrix.c b/arch/avr32/mach-at32ap/hmatrix.c
-index 48f5ede..2f55e69 100644
---- a/arch/avr32/mach-at32ap/hmatrix.c
-+++ b/arch/avr32/mach-at32ap/hmatrix.c
-@@ -54,6 +54,81 @@ u32 hmatrix_read_reg(unsigned long offset)
- }
- 
- /**
-+ * hmatrix_set_default_master - set default master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ */
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MASTER_LAST);
-+
-+	reg = HMATRIX_SCFG(slave);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	value = __hmatrix_read_reg(reg);
-+	value &= ~(HMATRIX_SCFG_FIXED_DEFMSTR(HMATRIX_MAX_SLAVE)
-+			| HMATRIX_SCFG_DEFMSTR_MASK);
-+
-+	switch (master) {
-+	case HMATRIX_MASTER_NONE:
-+		value |= HMATRIX_SCFG_DEFMSTR_NONE;
-+		break;
-+	case HMATRIX_MASTER_LAST:
-+		value |= HMATRIX_SCFG_DEFMSTR_LAST;
-+		break;
-+	default:
-+		value |= HMATRIX_SCFG_DEFMSTR_FIXED;
-+		value |= HMATRIX_SCFG_FIXED_DEFMSTR(master);
-+		break;
-+	}
-+
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-+ * hmatrix_set_priority - set the priority of a master on a given slave
-+ * @slave: HSB slave interface ID
-+ * @master: HSB master interface ID
-+ * @priority: Priority of @master when competing for access to @slave.
-+ *
-+ * Note that this is currently broken -- we need some way to enable
-+ * fixed-priority arbitration, and that happens to be broken on AP7000
-+ * rev C.
-+ */
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority)
-+{
-+	u32 value;
-+	unsigned int reg;
-+
-+	WARN_ON(slave > HMATRIX_MAX_SLAVE
-+			|| master > HMATRIX_MAX_MASTER
-+			|| priority > HMATRIX_MAX_PRIO);
-+
-+	clk_enable(&at32_hmatrix_clk);
-+	if (master < 8) {
-+		reg = HMATRIX_PRAS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRAS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRAS_PRIO(master, priority);
-+	} else {
-+		reg = HMATRIX_PRBS(slave);
-+		value = __hmatrix_read_reg(reg);
-+		value &= ~HMATRIX_PRBS_PRIO(master, HMATRIX_MAX_PRIO);
-+		value |= HMATRIX_PRBS_PRIO(master, priority);
-+	}
-+	__hmatrix_write_reg(reg, value);
-+	__hmatrix_read_reg(reg);
-+	clk_disable(&at32_hmatrix_clk);
-+}
-+
-+/**
-  * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
-  * @slave_id: operate on the SFR belonging to this slave
-  * @mask: mask of bits to be set in the SFR
-diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
-index 2875c11..3152e0f 100644
---- a/arch/avr32/mach-at32ap/hsmc.c
-+++ b/arch/avr32/mach-at32ap/hsmc.c
-@@ -229,10 +229,8 @@ static int hsmc_probe(struct platform_device *pdev)
- 	if (IS_ERR(pclk))
- 		return PTR_ERR(pclk);
- 	mck = clk_get(&pdev->dev, "mck");
--	if (IS_ERR(mck)) {
--		ret = PTR_ERR(mck);
--		goto out_put_pclk;
--	}
-+	if (IS_ERR(mck))
-+		mck = pclk;
- 
- 	ret = -ENOMEM;
- 	hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
-@@ -260,8 +258,8 @@ out_disable_clocks:
- 	clk_disable(pclk);
- 	kfree(hsmc);
- out_put_clocks:
--	clk_put(mck);
--out_put_pclk:
-+	if (mck != pclk)
-+		clk_put(mck);
- 	clk_put(pclk);
- 	hsmc = NULL;
- 	return ret;
-diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-index 1e9852d..5c4c971 100644
---- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-+++ b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
-@@ -83,4 +83,135 @@
- #define HMATRIX_BASE	0xfff00800
- #define SDRAMC_BASE	0xfff03800
- 
-+/* LCDC on port C */
-+#define ATMEL_LCDC_PC_CC	(1ULL << 19)
-+#define ATMEL_LCDC_PC_HSYNC	(1ULL << 20)
-+#define ATMEL_LCDC_PC_PCLK	(1ULL << 21)
-+#define ATMEL_LCDC_PC_VSYNC	(1ULL << 22)
-+#define ATMEL_LCDC_PC_DVAL	(1ULL << 23)
-+#define ATMEL_LCDC_PC_MODE	(1ULL << 24)
-+#define ATMEL_LCDC_PC_PWR	(1ULL << 25)
-+#define ATMEL_LCDC_PC_DATA0	(1ULL << 26)
-+#define ATMEL_LCDC_PC_DATA1	(1ULL << 27)
-+#define ATMEL_LCDC_PC_DATA2	(1ULL << 28)
-+#define ATMEL_LCDC_PC_DATA3	(1ULL << 29)
-+#define ATMEL_LCDC_PC_DATA4	(1ULL << 30)
-+#define ATMEL_LCDC_PC_DATA5	(1ULL << 31)
-+
-+/* LCDC on port D */
-+#define ATMEL_LCDC_PD_DATA6	(1ULL << 0)
-+#define ATMEL_LCDC_PD_DATA7	(1ULL << 1)
-+#define ATMEL_LCDC_PD_DATA8	(1ULL << 2)
-+#define ATMEL_LCDC_PD_DATA9	(1ULL << 3)
-+#define ATMEL_LCDC_PD_DATA10	(1ULL << 4)
-+#define ATMEL_LCDC_PD_DATA11	(1ULL << 5)
-+#define ATMEL_LCDC_PD_DATA12	(1ULL << 6)
-+#define ATMEL_LCDC_PD_DATA13	(1ULL << 7)
-+#define ATMEL_LCDC_PD_DATA14	(1ULL << 8)
-+#define ATMEL_LCDC_PD_DATA15	(1ULL << 9)
-+#define ATMEL_LCDC_PD_DATA16	(1ULL << 10)
-+#define ATMEL_LCDC_PD_DATA17	(1ULL << 11)
-+#define ATMEL_LCDC_PD_DATA18	(1ULL << 12)
-+#define ATMEL_LCDC_PD_DATA19	(1ULL << 13)
-+#define ATMEL_LCDC_PD_DATA20	(1ULL << 14)
-+#define ATMEL_LCDC_PD_DATA21	(1ULL << 15)
-+#define ATMEL_LCDC_PD_DATA22	(1ULL << 16)
-+#define ATMEL_LCDC_PD_DATA23	(1ULL << 17)
-+
-+/* LCDC on port E */
-+#define ATMEL_LCDC_PE_CC	(1ULL << (32 + 0))
-+#define ATMEL_LCDC_PE_DVAL	(1ULL << (32 + 1))
-+#define ATMEL_LCDC_PE_MODE	(1ULL << (32 + 2))
-+#define ATMEL_LCDC_PE_DATA0	(1ULL << (32 + 3))
-+#define ATMEL_LCDC_PE_DATA1	(1ULL << (32 + 4))
-+#define ATMEL_LCDC_PE_DATA2	(1ULL << (32 + 5))
-+#define ATMEL_LCDC_PE_DATA3	(1ULL << (32 + 6))
-+#define ATMEL_LCDC_PE_DATA4	(1ULL << (32 + 7))
-+#define ATMEL_LCDC_PE_DATA8	(1ULL << (32 + 8))
-+#define ATMEL_LCDC_PE_DATA9	(1ULL << (32 + 9))
-+#define ATMEL_LCDC_PE_DATA10	(1ULL << (32 + 10))
-+#define ATMEL_LCDC_PE_DATA11	(1ULL << (32 + 11))
-+#define ATMEL_LCDC_PE_DATA12	(1ULL << (32 + 12))
-+#define ATMEL_LCDC_PE_DATA16	(1ULL << (32 + 13))
-+#define ATMEL_LCDC_PE_DATA17	(1ULL << (32 + 14))
-+#define ATMEL_LCDC_PE_DATA18	(1ULL << (32 + 15))
-+#define ATMEL_LCDC_PE_DATA19	(1ULL << (32 + 16))
-+#define ATMEL_LCDC_PE_DATA20	(1ULL << (32 + 17))
-+#define ATMEL_LCDC_PE_DATA21	(1ULL << (32 + 18))
-+
-+
-+#define ATMEL_LCDC(PORT, PIN)	(ATMEL_LCDC_##PORT##_##PIN)
-+
-+
-+#define ATMEL_LCDC_PRI_24B_DATA	(					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) |	\
-+		ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) |	\
-+		ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_ALT_24B_DATA (					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA6)  | ATMEL_LCDC(PD, DATA7)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) |	\
-+		ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) |	\
-+		ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) |	\
-+		ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) |	\
-+		ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) |	\
-+		ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-+
-+#define ATMEL_LCDC_PRI_15B_DATA (					\
-+		ATMEL_LCDC(PC, DATA0)  | ATMEL_LCDC(PC, DATA1)  |	\
-+		ATMEL_LCDC(PC, DATA2)  | ATMEL_LCDC(PC, DATA3)  |	\
-+		ATMEL_LCDC(PC, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PD, DATA8)  | ATMEL_LCDC(PD, DATA9)  |	\
-+		ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) |	\
-+		ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA16) |	\
-+		ATMEL_LCDC(PD, DATA17) | ATMEL_LCDC(PD, DATA18) |	\
-+		ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20))
-+
-+#define ATMEL_LCDC_ALT_15B_DATA	(					\
-+		ATMEL_LCDC(PE, DATA0)  | ATMEL_LCDC(PE, DATA1)  |	\
-+		ATMEL_LCDC(PE, DATA2)  | ATMEL_LCDC(PE, DATA3)  |	\
-+		ATMEL_LCDC(PE, DATA4)  | ATMEL_LCDC(PC, DATA5)  |	\
-+		ATMEL_LCDC(PE, DATA8)  | ATMEL_LCDC(PE, DATA9)  |	\
-+		ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) |	\
-+		ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PE, DATA16) |	\
-+		ATMEL_LCDC(PE, DATA17) | ATMEL_LCDC(PE, DATA18) |	\
-+		ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20))
-+
-+#define ATMEL_LCDC_PRI_CONTROL (					\
-+		ATMEL_LCDC(PC, CC)   | ATMEL_LCDC(PC, DVAL) |		\
-+		ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_ALT_CONTROL (					\
-+		ATMEL_LCDC(PE, CC)   | ATMEL_LCDC(PE, DVAL) |		\
-+		ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
-+
-+#define ATMEL_LCDC_CONTROL (						\
-+		ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) |		\
-+		ATMEL_LCDC(PC, PCLK))
-+
-+#define ATMEL_LCDC_PRI_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
-+
-+#define ATMEL_LCDC_ALT_24BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
-+
-+#define ATMEL_LCDC_PRI_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
-+
-+#define ATMEL_LCDC_ALT_15BIT	(ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
-+
-+/* Bitmask for all EBI data (D16..D31) pins on port E */
-+#define ATMEL_EBI_PE_DATA_ALL  (0x0000FFFF)
-+
- #endif /* __ASM_ARCH_AT32AP700X_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap720x.h b/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
-new file mode 100644
-index 0000000..5a3082a
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/include/mach/at32ap720x.h
-@@ -0,0 +1,105 @@
-+/*
-+ * Pin definitions for AT32AP7200
-+ *
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ASM_ARCH_AT32AP7200_H__
-+#define __ASM_ARCH_AT32AP7200_H__
-+
-+#define GPIO_PERIPH_A	0x00
-+#define GPIO_PERIPH_B	0x01
-+#define GPIO_PERIPH_C	0x02
-+#define GPIO_PERIPH_D	0x03
-+
-+#define NR_GPIO_BANKS	8
-+
-+/*
-+ * Pin numbers identifying specific GPIO pins on the chip. They can
-+ * also be converted to IRQ numbers by passing them through
-+ * gpio_to_irq().
-+ */
-+#define GPIO_BASE	(0)
-+
-+#define GPIO_PA_BASE	(GPIO_BASE + 0 * 32)
-+#define GPIO_PB_BASE	(GPIO_BASE + 1 * 32)
-+#define GPIO_PC_BASE	(GPIO_BASE + 2 * 32)
-+#define GPIO_PD_BASE	(GPIO_BASE + 3 * 32)
-+#define GPIO_PE_BASE	(GPIO_BASE + 4 * 32)
-+#define GPIO_PF_BASE	(GPIO_BASE + 5 * 32)
-+#define GPIO_PX_BASE	(GPIO_BASE + 6 * 32)
-+
-+#define GPIO_PIN_PA(N)	(GPIO_PA_BASE + (N))
-+#define GPIO_PIN_PB(N)	(GPIO_PB_BASE + (N))
-+#define GPIO_PIN_PC(N)	(GPIO_PC_BASE + (N))
-+#define GPIO_PIN_PD(N)	(GPIO_PD_BASE + (N))
-+#define GPIO_PIN_PE(N)	(GPIO_PE_BASE + (N))
-+#define GPIO_PIN_PF(N)	(GPIO_PF_BASE + (N))
-+#define GPIO_PIN_PX(N)	(GPIO_PX_BASE + (N))
-+
-+#define gpio_decode_pin(s, bank, offset)				\
-+	do {								\
-+		switch (bank) {						\
-+		case 7:							\
-+			offset += 32;					\
-+			/* fall through */				\
-+		case 6:							\
-+			seq_printf(s, "PX%-2u", offset);		\
-+			break;						\
-+		default:						\
-+			seq_printf(s, "P%c%-2u", bank + 'A', offset);	\
-+			break;						\
-+		}							\
-+	} while (0)
-+
-+/* HSB master IDs */
-+#define HMATRIX_MASTER_CPU_ICACHE		 0
-+#define HMATRIX_MASTER_CPU_DCACHE		 1
-+#define HMATRIX_MASTER_PDCA			 2
-+#define HMATRIX_MASTER_LCDC			 4
-+#define HMATRIX_MASTER_MPOP_IBI			 5
-+#define HMATRIX_MASTER_MPOP_OBI			 6
-+#define HMATRIX_MASTER_MPOP_OM			 7
-+#define HMATRIX_MASTER_DMACA_M0			 8
-+#define HMATRIX_MASTER_DMACA_M1			 9
-+#define HMATRIX_MASTER_USBB			10
-+#define HMATRIX_MASTER_USBH_EHCI		11
-+#define HMATRIX_MASTER_USBH_OHCI		12
-+#define HMATRIX_MASTER_MACB			13
-+
-+/* HSB slave IDs */
-+#define HMATRIX_SLAVE_BOOTROM			 0
-+#define HMATRIX_SLAVE_PBA			 1
-+#define HMATRIX_SLAVE_PBB			 2
-+#define HMATRIX_SLAVE_PBC			 3
-+#define HMATRIX_SLAVE_SRAM0			 4
-+#define HMATRIX_SLAVE_SRAM1			 5
-+#define HMATRIX_SLAVE_EBI			 6
-+#define HMATRIX_SLAVE_LCDC			 7
-+#define HMATRIX_SLAVE_MPOP			 8
-+#define HMATRIX_SLAVE_DMACA			 9
-+#define HMATRIX_SLAVE_USBB			10
-+#define HMATRIX_SLAVE_EHCI			11
-+#define HMATRIX_SLAVE_OHCI			12
-+
-+/* Bits in HMATRIX SFR6 (EBI) */
-+#define HMATRIX_EBI_SDRAM_ENABLE		(1 << 1)
-+#define HMATRIX_EBI_NAND_ENABLE			(1 << 3)
-+#define HMATRIX_EBI_CF0_ENABLE			(1 << 4)
-+#define HMATRIX_EBI_CF1_ENABLE			(1 << 5)
-+
-+/*
-+ * Base addresses of controllers that may be accessed early by
-+ * platform code.
-+ */
-+#define GPIO_HW_BASE	0xffd02000
-+#define INTC_BASE	0xffd00000
-+#define PM_BASE		0xffd00400
-+#define SDC_BASE	0xffd00800
-+#define SDRAMC_BASE	0xffe04800
-+#define HMATRIX_BASE	0xffe05000
-+
-+#endif /* __ASM_ARCH_AT32AP7200_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
-index e60e907..85441ff 100644
---- a/arch/avr32/mach-at32ap/include/mach/board.h
-+++ b/arch/avr32/mach-at32ap/include/mach/board.h
-@@ -14,8 +14,14 @@
-  */
- extern unsigned long at32_board_osc_rates[];
-   
--/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
--void at32_add_system_devices(void);
-+/*
-+ * This used to add essential system devices, but this is now done
-+ * automatically. Please don't use it in new board code.
-+ */
-+static inline void __deprecated at32_add_system_devices(void)
-+{
-+
-+}
- 
- #define ATMEL_MAX_UART	4
- extern struct platform_device *atmel_default_console_device;
-@@ -43,12 +49,20 @@ struct atmel_lcdfb_info;
- struct platform_device *
- at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- 		     unsigned long fbmem_start, unsigned long fbmem_len,
--		     unsigned int pin_config);
-+		     u64 pin_mask);
-+
-+
-+struct platform_device *
-+at32_add_device_mpop(unsigned int id, struct platform_device *lcdc_pdev,
-+		     unsigned long fbmem_start, unsigned long fbmem_len);
- 
- struct usba_platform_data;
- struct platform_device *
- at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
- 
-+struct platform_device *at32_add_device_ohci(unsigned int id);
-+struct platform_device *at32_add_device_ehci(unsigned int id);
-+
- struct ide_platform_data {
- 	u8      cs;
- };
-diff --git a/arch/avr32/mach-at32ap/include/mach/chip.h b/arch/avr32/mach-at32ap/include/mach/chip.h
-index 5efca6d..09c0fe7 100644
---- a/arch/avr32/mach-at32ap/include/mach/chip.h
-+++ b/arch/avr32/mach-at32ap/include/mach/chip.h
-@@ -12,6 +12,8 @@
- 
- #if defined(CONFIG_CPU_AT32AP700X)
- # include <mach/at32ap700x.h>
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# include <mach/at32ap720x.h>
- #else
- # error Unknown chip type selected
- #endif
-diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
-index 44d0bfa..f4a5f26 100644
---- a/arch/avr32/mach-at32ap/include/mach/cpu.h
-+++ b/arch/avr32/mach-at32ap/include/mach/cpu.h
-@@ -20,6 +20,19 @@
- # define cpu_is_at32ap7000()	(0)
- #endif
- 
-+#ifdef CONFIG_CPU_AT32AP720X
-+# define cpu_is_at32ap7200()	(1)
-+#else
-+# define cpu_is_at32ap7200()	(0)
-+#endif
-+
-+/*
-+ * Unfortunately, only AP700x has a non-broken COUNT/COMPARE
-+ * implementation. Other chips need to use different timers. The good
-+ * news is that these timers are usually better anyway.
-+ */
-+#define cpu_has_working_compare()	(cpu_is_at32ap7000())
-+
- /*
-  * Since this is AVR32, we will never run on any AT91 CPU. But these
-  * definitions may reduce clutter in common drivers.
-diff --git a/arch/avr32/mach-at32ap/include/mach/hmatrix.h b/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-index 7a368f2..8417737 100644
---- a/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-+++ b/arch/avr32/mach-at32ap/include/mach/hmatrix.h
-@@ -15,6 +15,9 @@ extern struct clk at32_hmatrix_clk;
- void hmatrix_write_reg(unsigned long offset, u32 value);
- u32 hmatrix_read_reg(unsigned long offset);
- 
-+void hmatrix_set_default_master(unsigned int slave, unsigned int master);
-+void hmatrix_set_priority(unsigned int slave, unsigned int master,
-+		unsigned int priority);
- void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
- void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- 
-@@ -33,6 +36,7 @@ void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- # define HMATRIX_SCFG_DEFMSTR_NONE	(  0 << 16)	/* No default master */
- # define HMATRIX_SCFG_DEFMSTR_LAST	(  1 << 16)	/* Last def master */
- # define HMATRIX_SCFG_DEFMSTR_FIXED	(  2 << 16)	/* Fixed def master */
-+# define HMATRIX_SCFG_DEFMSTR_MASK	(  3 << 16)
- # define HMATRIX_SCFG_FIXED_DEFMSTR(m)	((m) << 18)	/* Fixed master ID */
- # define HMATRIX_SCFG_ARBT_ROUND_ROBIN	(  0 << 24)	/* RR arbitration */
- # define HMATRIX_SCFG_ARBT_FIXED_PRIO	(  1 << 24)	/* Fixed priority */
-@@ -52,4 +56,12 @@ void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
- /* Special Function Register. Bit definitions are chip-specific */
- #define HMATRIX_SFR(s)			(0x0110 + 4 * (s))
- 
-+#define HMATRIX_MAX_SLAVE	15
-+#define HMATRIX_MAX_MASTER	15
-+#define HMATRIX_MAX_PRIO	15
-+
-+/* Special master IDs for use with hmatrix_set_default_master() */
-+#define HMATRIX_MASTER_NONE	16	/* No default master */
-+#define HMATRIX_MASTER_LAST	17	/* Last master stays connected */
-+
- #endif /* __HMATRIX_H */
-diff --git a/arch/avr32/mach-at32ap/include/mach/init.h b/arch/avr32/mach-at32ap/include/mach/init.h
-index bc40e3d..66a6866 100644
---- a/arch/avr32/mach-at32ap/include/mach/init.h
-+++ b/arch/avr32/mach-at32ap/include/mach/init.h
-@@ -15,4 +15,10 @@ void setup_board(void);
- 
- void at32_setup_serial_console(unsigned int usart_id);
- 
-+/*
-+ * Called from time_init() when a broken COUNT/COMPARE implementation
-+ * is detected.
-+ */
-+void platform_time_init(void);
-+
- #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
-diff --git a/arch/avr32/mach-at32ap/include/mach/io.h b/arch/avr32/mach-at32ap/include/mach/io.h
-index 4ec6abc..22ea79b 100644
---- a/arch/avr32/mach-at32ap/include/mach/io.h
-+++ b/arch/avr32/mach-at32ap/include/mach/io.h
-@@ -1,8 +1,7 @@
- #ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
- #define __ASM_AVR32_ARCH_AT32AP_IO_H
- 
--/* For "bizarre" halfword swapping */
--#include <linux/byteorder/swabb.h>
-+#include <linux/swab.h>
- 
- #if defined(CONFIG_AP700X_32_BIT_SMC)
- # define __swizzle_addr_b(addr)	(addr ^ 3UL)
-diff --git a/arch/avr32/mach-at32ap/include/mach/irq.h b/arch/avr32/mach-at32ap/include/mach/irq.h
-index 608e350..21f37f3 100644
---- a/arch/avr32/mach-at32ap/include/mach/irq.h
-+++ b/arch/avr32/mach-at32ap/include/mach/irq.h
-@@ -6,7 +6,7 @@
- #define AT32_EXTINT(n)	(EIM_IRQ_BASE + (n))
- 
- #define GPIO_IRQ_BASE	(EIM_IRQ_BASE + NR_EIM_IRQS)
--#define NR_GPIO_CTLR	(5 /*internal*/ + 1 /*external*/)
-+#define NR_GPIO_CTLR	(8 /*internal*/ + 1 /*external*/)
- #define NR_GPIO_IRQS	(NR_GPIO_CTLR * 32)
- 
- #define NR_IRQS		(GPIO_IRQ_BASE + NR_GPIO_IRQS)
-diff --git a/arch/avr32/mach-at32ap/include/mach/pm.h b/arch/avr32/mach-at32ap/include/mach/pm.h
-index 979b355..3f65ab1 100644
---- a/arch/avr32/mach-at32ap/include/mach/pm.h
-+++ b/arch/avr32/mach-at32ap/include/mach/pm.h
-@@ -11,13 +11,17 @@
- #define __ASM_AVR32_ARCH_PM_H
- 
- /* Possible arguments to the "sleep" instruction */
--#define CPU_SLEEP_IDLE		0
--#define CPU_SLEEP_FROZEN	1
--#define CPU_SLEEP_STANDBY	2
--#define CPU_SLEEP_STOP		3
--#define CPU_SLEEP_STATIC	5
-+#define CPU_SLEEP_IDLE		0x00
-+#define CPU_SLEEP_FROZEN	0x01
-+#define CPU_SLEEP_STANDBY	0x02
-+#define CPU_SLEEP_STOP		0x03
-+#define CPU_SLEEP_DEEPSTOP	0x04	/* Not valid on AP700x */
-+#define CPU_SLEEP_STATIC	0x05
-+#define CPU_SLEEP_SHUTDOWN	0x06	/* Not valid on AP700x */
-+#define CPU_SLEEP_UNMASK_IRQ	0x80	/* Not valid on AP700x */
- 
- #ifndef __ASSEMBLY__
-+#if defined(CONFIG_CPU_AT32AP700X)
- extern void cpu_enter_idle(void);
- extern void cpu_enter_standby(unsigned long sdramc_base);
- 
-@@ -37,15 +41,57 @@ static inline void cpu_idle_sleep(void)
- {
- 	/*
- 	 * If we're using the COUNT and COMPARE registers for
--	 * timekeeping, we can't use the IDLE state.
-+	 * timekeeping on AP7000, we can't use the IDLE state.
- 	 */
- 	if (disable_idle_sleep)
- 		cpu_relax();
- 	else
- 		cpu_enter_idle();
- }
-+#else
-+static inline void cpu_disable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enable_idle_sleep(void)
-+{
-+
-+}
-+
-+static inline void cpu_enter_idle(void)
-+{
-+	/* Enable interrupts and sleep */
-+	asm volatile("sleep %0"
-+			:
-+			: "i"(CPU_SLEEP_IDLE | CPU_SLEEP_UNMASK_IRQ)
-+			: "memory");
-+}
-+
-+static inline void cpu_idle_sleep(void)
-+{
-+	local_irq_disable();
-+	if (!test_thread_flag(TIF_NEED_RESCHED))
-+		cpu_enter_idle();
-+	local_irq_enable();
-+}
-+#endif
- 
- void intc_set_suspend_handler(unsigned long offset);
-+
-+extern unsigned long at32_get_reset_cause(void);
-+
- #endif
- 
-+#define AT32_RCAUSE_POR		(1 <<  0)	/* Power-On Reset */
-+#define AT32_RCAUSE_BOD		(1 <<  1)	/* Brown-Out Detected */
-+#define AT32_RCAUSE_EXT		(1 <<  2)	/* External Reset */
-+#define AT32_RCAUSE_WDT		(1 <<  3)	/* Watchdog Timeout */
-+#define AT32_RCAUSE_JTAG	(1 <<  4)	/* JTAG Reset */
-+#define AT32_RCAUSE_NTAE	(1 <<  5)	/* NanoTrace Access Error */
-+#define AT32_RCAUSE_SLEEP	(1 <<  6)	/* Shutdown or Static mode */
-+#define AT32_RCAUSE_CPUERR	(1 <<  7)	/* CPU Error */
-+#define AT32_RCAUSE_OCDRST	(1 <<  8)	/* OCD Reset */
-+#define AT32_RCAUSE_JTAGHARD	(1 <<  9)	/* JTAG Hard Reset */
-+
- #endif /* __ASM_AVR32_ARCH_PM_H */
-diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h
-index b1abe6b..4873024 100644
---- a/arch/avr32/mach-at32ap/include/mach/portmux.h
-+++ b/arch/avr32/mach-at32ap/include/mach/portmux.h
-@@ -21,9 +21,10 @@
- #define AT32_GPIOF_DEGLITCH	0x00000008	/* (IN) Filter glitches */
- #define AT32_GPIOF_MULTIDRV	0x00000010	/* Enable multidriver option */
- 
--void at32_select_periph(unsigned int pin, unsigned int periph,
--			unsigned long flags);
-+void at32_select_periph(unsigned int port, unsigned int pin,
-+			unsigned int periph, unsigned long flags);
- void at32_select_gpio(unsigned int pin, unsigned long flags);
--void at32_reserve_pin(unsigned int pin);
-+void at32_deselect_pin(unsigned int pin);
-+void at32_reserve_pin(unsigned int port, u32 pin_mask);
- 
- #endif /* __ASM_ARCH_PORTMUX_H__ */
-diff --git a/arch/avr32/mach-at32ap/pdc.c b/arch/avr32/mach-at32ap/pdc.c
-index 1040bda..61ab15a 100644
---- a/arch/avr32/mach-at32ap/pdc.c
-+++ b/arch/avr32/mach-at32ap/pdc.c
-@@ -35,7 +35,6 @@ static int __init pdc_probe(struct platform_device *pdev)
- }
- 
- static struct platform_driver pdc_driver = {
--	.probe		= pdc_probe,
- 	.driver		= {
- 		.name	= "pdc",
- 	},
-@@ -43,6 +42,6 @@ static struct platform_driver pdc_driver = {
- 
- static int __init pdc_init(void)
- {
--	return platform_driver_register(&pdc_driver);
-+	return platform_driver_probe(&pdc_driver, pdc_probe);
- }
- arch_initcall(pdc_init);
-diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
-index 405ee6b..09a274c 100644
---- a/arch/avr32/mach-at32ap/pio.c
-+++ b/arch/avr32/mach-at32ap/pio.c
-@@ -50,35 +50,48 @@ static struct pio_device *gpio_to_pio(unsigned int gpio)
- }
- 
- /* Pin multiplexing API */
-+static DEFINE_SPINLOCK(pio_lock);
- 
--void __init at32_select_periph(unsigned int pin, unsigned int periph,
--			       unsigned long flags)
-+void __init at32_select_periph(unsigned int port, u32 pin_mask,
-+			       unsigned int periph, unsigned long flags)
- {
- 	struct pio_device *pio;
--	unsigned int pin_index = pin & 0x1f;
--	u32 mask = 1 << pin_index;
- 
--	pio = gpio_to_pio(pin);
-+	/* assign and verify pio */
-+	pio = gpio_to_pio(port);
- 	if (unlikely(!pio)) {
--		printk("pio: invalid pin %u\n", pin);
-+		printk(KERN_WARNING "pio: invalid port %u\n", port);
- 		goto fail;
- 	}
- 
--	if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask)
--			 || gpiochip_is_requested(&pio->chip, pin_index))) {
--		printk("%s: pin %u is busy\n", pio->name, pin_index);
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&pio_lock);
-+	if (unlikely(pio->pinmux_mask & pin_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
-+		       pio->name, pin_mask, pio->pinmux_mask & pin_mask);
-+		spin_unlock(&pio_lock);
- 		goto fail;
- 	}
- 
--	pio_writel(pio, PUER, mask);
-+	pio->pinmux_mask |= pin_mask;
-+
-+	/* enable pull ups */
-+	pio_writel(pio, PUER, pin_mask);
-+
-+	/* select either peripheral A or B */
- 	if (periph)
--		pio_writel(pio, BSR, mask);
-+		pio_writel(pio, BSR, pin_mask);
- 	else
--		pio_writel(pio, ASR, mask);
-+		pio_writel(pio, ASR, pin_mask);
- 
--	pio_writel(pio, PDR, mask);
-+	/* enable peripheral control */
-+	pio_writel(pio, PDR, pin_mask);
-+
-+	/* Disable pull ups if not requested. */
- 	if (!(flags & AT32_GPIOF_PULLUP))
--		pio_writel(pio, PUDR, mask);
-+		pio_writel(pio, PUDR, pin_mask);
-+
-+	spin_unlock(&pio_lock);
- 
- 	return;
- 
-@@ -134,8 +147,11 @@ fail:
- 	dump_stack();
- }
- 
--/* Reserve a pin, preventing anyone else from changing its configuration. */
--void __init at32_reserve_pin(unsigned int pin)
-+/*
-+ * Undo a previous pin reservation. Will not affect the hardware
-+ * configuration.
-+ */
-+void at32_deselect_pin(unsigned int pin)
- {
- 	struct pio_device *pio;
- 	unsigned int pin_index = pin & 0x1f;
-@@ -143,14 +159,37 @@ void __init at32_reserve_pin(unsigned int pin)
- 	pio = gpio_to_pio(pin);
- 	if (unlikely(!pio)) {
- 		printk("pio: invalid pin %u\n", pin);
-+		dump_stack();
-+		return;
-+	}
-+
-+	clear_bit(pin_index, &pio->pinmux_mask);
-+}
-+
-+/* Reserve a pin, preventing anyone else from changing its configuration. */
-+void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-+{
-+	struct pio_device *pio;
-+
-+	/* assign and verify pio */
-+	pio = gpio_to_pio(port);
-+	if (unlikely(!pio)) {
-+		printk(KERN_WARNING "pio: invalid port %u\n", port);
- 		goto fail;
- 	}
- 
--	if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
--		printk("%s: pin %u is busy\n", pio->name, pin_index);
-+	/* Test if any of the requested pins is already muxed */
-+	spin_lock(&pio_lock);
-+	if (unlikely(pio->pinmux_mask & pin_mask)) {
-+		printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
-+		       pio->name, pin_mask, pio->pinmux_mask & pin_mask);
-+		spin_unlock(&pio_lock);
- 		goto fail;
- 	}
- 
-+	/* Reserve pins */
-+	pio->pinmux_mask |= pin_mask;
-+	spin_unlock(&pio_lock);
- 	return;
- 
- fail:
-@@ -382,7 +421,6 @@ static int __init pio_probe(struct platform_device *pdev)
- }
- 
- static struct platform_driver pio_driver = {
--	.probe		= pio_probe,
- 	.driver		= {
- 		.name		= "pio",
- 	},
-@@ -390,7 +428,7 @@ static struct platform_driver pio_driver = {
- 
- static int __init pio_init(void)
- {
--	return platform_driver_register(&pio_driver);
-+	return platform_driver_probe(&pio_driver, pio_probe);
- }
- postcore_initcall(pio_init);
- 
-diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
-index 17503b0..3d210f8 100644
---- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
-+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
-@@ -12,12 +12,9 @@
- #include <asm/thread_info.h>
- #include <mach/pm.h>
- 
--#include "pm.h"
-+#include "pm-v1.h"
- #include "sdramc.h"
- 
--/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
--#define PM_BASE	-0x100000
--
- 	.section .bss, "wa", @nobits
- 	.global	disable_idle_sleep
- 	.type	disable_idle_sleep, @object
-diff --git a/arch/avr32/mach-at32ap/pm-at32ap720x.S b/arch/avr32/mach-at32ap/pm-at32ap720x.S
-new file mode 100644
-index 0000000..a765aa5
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-at32ap720x.S
-@@ -0,0 +1,110 @@
-+/*
-+ * Low-level Power Management code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <asm/asm.h>
-+#include <asm/asm-offsets.h>
-+#include <asm/thread_info.h>
-+#include <mach/pm.h>
-+
-+#include "pm-v3.h"
-+#include "sdramc.h"
-+
-+#ifdef CONFIG_PM
-+	.section .init.text, "ax", @progbits
-+
-+	.global	pm_exception
-+	.type	pm_exception, @function
-+pm_exception:
-+	/*
-+	 * Exceptions are masked when we switch to this handler, so
-+	 * we'll only get "unrecoverable" exceptions (offset 0.)
-+	 */
-+	sub	r12, pc, . - .Lpanic_msg
-+	lddpc	pc, .Lpanic_addr
-+
-+	.align	2
-+.Lpanic_addr:
-+	.long	panic
-+.Lpanic_msg:
-+	.asciz	"Unrecoverable exception during suspend\n"
-+	.size	pm_exception, . - pm_exception
-+
-+	.global	pm_irq0
-+	.type	pm_irq0, @function
-+pm_irq0:
-+	/* Disable interrupts and return after the sleep instruction */
-+	mfsr	r9, SYSREG_RSR_INT0
-+	mtsr	SYSREG_RAR_INT0, r8
-+	sbr	r9, SYSREG_GM_OFFSET
-+	mtsr	SYSREG_RSR_INT0, r9
-+	rete
-+
-+	/*
-+	 * void cpu_enter_standby(unsigned long sdramc_base)
-+	 *
-+	 * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
-+	 * are suspended and interrupts are disabled. Interrupts
-+	 * marked as 'wakeup' event sources may still come along and
-+	 * get us out of here.
-+	 *
-+	 * The SDRAM will be put into self-refresh mode (which does
-+	 * not require a clock from the CPU), and the CPU will be put
-+	 * into "frozen" mode (HSB bus stopped). The SDRAM controller
-+	 * will automatically bring the SDRAM into normal mode on the
-+	 * first access, and the power manager will automatically
-+	 * start the HSB and CPU clocks upon a wakeup event.
-+	 */
-+	.global	pm_standby
-+	.type	pm_standby, @function
-+pm_standby:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self Refresh */
-+	sync	0			/* flush write buffer */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+	sleep	CPU_SLEEP_FROZEN | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+	retal	r12
-+	.size	pm_standby, . - pm_standby
-+
-+	.global	pm_suspend_to_ram
-+	.type	pm_suspend_to_ram, @function
-+pm_suspend_to_ram:
-+	/*
-+	 * interrupts are already masked at this point, and EVBA
-+	 * points to pm_exception above.
-+	 */
-+	mov	r11, 0
-+	cache	r11[2], 8		/* clean all dcache lines */
-+	sync	0			/* flush write buffer */
-+	ld.w	r10, r12[SDRAMC_LPR]
-+	sub	r8, pc, . - 1f		/* return address for irq handler */
-+	mov	r11, SDRAMC_LPR_LPCB_SELF_RFR
-+	bfins	r10, r11, 0, 2		/* LPCB <- self refresh */
-+	st.w	r12[SDRAMC_LPR], r10	/* put SDRAM in self-refresh mode */
-+	ld.w	r11, r12[SDRAMC_LPR]
-+
-+	sleep	CPU_SLEEP_STOP | CPU_SLEEP_UNMASK_IRQ
-+1:	mask_interrupts
-+
-+	retal	r12
-+	.size	pm_suspend_to_ram, . - pm_suspend_to_ram
-+
-+	.global	pm_sram_end
-+	.type	pm_sram_end, @function
-+pm_sram_end:
-+	.size	pm_sram_end, 0
-+
-+#endif /* CONFIG_PM */
-diff --git a/arch/avr32/mach-at32ap/pm-v1.h b/arch/avr32/mach-at32ap/pm-v1.h
-new file mode 100644
-index 0000000..532a373
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-v1.h
-@@ -0,0 +1,112 @@
-+/*
-+ * Register definitions for the Power Manager (PM)
-+ */
-+#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
-+#define __ARCH_AVR32_MACH_AT32AP_PM_H__
-+
-+/* PM register offsets */
-+#define PM_MCCTRL				0x0000
-+#define PM_CKSEL				0x0004
-+#define PM_CPU_MASK				0x0008
-+#define PM_HSB_MASK				0x000c
-+#define PM_PBA_MASK				0x0010
-+#define PM_PBB_MASK				0x0014
-+#define PM_PLL0					0x0020
-+#define PM_PLL1					0x0024
-+#define PM_IER					0x0040
-+#define PM_IDR					0x0044
-+#define PM_IMR					0x0048
-+#define PM_ISR					0x004c
-+#define PM_ICR					0x0050
-+#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
-+#define PM_RCAUSE				0x00c0
-+
-+/* Bitfields in CKSEL */
-+#define PM_CPUSEL_OFFSET			0
-+#define PM_CPUSEL_SIZE				3
-+#define PM_CPUDIV_OFFSET			7
-+#define PM_CPUDIV_SIZE				1
-+#define PM_HSBSEL_OFFSET			8
-+#define PM_HSBSEL_SIZE				3
-+#define PM_HSBDIV_OFFSET			15
-+#define PM_HSBDIV_SIZE				1
-+#define PM_PBASEL_OFFSET			16
-+#define PM_PBASEL_SIZE				3
-+#define PM_PBADIV_OFFSET			23
-+#define PM_PBADIV_SIZE				1
-+#define PM_PBBSEL_OFFSET			24
-+#define PM_PBBSEL_SIZE				3
-+#define PM_PBBDIV_OFFSET			31
-+#define PM_PBBDIV_SIZE				1
-+
-+/* Bitfields in PLL0 */
-+#define PM_PLLEN_OFFSET				0
-+#define PM_PLLEN_SIZE				1
-+#define PM_PLLOSC_OFFSET			1
-+#define PM_PLLOSC_SIZE				1
-+#define PM_PLLOPT_OFFSET			2
-+#define PM_PLLOPT_SIZE				3
-+#define PM_PLLDIV_OFFSET			8
-+#define PM_PLLDIV_SIZE				8
-+#define PM_PLLMUL_OFFSET			16
-+#define PM_PLLMUL_SIZE				8
-+#define PM_PLLCOUNT_OFFSET			24
-+#define PM_PLLCOUNT_SIZE			6
-+#define PM_PLLTEST_OFFSET			31
-+#define PM_PLLTEST_SIZE				1
-+
-+/* Bitfields in ICR */
-+#define PM_LOCK0_OFFSET				0
-+#define PM_LOCK0_SIZE				1
-+#define PM_LOCK1_OFFSET				1
-+#define PM_LOCK1_SIZE				1
-+#define PM_WAKE_OFFSET				2
-+#define PM_WAKE_SIZE				1
-+#define PM_CKRDY_OFFSET				5
-+#define PM_CKRDY_SIZE				1
-+#define PM_MSKRDY_OFFSET			6
-+#define PM_MSKRDY_SIZE				1
-+
-+/* Bitfields in GCCTRL0 */
-+#define PM_OSCSEL_OFFSET			0
-+#define PM_OSCSEL_SIZE				1
-+#define PM_PLLSEL_OFFSET			1
-+#define PM_PLLSEL_SIZE				1
-+#define PM_CEN_OFFSET				2
-+#define PM_CEN_SIZE				1
-+#define PM_DIVEN_OFFSET				4
-+#define PM_DIVEN_SIZE				1
-+#define PM_DIV_OFFSET				8
-+#define PM_DIV_SIZE				8
-+
-+/* Bitfields in RCAUSE */
-+#define PM_POR_OFFSET				0
-+#define PM_POR_SIZE				1
-+#define PM_EXT_OFFSET				2
-+#define PM_EXT_SIZE				1
-+#define PM_WDT_OFFSET				3
-+#define PM_WDT_SIZE				1
-+#define PM_NTAE_OFFSET				4
-+#define PM_NTAE_SIZE				1
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)					\
-+	(1 << PM_##name##_OFFSET)
-+#define PM_BF(name,value)				\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
-+	 << PM_##name##_OFFSET)
-+#define PM_BFEXT(name,value)				\
-+	(((value) >> PM_##name##_OFFSET)		\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
-+		    << PM_##name##_OFFSET))		\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define pm_readl(reg)							\
-+	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
-+#define pm_writel(reg,value)						\
-+	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
-+
-+#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff --git a/arch/avr32/mach-at32ap/pm-v3.h b/arch/avr32/mach-at32ap/pm-v3.h
-new file mode 100644
-index 0000000..3c507b9
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-v3.h
-@@ -0,0 +1,283 @@
-+/*
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __PM_V3_H__
-+#define __PM_V3_H__
-+
-+#include <mach/chip.h>
-+
-+/* PM Register offsets */
-+#ifndef __ASSEMBLY__
-+struct pm_regs {
-+	u32	MCCTRL;			/* Main Clock Control */
-+	u32	CKSEL;			/* Clock Select */
-+	u32	CPUMASK;		/* CPU Clock Mask */
-+	u32	HSBMASK;		/* HSB Clock Mask */
-+	u32	PBAMASK;		/* PBA Clock Mask */
-+	u32	PBBMASK;		/* PBB Clock Mask */
-+	u32	PBADIVMASK;		/* Divided PBA Clock Mask */
-+	u32	PBBDIVMASK;		/* Divided PBB Clock Mask */
-+	u32	__reserved1[8];
-+	u32	PLL[3];			/* PLL Control */
-+	u32	__reserved2[13];
-+	u32	OSCCTRL[3];		/* Oscillator Control */
-+	u32	__reserved3[5];
-+	u32	OSCCTRL32;		/* 32 kHz Oscillator Control */
-+	u32	__reserved4[7];
-+	u32	IER;			/* Interrupt Enable */
-+	u32	IDR;			/* Interrupt Disable */
-+	u32	IMR;			/* Interrupt Mask */
-+	u32	ISR;			/* Interrupt Status */
-+	u32	ICR;			/* Interrupt Clear */
-+	u32	POSCSR;			/* Power and Oscillator Status */
-+	u32	__reserved5[10];
-+	u32	GCCTRL[8];		/* Generic Clock Control */
-+	u32	__reserved6[8];
-+	u32	RCCR;			/* RC Oscillator Calibration */
-+	u32	BGCR;			/* Bandgap Calibration */
-+	u32	VREGCR;			/* Buck Regulator Calibration */
-+	u32	BOD;			/* BOD Level */
-+	u32	PPCR;			/* Peripheral Power Control */
-+	u32	__reserved7[11];
-+	u32	RCAUSE;			/* Reset Cause */
-+	u32	WCAUSE;			/* Wake Cause */
-+	u32	AWEN;			/* Asynchronous Wake Enable */
-+	u32	__reserved8[14];
-+	u32	GPLP;			/* General Purpose Low-Power */
-+};
-+#endif
-+
-+/* Assembly-friendly register offsets; same as above */
-+#define PM_MCCTRL			0x0000
-+#define PM_CKSEL			0x0004
-+#define PM_CPUMASK			0x0008
-+#define PM_HSBMASK			0x000c
-+#define PM_PBAMASK			0x0010
-+#define PM_PBBMASK			0x0014
-+#define PM_PBADIVMASK			0x0018
-+#define PM_PBBDIVMASK			0x001c
-+#define PM_PLL0				0x0040
-+#define PM_PLL1				0x0044
-+#define PM_PLL2				0x0048
-+#define PM_OSCCTRL0			0x0080
-+#define PM_OSCCTRL1			0x0084
-+#define PM_OSCCTRL2			0x0088
-+#define PM_OSCCTRL32			0x00a0
-+#define PM_IER				0x00c0
-+#define PM_IDR				0x00c4
-+#define PM_IMR				0x00c8
-+#define PM_ISR				0x00cc
-+#define PM_ICR				0x00d0
-+#define PM_POSCSR			0x00d4
-+#define PM_GCCTRL			0x0100
-+#define PM_RCCR				0x0140
-+#define PM_BGCR				0x0144
-+#define PM_VREGCR			0x0148
-+#define PM_BOD				0x014c
-+#define PM_PPCR				0x0150
-+#define PM_RC_RCAUSE			0x0180
-+#define PM_WCAUSE			0x0184
-+#define PM_AWEN				0x0188
-+#define PM_GPLP				0x01c0
-+
-+/* Bits in MCCTRL */
-+#define PM_MCCTRL_MCSEL_START		0
-+#define PM_MCCTRL_MCSEL_SIZE		2
-+#define PM_MCCTRL_OSC0EN_BIT		2
-+#define PM_MCCTRL_OSC1EN_BIT		3
-+#define PM_MCCTRL_OSC2EN_BIT		4
-+#define PM_MCCTRL_CRIPEL_BIT		24
-+
-+/* Bits in CKSEL */
-+#define PM_CKSEL_CPUSEL_START		0
-+#define PM_CKSEL_CPUSEL_SIZE		3
-+#define PM_CKSEL_CPUDIV_BIT		7
-+#define PM_CKSEL_HSBSEL_START		8
-+#define PM_CKSEL_HSBSEL_SIZE		3
-+#define PM_CKSEL_HSBDIV_BIT		15
-+#define PM_CKSEL_PBASEL_START		16
-+#define PM_CKSEL_PBASEL_SIZE		3
-+#define PM_CKSEL_PBADIV_BIT		23
-+#define PM_CKSEL_PBBSEL_START		24
-+#define PM_CKSEL_PBBSEL_SIZE		3
-+#define PM_CKSEL_PBBDIV_BIT		31
-+
-+/* Bits in CPUMASK */
-+#define PM_CPUMASK_SYSTIMER_BIT		16
-+
-+/* Bits in PLLx */
-+#define PM_PLLx_PLLEN_BIT		0
-+#define PM_PLLx_PLLOSC_START		1
-+#define PM_PLLx_PLLOSC_SIZE		2
-+#define PM_PLLx_PLLOPT_START		3
-+#define PM_PLLx_PLLOPT_SIZE		3
-+#define PM_PLLx_PLLBPL_BIT		7
-+#define PM_PLLx_PLLDIV_START		8
-+#define PM_PLLx_PLLDIV_SIZE		6
-+#define PM_PLLx_PLLMUL_START		16
-+#define PM_PLLx_PLLMUL_SIZE		6
-+#define PM_PLLx_PLLCOUNT_START		24
-+#define PM_PLLx_PLLCOUNT_SIZE		6
-+#define PM_PLLx_PLLIOTESTEN_BIT		30
-+#define PM_PLLx_PLLTEST_BIT		31
-+
-+/* Bits in OSCCTRLx */
-+#define PM_OSCCTRLx_MODE_START		0
-+#define PM_OSCCTRLx_MODE_SIZE		4
-+#define PM_OSCCTRLx_STARTUP_START	8
-+#define PM_OSCCTRLx_STARTUP_SIZE	3
-+
-+/* Bits in OSCCTRL32 */
-+#define PM_OSCCTRL32_OSC32EN_BIT	0
-+#define PM_OSCCTRL32_MODE_START		8
-+#define PM_OSCCTRL32_MODE_SIZE		3
-+#define PM_OSCCTRL32_STARTUP_START	16
-+#define PM_OSCCTRL32_STARTUP_SIZE	3
-+
-+/* Bits in IER/IDR/IMR/ISR/ICR */
-+#define PM_ISR_OSC0RDY_BIT		0
-+#define PM_ISR_OSC1RDY_BIT		1
-+#define PM_ISR_OSC2RDY_BIT		2
-+#define PM_ISR_OSC32RDY_BIT		7
-+#define PM_ISR_LOCK0_BIT		8
-+#define PM_ISR_LOCK1_BIT		9
-+#define PM_ISR_LOCK2_BIT		10
-+#define PM_ISR_LOCK0LOST_BIT		16
-+#define PM_ISR_LOCK1LOST_BIT		17
-+#define PM_ISR_LOCK2LOST_BIT		18
-+#define PM_ISR_CKRDY_BIT		24
-+#define PM_ISR_MSKRDY_BIT		25
-+#define PM_ISR_WAKE_BIT			26
-+#define PM_ISR_BODDET_BIT		27
-+#define PM_ISR_PERRDY_BIT		28
-+
-+/* Bits in POSCSR */
-+#define PM_POSCSR_OSC0RDY_BIT		0
-+#define PM_POSCSR_OSC1RDY_BIT		1
-+#define PM_POSCSR_OSC32RDY_BIT		7
-+#define PM_POSCSR_LOCK0_BIT		8
-+#define PM_POSCSR_LOCK1_BIT		9
-+#define PM_POSCSR_LOCK0LOST_BIT		16
-+#define PM_POSCSR_LOCK1LOST_BIT		17
-+#define PM_POSCSR_CKRDY_BIT		24
-+#define PM_POSCSR_MSKRDY_BIT		25
-+#define PM_POSCSR_WAKE_BIT		26
-+#define PM_POSCSR_BODDET_BIT		27
-+#define PM_POSCSR_PERRDY_BIT		28
-+
-+/* Bits in GCCTRL */
-+#define PM_GCCTRL_CEN_BIT		0
-+#define PM_GCCTRL_DIVEN_BIT		1
-+#define PM_GCCTRL_OSCSEL_START		8
-+#define PM_GCCTRL_OSCSEL_SIZE		4
-+#define PM_GCCTRL_DIV_START		16
-+#define PM_GCCTRL_DIV_SIZE		8
-+
-+/* Bits in RCCR */
-+#define PM_RCCR_CALIB_START		0
-+#define PM_RCCR_CALIB_SIZE		10
-+#define PM_RCCR_FCD_BIT			16
-+#define PM_RCCR_KEY_START		24
-+#define PM_RCCR_KEY_SIZE		8
-+
-+/* Bits in BGCR */
-+#define PM_BGCR_CALIB_START		0
-+#define PM_BGCR_CALIB_SIZE		3
-+#define PM_BGCR_FCD_BIT			16
-+#define PM_BGCR_KEY_START		24
-+#define PM_BGCR_KEY_SIZE		8
-+
-+/* Bits in VREGCR */
-+#define PM_VREGCR_CALIB_START		0
-+#define PM_VREGCR_CALIB_SIZE		3
-+#define PM_VREGCR_FCD_BIT		16
-+#define PM_VREGCR_KEY_START		24
-+#define PM_VREGCR_KEY_SIZE		8
-+
-+/* Bits in BOD */
-+#define PM_BOD_LEVEL_START		0
-+#define PM_BOD_LEVEL_SIZE		6
-+#define PM_BOD_HYST_BIT			6
-+#define PM_BOD_CTRL_START		8
-+#define PM_BOD_CTRL_SIZE		2
-+#define PM_BOD_FCD_BIT			16
-+#define PM_BOD_KEY_START		24
-+#define PM_BOD_KEY_SIZE			8
-+
-+/* Bits in PPCR */
-+#define PM_PPCR_EBI_VOLT_BIT		0
-+#define PM_PPCR_UTMI_CTRL_BIT		1
-+#define PM_PPCR_KEY_START		24
-+#define PM_PPCR_KEY_SIZE		8
-+
-+/* Bits in RC_RCAUSE */
-+#define PM_RC_RCAUSE_POR_BIT		0
-+#define PM_RC_RCAUSE_BOD_BIT		1
-+#define PM_RC_RCAUSE_EXT_BIT		2
-+#define PM_RC_RCAUSE_WDT_BIT		3
-+#define PM_RC_RCAUSE_JTAG_BIT		4
-+#define PM_RC_RCAUSE_NTAE_BIT		5
-+#define PM_RC_RCAUSE_SLEEP_BIT		6
-+#define PM_RC_RCAUSE_CPUERR_BIT		7
-+#define PM_RC_RCAUSE_OCDRST_BIT		8
-+#define PM_RC_RCAUSE_JTAGHARD_BIT	9
-+
-+/* Bits in WCAUSE */
-+#define PM_WCAUSE_PERIPH0_BIT		0
-+#define PM_WCAUSE_PERIPH1_BIT		1
-+#define PM_WCAUSE_EIC_BIT		16
-+#define PM_WCAUSE_RTC_BIT		17
-+
-+/* Constants for MCCTRL:MCSEL */
-+#define PM_MCSEL_SLOW			0
-+#define PM_MCSEL_OSC0			1
-+#define PM_MCSEL_PLL0			2
-+
-+/* Constants for OSCCTRLx:MODE */
-+#define PM_MODE_EXT_CLOCK		0
-+#define PM_MODE_CRYSTAL_ACG		1
-+#define PM_MODE_CRYSTAL_G0		4
-+#define PM_MODE_CRYSTAL_G1		5
-+#define PM_MODE_CRYSTAL_G2		6
-+#define PM_MODE_CRYSTAL_G3		7
-+
-+/* Constants for GCCTRL:OSCSEL */
-+#define PM_OSCSEL_SLOW			0
-+#define PM_OSCSEL_CLK32			1
-+#define PM_OSCSEL_OSC0			2
-+#define PM_OSCSEL_OSC1			3
-+#define PM_OSCSEL_PLL0			4
-+#define PM_OSCSEL_PLL1			5
-+
-+/* Constants for BOD:CTRL */
-+#define PM_CTRL_OFF1			0
-+#define PM_CTRL_ENABLED			1
-+#define PM_CTRL_ENABLED_NORESET		2
-+#define PM_CTRL_OFF2			3
-+
-+/* Bit manipulation macros */
-+#define PM_BIT(name)						\
-+	(1 << PM_##name##_BIT)
-+#define PM_BF(name,value)					\
-+	(((value) & ((1 << PM_##name##_SIZE) - 1))		\
-+	 << PM_##name##_START)
-+#define PM_BFEXT(name,value)					\
-+	(((value) >> PM_##name##_START)				\
-+	 & ((1 << PM_##name##_SIZE) - 1))
-+#define PM_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << PM_##name##_SIZE) - 1)		\
-+		    << PM_##name##_START))			\
-+	 | PM_BF(name,value))
-+
-+/* Register access macros */
-+#define __pm_regs ((struct pm_regs __iomem __force *)PM_BASE)
-+#define pm_readl(reg)						\
-+	__raw_readl(&__pm_regs->reg)
-+#define pm_writel(reg, value)					\
-+	__raw_writel(value, &__pm_regs->reg)
-+
-+#endif /* __PM_V3_H__ */
-diff --git a/arch/avr32/mach-at32ap/pm.h b/arch/avr32/mach-at32ap/pm.h
-deleted file mode 100644
-index 532a373..0000000
---- a/arch/avr32/mach-at32ap/pm.h
-+++ /dev/null
-@@ -1,112 +0,0 @@
--/*
-- * Register definitions for the Power Manager (PM)
-- */
--#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
--#define __ARCH_AVR32_MACH_AT32AP_PM_H__
--
--/* PM register offsets */
--#define PM_MCCTRL				0x0000
--#define PM_CKSEL				0x0004
--#define PM_CPU_MASK				0x0008
--#define PM_HSB_MASK				0x000c
--#define PM_PBA_MASK				0x0010
--#define PM_PBB_MASK				0x0014
--#define PM_PLL0					0x0020
--#define PM_PLL1					0x0024
--#define PM_IER					0x0040
--#define PM_IDR					0x0044
--#define PM_IMR					0x0048
--#define PM_ISR					0x004c
--#define PM_ICR					0x0050
--#define PM_GCCTRL(x)				(0x0060 + 4 * (x))
--#define PM_RCAUSE				0x00c0
--
--/* Bitfields in CKSEL */
--#define PM_CPUSEL_OFFSET			0
--#define PM_CPUSEL_SIZE				3
--#define PM_CPUDIV_OFFSET			7
--#define PM_CPUDIV_SIZE				1
--#define PM_HSBSEL_OFFSET			8
--#define PM_HSBSEL_SIZE				3
--#define PM_HSBDIV_OFFSET			15
--#define PM_HSBDIV_SIZE				1
--#define PM_PBASEL_OFFSET			16
--#define PM_PBASEL_SIZE				3
--#define PM_PBADIV_OFFSET			23
--#define PM_PBADIV_SIZE				1
--#define PM_PBBSEL_OFFSET			24
--#define PM_PBBSEL_SIZE				3
--#define PM_PBBDIV_OFFSET			31
--#define PM_PBBDIV_SIZE				1
--
--/* Bitfields in PLL0 */
--#define PM_PLLEN_OFFSET				0
--#define PM_PLLEN_SIZE				1
--#define PM_PLLOSC_OFFSET			1
--#define PM_PLLOSC_SIZE				1
--#define PM_PLLOPT_OFFSET			2
--#define PM_PLLOPT_SIZE				3
--#define PM_PLLDIV_OFFSET			8
--#define PM_PLLDIV_SIZE				8
--#define PM_PLLMUL_OFFSET			16
--#define PM_PLLMUL_SIZE				8
--#define PM_PLLCOUNT_OFFSET			24
--#define PM_PLLCOUNT_SIZE			6
--#define PM_PLLTEST_OFFSET			31
--#define PM_PLLTEST_SIZE				1
--
--/* Bitfields in ICR */
--#define PM_LOCK0_OFFSET				0
--#define PM_LOCK0_SIZE				1
--#define PM_LOCK1_OFFSET				1
--#define PM_LOCK1_SIZE				1
--#define PM_WAKE_OFFSET				2
--#define PM_WAKE_SIZE				1
--#define PM_CKRDY_OFFSET				5
--#define PM_CKRDY_SIZE				1
--#define PM_MSKRDY_OFFSET			6
--#define PM_MSKRDY_SIZE				1
--
--/* Bitfields in GCCTRL0 */
--#define PM_OSCSEL_OFFSET			0
--#define PM_OSCSEL_SIZE				1
--#define PM_PLLSEL_OFFSET			1
--#define PM_PLLSEL_SIZE				1
--#define PM_CEN_OFFSET				2
--#define PM_CEN_SIZE				1
--#define PM_DIVEN_OFFSET				4
--#define PM_DIVEN_SIZE				1
--#define PM_DIV_OFFSET				8
--#define PM_DIV_SIZE				8
--
--/* Bitfields in RCAUSE */
--#define PM_POR_OFFSET				0
--#define PM_POR_SIZE				1
--#define PM_EXT_OFFSET				2
--#define PM_EXT_SIZE				1
--#define PM_WDT_OFFSET				3
--#define PM_WDT_SIZE				1
--#define PM_NTAE_OFFSET				4
--#define PM_NTAE_SIZE				1
--
--/* Bit manipulation macros */
--#define PM_BIT(name)					\
--	(1 << PM_##name##_OFFSET)
--#define PM_BF(name,value)				\
--	(((value) & ((1 << PM_##name##_SIZE) - 1))	\
--	 << PM_##name##_OFFSET)
--#define PM_BFEXT(name,value)				\
--	(((value) >> PM_##name##_OFFSET)		\
--	 & ((1 << PM_##name##_SIZE) - 1))
--#define PM_BFINS(name,value,old)\
--	(((old) & ~(((1 << PM_##name##_SIZE) - 1)	\
--		    << PM_##name##_OFFSET))		\
--	 | PM_BF(name,value))
--
--/* Register access macros */
--#define pm_readl(reg)							\
--	__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
--#define pm_writel(reg,value)						\
--	__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
--
--#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
-diff --git a/arch/avr32/mach-at32ap/sdc.h b/arch/avr32/mach-at32ap/sdc.h
-new file mode 100644
-index 0000000..6f5ec00
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/sdc.h
-@@ -0,0 +1,103 @@
-+/* SDC */
-+
-+/* Register offsets */
-+#define SDC_CTRL			0x0000
-+#define SDC_ASYNC			0x0004
-+#define SDC_SYNC			0x0008
-+#define SDC_FILTERDUR			0x000c
-+#define SDC_OSCCTRL32			0x0010
-+#define SDC_STATUS			0x0014
-+#define SDC_ECR				0x0018
-+#define SDC_IER				0x001c
-+#define SDC_IDR				0x0020
-+#define SDC_IMR				0x0024
-+#define SDC_GPLP			0x0040
-+
-+/* Bits in CTRL */
-+#define SDC_CTRL_PIN_EN_BIT		0
-+#define SDC_CTRL_AST_EN_BIT		8
-+#define SDC_CTRL_WDT_EN_BIT		9
-+#define SDC_CTRL_OCD_EN_BIT		10
-+#define SDC_CTRL_JTAG_EN_BIT		11
-+#define SDC_CTRL_CORE_POR_TEST_BIT	23
-+#define SDC_CTRL_KEY_START		24
-+#define SDC_CTRL_KEY_SIZE		8
-+
-+/* Bits in ASYNC */
-+#define SDC_ASYNC_MODE_BIT		4
-+#define SDC_ASYNC_POL_BIT		8
-+#define SDC_ASYNC_KEY_START		24
-+#define SDC_ASYNC_KEY_SIZE		8
-+
-+/* Bits in SYNC */
-+#define SDC_SYNC_EN_BIT			0
-+#define SDC_SYNC_MODE_BIT		4
-+#define SDC_SYNC_POL_BIT		8
-+#define SDC_SYNC_FILTER_BIT		12
-+#define SDC_SYNC_KEY_START		24
-+#define SDC_SYNC_KEY_SIZE		8
-+
-+/* Bits in FILTERDUR */
-+#define SDC_FILTERDUR_Duration_START	0
-+#define SDC_FILTERDUR_Duration_SIZE	16
-+#define SDC_FILTERDUR_KEY_START		24
-+#define SDC_FILTERDUR_KEY_SIZE		8
-+
-+/* Bits in OSCCTRL32 */
-+#define SDC_OSCCTRL32_OSC32EN_BIT	0
-+#define SDC_OSCCTRL32_MODE_START	8
-+#define SDC_OSCCTRL32_MODE_SIZE		4
-+#define SDC_OSCCTRL32_STARTUP_START	16
-+#define SDC_OSCCTRL32_STARTUP_SIZE	3
-+#define SDC_OSCCTRL32_KEY_START		24
-+#define SDC_OSCCTRL32_KEY_SIZE		8
-+
-+/* Bits in STATUS */
-+#define SDC_STATUS_PIN_EVENT_BIT	0
-+#define SDC_STATUS_AST_EVENT_BIT	8
-+#define SDC_STATUS_WDT_EVENT_BIT	9
-+#define SDC_STATUS_OCD_EVENT_BIT	10
-+#define SDC_STATUS_JTAG_EVENT_BIT	11
-+#define SDC_STATUS_PIN_BIT		16
-+#define SDC_STATUS_BUSY_BIT		24
-+#define SDC_STATUS_SWTCH_BIT		30
-+#define SDC_STATUS_VBAT_BIT		31
-+
-+/* Bits in ECR */
-+#define SDC_ECR_PIN_EVENT_BIT		0
-+#define SDC_ECR_AST_EVENT_BIT		8
-+#define SDC_ECR_WDT_EVENT_BIT		9
-+#define SDC_ECR_OCD_EVENT_BIT		10
-+#define SDC_ECR_JTAG_EVENT_BIT		11
-+
-+/* Bits in IER */
-+#define SDC_IER_PIN_EVENT_BIT		0
-+#define SDC_IER_READY_BIT		24
-+
-+/* Bits in IDR */
-+#define SDC_IDR_PIN_EVENT_BIT		0
-+#define SDC_IDR_READY_BIT		24
-+
-+/* Bits in IMR */
-+#define SDC_IMR_PIN_EVENT_BIT		0
-+#define SDC_IMR_READY_BIT		24
-+
-+/* Bit manipulation macros */
-+#define SDC_BIT(name)						\
-+	(1 << SDC_##name##_BIT)
-+#define SDC_BF(name,value)					\
-+	(((value) & ((1 << SDC_##name##_SIZE) - 1))		\
-+	 << SDC_##name##_START)
-+#define SDC_BFEXT(name,value)					\
-+	(((value) >> SDC_##name##_START)			\
-+	 & ((1 << SDC_##name##_SIZE) - 1))
-+#define SDC_BFINS(name,value,old)				\
-+	(((old) & ~(((1 << SDC_##name##_SIZE) - 1)		\
-+		    << SDC_##name##_START))			\
-+	 | SDC_BF(name,value))
-+
-+/* Register access macros */
-+#define sdc_readl(reg)						\
-+	__raw_readl((void __iomem __force *)(SDC_BASE + SDC_##reg))
-+#define sdc_writel(reg, value)					\
-+	__raw_writel(value, (void __iomem __force *)(SDC_BASE + SDC_##reg))
-diff --git a/arch/avr32/mach-at32ap/timer-ast.c b/arch/avr32/mach-at32ap/timer-ast.c
-new file mode 100644
-index 0000000..0afff19
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/timer-ast.c
-@@ -0,0 +1,191 @@
-+/*
-+ * Asynchronous Timer (AST) used as clocksource / clockevent
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/clockchips.h>
-+#include <linux/clocksource.h>
-+#include <linux/interrupt.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/irq.h>
-+#include <linux/platform_device.h>
-+
-+#include <asm/ast_regs.h>
-+
-+static void __iomem *ast_regs;
-+
-+static inline void ast_wait_ready(void)
-+{
-+	while (ast_readl(ast_regs, SR) & AST_BIT(BUSY))
-+		cpu_relax();
-+}
-+
-+static cycle_t read_ast_counter(void)
-+{
-+	return ast_readl(ast_regs, CV);
-+}
-+
-+static struct clocksource ast_clksrc = {
-+	.name	= "ast",
-+	.rating	= 400,
-+	.read	= read_ast_counter,
-+	.mask	= CLOCKSOURCE_MASK(32),
-+	.shift	= 16,
-+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
-+};
-+
-+static irqreturn_t ast_clkevt_interrupt(int irq, void *dev_id)
-+{
-+	struct clock_event_device *clkevt = dev_id;
-+
-+	/*
-+	 * We make sure delta is always long enough so that the BUSY
-+	 * bit is never set at this point.
-+	 */
-+	ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+	clkevt->event_handler(clkevt);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ast_clkevt_irqaction = {
-+	.handler	= ast_clkevt_interrupt,
-+	.flags		= IRQF_TIMER | IRQF_DISABLED,
-+	.name		= "timer-ast",
-+};
-+
-+static int ast_next_event(unsigned long delta,
-+		struct clock_event_device *clkevt)
-+{
-+	ast_wait_ready();
-+	ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) + delta);
-+
-+	return 0;
-+}
-+
-+static void ast_mode(enum clock_event_mode mode,
-+		struct clock_event_device *evdev)
-+{
-+	switch (mode) {
-+	case CLOCK_EVT_MODE_ONESHOT:
-+	case CLOCK_EVT_MODE_RESUME:
-+		/* Make sure we don't trigger an alarm before we get
-+		 * around to reprogramming it.
-+		 */
-+		ast_wait_ready();
-+		ast_writel(ast_regs, AR0, ast_readl(ast_regs, CV) - 1);
-+		ast_wait_ready();
-+		ast_writel(ast_regs, SCR, AST_BIT(ALARM0));
-+		ast_wait_ready();
-+		ast_writel(ast_regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case CLOCK_EVT_MODE_UNUSED:
-+	case CLOCK_EVT_MODE_SHUTDOWN:
-+		ast_writel(ast_regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	default:
-+		BUG();
-+	}
-+}
-+
-+static struct clock_event_device ast_clkevt = {
-+	.name		= "ast",
-+	.features	= CLOCK_EVT_FEAT_ONESHOT,
-+	.shift		= 16,
-+	.rating		= 400,
-+	.cpumask	= CPU_MASK_CPU0,
-+	.set_next_event	= ast_next_event,
-+	.set_mode	= ast_mode,
-+};
-+
-+void __init ast_time_init(struct platform_device *pdev, unsigned int clksel)
-+{
-+	struct clk *clk, *pclk;
-+	struct resource *regs;
-+	unsigned long ast_hz;
-+	int irq;
-+	int ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		pr_debug("AST: No MMIO resource\n");
-+		return;
-+	}
-+
-+	pclk = clk_get(&pdev->dev, "pclk");
-+	if (!pclk) {
-+		pr_debug("AST: No peripheral clock (pclk)\n");
-+		return;
-+	}
-+	clk_enable(pclk);
-+
-+	/* Too early for ioremap() */
-+	ast_regs = (void __iomem __force *)regs->start;
-+
-+	switch (clksel) {
-+	case AST_CLOCK_SLOW:
-+		clk = clk_get(NULL, "rcosc");
-+		break;
-+	case AST_CLOCK_OSC32:
-+		clk = clk_get(NULL, "osc32");
-+		break;
-+	case AST_CLOCK_PB:
-+		clk = pclk;
-+		break;
-+	case AST_CLOCK_GC:
-+		clk = clk_get(&pdev->dev, "gclk");
-+		break;
-+	default:
-+		clk = NULL;
-+		break;
-+	}
-+
-+	if (!clk) {
-+		pr_debug("AST: clock %u invalid, using pb clock\n", clksel);
-+		clk = pclk;
-+	}
-+	clk_enable(clk);
-+
-+	ast_writel(ast_regs, CLOCK,
-+			AST_BF(CLOCK_CSSEL, clksel) | AST_BIT(CLOCK_CEN));
-+	ast_writel(ast_regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR));
-+
-+	/* Using hardcoded divide-by-two prescaler */
-+	ast_hz = clk_get_rate(clk) / 2;
-+	ast_clksrc.mult = clocksource_hz2mult(ast_hz, ast_clksrc.shift);
-+
-+	ret = clocksource_register(&ast_clksrc);
-+	if (ret)
-+		pr_debug("AST: could not register clocksource: %d\n", ret);
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		pr_debug("AST: No IRQ resource, won't setup clockevent\n");
-+		return;
-+	}
-+
-+	ast_clkevt.mult = div_sc(ast_hz, NSEC_PER_SEC, ast_clkevt.shift);
-+	ast_clkevt.max_delta_ns = clockevent_delta2ns((u32)~0U, &ast_clkevt);
-+	ast_clkevt.min_delta_ns = clockevent_delta2ns(2, &ast_clkevt) + 100;
-+
-+	ast_clkevt_irqaction.dev_id = &ast_clkevt;
-+
-+	ret = setup_irq(irq, &ast_clkevt_irqaction);
-+	if (ret) {
-+		pr_debug("AST: Could not request IRQ %d: %d\n", irq, ret);
-+		return;
-+	}
-+
-+	clockevents_register_device(&ast_clkevt);
-+
-+	pr_info("Using Asynchronous Timer %d @ %lu.%03lu Mhz"
-+			" (regs 0x%p, irq %d)\n",
-+			pdev->id, ((ast_hz + 500) / 1000) / 1000,
-+			((ast_hz + 500) / 1000) % 1000, ast_regs, irq);
-+}
-diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c
-index 06677be..cede41b 100644
---- a/arch/avr32/mm/tlb.c
-+++ b/arch/avr32/mm/tlb.c
-@@ -12,7 +12,13 @@
- #include <asm/mmu_context.h>
- 
- /* TODO: Get the correct number from the CONFIG1 system register */
--#define NR_TLB_ENTRIES 32
-+#if defined(CONFIG_CPU_AT32AP700X)
-+# define NR_TLB_ENTRIES 32
-+#elif defined(CONFIG_CPU_AT32AP720X)
-+# define NR_TLB_ENTRIES 64
-+#else
-+# error Unknown CPU type
-+#endif
- 
- static void show_dtlb_entry(unsigned int index)
- {
-@@ -85,9 +91,15 @@ static void update_dtlb(unsigned long address, pte_t pte)
- 		u32 tlbar = sysreg_read(TLBARLO);
- 
- 		rp = 32 - fls(tlbar);
--		if (rp == 32) {
-+		if (NR_TLB_ENTRIES > 32 && rp >= 32) {
-+			tlbar = sysreg_read(TLBARHI);
-+			rp = 64 - fls(tlbar);
-+		}
-+		if (rp >= NR_TLB_ENTRIES) {
- 			rp = 0;
- 			sysreg_write(TLBARLO, -1L);
-+			if (NR_TLB_ENTRIES > 32)
-+				sysreg_write(TLBARHI, -1L);
- 		}
- 
- 		mmucr = SYSREG_BFINS(DRP, rp, mmucr);
-@@ -131,16 +143,22 @@ static void __flush_tlb_page(unsigned long asid, unsigned long page)
- 
- 	if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
- 		unsigned int entry;
--		u32 tlbarlo;
-+		u32 tlbarlo, tlbarhi;
- 
- 		/* Clear the "valid" bit */
- 		sysreg_write(TLBEHI, tlbehi);
- 
- 		/* mark the entry as "not accessed" */
- 		entry = SYSREG_BFEXT(DRP, mmucr);
--		tlbarlo = sysreg_read(TLBARLO);
--		tlbarlo |= (0x80000000UL >> entry);
--		sysreg_write(TLBARLO, tlbarlo);
-+		if (NR_TLB_ENTRIES > 32 && entry > 32) {
-+			tlbarhi = sysreg_read(TLBARHI);
-+			tlbarhi |= (0x80000000UL >> (entry - 32));
-+			sysreg_write(TLBARHI, tlbarhi);
-+		} else {
-+			tlbarlo = sysreg_read(TLBARLO);
-+			tlbarlo |= (0x80000000UL >> entry);
-+			sysreg_write(TLBARLO, tlbarlo);
-+		}
- 
- 		/* update the entry with valid bit clear */
- 		__builtin_tlbw();
-@@ -179,9 +197,10 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
- 		unsigned long flags;
- 		int size;
- 
--		local_irq_save(flags);
- 		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
- 
-+		local_irq_save(flags);
-+
- 		if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
- 			mm->context = NO_CONTEXT;
- 			if (mm == current->mm)
-diff --git a/arch/avr32/oprofile/Makefile b/arch/avr32/oprofile/Makefile
-index 1fe81c3..e0eb520 100644
---- a/arch/avr32/oprofile/Makefile
-+++ b/arch/avr32/oprofile/Makefile
-@@ -5,4 +5,4 @@ oprofile-y		:= $(addprefix ../../../drivers/oprofile/,	\
- 				event_buffer.o oprofile_files.o		\
- 				oprofilefs.o oprofile_stats.o		\
- 				timer_int.o)
--oprofile-y		+= op_model_avr32.o
-+oprofile-y		+= op_model_avr32.o backtrace.o
-diff --git a/arch/avr32/oprofile/backtrace.c b/arch/avr32/oprofile/backtrace.c
-new file mode 100644
-index 0000000..75d9ad6
---- /dev/null
-+++ b/arch/avr32/oprofile/backtrace.c
-@@ -0,0 +1,81 @@
-+/*
-+ * AVR32 specific backtracing code for oprofile
-+ *
-+ * Copyright 2008 Weinmann GmbH
-+ *
-+ * Author: Nikolaus Voss <n.voss at weinmann.de>
-+ *
-+ * Based on i386 oprofile backtrace code by John Levon and David Smith
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/oprofile.h>
-+#include <linux/sched.h>
-+#include <linux/uaccess.h>
-+
-+/* The first two words of each frame on the stack look like this if we have
-+ * frame pointers */
-+struct frame_head {
-+	unsigned long lr;
-+	struct frame_head *fp;
-+};
-+
-+/* copied from arch/avr32/kernel/process.c */
-+static inline int valid_stack_ptr(struct thread_info *tinfo, unsigned long p)
-+{
-+	return (p > (unsigned long)tinfo)
-+		&& (p < (unsigned long)tinfo + THREAD_SIZE - 3);
-+}
-+
-+/* copied from arch/x86/oprofile/backtrace.c */
-+static struct frame_head *dump_user_backtrace(struct frame_head *head)
-+{
-+	struct frame_head bufhead[2];
-+
-+	/* Also check accessibility of one struct frame_head beyond */
-+	if (!access_ok(VERIFY_READ, head, sizeof(bufhead)))
-+		return NULL;
-+	if (__copy_from_user_inatomic(bufhead, head, sizeof(bufhead)))
-+		return NULL;
-+
-+	oprofile_add_trace(bufhead[0].lr);
-+
-+	/* frame pointers should strictly progress back up the stack
-+	 * (towards higher addresses) */
-+	if (bufhead[0].fp <= head)
-+		return NULL;
-+
-+	return bufhead[0].fp;
-+}
-+
-+void avr32_backtrace(struct pt_regs * const regs, unsigned int depth)
-+{
-+	/* Get first frame pointer */
-+	struct frame_head *head = (struct frame_head *)(regs->r7);
-+
-+	if (!user_mode(regs)) {
-+#ifdef CONFIG_FRAME_POINTER
-+		/*
-+		 * Traverse the kernel stack from frame to frame up to
-+		 * "depth" steps.
-+		 */
-+		while (depth-- && valid_stack_ptr(task_thread_info(current),
-+						  (unsigned long)head)) {
-+			oprofile_add_trace(head->lr);
-+			if (head->fp <= head)
-+				break;
-+			head = head->fp;
-+		}
-+#endif
-+	} else {
-+		/* Assume we have frame pointers in user mode process */
-+		while (depth-- && head)
-+			head = dump_user_backtrace(head);
-+	}
-+}
-+
-+
-diff --git a/arch/avr32/oprofile/op_model_avr32.c b/arch/avr32/oprofile/op_model_avr32.c
-index df42325..a3e9b3c 100644
---- a/arch/avr32/oprofile/op_model_avr32.c
-+++ b/arch/avr32/oprofile/op_model_avr32.c
-@@ -22,6 +22,8 @@
- #define AVR32_PERFCTR_IRQ_GROUP	0
- #define AVR32_PERFCTR_IRQ_LINE	1
- 
-+void avr32_backtrace(struct pt_regs * const regs, unsigned int depth);
-+
- enum { PCCNT, PCNT0, PCNT1, NR_counter };
- 
- struct avr32_perf_counter {
-@@ -223,6 +225,8 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
- 	memcpy(ops, &avr32_perf_counter_ops,
- 			sizeof(struct oprofile_operations));
- 
-+	ops->backtrace = avr32_backtrace;
-+
- 	printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n");
- 
- 	return 0;
-diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
-index cd30390..9322b91 100644
---- a/drivers/dma/Kconfig
-+++ b/drivers/dma/Kconfig
-@@ -38,6 +38,20 @@ config INTEL_IOP_ADMA
- 	help
- 	  Enable support for the Intel(R) IOP Series RAID engines.
- 
-+config ATMEL_PDCA
-+	tristate "Atmel Peripheral DMA Controller A support"
-+	depends on AVR32
-+	select DMA_ENGINE
-+	default y if CPU_AT32AP7200
-+	help
-+	  Support the Atmel Peripheral DMA Controller found on AVR32
-+	  UC3 chips as well as newer AP7 chips. This controller is
-+	  similar to the PDC found on AT32AP7000 and various AT91
-+	  chips, but has its own register bank.
-+
-+	  This controller only supports peripheral (slave) transfers,
-+	  not memory-to-memory transfers.
-+
- config DW_DMAC
- 	tristate "Synopsys DesignWare AHB DMA support"
- 	depends on AVR32
-diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
-index 14f5952..1623a6d 100644
---- a/drivers/dma/Makefile
-+++ b/drivers/dma/Makefile
-@@ -4,6 +4,7 @@ obj-$(CONFIG_DMATEST) += dmatest.o
- obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
- ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
- obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
-+obj-$(CONFIG_ATMEL_PDCA) += atmel_pdca.o
- obj-$(CONFIG_FSL_DMA) += fsldma.o
- obj-$(CONFIG_MV_XOR) += mv_xor.o
- obj-$(CONFIG_DW_DMAC) += dw_dmac.o
-diff --git a/drivers/dma/atmel_pdca.c b/drivers/dma/atmel_pdca.c
-new file mode 100644
-index 0000000..0d2f49f
---- /dev/null
-+++ b/drivers/dma/atmel_pdca.c
-@@ -0,0 +1,668 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#define DEBUG
-+#include <linux/atmel_pdca.h>
-+#include <linux/clk.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/scatterlist.h>
-+#include <linux/spinlock.h>
-+
-+/*
-+ * Since each descriptor can hold a whole scatterlist, we don't need
-+ * many of them.
-+ */
-+#define NR_DESCS_PER_CHANNEL	8
-+
-+static struct pdca_desc *pdca_desc_entry(struct list_head *node)
-+{
-+	return list_entry(node, struct pdca_desc, desc_node);
-+}
-+
-+static struct pdca_desc *pdca_next_desc(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	if (desc->desc_node.next != &pch->queue)
-+		return pdca_desc_entry(desc->desc_node.next);
-+	return NULL;
-+}
-+
-+static struct pdca_desc *pdca_desc_get(struct pdca_chan *pch)
-+{
-+	struct pdca_desc		*desc = NULL;
-+
-+	spin_lock_bh(&pch->lock);
-+	if (likely(!list_empty(&pch->freelist))) {
-+		desc = pdca_desc_entry(pch->freelist.next);
-+		list_del(&desc->desc_node);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+
-+	return desc;
-+}
-+
-+static dma_cookie_t pdca_assign_cookie(struct pdca_chan *pch,
-+		struct pdca_desc *desc)
-+{
-+	dma_cookie_t cookie = pch->chan.cookie;
-+
-+	if (++cookie < 0)
-+		cookie = 1;
-+
-+	pch->chan.cookie = cookie;
-+	desc->txd.cookie = cookie;
-+
-+	return cookie;
-+}
-+
-+static void pdca_desc_done(struct pdca_chan *pch, struct pdca_desc *desc)
-+{
-+	struct dma_async_tx_descriptor	*txd = &desc->txd;
-+	dma_async_tx_callback		callback;
-+	void				*param;
-+
-+	pch->completed = txd->cookie;
-+	callback = txd->callback;
-+	param = txd->callback_param;
-+
-+	dev_vdbg(&pch->chan.dev, "  completed %u\n", txd->cookie);
-+
-+	/*
-+	 * We can only handle scatterlists, so this is easy. No other
-+	 * drivers do the right thing with scatterlists though...
-+	 *
-+	 * Note that we ensure that at least one of these flags are
-+	 * set when the descriptor is prepared, as we never need to
-+	 * unmap the peripheral side.
-+	 */
-+	if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_FROM_DEVICE);
-+	if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP))
-+		dma_unmap_sg(pch->chan.dev.parent, desc->sg, desc->sg_len,
-+				DMA_TO_DEVICE);
-+
-+	list_move(&desc->desc_node, &pch->freelist);
-+
-+	if (callback)
-+		callback(param);
-+}
-+
-+static void pdca_chan_tasklet(unsigned long param)
-+{
-+	struct pdca_chan		*pch = (struct pdca_chan *)param;
-+	void __iomem			*regs = pch->regs;
-+	struct pdca_desc		*cur;
-+	struct pdca_desc		*next;
-+	struct scatterlist		*cur_sg;
-+	struct scatterlist		*next_sg;
-+	u32				intflags;
-+	u32				status;
-+
-+	spin_lock(&pch->lock);
-+
-+	cur = pdca_desc_entry(pch->queue.next);
-+	next = pdca_next_desc(pch, cur);
-+
-+	cur_sg = pch->cur_sg;
-+	next_sg = pch->next_sg;
-+
-+	intflags = PDCA_TERR | PDCA_TRC | PDCA_RCZ;
-+
-+	status = pdca_readl(regs, ISR);
-+	dev_vdbg(&pch->chan.dev, "tasklet: status=%08x\n", status);
-+
-+	if (status & PDCA_TRC) {
-+		if (cur_sg) {
-+			if (sg_is_last(cur_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  cur sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (next_sg && sg_is_last(next_sg)) {
-+				dev_vdbg(&pch->chan.dev,
-+						"  next sg was last in %u\n",
-+						cur->txd.cookie);
-+				pdca_desc_done(pch, cur);
-+				cur = next;
-+				next = NULL;
-+			}
-+			if (!cur) {
-+				dev_vdbg(&pch->chan.dev, "  all done\n");
-+				pdca_writel(regs, CR, PDCA_CR_TDIS);
-+				cur_sg = next_sg = NULL;
-+				intflags = 0;
-+				goto done;
-+			}
-+			cur_sg = next_sg ? sg_next(next_sg) : NULL;
-+		}
-+
-+		if (!cur_sg) {
-+			dev_vdbg(&pch->chan.dev, "  load sg from %u\n",
-+					cur->txd.cookie);
-+			cur_sg = cur->sg;
-+			pdca_writel(regs, PSR, cur->periph_id);
-+			pdca_writel(regs, MR, cur->reg_width);
-+		}
-+		dev_vdbg(&pch->chan.dev, "  START: %08x count: %08x\n",
-+				sg_dma_address(cur_sg),
-+				sg_dma_len(cur_sg) >> cur->reg_width);
-+		pdca_writel(regs, MAR, sg_dma_address(cur_sg));
-+		pdca_writel(regs, TCR, sg_dma_len(cur_sg) >> cur->reg_width);
-+
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id) {
-+				dev_vdbg(&pch->chan.dev,
-+						"loading next_sg from %u\n",
-+						next->txd.cookie);
-+				next_sg = next->sg;
-+			}
-+		}
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	} else if (next_sg && (status & PDCA_RCZ)) {
-+		if (sg_is_last(cur_sg)) {
-+			dev_vdbg(&pch->chan.dev, "  cur sg was last in %u\n",
-+					cur->txd.cookie);
-+			next = pdca_next_desc(pch, cur);
-+			pdca_desc_done(pch, cur);
-+			cur = next;
-+			next = NULL;
-+		}
-+
-+		cur_sg = next_sg;
-+		next_sg = sg_next(cur_sg);
-+		if (!next_sg) {
-+			next = pdca_next_desc(pch, cur);
-+			if (next && next->reg_width == cur->reg_width
-+					&& next->periph_id == cur->periph_id)
-+				next_sg = next->sg;
-+		}
-+
-+		if (next_sg) {
-+			dev_vdbg(&pch->chan.dev, "  NEXT: %08x count: %08x\n",
-+					sg_dma_address(next_sg),
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+			pdca_writel(regs, MARR, sg_dma_address(next_sg));
-+			pdca_writel(regs, TCRR,
-+					sg_dma_len(next_sg) >> cur->reg_width);
-+		} else {
-+			dev_vdbg(&pch->chan.dev, "  no next sg\n");
-+			intflags &= ~PDCA_RCZ;
-+		}
-+	}
-+
-+done:
-+	if (status & PDCA_TERR) {
-+		/*
-+		 * Head of queue is busted. We must remove it, clear
-+		 * the error and restart the queue.
-+		 */
-+		pdca_writel(regs, TCRR, 0);
-+		pdca_writel(regs, TCR, 0);
-+		pdca_writel(regs, CR, PDCA_CR_ECLR);
-+		cur_sg = next_sg = NULL;
-+
-+		if (!cur)
-+			dev_err(&pch->chan.dev,
-+					"Transfer Error with empty queue\n");
-+		else {
-+			dev_vdbg(&pch->chan.dev,
-+					"  %u is busted\n", cur->txd.cookie);
-+			pdca_desc_done(pch, cur);
-+		}
-+
-+		if (list_empty(&pch->queue)) {
-+			pdca_writel(regs, CR, PDCA_CR_TDIS);
-+			intflags = 0;
-+		}
-+	}
-+
-+	pch->cur_sg = cur_sg;
-+	pch->next_sg = next_sg;
-+
-+	dev_vdbg(&pch->chan.dev, "  enabling interrupts: %08x\n", intflags);
-+	pdca_writel(regs, IER, intflags);
-+	pdca_readl(regs, SR);
-+
-+	spin_unlock(&pch->lock);
-+}
-+
-+static irqreturn_t pdca_interrupt(int irq, void *dev_id)
-+{
-+	struct pdca_dev			*pdca = dev_id;
-+	struct pdca_chan		*pch;
-+	void __iomem			*regs;
-+	unsigned long			pending;
-+	unsigned int			chan;
-+
-+	pending = intc_get_pending(irq);
-+	if (unlikely(!pending))
-+		return IRQ_NONE;
-+
-+	do {
-+		chan = __ffs(pending);
-+		pch = &pdca->chan[chan];
-+		regs = pch->regs;
-+		pdca_writel(regs, IDR, ~0UL);
-+		tasklet_schedule(&pch->tasklet);
-+		pdca_readl(regs, IMR);
-+		pending &= ~(1 << chan);
-+	} while (pending);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static dma_cookie_t pdca_tx_submit(struct dma_async_tx_descriptor *txd)
-+{
-+	struct pdca_desc		*desc = txd_to_pdca_desc(txd);
-+	struct pdca_chan		*pch = dma_to_pdca_chan(txd->chan);
-+	void __iomem			*regs = pch->regs;
-+	dma_cookie_t			cookie;
-+
-+	spin_lock_bh(&pch->lock);
-+	cookie = pdca_assign_cookie(pch, desc);
-+	dev_vdbg(&pch->chan.dev, "submitted %u\n", cookie);
-+	list_add_tail(&desc->desc_node, &pch->queue);
-+	pdca_writel(regs, CR, PDCA_CR_TEN);
-+	pdca_writel(regs, IER, PDCA_TERR | PDCA_RCZ);
-+	/* The tasklet will kickstart the queue if necessary */
-+	spin_unlock_bh(&pch->lock);
-+
-+	return cookie;
-+}
-+
-+static struct dma_async_tx_descriptor *pdca_prep_slave_sg(struct dma_chan *chan,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		enum dma_data_direction direction, unsigned long flags)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_slave		*pslave = pch->pslave;
-+	struct pdca_desc		*desc;
-+	unsigned int			periph_id;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		periph_id = pslave->tx_periph_id;
-+		flags |= DMA_COMPL_SKIP_DEST_UNMAP;
-+		break;
-+	case DMA_FROM_DEVICE:
-+		periph_id = pslave->rx_periph_id;
-+		flags |= DMA_COMPL_SKIP_SRC_UNMAP;
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	desc = pdca_desc_get(pch);
-+	if (!desc) {
-+		dev_err(&chan->dev,
-+			"not enough descriptors available\n");
-+		return NULL;
-+	}
-+	desc->sg = sgl;
-+	desc->sg_len = sg_len;
-+	desc->periph_id = periph_id;
-+	desc->reg_width = pslave->slave.reg_width;
-+	desc->txd.flags = flags;
-+
-+	return &desc->txd;
-+}
-+
-+static void pdca_terminate_all(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_desc		*desc, *_desc;
-+	void __iomem			*regs = pch->regs;
-+
-+	spin_lock_bh(&pch->lock);
-+	pdca_writel(regs, CR, PDCA_CR_TDIS);
-+	pdca_writel(regs, TCRR, 0);
-+	pdca_writel(regs, TCR, 0);
-+	while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		cpu_relax();
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->queue, desc_node)
-+		pdca_desc_done(pch, desc);
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static enum dma_status pdca_is_tx_complete(struct dma_chan *chan,
-+		dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	dma_cookie_t			last_used;
-+	dma_cookie_t			last_complete;
-+
-+	last_complete = pch->completed;
-+	last_used = chan->cookie;
-+
-+	if (done)
-+		*done = last_complete;
-+	if (used)
-+		*used = last_used;
-+
-+	return dma_async_is_complete(cookie, last_complete, last_used);
-+}
-+
-+static void pdca_issue_pending(struct dma_chan *chan)
-+{
-+	/* We always issue descriptors ASAP */
-+}
-+
-+static int pdca_alloc_chan_resources(struct dma_chan *chan,
-+		struct dma_client *client)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct dma_slave		*slave = client->slave;
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * Channels doing slave DMA can only handle one client. This
-+	 * controller can only do slave DMA.
-+	 */
-+	if (chan->client_count)
-+		return -EBUSY;
-+	if (!slave || !slave->dma_dev || slave->dma_dev != pdca->dma.dev)
-+		return -EINVAL;
-+
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+		dev_err(&chan->dev, "DMA channel not idle!\n");
-+
-+	/*
-+	 * We may get called multiple times if a client rejects the
-+	 * channel...
-+	 */
-+	if (!pch->enabled) {
-+		pch->enabled = true;
-+		clk_enable(pdca->pclk);
-+		clk_enable(pdca->hclk);
-+	}
-+
-+	pch->chan.cookie = pch->completed = 1;
-+	pch->pslave = dma_to_pdca_slave(slave);
-+
-+	while (pch->descs_allocated < NR_DESCS_PER_CHANNEL) {
-+		struct pdca_desc	*desc;
-+
-+		desc = kzalloc(sizeof(struct pdca_desc), GFP_KERNEL);
-+		if (!desc) {
-+			dev_info(&chan->dev, "only allocated %d descriptors\n",
-+					pch->descs_allocated);
-+			break;
-+		}
-+
-+		dma_async_tx_descriptor_init(&desc->txd, chan);
-+		desc->txd.tx_submit = pdca_tx_submit;
-+		desc->txd.flags = DMA_CTRL_ACK;
-+		INIT_LIST_HEAD(&desc->txd.tx_list);
-+		list_add(&desc->desc_node, &pch->freelist);
-+		pch->descs_allocated++;
-+	}
-+
-+	return pch->descs_allocated ? 0 : -ENOMEM;
-+}
-+
-+static void pdca_free_chan_resources(struct dma_chan *chan)
-+{
-+	struct pdca_chan		*pch = dma_to_pdca_chan(chan);
-+	struct pdca_dev			*pdca = dma_to_pdca_dev(chan->device);
-+	struct pdca_desc		*desc, *_desc;
-+
-+	WARN_ON(!list_empty(&pch->queue));
-+	WARN_ON(pdca_readl(pch->regs, SR) & PDCA_SR_TEN);
-+	WARN_ON(pdca_readl(pch->regs, IMR));
-+
-+	clk_disable(pdca->hclk);
-+	clk_disable(pdca->pclk);
-+	pch->enabled = false;
-+
-+	list_for_each_entry_safe(desc, _desc, &pch->freelist, desc_node) {
-+		list_del(&desc->desc_node);
-+		kfree(desc);
-+	}
-+
-+	pch->descs_allocated = 0;
-+}
-+
-+static void pdca_suspend_channel(struct pdca_dev *pdca, struct pdca_chan *pch)
-+{
-+	void __iomem			*regs = pch->regs;
-+
-+	/*
-+	 * REVISIT this whole business.
-+	 *
-+	 * The plan is to ensure that the PDCA doesn't do any bus
-+	 * transactions when we're suspended or shut down. Ideally,
-+	 * the client should make sure that all transfers have already
-+	 * been completed or terminated when we reach suspend_late(),
-+	 * but just in case that didn't happen, we should just stop
-+	 * the controller and turn it back on when resuming. Hopefully
-+	 * it will simply continue where it left off.
-+	 *
-+	 * We _probably_ need to save some sort of state to make this
-+	 * happen. Or we can just rely on interrupts being globally
-+	 * disabled at least until we reach resume_early. But that
-+	 * might not be the case for shutdown.
-+	 */
-+	tasklet_kill(&pch->tasklet);
-+	spin_lock_bh(&pch->lock);
-+	if (pdca_readl(regs, SR) & PDCA_SR_TEN) {
-+		pdca_writel(regs, CR, PDCA_CR_TDIS);
-+		while (pdca_readl(regs, SR) & PDCA_SR_TEN)
-+			cpu_relax();
-+
-+		clk_disable(pdca->hclk);
-+		clk_disable(pdca->pclk);
-+	}
-+	spin_unlock_bh(&pch->lock);
-+}
-+
-+static void __init pdca_init_channel(struct pdca_dev *pdca, unsigned int i)
-+{
-+	struct pdca_chan		*pch = &pdca->chan[i];
-+
-+	pch->chan.device = &pdca->dma;
-+	pch->chan.chan_id = i;
-+	pch->regs = pdca->regs + i * PDCA_CHAN_SIZE;
-+	tasklet_init(&pch->tasklet, pdca_chan_tasklet, (unsigned long)pch);
-+	spin_lock_init(&pch->lock);
-+	INIT_LIST_HEAD(&pch->freelist);
-+	INIT_LIST_HEAD(&pch->queue);
-+
-+	list_add_tail(&pch->chan.device_node, &pdca->dma.channels);
-+}
-+
-+static int __init pdca_probe(struct platform_device *pdev)
-+{
-+	struct pdca_pdata		*pdata;
-+	struct resource			*mmio;
-+	struct pdca_dev			*pdca;
-+	size_t				mmio_len;
-+	size_t				size;
-+	unsigned int			i;
-+	int				irq;
-+	int				ret;
-+
-+	pdata = pdev->dev.platform_data;
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	irq = platform_get_irq(pdev, 0);
-+	if (!pdata || pdata->nr_channels > 32 || !mmio || !irq) {
-+		dev_dbg(&pdev->dev, "invalid params from platform code\n");
-+		return -EINVAL;
-+	}
-+
-+	mmio_len = mmio->end - mmio->start + 1;
-+	if (!request_mem_region(mmio->start, mmio_len, "atmel_pdca")) {
-+		dev_dbg(&pdev->dev, "mmio resource busy\n");
-+		return -EBUSY;
-+	}
-+
-+	size = sizeof(struct pdca_dev);
-+	size += pdata->nr_channels * sizeof(struct pdca_chan);
-+	pdca = kzalloc(size, GFP_KERNEL);
-+	if (!pdca) {
-+		dev_dbg(&pdev->dev, "insufficient memory\n");
-+		ret = -ENOMEM;
-+		goto err_alloc_pdca;
-+	}
-+
-+	pdca->hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(pdca->hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		ret = PTR_ERR(pdca->hclk);
-+		goto err_get_hclk;
-+	}
-+	pdca->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(pdca->pclk)) {
-+		dev_dbg(&pdev->dev, "no PB clock\n");
-+		ret = PTR_ERR(pdca->pclk);
-+		goto err_get_pclk;
-+	}
-+
-+	pdca->regs = ioremap(mmio->start, mmio_len);
-+	if (!pdca->regs) {
-+		dev_dbg(&pdev->dev, "ioremap failed\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	INIT_LIST_HEAD(&pdca->dma.channels);
-+	for (i = 0; i < pdata->nr_channels; i++, pdca->dma.chancnt++)
-+		pdca_init_channel(pdca, i);
-+
-+	ret = request_irq(irq, pdca_interrupt, 0, pdev->dev.bus_id, pdca);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "request_irq failed\n");
-+		goto err_irq;
-+	}
-+
-+	dma_cap_set(DMA_SLAVE, pdca->dma.cap_mask);
-+	pdca->dma.dev = &pdev->dev;
-+	pdca->dma.device_alloc_chan_resources = pdca_alloc_chan_resources;
-+	pdca->dma.device_free_chan_resources = pdca_free_chan_resources;
-+	pdca->dma.device_prep_slave_sg = pdca_prep_slave_sg;
-+	pdca->dma.device_terminate_all = pdca_terminate_all;
-+	pdca->dma.device_is_tx_complete = pdca_is_tx_complete;
-+	pdca->dma.device_issue_pending = pdca_issue_pending;
-+
-+	platform_set_drvdata(pdev, pdca);
-+	dma_async_device_register(&pdca->dma);
-+
-+	dev_info(&pdev->dev, "Atmel PDCA at 0x%08lx (irq %d) %u channels\n",
-+			(unsigned long)mmio->start, irq, pdca->dma.chancnt);
-+
-+	return 0;
-+
-+err_irq:
-+	iounmap(pdca->regs);
-+err_ioremap:
-+	clk_put(pdca->pclk);
-+err_get_pclk:
-+	clk_put(pdca->hclk);
-+err_get_hclk:
-+	kfree(pdca);
-+err_alloc_pdca:
-+	release_resource(mmio);
-+	return ret;
-+}
-+
-+static int __exit pdca_remove(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+	struct resource		*mmio;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+
-+	dma_async_device_unregister(&pdca->dma);
-+	free_irq(platform_get_irq(pdev, 0), pdca);
-+	clk_put(pdca->pclk);
-+	clk_put(pdca->hclk);
-+	iounmap(pdca->regs);
-+	kfree(pdca);
-+
-+	mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	release_resource(mmio);
-+
-+	return 0;
-+}
-+
-+static void pdca_shutdown(struct platform_device *pdev)
-+{
-+	struct pdca_dev		*pdca = platform_get_drvdata(pdev);
-+	struct pdca_chan	*pch;
-+
-+	list_for_each_entry(pch, &pdca->dma.channels, chan.device_node)
-+		pdca_suspend_channel(pdca, pch);
-+}
-+
-+static int pdca_suspend_late(struct platform_device *pdev, pm_message_t state)
-+{
-+	return 0;
-+}
-+
-+static int pdca_resume_early(struct platform_device *pdev)
-+{
-+	return 0;
-+}
-+
-+static struct platform_driver pdca_driver = {
-+	.remove		= __exit_p(pdca_remove),
-+	.shutdown	= pdca_shutdown,
-+	.suspend_late	= pdca_suspend_late,
-+	.resume_early	= pdca_resume_early,
-+	.driver		= {
-+		.name	= "atmel_pdca",
-+	},
-+};
-+
-+static int __init pdca_init(void)
-+{
-+	return platform_driver_probe(&pdca_driver, pdca_probe);
-+}
-+subsys_initcall(pdca_init);
-+
-+static void __exit pdca_exit(void)
-+{
-+	platform_driver_unregister(&pdca_driver);
-+}
-+module_exit(pdca_exit);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_DESCRIPTION("Atmel PDCA DMA Controller driver");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-diff --git a/drivers/dma/dw_dmac.c b/drivers/dma/dw_dmac.c
-index 0778d99..a7686b9 100644
---- a/drivers/dma/dw_dmac.c
-+++ b/drivers/dma/dw_dmac.c
-@@ -545,109 +545,51 @@ err_desc_get:
- 	return NULL;
- }
- 
--static struct dma_async_tx_descriptor *
--dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
--		unsigned int sg_len, enum dma_data_direction direction,
--		unsigned long flags)
-+static struct dw_desc *dwc_init_slave_descs(struct dw_dma_chan *dwc,
-+		struct scatterlist *sgl, unsigned int sg_len,
-+		u32 ctllo, dma_addr_t src_reg, dma_addr_t dst_reg,
-+		unsigned int reg_width, unsigned long flags)
- {
--	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
--	struct dw_dma_slave	*dws = dwc->dws;
--	struct dw_desc		*prev;
--	struct dw_desc		*first;
--	u32			ctllo;
--	dma_addr_t		reg;
--	unsigned int		reg_width;
--	unsigned int		mem_width;
--	unsigned int		i;
-+	struct dma_chan		*chan = &dwc->chan;
- 	struct scatterlist	*sg;
-+	struct dw_desc		*desc;
-+	struct dw_desc		*first = NULL;
-+	struct dw_desc		*prev = NULL;
-+	unsigned int		align_mask;
-+	unsigned int		i;
- 	size_t			total_len = 0;
- 
--	dev_vdbg(&chan->dev, "prep_dma_slave\n");
--
--	if (unlikely(!dws || !sg_len))
--		return NULL;
--
--	reg_width = dws->slave.reg_width;
--	prev = first = NULL;
--
--	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-+	align_mask = (1 << reg_width) - 1;
-+	for_each_sg(sgl, sg, sg_len, i) {
-+		u32		len;
-+		u32		desc_len;
-+		u32		mem;
- 
--	switch (direction) {
--	case DMA_TO_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_DST_WIDTH(reg_width)
--				| DWC_CTLL_DST_FIX
--				| DWC_CTLL_SRC_INC
--				| DWC_CTLL_FC_M2P);
--		reg = dws->slave.tx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
-+		mem = sg_phys(sg);
-+		len = sg_dma_len(sg);
-+		total_len += len;
- 
-+		while (len) {
-+			desc_len = min(len, DWC_MAX_COUNT << reg_width);
- 			desc = dwc_desc_get(dwc);
- 			if (!desc) {
- 				dev_err(&chan->dev,
- 					"not enough descriptors available\n");
- 				goto err_desc_get;
- 			}
-+			len -= desc_len;
- 
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
-+			if (unlikely((mem & align_mask) || (len & align_mask)))
-+				goto err_align;
- 
--			desc->lli.sar = mem;
--			desc->lli.dar = reg;
--			desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> mem_width;
--
--			if (!first) {
--				first = desc;
--			} else {
--				prev->lli.llp = desc->txd.phys;
--				dma_sync_single_for_device(chan->dev.parent,
--						prev->txd.phys,
--						sizeof(prev->lli),
--						DMA_TO_DEVICE);
--				list_add_tail(&desc->desc_node,
--						&first->txd.tx_list);
--			}
--			prev = desc;
--			total_len += len;
--		}
--		break;
--	case DMA_FROM_DEVICE:
--		ctllo = (DWC_DEFAULT_CTLLO
--				| DWC_CTLL_SRC_WIDTH(reg_width)
--				| DWC_CTLL_DST_INC
--				| DWC_CTLL_SRC_FIX
--				| DWC_CTLL_FC_P2M);
--
--		reg = dws->slave.rx_reg;
--		for_each_sg(sgl, sg, sg_len, i) {
--			struct dw_desc	*desc;
--			u32		len;
--			u32		mem;
--
--			desc = dwc_desc_get(dwc);
--			if (!desc) {
--				dev_err(&chan->dev,
--					"not enough descriptors available\n");
--				goto err_desc_get;
--			}
--
--			mem = sg_phys(sg);
--			len = sg_dma_len(sg);
--			mem_width = 2;
--			if (unlikely(mem & 3 || len & 3))
--				mem_width = 0;
--
--			desc->lli.sar = reg;
--			desc->lli.dar = mem;
--			desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
--			desc->lli.ctlhi = len >> reg_width;
-+			desc->lli.sar = src_reg ? src_reg : mem;
-+			desc->lli.dar = dst_reg ? dst_reg : mem;
-+			desc->lli.ctllo = ctllo;
-+			desc->lli.ctlhi = desc_len >> reg_width;
-+			dev_vdbg(&dwc->chan.dev,
-+					"  s%08x d%08x c%08x:%08x\n",
-+					desc->lli.sar, desc->lli.dar,
-+					ctllo, desc_len >> reg_width);
- 
- 			if (!first) {
- 				first = desc;
-@@ -661,11 +603,8 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
- 						&first->txd.tx_list);
- 			}
- 			prev = desc;
--			total_len += len;
-+			mem += desc_len;
- 		}
--		break;
--	default:
--		return NULL;
- 	}
- 
- 	if (flags & DMA_PREP_INTERRUPT)
-@@ -679,13 +618,69 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
- 
- 	first->len = total_len;
- 
--	return &first->txd;
-+	return first;
- 
-+err_align:
-+	dwc_desc_put(dwc, desc);
- err_desc_get:
- 	dwc_desc_put(dwc, first);
- 	return NULL;
- }
- 
-+static struct dma_async_tx_descriptor *
-+dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
-+		unsigned int sg_len, enum dma_data_direction direction,
-+		unsigned long flags)
-+{
-+	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-+	struct dw_dma_slave	*dws = dwc->dws;
-+	struct dw_desc		*first;
-+	u32			ctllo;
-+	unsigned int		reg_width;
-+
-+	dev_vdbg(&chan->dev, "prep_dma_slave: %s %u segments, flags: %lx\n",
-+			direction == DMA_TO_DEVICE ? "OUT" : "IN",
-+			sg_len, flags);
-+
-+	if (unlikely(!dws || !sg_len))
-+		return NULL;
-+
-+	reg_width = dws->slave.reg_width;
-+	sg_len = dma_map_sg(chan->dev.parent, sgl, sg_len, direction);
-+
-+	switch (direction) {
-+	case DMA_TO_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_FIX
-+				| DWC_CTLL_SRC_INC
-+				| DWC_CTLL_FC_M2P);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				0, dws->slave.tx_reg, reg_width, flags);
-+		break;
-+	case DMA_FROM_DEVICE:
-+		ctllo = (DWC_DEFAULT_CTLLO
-+				| DWC_CTLL_SRC_WIDTH(reg_width)
-+				| DWC_CTLL_DST_WIDTH(reg_width)
-+				| DWC_CTLL_DST_INC
-+				| DWC_CTLL_SRC_FIX
-+				| DWC_CTLL_FC_P2M);
-+		first = dwc_init_slave_descs(dwc, sgl, sg_len, ctllo,
-+				dws->slave.rx_reg, 0, reg_width, flags);
-+		break;
-+	default:
-+		return NULL;
-+	}
-+
-+	if (unlikely(!first)) {
-+		dma_unmap_sg(chan->dev.parent, sgl, sg_len, direction);
-+		return NULL;
-+	}
-+
-+	return &first->txd;
-+}
-+
- static void dwc_terminate_all(struct dma_chan *chan)
- {
- 	struct dw_dma_chan	*dwc = to_dw_dma_chan(chan);
-@@ -1109,7 +1104,7 @@ static int __init dw_init(void)
- {
- 	return platform_driver_probe(&dw_driver, dw_probe);
- }
--module_init(dw_init);
-+subsys_initcall(dw_init);
- 
- static void __exit dw_exit(void)
- {
-diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
-index ea8d7a3..1ce21d4 100644
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -114,6 +114,17 @@ config MMC_ATMELMCI
- 
- 	  If unsure, say N.
- 
-+config MMC_ATMELMCI_DMA
-+	bool "Atmel MCI DMA support (EXPERIMENTAL)"
-+	depends on MMC_ATMELMCI && DMA_ENGINE && EXPERIMENTAL
-+	help
-+	  Say Y here to have the Atmel MCI driver use a DMA engine to
-+	  do data transfers and thus increase the throughput and
-+	  reduce the CPU utilization. Note that this is highly
-+	  experimental and may cause the driver to lock up.
-+
-+	  If unsure, say N.
-+
- config MMC_IMX
- 	tristate "Motorola i.MX Multimedia Card Interface support"
- 	depends on ARCH_IMX
-diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
-index 26bd80e..cfb7ce1 100644
---- a/drivers/mmc/host/atmel-mci-regs.h
-+++ b/drivers/mmc/host/atmel-mci-regs.h
-@@ -10,13 +10,21 @@
- #ifndef __DRIVERS_MMC_ATMEL_MCI_H__
- #define __DRIVERS_MMC_ATMEL_MCI_H__
- 
--/* MCI Register Definitions */
-+/*
-+ * MCI Register Definitions. Registers and bitfields marked with [2]
-+ * are only available in MCI2.
-+ */
- #define MCI_CR			0x0000	/* Control */
- # define MCI_CR_MCIEN		(  1 <<  0)	/* MCI Enable */
- # define MCI_CR_MCIDIS		(  1 <<  1)	/* MCI Disable */
-+# define MCI_CR_PWSEN		(  1 <<  2)	/* Powersave Enable[2] */
-+# define MCI_CR_PWSDIS		(  1 <<  3)	/* Powersave Disable[2] */
-+# define MCI_CR_IOWAITEN	(  1 <<  4)	/* SDIO Read Wait Enable[2] */
-+# define MCI_CR_IOWAITDIS	(  1 <<  5)	/* SDIO Read Wait Disable[2] */
- # define MCI_CR_SWRST		(  1 <<  7)	/* Software Reset */
- #define MCI_MR			0x0004	/* Mode */
- # define MCI_MR_CLKDIV(x)	((x) <<  0)	/* Clock Divider */
-+# define MCI_MR_PWSDIV(x)	((x) <<  8)	/* Powersave Divider[2] */
- # define MCI_MR_RDPROOF		(  1 << 11)	/* Read Proof */
- # define MCI_MR_WRPROOF		(  1 << 12)	/* Write Proof */
- #define MCI_DTOR		0x0008	/* Data Timeout */
-@@ -24,9 +32,12 @@
- # define MCI_DTOMUL(x)		((x) <<  4)	/* Data Timeout Multiplier */
- #define MCI_SDCR		0x000c	/* SD Card / SDIO */
- # define MCI_SDCSEL_SLOT_A	(  0 <<  0)	/* Select SD slot A */
--# define MCI_SDCSEL_SLOT_B	(  1 <<  0)	/* Select SD slot A */
--# define MCI_SDCBUS_1BIT	(  0 <<  7)	/* 1-bit data bus */
--# define MCI_SDCBUS_4BIT	(  1 <<  7)	/* 4-bit data bus */
-+# define MCI_SDCSEL_SLOT_B	(  1 <<  0)	/* Select SD slot B */
-+# define MCI_SDCSEL_MASK	(  3 <<  0)
-+# define MCI_SDCBUS_1BIT	(  0 <<  6)	/* 1-bit data bus */
-+# define MCI_SDCBUS_4BIT	(  2 <<  6)	/* 4-bit data bus */
-+# define MCI_SDCBUS_8BIT	(  3 <<  6)	/* 8-bit data bus[2] */
-+# define MCI_SDCBUS_MASK	(  3 <<  6)
- #define MCI_ARGR		0x0010	/* Command Argument */
- #define MCI_CMDR		0x0014	/* Command */
- # define MCI_CMDR_CMDNB(x)	((x) <<  0)	/* Command Opcode */
-@@ -54,6 +65,9 @@
- #define MCI_BLKR		0x0018	/* Block */
- # define MCI_BCNT(x)		((x) <<  0)	/* Data Block Count */
- # define MCI_BLKLEN(x)		((x) << 16)	/* Data Block Length */
-+#define MCI_CSTOR		0x001c	/* Completion Signal Timeout[2] */
-+# define MCI_CSTOCYC(x)		((x) <<  0)	/* CST cycles */
-+# define MCI_CSTOMUL(x)		((x) <<  4)	/* CST multiplier */
- #define MCI_RSPR		0x0020	/* Response 0 */
- #define MCI_RSPR1		0x0024	/* Response 1 */
- #define MCI_RSPR2		0x0028	/* Response 2 */
-@@ -64,24 +78,45 @@
- #define MCI_IER			0x0044	/* Interrupt Enable */
- #define MCI_IDR			0x0048	/* Interrupt Disable */
- #define MCI_IMR			0x004c	/* Interrupt Mask */
--# define MCI_CMDRDY		(  1 <<   0)	/* Command Ready */
--# define MCI_RXRDY		(  1 <<   1)	/* Receiver Ready */
--# define MCI_TXRDY		(  1 <<   2)	/* Transmitter Ready */
--# define MCI_BLKE		(  1 <<   3)	/* Data Block Ended */
--# define MCI_DTIP		(  1 <<   4)	/* Data Transfer In Progress */
--# define MCI_NOTBUSY		(  1 <<   5)	/* Data Not Busy */
--# define MCI_SDIOIRQA		(  1 <<   8)	/* SDIO IRQ in slot A */
--# define MCI_SDIOIRQB		(  1 <<   9)	/* SDIO IRQ in slot B */
--# define MCI_RINDE		(  1 <<  16)	/* Response Index Error */
--# define MCI_RDIRE		(  1 <<  17)	/* Response Direction Error */
--# define MCI_RCRCE		(  1 <<  18)	/* Response CRC Error */
--# define MCI_RENDE		(  1 <<  19)	/* Response End Bit Error */
--# define MCI_RTOE		(  1 <<  20)	/* Response Time-Out Error */
--# define MCI_DCRCE		(  1 <<  21)	/* Data CRC Error */
--# define MCI_DTOE		(  1 <<  22)	/* Data Time-Out Error */
--# define MCI_OVRE		(  1 <<  30)	/* RX Overrun Error */
--# define MCI_UNRE		(  1 <<  31)	/* TX Underrun Error */
-+# define MCI_CMDRDY		(  1 <<  0)	/* Command Ready */
-+# define MCI_RXRDY		(  1 <<  1)	/* Receiver Ready */
-+# define MCI_TXRDY		(  1 <<  2)	/* Transmitter Ready */
-+# define MCI_BLKE		(  1 <<  3)	/* Data Block Ended */
-+# define MCI_DTIP		(  1 <<  4)	/* Data Transfer In Progress */
-+# define MCI_NOTBUSY		(  1 <<  5)	/* Data Not Busy */
-+# define MCI_SDIOIRQA		(  1 <<  8)	/* SDIO IRQ in slot A */
-+# define MCI_SDIOIRQB		(  1 <<  9)	/* SDIO IRQ in slot B */
-+# define MCI_RINDE		(  1 << 16)	/* Response Index Error */
-+# define MCI_RDIRE		(  1 << 17)	/* Response Direction Error */
-+# define MCI_RCRCE		(  1 << 18)	/* Response CRC Error */
-+# define MCI_RENDE		(  1 << 19)	/* Response End Bit Error */
-+# define MCI_RTOE		(  1 << 20)	/* Response Time-Out Error */
-+# define MCI_DCRCE		(  1 << 21)	/* Data CRC Error */
-+# define MCI_DTOE		(  1 << 22)	/* Data Time-Out Error */
-+# define MCI_OVRE		(  1 << 30)	/* RX Overrun Error */
-+# define MCI_UNRE		(  1 << 31)	/* TX Underrun Error */
-+#define MCI_DMA			0x0050	/* DMA Configuration[2] */
-+# define MCI_DMA_OFFSET(x)	((x) <<  0)	/* DMA write buffer offset */
-+# define MCI_DMA_CHKSIZE_1	(  0 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_4	(  1 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_8	(  2 <<  5)	/* DMA chunk size */
-+# define MCI_DMA_CHKSIZE_16	(  3 <<  5)	/* DMA chunk size */
-+# define MCI_DMAEN		(  1 <<  8)	/* DMA HW handshake enable */
-+#define MCI_CFG			0x0054	/* Configuration[2] */
-+# define MCI_CFG_FIFOMODE	(  1 <<  0)	/* Start transfer ASAP */
-+# define MCI_CFG_FERRCTRL	(  1 <<  4)	/* xrun flags clear-on-read */
-+# define MCI_CFG_HSMODE		(  1 <<  8)	/* Use high-speed signaling */
-+# define MCI_CFG_LSYNC		(  1 << 12)	/* Synchronize on last block */
-+#define MCI_WPMR		0x00e4	/* Write Protect Mode[2] */
-+# define MCI_WP_EN		(  1 <<  0)	/* WP Enable */
-+# define MCI_WP_KEY		(0x4d4349 << 8)	/* WP Key */
-+#define MCI_WPSR		0x00e8	/* Write Protect Status[2] */
-+# define MCI_GET_WP_VS(x)	((x) & 0x0f)
-+# define MCI_GET_WP_VSRC(x)	(((x) >> 8) & 0xffff)
-+#define MCI_VERSION		0x00fc	/* MCI Core Version[2] */
-+#define MCI_FIFO_APERTURE	0x0200	/* FIFO Aperture[2] */
- 
-+/* This is not including the FIFO Aperture on MCI2 */
- #define MCI_REGS_SIZE		0x100
- 
- /* Register access macros */
-diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
-index 0000896..3480a5a 100644
---- a/drivers/mmc/host/atmel-mci.c
-+++ b/drivers/mmc/host/atmel-mci.c
-@@ -11,6 +11,8 @@
- #include <linux/clk.h>
- #include <linux/debugfs.h>
- #include <linux/device.h>
-+#include <linux/dmaengine.h>
-+#include <linux/dma-mapping.h>
- #include <linux/err.h>
- #include <linux/gpio.h>
- #include <linux/init.h>
-@@ -29,68 +31,195 @@
- #include <asm/unaligned.h>
- 
- #include <mach/board.h>
-+#include <mach/cpu.h>
- 
- #include "atmel-mci-regs.h"
- 
- #define ATMCI_DATA_ERROR_FLAGS	(MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
-+#define ATMCI_DMA_THRESHOLD	16
- 
- enum {
- 	EVENT_CMD_COMPLETE = 0,
--	EVENT_DATA_ERROR,
--	EVENT_DATA_COMPLETE,
--	EVENT_STOP_SENT,
--	EVENT_STOP_COMPLETE,
- 	EVENT_XFER_COMPLETE,
-+	EVENT_DATA_COMPLETE,
-+	EVENT_DATA_ERROR,
-+};
-+
-+enum atmel_mci_state {
-+	STATE_IDLE = 0,
-+	STATE_SENDING_CMD,
-+	STATE_SENDING_DATA,
-+	STATE_DATA_BUSY,
-+	STATE_SENDING_STOP,
-+	STATE_DATA_ERROR,
-+};
-+
-+struct atmel_mci_dma {
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	struct dma_client		client;
-+	struct dma_chan			*chan;
-+	struct dma_async_tx_descriptor	*data_desc;
-+#endif
- };
- 
-+/**
-+ * struct atmel_mci - MMC controller state shared between all slots
-+ * @lock: Spinlock protecting the queue and associated data.
-+ * @regs: Pointer to MMIO registers.
-+ * @sg: Scatterlist entry currently being processed by PIO code, if any.
-+ * @pio_offset: Offset into the current scatterlist entry.
-+ * @cur_slot: The slot which is currently using the controller.
-+ * @mrq: The request currently being processed on @cur_slot,
-+ *	or NULL if the controller is idle.
-+ * @cmd: The command currently being sent to the card, or NULL.
-+ * @data: The data currently being transferred, or NULL if no data
-+ *	transfer is in progress.
-+ * @dma: DMA client state.
-+ * @data_chan: DMA channel being used for the current data transfer.
-+ * @cmd_status: Snapshot of SR taken upon completion of the current
-+ *	command. Only valid when EVENT_CMD_COMPLETE is pending.
-+ * @data_status: Snapshot of SR taken upon completion of the current
-+ *	data transfer. Only valid when EVENT_DATA_COMPLETE or
-+ *	EVENT_DATA_ERROR is pending.
-+ * @stop_cmdr: Value to be loaded into CMDR when the stop command is
-+ *	to be sent.
-+ * @tasklet: Tasklet running the request state machine.
-+ * @pending_events: Bitmask of events flagged by the interrupt handler
-+ *	to be processed by the tasklet.
-+ * @completed_events: Bitmask of events which the state machine has
-+ *	processed.
-+ * @state: Tasklet state.
-+ * @queue: List of slots waiting for access to the controller.
-+ * @need_clock_update: Update the clock rate before the next request.
-+ * @need_reset: Reset controller before next request.
-+ * @mode_reg: Value of the MR register.
-+ * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
-+ *	rate and timeout calculations.
-+ * @mapbase: Physical address of the MMIO registers.
-+ * @mck: The peripheral bus clock hooked up to the MMC controller.
-+ * @pdev: Platform device associated with the MMC controller.
-+ * @slot: Slots sharing this MMC controller.
-+ *
-+ * Locking
-+ * =======
-+ *
-+ * @lock is a softirq-safe spinlock protecting @queue as well as
-+ * @cur_slot, @mrq and @state. These must always be updated
-+ * at the same time while holding @lock.
-+ *
-+ * @lock also protects mode_reg and need_clock_update since these are
-+ * used to synchronize mode register updates with the queue
-+ * processing.
-+ *
-+ * The @mrq field of struct atmel_mci_slot is also protected by @lock,
-+ * and must always be written at the same time as the slot is added to
-+ * @queue.
-+ *
-+ * @pending_events and @completed_events are accessed using atomic bit
-+ * operations, so they don't need any locking.
-+ *
-+ * None of the fields touched by the interrupt handler need any
-+ * locking. However, ordering is important: Before EVENT_DATA_ERROR or
-+ * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
-+ * interrupts must be disabled and @data_status updated with a
-+ * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
-+ * CMDRDY interupt must be disabled and @cmd_status updated with a
-+ * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
-+ * bytes_xfered field of @data must be written. This is ensured by
-+ * using barriers.
-+ */
- struct atmel_mci {
--	struct mmc_host		*mmc;
-+	spinlock_t		lock;
- 	void __iomem		*regs;
- 
- 	struct scatterlist	*sg;
- 	unsigned int		pio_offset;
- 
-+	struct atmel_mci_slot	*cur_slot;
- 	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
- 	struct mmc_data		*data;
- 
-+	struct atmel_mci_dma	dma;
-+	struct dma_chan		*data_chan;
-+
- 	u32			cmd_status;
- 	u32			data_status;
--	u32			stop_status;
- 	u32			stop_cmdr;
- 
--	u32			mode_reg;
--	u32			sdc_reg;
--
- 	struct tasklet_struct	tasklet;
- 	unsigned long		pending_events;
- 	unsigned long		completed_events;
-+	enum atmel_mci_state	state;
-+	struct list_head	queue;
- 
--	int			present;
--	int			detect_pin;
--	int			wp_pin;
--
--	/* For detect pin debouncing */
--	struct timer_list	detect_timer;
--
-+	bool			need_clock_update;
-+	bool			need_reset;
-+	u32			mode_reg;
- 	unsigned long		bus_hz;
- 	unsigned long		mapbase;
- 	struct clk		*mck;
- 	struct platform_device	*pdev;
-+
-+	struct atmel_mci_slot	*slot[ATMEL_MCI_MAX_NR_SLOTS];
-+};
-+
-+/**
-+ * struct atmel_mci_slot - MMC slot state
-+ * @mmc: The mmc_host representing this slot.
-+ * @host: The MMC controller this slot is using.
-+ * @sdc_reg: Value of SDCR to be written before using this slot.
-+ * @mrq: mmc_request currently being processed or waiting to be
-+ *	processed, or NULL when the slot is idle.
-+ * @queue_node: List node for placing this node in the @queue list of
-+ *	&struct atmel_mci.
-+ * @clock: Clock rate configured by set_ios(). Protected by host->lock.
-+ * @flags: Random state bits associated with the slot.
-+ * @detect_pin: GPIO pin used for card detection, or negative if not
-+ *	available.
-+ * @wp_pin: GPIO pin used for card write protect sending, or negative
-+ *	if not available.
-+ * @detect_timer: Timer used for debouncing @detect_pin interrupts.
-+ */
-+struct atmel_mci_slot {
-+	struct mmc_host		*mmc;
-+	struct atmel_mci	*host;
-+
-+	u32			sdc_reg;
-+
-+	struct mmc_request	*mrq;
-+	struct list_head	queue_node;
-+
-+	unsigned int		clock;
-+	unsigned long		flags;
-+#define ATMCI_CARD_PRESENT	0
-+#define ATMCI_CARD_NEED_INIT	1
-+#define ATMCI_SHUTDOWN		2
-+
-+	int			detect_pin;
-+	int			wp_pin;
-+
-+	struct timer_list	detect_timer;
- };
- 
--#define atmci_is_completed(host, event)				\
--	test_bit(event, &host->completed_events)
- #define atmci_test_and_clear_pending(host, event)		\
- 	test_and_clear_bit(event, &host->pending_events)
--#define atmci_test_and_set_completed(host, event)		\
--	test_and_set_bit(event, &host->completed_events)
- #define atmci_set_completed(host, event)			\
- 	set_bit(event, &host->completed_events)
- #define atmci_set_pending(host, event)				\
- 	set_bit(event, &host->pending_events)
--#define atmci_clear_pending(host, event)			\
--	clear_bit(event, &host->pending_events)
-+
-+/*
-+ * The new MCI2 module isn't 100% compatible with the old MCI module,
-+ * and it has a few nice features which we want to use...
-+ */
-+static inline bool atmci_is_mci2(void)
-+{
-+	if (cpu_is_at32ap7200())
-+		return true;
-+
-+	return false;
-+}
- 
- /*
-  * The debugfs stuff below is mostly optimized away when
-@@ -98,14 +227,15 @@ struct atmel_mci {
-  */
- static int atmci_req_show(struct seq_file *s, void *v)
- {
--	struct atmel_mci	*host = s->private;
--	struct mmc_request	*mrq = host->mrq;
-+	struct atmel_mci_slot	*slot = s->private;
-+	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
- 	struct mmc_command	*stop;
- 	struct mmc_data		*data;
- 
- 	/* Make sure we get a consistent snapshot */
--	spin_lock_irq(&host->mmc->lock);
-+	spin_lock_bh(&slot->host->lock);
-+	mrq = slot->mrq;
- 
- 	if (mrq) {
- 		cmd = mrq->cmd;
-@@ -130,7 +260,7 @@ static int atmci_req_show(struct seq_file *s, void *v)
- 				stop->resp[2], stop->error);
- 	}
- 
--	spin_unlock_irq(&host->mmc->lock);
-+	spin_unlock_bh(&slot->host->lock);
- 
- 	return 0;
- }
-@@ -158,8 +288,15 @@ static void atmci_show_status_reg(struct seq_file *s,
- 		[3]	= "BLKE",
- 		[4]	= "DTIP",
- 		[5]	= "NOTBUSY",
-+		[6]	= "ENDRX",
-+		[7]	= "ENDTX",
- 		[8]	= "SDIOIRQA",
- 		[9]	= "SDIOIRQB",
-+		[10]	= "SDIOIRQC",
-+		[11]	= "SDIOIRQD",
-+		[12]	= "SDIOWAIT",
-+		[14]	= "RXBUFF",
-+		[15]	= "TXBUFE",
- 		[16]	= "RINDE",
- 		[17]	= "RDIRE",
- 		[18]	= "RCRCE",
-@@ -167,6 +304,11 @@ static void atmci_show_status_reg(struct seq_file *s,
- 		[20]	= "RTOE",
- 		[21]	= "DCRCE",
- 		[22]	= "DTOE",
-+		[23]	= "CSTOE",
-+		[24]	= "BLKOVRE",
-+		[25]	= "DMADONE",
-+		[26]	= "FIFOEMPTY",
-+		[27]	= "XFRDONE",
- 		[30]	= "OVRE",
- 		[31]	= "UNRE",
- 	};
-@@ -193,12 +335,16 @@ static int atmci_regs_show(struct seq_file *s, void *v)
- 	if (!buf)
- 		return -ENOMEM;
- 
--	/* Grab a more or less consistent snapshot */
--	spin_lock_irq(&host->mmc->lock);
-+	/*
-+	 * Grab a more or less consistent snapshot. Note that we're
-+	 * not disabling interrupts, so IMR and SR may not be
-+	 * consistent.
-+	 */
-+	spin_lock_bh(&host->lock);
- 	clk_enable(host->mck);
- 	memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
- 	clk_disable(host->mck);
--	spin_unlock_irq(&host->mmc->lock);
-+	spin_unlock_bh(&host->lock);
- 
- 	seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
- 			buf[MCI_MR / 4],
-@@ -236,13 +382,13 @@ static const struct file_operations atmci_regs_fops = {
- 	.release	= single_release,
- };
- 
--static void atmci_init_debugfs(struct atmel_mci *host)
-+static void atmci_init_debugfs(struct atmel_mci_slot *slot)
- {
--	struct mmc_host	*mmc;
--	struct dentry	*root;
--	struct dentry	*node;
-+	struct mmc_host		*mmc = slot->mmc;
-+	struct atmel_mci	*host = slot->host;
-+	struct dentry		*root;
-+	struct dentry		*node;
- 
--	mmc = host->mmc;
- 	root = mmc->debugfs_root;
- 	if (!root)
- 		return;
-@@ -254,7 +400,11 @@ static void atmci_init_debugfs(struct atmel_mci *host)
- 	if (!node)
- 		goto err;
- 
--	node = debugfs_create_file("req", S_IRUSR, root, host, &atmci_req_fops);
-+	node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
-+	if (!node)
-+		goto err;
-+
-+	node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
- 	if (!node)
- 		goto err;
- 
-@@ -271,25 +421,7 @@ static void atmci_init_debugfs(struct atmel_mci *host)
- 	return;
- 
- err:
--	dev_err(&host->pdev->dev,
--		"failed to initialize debugfs for controller\n");
--}
--
--static void atmci_enable(struct atmel_mci *host)
--{
--	clk_enable(host->mck);
--	mci_writel(host, CR, MCI_CR_MCIEN);
--	mci_writel(host, MR, host->mode_reg);
--	mci_writel(host, SDCR, host->sdc_reg);
--}
--
--static void atmci_disable(struct atmel_mci *host)
--{
--	mci_writel(host, CR, MCI_CR_SWRST);
--
--	/* Stall until write is complete, then disable the bus clock */
--	mci_readl(host, SR);
--	clk_disable(host->mck);
-+	dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
- }
- 
- static inline unsigned int ns_to_clocks(struct atmel_mci *host,
-@@ -299,7 +431,7 @@ static inline unsigned int ns_to_clocks(struct atmel_mci *host,
- }
- 
- static void atmci_set_timeout(struct atmel_mci *host,
--			      struct mmc_data *data)
-+		struct atmel_mci_slot *slot, struct mmc_data *data)
- {
- 	static unsigned	dtomul_to_shift[] = {
- 		0, 4, 7, 8, 10, 12, 16, 20
-@@ -322,7 +454,7 @@ static void atmci_set_timeout(struct atmel_mci *host,
- 		dtocyc = 15;
- 	}
- 
--	dev_vdbg(&host->mmc->class_dev, "setting timeout to %u cycles\n",
-+	dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
- 			dtocyc << dtomul_to_shift[dtomul]);
- 	mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
- }
-@@ -375,15 +507,12 @@ static u32 atmci_prepare_command(struct mmc_host *mmc,
- }
- 
- static void atmci_start_command(struct atmel_mci *host,
--				struct mmc_command *cmd,
--				u32 cmd_flags)
-+		struct mmc_command *cmd, u32 cmd_flags)
- {
--	/* Must read host->cmd after testing event flags */
--	smp_rmb();
- 	WARN_ON(host->cmd);
- 	host->cmd = cmd;
- 
--	dev_vdbg(&host->mmc->class_dev,
-+	dev_vdbg(&host->pdev->dev,
- 			"start command: ARGR=0x%08x CMDR=0x%08x\n",
- 			cmd->arg, cmd_flags);
- 
-@@ -391,34 +520,172 @@ static void atmci_start_command(struct atmel_mci *host,
- 	mci_writel(host, CMDR, cmd_flags);
- }
- 
--static void send_stop_cmd(struct mmc_host *mmc, struct mmc_data *data)
-+static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
- {
--	struct atmel_mci *host = mmc_priv(mmc);
--
- 	atmci_start_command(host, data->stop, host->stop_cmdr);
- 	mci_writel(host, IER, MCI_CMDRDY);
- }
- 
--static void atmci_request_end(struct mmc_host *mmc, struct mmc_request *mrq)
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+static void atmci_dma_cleanup(struct atmel_mci *host)
- {
--	struct atmel_mci *host = mmc_priv(mmc);
-+	struct mmc_data			*data = host->data;
- 
--	WARN_ON(host->cmd || host->data);
--	host->mrq = NULL;
-+	dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
-+		     ((data->flags & MMC_DATA_WRITE)
-+		      ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
-+}
-+
-+static void atmci_stop_dma(struct atmel_mci *host)
-+{
-+	struct dma_chan *chan = host->data_chan;
-+
-+	if (chan) {
-+		chan->device->device_terminate_all(chan);
-+		atmci_dma_cleanup(host);
-+	} else {
-+		/* Data transfer was stopped by the interrupt handler */
-+		atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+		mci_writel(host, IER, MCI_NOTBUSY);
-+	}
-+}
-+
-+/* This function is called by the DMA driver from tasklet context. */
-+static void atmci_dma_complete(void *arg)
-+{
-+	struct atmel_mci	*host = arg;
-+	struct mmc_data		*data = host->data;
-+
-+	dev_vdbg(&host->pdev->dev, "DMA complete\n");
-+
-+	atmci_dma_cleanup(host);
-+
-+	/*
-+	 * If the card was removed, data will be NULL. No point trying
-+	 * to send the stop command or waiting for NBUSY in this case.
-+	 */
-+	if (data) {
-+		atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+		tasklet_schedule(&host->tasklet);
-+
-+		/*
-+		 * Regardless of what the documentation says, we have
-+		 * to wait for NOTBUSY even after block read
-+		 * operations.
-+		 *
-+		 * When the DMA transfer is complete, the controller
-+		 * may still be reading the CRC from the card, i.e.
-+		 * the data transfer is still in progress and we
-+		 * haven't seen all the potential error bits yet.
-+		 *
-+		 * The interrupt handler will schedule a different
-+		 * tasklet to finish things up when the data transfer
-+		 * is completely done.
-+		 *
-+		 * We may not complete the mmc request here anyway
-+		 * because the mmc layer may call back and cause us to
-+		 * violate the "don't submit new operations from the
-+		 * completion callback" rule of the dma engine
-+		 * framework.
-+		 */
-+		mci_writel(host, IER, MCI_NOTBUSY);
-+	}
-+}
-+
-+static int
-+atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
-+{
-+	struct dma_chan			*chan;
-+	struct dma_async_tx_descriptor	*desc;
-+	struct scatterlist		*sg;
-+	unsigned int			i;
-+	enum dma_data_direction		direction;
-+
-+	/*
-+	 * We don't do DMA on "complex" transfers, i.e. with
-+	 * non-word-aligned buffers or lengths. Also, we don't bother
-+	 * with all the DMA setup overhead for short transfers.
-+	 */
-+	if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
-+		return -EINVAL;
-+	if (data->blksz & 3)
-+		return -EINVAL;
-+
-+	for_each_sg(data->sg, sg, data->sg_len, i) {
-+		if (sg->offset & 3 || sg->length & 3)
-+			return -EINVAL;
-+	}
-+
-+	/* If we don't have a channel, we can't do DMA */
-+	chan = host->dma.chan;
-+	if (chan) {
-+		dma_chan_get(chan);
-+		host->data_chan = chan;
-+	}
-+
-+	if (!chan)
-+		return -ENODEV;
-+
-+	if (atmci_is_mci2())
-+		mci_writel(host, DMA, MCI_DMAEN);
-+
-+	if (data->flags & MMC_DATA_READ)
-+		direction = DMA_FROM_DEVICE;
-+	else
-+		direction = DMA_TO_DEVICE;
-+
-+	desc = chan->device->device_prep_slave_sg(chan,
-+			data->sg, data->sg_len, direction,
-+			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-+	if (!desc)
-+		return -ENOMEM;
-+
-+	host->dma.data_desc = desc;
-+	desc->callback = atmci_dma_complete;
-+	desc->callback_param = host;
-+
-+	return 0;
-+}
-+
-+static void atmci_submit_data(struct atmel_mci *host)
-+{
-+	struct dma_chan			*chan = host->data_chan;
-+	struct dma_async_tx_descriptor	*desc = host->dma.data_desc;
-+
-+	if (chan) {
-+		desc->tx_submit(desc);
-+		chan->device->device_issue_pending(chan);
-+	}
-+}
- 
--	atmci_disable(host);
-+#else /* CONFIG_MMC_ATMELMCI_DMA */
- 
--	mmc_request_done(mmc, mrq);
-+static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
-+{
-+	return -ENOSYS;
- }
- 
-+static void atmci_submit_data(struct atmel_mci *host)
-+{
-+
-+}
-+
-+static void atmci_stop_dma(struct atmel_mci *host)
-+{
-+	/* Data transfer was stopped by the interrupt handler */
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
-+	mci_writel(host, IER, MCI_NOTBUSY);
-+}
-+
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
-+
- /*
-  * Returns a mask of interrupt flags to be enabled after the whole
-  * request has been prepared.
-  */
--static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data)
-+static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--	u32			iflags;
-+	u32 iflags;
- 
- 	data->error = -EINPROGRESS;
- 
-@@ -426,77 +693,95 @@ static u32 atmci_submit_data(struct mmc_host *mmc, struct mmc_data *data)
- 	host->sg = NULL;
- 	host->data = data;
- 
--	dev_vdbg(&mmc->class_dev, "BLKR=0x%08x\n",
--			MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
--
- 	iflags = ATMCI_DATA_ERROR_FLAGS;
--	host->sg = data->sg;
--	host->pio_offset = 0;
--	if (data->flags & MMC_DATA_READ)
--		iflags |= MCI_RXRDY;
--	else
--		iflags |= MCI_TXRDY;
-+	if (atmci_prepare_data_dma(host, data)) {
-+		if (atmci_is_mci2())
-+			mci_writel(host, DMA, 0);
-+		host->data_chan = NULL;
-+
-+		/*
-+		 * Errata: MMC data write operation with less than 12
-+		 * bytes is impossible.
-+		 *
-+		 * Errata: MCI Transmit Data Register (TDR) FIFO
-+		 * corruption when length is not multiple of 4.
-+		 */
-+		if (data->blocks * data->blksz < 12
-+				|| (data->blocks * data->blksz) & 3)
-+			host->need_reset = true;
-+
-+		host->sg = data->sg;
-+		host->pio_offset = 0;
-+		if (data->flags & MMC_DATA_READ)
-+			iflags |= MCI_RXRDY;
-+		else
-+			iflags |= MCI_TXRDY;
-+	}
- 
- 	return iflags;
- }
- 
--static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+static void atmci_start_request(struct atmel_mci *host,
-+		struct atmel_mci_slot *slot)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--	struct mmc_data		*data;
-+	struct mmc_request	*mrq;
- 	struct mmc_command	*cmd;
-+	struct mmc_data		*data;
- 	u32			iflags;
--	u32			cmdflags = 0;
-+	u32			cmdflags;
- 
--	iflags = mci_readl(host, IMR);
--	if (iflags)
--		dev_warn(&mmc->class_dev, "WARNING: IMR=0x%08x\n",
--				mci_readl(host, IMR));
-+	mrq = slot->mrq;
-+	host->cur_slot = slot;
-+	host->mrq = mrq;
- 
--	WARN_ON(host->mrq != NULL);
-+	host->pending_events = 0;
-+	host->completed_events = 0;
-+	host->data_status = 0;
- 
--	/*
--	 * We may "know" the card is gone even though there's still an
--	 * electrical connection. If so, we really need to communicate
--	 * this to the MMC core since there won't be any more
--	 * interrupts as the card is completely removed. Otherwise,
--	 * the MMC core might believe the card is still there even
--	 * though the card was just removed very slowly.
--	 */
--	if (!host->present) {
--		mrq->cmd->error = -ENOMEDIUM;
--		mmc_request_done(mmc, mrq);
--		return;
-+	if (host->need_reset) {
-+		mci_writel(host, CR, MCI_CR_SWRST);
-+		mci_writel(host, CR, MCI_CR_MCIEN);
-+		mci_writel(host, MR, host->mode_reg);
-+		host->need_reset = false;
- 	}
-+	mci_writel(host, SDCR, slot->sdc_reg);
- 
--	host->mrq = mrq;
--	host->pending_events = 0;
--	host->completed_events = 0;
-+	iflags = mci_readl(host, IMR);
-+	if (iflags)
-+		dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
-+				iflags);
- 
--	atmci_enable(host);
-+	if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
-+		/* Send init sequence (74 clock cycles) */
-+		mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
-+		while (!(mci_readl(host, SR) & MCI_CMDRDY))
-+			cpu_relax();
-+	}
- 
--	/* We don't support multiple blocks of weird lengths. */
-+	iflags = 0;
- 	data = mrq->data;
- 	if (data) {
--		if (data->blocks > 1 && data->blksz & 3)
--			goto fail;
--		atmci_set_timeout(host, data);
-+		atmci_set_timeout(host, slot, data);
- 
- 		/* Must set block count/size before sending command */
- 		mci_writel(host, BLKR, MCI_BCNT(data->blocks)
- 				| MCI_BLKLEN(data->blksz));
-+		dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
-+			MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
-+
-+		iflags |= atmci_prepare_data(host, data);
- 	}
- 
--	iflags = MCI_CMDRDY;
-+	iflags |= MCI_CMDRDY;
- 	cmd = mrq->cmd;
--	cmdflags = atmci_prepare_command(mmc, cmd);
-+	cmdflags = atmci_prepare_command(slot->mmc, cmd);
- 	atmci_start_command(host, cmd, cmdflags);
- 
- 	if (data)
--		iflags |= atmci_submit_data(mmc, data);
-+		atmci_submit_data(host);
- 
- 	if (mrq->stop) {
--		host->stop_cmdr = atmci_prepare_command(mmc, mrq->stop);
-+		host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
- 		host->stop_cmdr |= MCI_CMDR_STOP_XFER;
- 		if (!(data->flags & MMC_DATA_WRITE))
- 			host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
-@@ -513,59 +798,156 @@ static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
- 	 * prepared yet.)
- 	 */
- 	mci_writel(host, IER, iflags);
-+}
- 
--	return;
-+static void atmci_queue_request(struct atmel_mci *host,
-+		struct atmel_mci_slot *slot, struct mmc_request *mrq)
-+{
-+	dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
-+			host->state);
-+
-+	spin_lock_bh(&host->lock);
-+	slot->mrq = mrq;
-+	if (host->state == STATE_IDLE) {
-+		host->state = STATE_SENDING_CMD;
-+		atmci_start_request(host, slot);
-+	} else {
-+		list_add_tail(&slot->queue_node, &host->queue);
-+	}
-+	spin_unlock_bh(&host->lock);
-+}
- 
--fail:
--	atmci_disable(host);
--	host->mrq = NULL;
--	mrq->cmd->error = -EINVAL;
--	mmc_request_done(mmc, mrq);
-+static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
-+{
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+	struct atmel_mci	*host = slot->host;
-+	struct mmc_data		*data;
-+
-+	WARN_ON(slot->mrq);
-+
-+	/*
-+	 * We may "know" the card is gone even though there's still an
-+	 * electrical connection. If so, we really need to communicate
-+	 * this to the MMC core since there won't be any more
-+	 * interrupts as the card is completely removed. Otherwise,
-+	 * the MMC core might believe the card is still there even
-+	 * though the card was just removed very slowly.
-+	 */
-+	if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
-+		mrq->cmd->error = -ENOMEDIUM;
-+		mmc_request_done(mmc, mrq);
-+		return;
-+	}
-+
-+	/* We don't support multiple blocks of weird lengths. */
-+	data = mrq->data;
-+	if (data && data->blocks > 1 && data->blksz & 3) {
-+		mrq->cmd->error = -EINVAL;
-+		mmc_request_done(mmc, mrq);
-+	}
-+
-+	atmci_queue_request(host, slot, mrq);
- }
- 
- static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+	struct atmel_mci	*host = slot->host;
-+	unsigned int		i;
-+
-+	slot->sdc_reg &= ~MCI_SDCBUS_MASK;
-+	switch (ios->bus_width) {
-+	case MMC_BUS_WIDTH_1:
-+		slot->sdc_reg |= MCI_SDCBUS_1BIT;
-+		break;
-+	case MMC_BUS_WIDTH_4:
-+		slot->sdc_reg |= MCI_SDCBUS_4BIT;
-+		break;
-+	}
- 
- 	if (ios->clock) {
-+		unsigned int clock_min = ~0U;
- 		u32 clkdiv;
- 
--		/* Set clock rate */
--		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * ios->clock) - 1;
-+		spin_lock_bh(&host->lock);
-+		if (!host->mode_reg) {
-+			clk_enable(host->mck);
-+			mci_writel(host, CR, MCI_CR_SWRST);
-+			mci_writel(host, CR, MCI_CR_MCIEN);
-+		}
-+
-+		/*
-+		 * Use mirror of ios->clock to prevent race with mmc
-+		 * core ios update when finding the minimum.
-+		 */
-+		slot->clock = ios->clock;
-+		for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+			if (host->slot[i] && host->slot[i]->clock
-+					&& host->slot[i]->clock < clock_min)
-+				clock_min = host->slot[i]->clock;
-+		}
-+
-+		/* Calculate clock divider */
-+		clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
- 		if (clkdiv > 255) {
- 			dev_warn(&mmc->class_dev,
- 				"clock %u too slow; using %lu\n",
--				ios->clock, host->bus_hz / (2 * 256));
-+				clock_min, host->bus_hz / (2 * 256));
- 			clkdiv = 255;
- 		}
- 
-+		/*
-+		 * WRPROOF and RDPROOF prevent overruns/underruns by
-+		 * stopping the clock when the FIFO is full/empty.
-+		 * This state is not expected to last for long.
-+		 */
- 		host->mode_reg = MCI_MR_CLKDIV(clkdiv) | MCI_MR_WRPROOF
- 					| MCI_MR_RDPROOF;
--	}
- 
--	switch (ios->bus_width) {
--	case MMC_BUS_WIDTH_1:
--		host->sdc_reg = 0;
--		break;
--	case MMC_BUS_WIDTH_4:
--		host->sdc_reg = MCI_SDCBUS_4BIT;
--		break;
-+		if (list_empty(&host->queue))
-+			mci_writel(host, MR, host->mode_reg);
-+		else
-+			host->need_clock_update = true;
-+
-+		spin_unlock_bh(&host->lock);
-+	} else {
-+		bool any_slot_active = false;
-+
-+		spin_lock_bh(&host->lock);
-+		slot->clock = 0;
-+		for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+			if (host->slot[i] && host->slot[i]->clock) {
-+				any_slot_active = true;
-+				break;
-+			}
-+		}
-+		if (!any_slot_active) {
-+			mci_writel(host, CR, MCI_CR_MCIDIS);
-+			if (host->mode_reg) {
-+				mci_readl(host, MR);
-+				clk_disable(host->mck);
-+			}
-+			host->mode_reg = 0;
-+		}
-+		spin_unlock_bh(&host->lock);
- 	}
- 
- 	switch (ios->power_mode) {
--	case MMC_POWER_ON:
--		/* Send init sequence (74 clock cycles) */
--		atmci_enable(host);
--		mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
--		while (!(mci_readl(host, SR) & MCI_CMDRDY))
--			cpu_relax();
--		atmci_disable(host);
-+	case MMC_POWER_UP:
-+		set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
- 		break;
- 	default:
- 		/*
- 		 * TODO: None of the currently available AVR32-based
- 		 * boards allow MMC power to be turned off. Implement
- 		 * power control when this can be tested properly.
-+		 *
-+		 * We also need to hook this into the clock management
-+		 * somehow so that newly inserted cards aren't
-+		 * subjected to a fast clock before we have a chance
-+		 * to figure out what the maximum rate is. Currently,
-+		 * there's no way to avoid this, and there never will
-+		 * be for boards that don't support power control.
- 		 */
- 		break;
- 	}
-@@ -573,31 +955,82 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
- 
- static int atmci_get_ro(struct mmc_host *mmc)
- {
--	int			read_only = 0;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	int			read_only = -ENOSYS;
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
- 
--	if (gpio_is_valid(host->wp_pin)) {
--		read_only = gpio_get_value(host->wp_pin);
-+	if (gpio_is_valid(slot->wp_pin)) {
-+		read_only = gpio_get_value(slot->wp_pin);
- 		dev_dbg(&mmc->class_dev, "card is %s\n",
- 				read_only ? "read-only" : "read-write");
--	} else {
--		dev_dbg(&mmc->class_dev,
--			"no pin for checking read-only switch."
--			" Assuming write-enable.\n");
- 	}
- 
- 	return read_only;
- }
- 
--static struct mmc_host_ops atmci_ops = {
-+static int atmci_get_cd(struct mmc_host *mmc)
-+{
-+	int			present = -ENOSYS;
-+	struct atmel_mci_slot	*slot = mmc_priv(mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		present = !gpio_get_value(slot->detect_pin);
-+		dev_dbg(&mmc->class_dev, "card is %spresent\n",
-+				present ? "" : "not ");
-+	}
-+
-+	return present;
-+}
-+
-+static const struct mmc_host_ops atmci_ops = {
- 	.request	= atmci_request,
- 	.set_ios	= atmci_set_ios,
- 	.get_ro		= atmci_get_ro,
-+	.get_cd		= atmci_get_cd,
- };
- 
-+/* Called with host->lock held */
-+static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
-+	__releases(&host->lock)
-+	__acquires(&host->lock)
-+{
-+	struct atmel_mci_slot	*slot = NULL;
-+	struct mmc_host		*prev_mmc = host->cur_slot->mmc;
-+
-+	WARN_ON(host->cmd || host->data);
-+
-+	/*
-+	 * Update the MMC clock rate if necessary. This may be
-+	 * necessary if set_ios() is called when a different slot is
-+	 * busy transfering data.
-+	 */
-+	if (host->need_clock_update)
-+		mci_writel(host, MR, host->mode_reg);
-+
-+	host->cur_slot->mrq = NULL;
-+	host->mrq = NULL;
-+	if (!list_empty(&host->queue)) {
-+		slot = list_entry(host->queue.next,
-+				struct atmel_mci_slot, queue_node);
-+		list_del(&slot->queue_node);
-+		dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
-+				mmc_hostname(slot->mmc));
-+		host->state = STATE_SENDING_CMD;
-+		atmci_start_request(host, slot);
-+	} else {
-+		dev_vdbg(&host->pdev->dev, "list empty\n");
-+		host->state = STATE_IDLE;
-+	}
-+
-+	spin_unlock(&host->lock);
-+	mmc_request_done(prev_mmc, mrq);
-+	spin_lock(&host->lock);
-+}
-+
- static void atmci_command_complete(struct atmel_mci *host,
--			struct mmc_command *cmd, u32 status)
-+			struct mmc_command *cmd)
- {
-+	u32		status = host->cmd_status;
-+
- 	/* Read the response from the card (up to 16 bytes) */
- 	cmd->resp[0] = mci_readl(host, RSPR);
- 	cmd->resp[1] = mci_readl(host, RSPR);
-@@ -614,11 +1047,12 @@ static void atmci_command_complete(struct atmel_mci *host,
- 		cmd->error = 0;
- 
- 	if (cmd->error) {
--		dev_dbg(&host->mmc->class_dev,
-+		dev_dbg(&host->pdev->dev,
- 			"command error: status=0x%08x\n", status);
- 
- 		if (cmd->data) {
- 			host->data = NULL;
-+			atmci_stop_dma(host);
- 			mci_writel(host, IDR, MCI_NOTBUSY
- 					| MCI_TXRDY | MCI_RXRDY
- 					| ATMCI_DATA_ERROR_FLAGS);
-@@ -628,146 +1062,222 @@ static void atmci_command_complete(struct atmel_mci *host,
- 
- static void atmci_detect_change(unsigned long data)
- {
--	struct atmel_mci *host = (struct atmel_mci *)data;
--	struct mmc_request *mrq = host->mrq;
--	int present;
-+	struct atmel_mci_slot	*slot = (struct atmel_mci_slot *)data;
-+	bool			present;
-+	bool			present_old;
- 
- 	/*
--	 * atmci_remove() sets detect_pin to -1 before freeing the
--	 * interrupt. We must not re-enable the interrupt if it has
--	 * been freed.
-+	 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
-+	 * freeing the interrupt. We must not re-enable the interrupt
-+	 * if it has been freed, and if we're shutting down, it
-+	 * doesn't really matter whether the card is present or not.
- 	 */
- 	smp_rmb();
--	if (!gpio_is_valid(host->detect_pin))
-+	if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
- 		return;
- 
--	enable_irq(gpio_to_irq(host->detect_pin));
--	present = !gpio_get_value(host->detect_pin);
-+	enable_irq(gpio_to_irq(slot->detect_pin));
-+	present = !gpio_get_value(slot->detect_pin);
-+	present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+
-+	dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
-+			present, present_old);
- 
--	dev_vdbg(&host->pdev->dev, "detect change: %d (was %d)\n",
--			present, host->present);
-+	if (present != present_old) {
-+		struct atmel_mci	*host = slot->host;
-+		struct mmc_request	*mrq;
- 
--	if (present != host->present) {
--		dev_dbg(&host->mmc->class_dev, "card %s\n",
-+		dev_dbg(&slot->mmc->class_dev, "card %s\n",
- 			present ? "inserted" : "removed");
--		host->present = present;
- 
--		/* Reset controller if card is gone */
--		if (!present) {
--			mci_writel(host, CR, MCI_CR_SWRST);
--			mci_writel(host, IDR, ~0UL);
--			mci_writel(host, CR, MCI_CR_MCIEN);
--		}
-+		spin_lock(&host->lock);
-+
-+		if (!present)
-+			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+		else
-+			set_bit(ATMCI_CARD_PRESENT, &slot->flags);
- 
- 		/* Clean up queue if present */
-+		mrq = slot->mrq;
- 		if (mrq) {
--			/*
--			 * Reset controller to terminate any ongoing
--			 * commands or data transfers.
--			 */
--			mci_writel(host, CR, MCI_CR_SWRST);
-+			if (mrq == host->mrq) {
-+				/*
-+				 * Reset controller to terminate any ongoing
-+				 * commands or data transfers.
-+				 */
-+				mci_writel(host, CR, MCI_CR_SWRST);
-+				mci_writel(host, CR, MCI_CR_MCIEN);
-+				mci_writel(host, MR, host->mode_reg);
- 
--			if (!atmci_is_completed(host, EVENT_CMD_COMPLETE))
--				mrq->cmd->error = -ENOMEDIUM;
--
--			if (mrq->data && !atmci_is_completed(host,
--						EVENT_DATA_COMPLETE)) {
- 				host->data = NULL;
--				mrq->data->error = -ENOMEDIUM;
-+				host->cmd = NULL;
-+
-+				switch (host->state) {
-+				case STATE_IDLE:
-+					break;
-+				case STATE_SENDING_CMD:
-+					mrq->cmd->error = -ENOMEDIUM;
-+					if (!mrq->data)
-+						break;
-+					/* fall through */
-+				case STATE_SENDING_DATA:
-+					mrq->data->error = -ENOMEDIUM;
-+					atmci_stop_dma(host);
-+					break;
-+				case STATE_DATA_BUSY:
-+				case STATE_DATA_ERROR:
-+					if (mrq->data->error == -EINPROGRESS)
-+						mrq->data->error = -ENOMEDIUM;
-+					if (!mrq->stop)
-+						break;
-+					/* fall through */
-+				case STATE_SENDING_STOP:
-+					mrq->stop->error = -ENOMEDIUM;
-+					break;
-+				}
-+
-+				atmci_request_end(host, mrq);
-+			} else {
-+				list_del(&slot->queue_node);
-+				mrq->cmd->error = -ENOMEDIUM;
-+				if (mrq->data)
-+					mrq->data->error = -ENOMEDIUM;
-+				if (mrq->stop)
-+					mrq->stop->error = -ENOMEDIUM;
-+
-+				spin_unlock(&host->lock);
-+				mmc_request_done(slot->mmc, mrq);
-+				spin_lock(&host->lock);
- 			}
--			if (mrq->stop && !atmci_is_completed(host,
--						EVENT_STOP_COMPLETE))
--				mrq->stop->error = -ENOMEDIUM;
--
--			host->cmd = NULL;
--			atmci_request_end(host->mmc, mrq);
- 		}
-+		spin_unlock(&host->lock);
- 
--		mmc_detect_change(host->mmc, 0);
-+		mmc_detect_change(slot->mmc, 0);
- 	}
- }
- 
- static void atmci_tasklet_func(unsigned long priv)
- {
--	struct mmc_host		*mmc = (struct mmc_host *)priv;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci	*host = (struct atmel_mci *)priv;
- 	struct mmc_request	*mrq = host->mrq;
- 	struct mmc_data		*data = host->data;
-+	struct mmc_command	*cmd = host->cmd;
-+	enum atmel_mci_state	state = host->state;
-+	enum atmel_mci_state	prev_state;
-+	u32			status;
-+
-+	spin_lock(&host->lock);
- 
--	dev_vdbg(&mmc->class_dev,
--		"tasklet: pending/completed/mask %lx/%lx/%x\n",
--		host->pending_events, host->completed_events,
-+	state = host->state;
-+
-+	dev_vdbg(&host->pdev->dev,
-+		"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
-+		state, host->pending_events, host->completed_events,
- 		mci_readl(host, IMR));
- 
--	if (atmci_test_and_clear_pending(host, EVENT_CMD_COMPLETE)) {
--		/*
--		 * host->cmd must be set to NULL before the interrupt
--		 * handler sees EVENT_CMD_COMPLETE
--		 */
--		host->cmd = NULL;
--		smp_wmb();
--		atmci_set_completed(host, EVENT_CMD_COMPLETE);
--		atmci_command_complete(host, mrq->cmd, host->cmd_status);
--
--		if (!mrq->cmd->error && mrq->stop
--				&& atmci_is_completed(host, EVENT_XFER_COMPLETE)
--				&& !atmci_test_and_set_completed(host,
--					EVENT_STOP_SENT))
--			send_stop_cmd(host->mmc, mrq->data);
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_STOP_COMPLETE)) {
--		/*
--		 * host->cmd must be set to NULL before the interrupt
--		 * handler sees EVENT_STOP_COMPLETE
--		 */
--		host->cmd = NULL;
--		smp_wmb();
--		atmci_set_completed(host, EVENT_STOP_COMPLETE);
--		atmci_command_complete(host, mrq->stop, host->stop_status);
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_DATA_ERROR)) {
--		u32 status = host->data_status;
-+	do {
-+		prev_state = state;
- 
--		dev_vdbg(&mmc->class_dev, "data error: status=%08x\n", status);
-+		switch (state) {
-+		case STATE_IDLE:
-+			break;
- 
--		atmci_set_completed(host, EVENT_DATA_ERROR);
--		atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+		case STATE_SENDING_CMD:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_CMD_COMPLETE))
-+				break;
- 
--		if (status & MCI_DTOE) {
--			dev_dbg(&mmc->class_dev,
--					"data timeout error\n");
--			data->error = -ETIMEDOUT;
--		} else if (status & MCI_DCRCE) {
--			dev_dbg(&mmc->class_dev, "data CRC error\n");
--			data->error = -EILSEQ;
--		} else {
--			dev_dbg(&mmc->class_dev,
--					"data FIFO error (status=%08x)\n",
--					status);
--			data->error = -EIO;
--		}
-+			host->cmd = NULL;
-+			atmci_set_completed(host, EVENT_CMD_COMPLETE);
-+			atmci_command_complete(host, mrq->cmd);
-+			if (!mrq->data || cmd->error) {
-+				atmci_request_end(host, host->mrq);
-+				goto unlock;
-+			}
-+
-+			prev_state = state = STATE_SENDING_DATA;
-+			/* fall through */
-+
-+		case STATE_SENDING_DATA:
-+			if (atmci_test_and_clear_pending(host,
-+						EVENT_DATA_ERROR)) {
-+				atmci_stop_dma(host);
-+				if (data->stop)
-+					send_stop_cmd(host, data);
-+				state = STATE_DATA_ERROR;
-+				break;
-+			}
- 
--		if (host->present && data->stop
--				&& atmci_is_completed(host, EVENT_CMD_COMPLETE)
--				&& !atmci_test_and_set_completed(
--					host, EVENT_STOP_SENT))
--			send_stop_cmd(host->mmc, data);
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_XFER_COMPLETE))
-+				break;
- 
--		host->data = NULL;
--	}
--	if (atmci_test_and_clear_pending(host, EVENT_DATA_COMPLETE)) {
--		atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+			atmci_set_completed(host, EVENT_XFER_COMPLETE);
-+			prev_state = state = STATE_DATA_BUSY;
-+			/* fall through */
-+
-+		case STATE_DATA_BUSY:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_DATA_COMPLETE))
-+				break;
-+
-+			host->data = NULL;
-+			atmci_set_completed(host, EVENT_DATA_COMPLETE);
-+			status = host->data_status;
-+			if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
-+				if (status & MCI_DTOE) {
-+					dev_dbg(&host->pdev->dev,
-+							"data timeout error\n");
-+					data->error = -ETIMEDOUT;
-+				} else if (status & MCI_DCRCE) {
-+					dev_dbg(&host->pdev->dev,
-+							"data CRC error\n");
-+					data->error = -EILSEQ;
-+				} else {
-+					dev_dbg(&host->pdev->dev,
-+						"data FIFO error (status=%08x)\n",
-+						status);
-+					data->error = -EIO;
-+				}
-+			} else {
-+				data->bytes_xfered = data->blocks * data->blksz;
-+				data->error = 0;
-+			}
-+
-+			if (!data->stop) {
-+				atmci_request_end(host, host->mrq);
-+				goto unlock;
-+			}
-+
-+			prev_state = state = STATE_SENDING_STOP;
-+			if (!data->error)
-+				send_stop_cmd(host, data);
-+			/* fall through */
-+
-+		case STATE_SENDING_STOP:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_CMD_COMPLETE))
-+				break;
-+
-+			host->cmd = NULL;
-+			atmci_command_complete(host, mrq->stop);
-+			atmci_request_end(host, host->mrq);
-+			goto unlock;
-+
-+		case STATE_DATA_ERROR:
-+			if (!atmci_test_and_clear_pending(host,
-+						EVENT_XFER_COMPLETE))
-+				break;
- 
--		if (!atmci_is_completed(host, EVENT_DATA_ERROR)) {
--			data->bytes_xfered = data->blocks * data->blksz;
--			data->error = 0;
-+			state = STATE_DATA_BUSY;
-+			break;
- 		}
-+	} while (state != prev_state);
- 
--		host->data = NULL;
--	}
-+	host->state = state;
- 
--	if (host->mrq && !host->cmd && !host->data)
--		atmci_request_end(mmc, host->mrq);
-+unlock:
-+	spin_unlock(&host->lock);
- }
- 
- static void atmci_read_data_pio(struct atmel_mci *host)
-@@ -789,6 +1299,7 @@ static void atmci_read_data_pio(struct atmel_mci *host)
- 			nbytes += 4;
- 
- 			if (offset == sg->length) {
-+				flush_dcache_page(sg_page(sg));
- 				host->sg = sg = sg_next(sg);
- 				if (!sg)
- 					goto done;
-@@ -817,9 +1328,11 @@ static void atmci_read_data_pio(struct atmel_mci *host)
- 			mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
- 						| ATMCI_DATA_ERROR_FLAGS));
- 			host->data_status = status;
-+			data->bytes_xfered += nbytes;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
--			break;
-+			return;
- 		}
- 	} while (status & MCI_RXRDY);
- 
-@@ -832,10 +1345,8 @@ done:
- 	mci_writel(host, IDR, MCI_RXRDY);
- 	mci_writel(host, IER, MCI_NOTBUSY);
- 	data->bytes_xfered += nbytes;
--	atmci_set_completed(host, EVENT_XFER_COMPLETE);
--	if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE)
--			&& !atmci_test_and_set_completed(host, EVENT_STOP_SENT))
--		send_stop_cmd(host->mmc, data);
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
- }
- 
- static void atmci_write_data_pio(struct atmel_mci *host)
-@@ -888,9 +1399,11 @@ static void atmci_write_data_pio(struct atmel_mci *host)
- 			mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
- 						| ATMCI_DATA_ERROR_FLAGS));
- 			host->data_status = status;
-+			data->bytes_xfered += nbytes;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
--			break;
-+			return;
- 		}
- 	} while (status & MCI_TXRDY);
- 
-@@ -903,38 +1416,26 @@ done:
- 	mci_writel(host, IDR, MCI_TXRDY);
- 	mci_writel(host, IER, MCI_NOTBUSY);
- 	data->bytes_xfered += nbytes;
--	atmci_set_completed(host, EVENT_XFER_COMPLETE);
--	if (data->stop && atmci_is_completed(host, EVENT_CMD_COMPLETE)
--			&& !atmci_test_and_set_completed(host, EVENT_STOP_SENT))
--		send_stop_cmd(host->mmc, data);
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_XFER_COMPLETE);
- }
- 
--static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
-+static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
- {
--	struct atmel_mci	*host = mmc_priv(mmc);
--
- 	mci_writel(host, IDR, MCI_CMDRDY);
- 
--	if (atmci_is_completed(host, EVENT_STOP_SENT)) {
--		host->stop_status = status;
--		atmci_set_pending(host, EVENT_STOP_COMPLETE);
--	} else {
--		host->cmd_status = status;
--		atmci_set_pending(host, EVENT_CMD_COMPLETE);
--	}
--
-+	host->cmd_status = status;
-+	smp_wmb();
-+	atmci_set_pending(host, EVENT_CMD_COMPLETE);
- 	tasklet_schedule(&host->tasklet);
- }
- 
- static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- {
--	struct mmc_host		*mmc = dev_id;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci	*host = dev_id;
- 	u32			status, mask, pending;
- 	unsigned int		pass_count = 0;
- 
--	spin_lock(&mmc->lock);
--
- 	do {
- 		status = mci_readl(host, SR);
- 		mask = mci_readl(host, IMR);
-@@ -946,13 +1447,18 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- 			mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
- 					| MCI_RXRDY | MCI_TXRDY);
- 			pending &= mci_readl(host, IMR);
-+
- 			host->data_status = status;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_ERROR);
- 			tasklet_schedule(&host->tasklet);
- 		}
- 		if (pending & MCI_NOTBUSY) {
--			mci_writel(host, IDR, (MCI_NOTBUSY
--					       | ATMCI_DATA_ERROR_FLAGS));
-+			mci_writel(host, IDR,
-+					ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
-+			if (!host->data_status)
-+				host->data_status = status;
-+			smp_wmb();
- 			atmci_set_pending(host, EVENT_DATA_COMPLETE);
- 			tasklet_schedule(&host->tasklet);
- 		}
-@@ -962,18 +1468,15 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
- 			atmci_write_data_pio(host);
- 
- 		if (pending & MCI_CMDRDY)
--			atmci_cmd_interrupt(mmc, status);
-+			atmci_cmd_interrupt(host, status);
- 	} while (pass_count++ < 5);
- 
--	spin_unlock(&mmc->lock);
--
- 	return pass_count ? IRQ_HANDLED : IRQ_NONE;
- }
- 
- static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
- {
--	struct mmc_host		*mmc = dev_id;
--	struct atmel_mci	*host = mmc_priv(mmc);
-+	struct atmel_mci_slot	*slot = dev_id;
- 
- 	/*
- 	 * Disable interrupts until the pin has stabilized and check
-@@ -981,19 +1484,176 @@ static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
- 	 * middle of the timer routine when this interrupt triggers.
- 	 */
- 	disable_irq_nosync(irq);
--	mod_timer(&host->detect_timer, jiffies + msecs_to_jiffies(20));
-+	mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
- 
- 	return IRQ_HANDLED;
- }
- 
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+
-+static inline struct atmel_mci *
-+dma_client_to_atmel_mci(struct dma_client *client)
-+{
-+	return container_of(client, struct atmel_mci, dma.client);
-+}
-+
-+static enum dma_state_client atmci_dma_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_mci	*host;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	host = dma_client_to_atmel_mci(client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		spin_lock_bh(&host->lock);
-+		if (!host->dma.chan) {
-+			host->dma.chan = chan;
-+			ret = DMA_ACK;
-+		}
-+		spin_unlock_bh(&host->lock);
-+
-+		if (ret == DMA_ACK)
-+			dev_info(&host->pdev->dev,
-+					"Using %s for DMA transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		spin_lock_bh(&host->lock);
-+		if (host->dma.chan == chan) {
-+			host->dma.chan = NULL;
-+			ret = DMA_ACK;
-+		}
-+		spin_unlock_bh(&host->lock);
-+
-+		if (ret == DMA_ACK)
-+			dev_info(&host->pdev->dev,
-+					"Lost %s, falling back to PIO\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+
-+	return ret;
-+}
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
-+
-+static int __init atmci_init_slot(struct atmel_mci *host,
-+		struct mci_slot_pdata *slot_data, unsigned int id,
-+		u32 sdc_reg)
-+{
-+	struct mmc_host			*mmc;
-+	struct atmel_mci_slot		*slot;
-+
-+	mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
-+	if (!mmc)
-+		return -ENOMEM;
-+
-+	slot = mmc_priv(mmc);
-+	slot->mmc = mmc;
-+	slot->host = host;
-+	slot->detect_pin = slot_data->detect_pin;
-+	slot->wp_pin = slot_data->wp_pin;
-+	slot->sdc_reg = sdc_reg;
-+
-+	mmc->ops = &atmci_ops;
-+	mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
-+	mmc->f_max = host->bus_hz / 2;
-+	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
-+	if (slot_data->bus_width >= 4)
-+		mmc->caps |= MMC_CAP_4_BIT_DATA;
-+
-+	mmc->max_hw_segs = 64;
-+	mmc->max_phys_segs = 64;
-+	mmc->max_req_size = 32768 * 512;
-+	mmc->max_blk_size = 32768;
-+	mmc->max_blk_count = 512;
-+
-+	/* Assume card is present initially */
-+	set_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		if (gpio_request(slot->detect_pin, "mmc_detect")) {
-+			dev_dbg(&mmc->class_dev, "no detect pin available\n");
-+			slot->detect_pin = -EBUSY;
-+		} else if (gpio_get_value(slot->detect_pin)) {
-+			clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
-+		}
-+	}
-+
-+	if (!gpio_is_valid(slot->detect_pin))
-+		mmc->caps |= MMC_CAP_NEEDS_POLL;
-+
-+	if (gpio_is_valid(slot->wp_pin)) {
-+		if (gpio_request(slot->wp_pin, "mmc_wp")) {
-+			dev_dbg(&mmc->class_dev, "no WP pin available\n");
-+			slot->wp_pin = -EBUSY;
-+		}
-+	}
-+
-+	host->slot[id] = slot;
-+	mmc_add_host(mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		int ret;
-+
-+		setup_timer(&slot->detect_timer, atmci_detect_change,
-+				(unsigned long)slot);
-+
-+		ret = request_irq(gpio_to_irq(slot->detect_pin),
-+				atmci_detect_interrupt,
-+				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-+				"mmc-detect", slot);
-+		if (ret) {
-+			dev_dbg(&mmc->class_dev,
-+				"could not request IRQ %d for detect pin\n",
-+				gpio_to_irq(slot->detect_pin));
-+			gpio_free(slot->detect_pin);
-+			slot->detect_pin = -EBUSY;
-+		}
-+	}
-+
-+	atmci_init_debugfs(slot);
-+
-+	return 0;
-+}
-+
-+static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
-+		unsigned int id)
-+{
-+	/* Debugfs stuff is cleaned up by mmc core */
-+
-+	set_bit(ATMCI_SHUTDOWN, &slot->flags);
-+	smp_wmb();
-+
-+	mmc_remove_host(slot->mmc);
-+
-+	if (gpio_is_valid(slot->detect_pin)) {
-+		int pin = slot->detect_pin;
-+
-+		free_irq(gpio_to_irq(pin), slot);
-+		del_timer_sync(&slot->detect_timer);
-+		gpio_free(pin);
-+	}
-+	if (gpio_is_valid(slot->wp_pin))
-+		gpio_free(slot->wp_pin);
-+
-+	slot->host->slot[id] = NULL;
-+	mmc_free_host(slot->mmc);
-+}
-+
- static int __init atmci_probe(struct platform_device *pdev)
- {
- 	struct mci_platform_data	*pdata;
--	struct atmel_mci *host;
--	struct mmc_host *mmc;
--	struct resource *regs;
--	int irq;
--	int ret;
-+	struct atmel_mci		*host;
-+	struct resource			*regs;
-+	unsigned int			nr_slots;
-+	int				irq;
-+	int				ret;
- 
- 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- 	if (!regs)
-@@ -1005,15 +1665,13 @@ static int __init atmci_probe(struct platform_device *pdev)
- 	if (irq < 0)
- 		return irq;
- 
--	mmc = mmc_alloc_host(sizeof(struct atmel_mci), &pdev->dev);
--	if (!mmc)
-+	host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
-+	if (!host)
- 		return -ENOMEM;
- 
--	host = mmc_priv(mmc);
- 	host->pdev = pdev;
--	host->mmc = mmc;
--	host->detect_pin = pdata->detect_pin;
--	host->wp_pin = pdata->wp_pin;
-+	spin_lock_init(&host->lock);
-+	INIT_LIST_HEAD(&host->queue);
- 
- 	host->mck = clk_get(&pdev->dev, "mci_clk");
- 	if (IS_ERR(host->mck)) {
-@@ -1033,122 +1691,102 @@ static int __init atmci_probe(struct platform_device *pdev)
- 
- 	host->mapbase = regs->start;
- 
--	mmc->ops = &atmci_ops;
--	mmc->f_min = (host->bus_hz + 511) / 512;
--	mmc->f_max = host->bus_hz / 2;
--	mmc->ocr_avail	= MMC_VDD_32_33 | MMC_VDD_33_34;
--	mmc->caps |= MMC_CAP_4_BIT_DATA;
-+	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
- 
--	mmc->max_hw_segs = 64;
--	mmc->max_phys_segs = 64;
--	mmc->max_req_size = 32768 * 512;
--	mmc->max_blk_size = 32768;
--	mmc->max_blk_count = 512;
--
--	tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)mmc);
--
--	ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, mmc);
-+	ret = request_irq(irq, atmci_interrupt, 0, pdev->dev.bus_id, host);
- 	if (ret)
- 		goto err_request_irq;
- 
--	/* Assume card is present if we don't have a detect pin */
--	host->present = 1;
--	if (gpio_is_valid(host->detect_pin)) {
--		if (gpio_request(host->detect_pin, "mmc_detect")) {
--			dev_dbg(&mmc->class_dev, "no detect pin available\n");
--			host->detect_pin = -1;
--		} else {
--			host->present = !gpio_get_value(host->detect_pin);
--		}
--	}
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (pdata->dma_slave) {
-+		struct dma_slave *slave = pdata->dma_slave;
- 
--	if (!gpio_is_valid(host->detect_pin))
--		mmc->caps |= MMC_CAP_NEEDS_POLL;
-+		slave->tx_reg = regs->start + MCI_TDR;
-+		slave->rx_reg = regs->start + MCI_RDR;
- 
--	if (gpio_is_valid(host->wp_pin)) {
--		if (gpio_request(host->wp_pin, "mmc_wp")) {
--			dev_dbg(&mmc->class_dev, "no WP pin available\n");
--			host->wp_pin = -1;
--		}
-+		/* Try to grab a DMA channel */
-+		host->dma.client.event_callback = atmci_dma_event;
-+		dma_cap_set(DMA_SLAVE, host->dma.client.cap_mask);
-+		host->dma.client.slave = slave;
-+
-+		dma_async_client_register(&host->dma.client);
-+		dma_async_client_chan_request(&host->dma.client);
-+	} else {
-+		dev_notice(&pdev->dev, "DMA not available, using PIO\n");
- 	}
-+#endif /* CONFIG_MMC_ATMELMCI_DMA */
- 
- 	platform_set_drvdata(pdev, host);
- 
--	mmc_add_host(mmc);
--
--	if (gpio_is_valid(host->detect_pin)) {
--		setup_timer(&host->detect_timer, atmci_detect_change,
--				(unsigned long)host);
--
--		ret = request_irq(gpio_to_irq(host->detect_pin),
--				atmci_detect_interrupt,
--				IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
--				"mmc-detect", mmc);
--		if (ret) {
--			dev_dbg(&mmc->class_dev,
--				"could not request IRQ %d for detect pin\n",
--				gpio_to_irq(host->detect_pin));
--			gpio_free(host->detect_pin);
--			host->detect_pin = -1;
--		}
-+	/* We need at least one slot to succeed */
-+	nr_slots = 0;
-+	ret = -ENODEV;
-+	if (pdata->slot[0].bus_width) {
-+		ret = atmci_init_slot(host, &pdata->slot[0],
-+				MCI_SDCSEL_SLOT_A, 0);
-+		if (!ret)
-+			nr_slots++;
-+	}
-+	if (pdata->slot[1].bus_width) {
-+		ret = atmci_init_slot(host, &pdata->slot[1],
-+				MCI_SDCSEL_SLOT_B, 1);
-+		if (!ret)
-+			nr_slots++;
- 	}
- 
--	dev_info(&mmc->class_dev,
--			"Atmel MCI controller at 0x%08lx irq %d\n",
--			host->mapbase, irq);
-+	if (!nr_slots)
-+		goto err_init_slot;
- 
--	atmci_init_debugfs(host);
-+	dev_info(&pdev->dev,
-+			"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
-+			host->mapbase, irq, nr_slots);
- 
- 	return 0;
- 
-+err_init_slot:
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (pdata->dma_slave)
-+		dma_async_client_unregister(&host->dma.client);
-+#endif
-+	free_irq(irq, host);
- err_request_irq:
- 	iounmap(host->regs);
- err_ioremap:
- 	clk_put(host->mck);
- err_clk_get:
--	mmc_free_host(mmc);
-+	kfree(host);
- 	return ret;
- }
- 
- static int __exit atmci_remove(struct platform_device *pdev)
- {
--	struct atmel_mci *host = platform_get_drvdata(pdev);
-+	struct atmel_mci	*host = platform_get_drvdata(pdev);
-+	unsigned int		i;
- 
- 	platform_set_drvdata(pdev, NULL);
- 
--	if (host) {
--		/* Debugfs stuff is cleaned up by mmc core */
--
--		if (gpio_is_valid(host->detect_pin)) {
--			int pin = host->detect_pin;
--
--			/* Make sure the timer doesn't enable the interrupt */
--			host->detect_pin = -1;
--			smp_wmb();
--
--			free_irq(gpio_to_irq(pin), host->mmc);
--			del_timer_sync(&host->detect_timer);
--			gpio_free(pin);
--		}
--
--		mmc_remove_host(host->mmc);
-+	for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
-+		if (host->slot[i])
-+			atmci_cleanup_slot(host->slot[i], i);
-+	}
- 
--		clk_enable(host->mck);
--		mci_writel(host, IDR, ~0UL);
--		mci_writel(host, CR, MCI_CR_MCIDIS);
--		mci_readl(host, SR);
--		clk_disable(host->mck);
-+	clk_enable(host->mck);
-+	mci_writel(host, IDR, ~0UL);
-+	mci_writel(host, CR, MCI_CR_MCIDIS);
-+	mci_readl(host, SR);
-+	clk_disable(host->mck);
- 
--		if (gpio_is_valid(host->wp_pin))
--			gpio_free(host->wp_pin);
-+#ifdef CONFIG_MMC_ATMELMCI_DMA
-+	if (host->dma.client.slave)
-+		dma_async_client_unregister(&host->dma.client);
-+#endif
- 
--		free_irq(platform_get_irq(pdev, 0), host->mmc);
--		iounmap(host->regs);
-+	free_irq(platform_get_irq(pdev, 0), host);
-+	iounmap(host->regs);
- 
--		clk_put(host->mck);
-+	clk_put(host->mck);
-+	kfree(host);
- 
--		mmc_free_host(host->mmc);
--	}
- 	return 0;
- }
- 
-diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
-index 9e7a236..6033e74 100644
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -178,10 +178,18 @@ static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
- 	if (atmel_pri.Features & 0x02)
- 		extp->EraseSuspend = 2;
- 
--	if (atmel_pri.BottomBoot)
--		extp->TopBottom = 2;
--	else
--		extp->TopBottom = 3;
-+	/* Some chips got it backwards... */
-+	if (cfi->id == AT49BV6416) {
-+		if (atmel_pri.BottomBoot)
-+			extp->TopBottom = 3;
-+		else
-+			extp->TopBottom = 2;
-+	} else {
-+		if (atmel_pri.BottomBoot)
-+			extp->TopBottom = 2;
-+		else
-+			extp->TopBottom = 3;
-+	}
- 
- 	/* burst write mode not supported */
- 	cfi->cfiq->BufWriteTimeoutTyp = 0;
-diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
-index 3387e0d..4af80c0 100644
---- a/drivers/mtd/nand/atmel_nand.c
-+++ b/drivers/mtd/nand/atmel_nand.c
-@@ -500,7 +500,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
- 	platform_set_drvdata(pdev, host);
- 	atmel_nand_enable(host);
- 
--	if (host->board->det_pin) {
-+	if (gpio_is_valid(host->board->det_pin)) {
- 		if (gpio_get_value(host->board->det_pin)) {
- 			printk("No SmartMedia card inserted.\n");
- 			res = ENXIO;
-diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
-index 9a9755c..13f4fb0 100644
---- a/drivers/rtc/Kconfig
-+++ b/drivers/rtc/Kconfig
-@@ -559,6 +559,22 @@ config RTC_DRV_AT91SAM9_GPBR
- 	  will be used.  The default of zero is normally OK to use, but
- 	  on some systems other software needs to use that register.
- 
-+config RTC_DRV_AVR32_AST
-+	tristate "AVR32 Asynchronous Timer"
-+	depends on AVR32
-+	help
-+	  RTC driver for the AVR32 Asynchronous Timers. The AST is a
-+	  simple and flexible timer that can be used both as a
-+	  high-resolution system timer and an RTC, depending on what
-+	  clock source it is running from.
-+
-+	  If you say yes here, and add one or more platform_device
-+	  called "rtc-ast", those devices will be clocked from a
-+	  32.768 kHz crystal oscillator and used as RTCs.
-+
-+	  This driver can also be built as a module. If so, the module
-+	  will be called rtc-ast.
-+
- config RTC_DRV_BFIN
- 	tristate "Blackfin On-Chip RTC"
- 	depends on BLACKFIN && !BF561
-diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
-index 18622ef..5ad1266 100644
---- a/drivers/rtc/Makefile
-+++ b/drivers/rtc/Makefile
-@@ -20,6 +20,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o
- obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o
- obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o
- obj-$(CONFIG_RTC_DRV_AT91SAM9)	+= rtc-at91sam9.o
-+obj-$(CONFIG_RTC_DRV_AVR32_AST)	+= rtc-ast.o
- obj-$(CONFIG_RTC_DRV_BFIN)	+= rtc-bfin.o
- obj-$(CONFIG_RTC_DRV_CMOS)	+= rtc-cmos.o
- obj-$(CONFIG_RTC_DRV_DS1216)	+= rtc-ds1216.o
-diff --git a/drivers/rtc/rtc-ast.c b/drivers/rtc/rtc-ast.c
-new file mode 100644
-index 0000000..be7db91
---- /dev/null
-+++ b/drivers/rtc/rtc-ast.c
-@@ -0,0 +1,546 @@
-+/*
-+ * An RTC driver for the AVR32 Asynchronous Timer
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/rtc.h>
-+
-+#include <asm/ast_regs.h>
-+
-+/*
-+ * The AST - ASynchronous Timer - is built around a simple cycle
-+ * counter that can be driven from one of four selectable clocks with
-+ * a selectable power-of-two prescaler. It also has two alarms (ALARM0
-+ * and ALARM1) and two periodic event generators (PER0 and PER1). The
-+ * latter can be driven by different tappings of the same prescaler
-+ * that drives the counter.
-+ *
-+ * This driver uses the 32.768 kHz crystal oscillator as a clock
-+ * source and a prescaler that gives a 1 Hz counter frequency. It uses
-+ * ALARM0 to support both "old-school" and "wake" alarms, PER0 to
-+ * support periodic interrupts (PIE) up to 16.384 kHz (at power-of-two
-+ * intervals), and PER1 to support a 1 Hz update interrupt (UIE).
-+ *
-+ * Watchdog interrupts seem to be undocumented and unsupported by
-+ * everyone else, so those are not supported for now.
-+ *
-+ * The AST can wake the system from any sleep mode given that the
-+ * source clock is running. On AT32AP720x, the 32.768 kHz crystal
-+ * oscillator runs in all sleep modes except "static" and "shutdown".
-+ */
-+
-+/* 32768 Hz means up to 60 us for synchronization + a bit of slack */
-+#define AST_SYNC_TIMEOUT_US	100
-+
-+#define AST_CLK_RATE		32768
-+#define AST_1S_PRESCALER	14	/* log2(32768) - 1 */
-+
-+struct rtc_ast {
-+	/* Protects I/O registers */
-+	spinlock_t		lock;
-+
-+	struct rtc_device	*rtc;
-+	void __iomem		*regs;
-+	struct clk		*osc32;
-+	struct clk		*pclk;
-+};
-+
-+/*
-+ * Because the AST is, well, asynchronous, we must make sure we don't
-+ * write to certain registers while the previous write is being
-+ * synchronized between clock domains. This affects writes to CR, CV,
-+ * SCR, WER, PIRx and ARx. To keep the delays minimal, we always
-+ * synchronize _before_ writes to these registers.
-+ *
-+ * This function is also used to synchronize when changing the clock
-+ * source, using a different bit in the status register.
-+ */
-+static int ast_wait_ready(void __iomem *regs, unsigned int busy_mask)
-+{
-+	unsigned long	timeout = AST_SYNC_TIMEOUT_US;
-+
-+	while (ast_readl(regs, SR) & busy_mask) {
-+		udelay(1);
-+		if (--timeout == 0)
-+			return -ETIMEDOUT;
-+		cpu_relax();
-+	}
-+
-+	return 0;
-+}
-+
-+static void rtc_ast_release(struct device *dev)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	/* Disable all interrupts */
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	clk_disable(ast->pclk);
-+}
-+
-+static int rtc_ast_ioctl(struct device *dev, unsigned int cmd,
-+		unsigned long arg)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	switch (cmd) {
-+		/* REVISIT: Should perhaps verify that irq_task is NULL */
-+	case RTC_AIE_ON:
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+		break;
-+	case RTC_AIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(ALARM0));
-+		break;
-+	case RTC_UIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER1));
-+			ast_writel(ast->regs, IER, AST_BIT(PER1));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+
-+		break;
-+	case RTC_UIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#if 0
-+	case RTC_PIE_ON:
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			break;
-+		ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+		spin_unlock_irq(&ast->lock);
-+
-+		ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		break;
-+	case RTC_PIE_OFF:
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+		break;
-+#endif
-+	default:
-+		ret = -ENOIOCTLCMD;
-+		break;
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_time(struct device *dev, struct rtc_time *tm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+	rtc_time_to_tm(ast_readl(ast->regs, CV), tm);
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_mmss(struct device *dev, unsigned long secs)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (!ret)
-+		ast_writel(ast->regs, CV, secs);
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_set_time(struct device *dev, struct rtc_time *tm)
-+{
-+	unsigned long	secs;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(tm, &secs);
-+	if (!ret)
-+		ret = rtc_ast_set_mmss(dev, secs);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	rtc_time_to_tm(ast_readl(ast->regs, AR0), &alrm->time);
-+	alrm->enabled = !!(ast_readl(ast->regs, IMR) & AST_BIT(ALARM0));
-+	alrm->pending = !!(ast_readl(ast->regs, SR) & AST_BIT(ALARM0));
-+	spin_unlock_irq(&ast->lock);
-+
-+	clk_disable(ast->pclk);
-+
-+	return 0;
-+}
-+
-+static int rtc_ast_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned long	seconds;
-+	int		ret;
-+
-+	ret = rtc_tm_to_time(&alrm->time, &seconds);
-+	if (ret)
-+		return ret;
-+
-+	clk_enable(ast->pclk);
-+
-+	/*
-+	 * REVISIT: The alarm may trigger before we are done here.
-+	 * Who's responsible for handling that?
-+	 *
-+	 * We don't want to clear the ALARM0 flag before we update AR0
-+	 * because the previous value of AR0 might trigger an alarm
-+	 * right after we clear the flag.
-+	 */
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+	ast_writel(ast->regs, AR0, seconds);
-+
-+	/* Try to avoid synchronization penalty */
-+	if (ast_readl(ast->regs, SR) & AST_BIT(ALARM0)) {
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (ret)
-+			goto unlock;
-+		ast_writel(ast->regs, SCR, AST_BIT(ALARM0));
-+	}
-+
-+	if (alrm->enabled)
-+		ast_writel(ast->regs, IER, AST_BIT(ALARM0));
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_proc(struct device *dev, struct seq_file *seq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	u32		imr;
-+
-+	clk_enable(ast->pclk);
-+	imr = ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	return seq_printf(seq,
-+			"periodic_IRQ\t: %s\n"
-+			"update_IRQ\t: %s\n"
-+			"periodic_freq\t: %d\n",
-+			(imr & AST_BIT(PER0)) ? "yes" : "no",
-+			(imr & AST_BIT(PER1)) ? "yes" : "no",
-+			ast->rtc->irq_freq);
-+}
-+
-+static int rtc_ast_irq_set_freq(struct device *dev, int freq)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	unsigned int	pres_bit;
-+	int		ret;
-+
-+	/* RTC core currently ensures this. */
-+	BUG_ON(!freq);
-+
-+	pres_bit = __ffs(freq);
-+	if (pres_bit > AST_1S_PRESCALER)
-+		return -EINVAL;
-+	pres_bit = AST_1S_PRESCALER - pres_bit;
-+
-+	clk_enable(ast->pclk);
-+
-+	spin_lock_irq(&ast->lock);
-+	ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	if (ret)
-+		goto unlock;
-+
-+	ast_writel(ast->regs, PIR0, pres_bit);
-+
-+unlock:
-+	spin_unlock_irq(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static int rtc_ast_irq_set_state(struct device *dev, int enabled)
-+{
-+	struct rtc_ast	*ast = dev_get_drvdata(dev);
-+	int		ret = 0;
-+
-+	clk_enable(ast->pclk);
-+
-+	if (enabled) {
-+		spin_lock_irq(&ast->lock);
-+		ret = ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		if (!ret) {
-+			ast_writel(ast->regs, SCR, AST_BIT(PER0));
-+			ast_writel(ast->regs, IER, AST_BIT(PER0));
-+		}
-+		spin_unlock_irq(&ast->lock);
-+	} else {
-+		ast_writel(ast->regs, IDR, AST_BIT(PER1));
-+	}
-+
-+	clk_disable(ast->pclk);
-+
-+	return ret;
-+}
-+
-+static const struct rtc_class_ops rtc_ast_ops = {
-+	.release	= rtc_ast_release,
-+	.ioctl		= rtc_ast_ioctl,
-+	.read_time	= rtc_ast_read_time,
-+	.set_time	= rtc_ast_set_time,
-+	.read_alarm	= rtc_ast_read_alarm,
-+	.set_alarm	= rtc_ast_set_alarm,
-+	.proc		= rtc_ast_proc,
-+	.set_mmss	= rtc_ast_set_mmss,
-+	.irq_set_freq	= rtc_ast_irq_set_freq,
-+	.irq_set_state	= rtc_ast_irq_set_state,
-+};
-+
-+static irqreturn_t rtc_ast_interrupt(int irq, void *dev_id)
-+{
-+	struct rtc_ast	*ast = dev_id;
-+	unsigned long	events;
-+	unsigned long	num;
-+	u32		status;
-+	u32		pending;
-+	irqreturn_t	ret = IRQ_NONE;
-+
-+	clk_enable(ast->pclk);
-+	spin_lock(&ast->lock);
-+
-+	status = ast_readl(ast->regs, SR);
-+	pending = status & ast_readl(ast->regs, IMR);
-+	if (unlikely(!pending))
-+		goto out;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, SCR, pending);
-+
-+	events = RTC_IRQF;
-+	num = 0;
-+	if (pending & AST_BIT(ALARM0)) {
-+		num++;
-+		events |= RTC_AF;
-+	}
-+	if (pending & AST_BIT(PER0)) {
-+		num++;
-+		events |= RTC_PF;
-+	}
-+	if (pending & AST_BIT(PER1)) {
-+		num++;
-+		events |= RTC_UF;
-+	}
-+
-+	rtc_update_irq(ast->rtc, num, events);
-+	ret = IRQ_HANDLED;
-+
-+out:
-+	spin_unlock(&ast->lock);
-+	clk_disable(ast->pclk);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init rtc_ast_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	struct rtc_ast	*ast;
-+	int		irq;
-+	int		ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no irq\n");
-+		return -ENXIO;
-+	}
-+
-+	ast = kzalloc(sizeof(struct rtc_ast), GFP_KERNEL);
-+	if (!ast) {
-+		dev_dbg(&pdev->dev, "out of memory\n");
-+		return -ENOMEM;
-+	}
-+
-+	ast->osc32 = clk_get(NULL, "osc32k");
-+	if (IS_ERR(ast->osc32)) {
-+		ret = PTR_ERR(ast->osc32);
-+		dev_dbg(&pdev->dev, "no 32 kHz oscillator\n");
-+		goto err_osc32;
-+	}
-+
-+	ast->pclk = clk_get(&pdev->dev, "pclk");
-+	if (IS_ERR(ast->pclk)) {
-+		ret = PTR_ERR(ast->pclk);
-+		dev_dbg(&pdev->dev, "no peripheral clock\n");
-+		goto err_pclk;
-+	}
-+
-+	spin_lock_init(&ast->lock);
-+
-+	ast->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!ast->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		ret = -ENOMEM;
-+		goto err_ioremap;
-+	}
-+
-+	clk_enable(ast->osc32);
-+	clk_enable(ast->pclk);
-+
-+	/* Initialize the AST if it isn't running already */
-+	if (!(ast_readl(ast->regs, CR) & AST_BIT(CR_EN))) {
-+		ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		ast_writel(ast->regs, CLOCK,
-+				AST_BF(CLOCK_CSSEL, AST_CLOCK_OSC32)
-+				| AST_BIT(CLOCK_CEN));
-+		ret = ast_wait_ready(ast->regs, AST_BIT(CLK_BUSY));
-+		if (ret) {
-+			dev_dbg(&pdev->dev,
-+				"timed out selecting clock source\n");
-+			goto err_clksel;
-+		}
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CV, 0);
-+		ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+		ast_writel(ast->regs, CR, AST_BIT(CR_EN) | AST_BIT(CR_PCLR)
-+				| AST_BF(CR_PSEL, AST_1S_PRESCALER));
-+	}
-+
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, WER, 0);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR0, AST_1S_PRESCALER);
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	ast_writel(ast->regs, PIR1, AST_1S_PRESCALER);
-+
-+	ret = request_irq(irq, rtc_ast_interrupt, 0, "rtc-ast", ast);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
-+		goto err_request_irq;
-+	}
-+
-+	ast->rtc = rtc_device_register("rtc-ast", &pdev->dev,
-+			&rtc_ast_ops, THIS_MODULE);
-+	if (IS_ERR(ast->rtc)) {
-+		dev_dbg(&pdev->dev, "could not register rtc device\n");
-+		ret = PTR_ERR(ast->rtc);
-+		goto err_register;
-+	}
-+
-+	ast->rtc->max_user_freq = AST_CLK_RATE / 2;
-+	ast->rtc->irq_freq = 1;
-+
-+	ast_wait_ready(ast->regs, AST_BIT(BUSY));
-+	clk_disable(ast->pclk);
-+	platform_set_drvdata(pdev, ast);
-+	device_init_wakeup(&pdev->dev, 1);
-+
-+	dev_info(&pdev->dev, "AVR32 Asynchronous Timer at %08lx irq %d\n",
-+			(unsigned long)regs->start, irq);
-+
-+	return 0;
-+
-+err_register:
-+	free_irq(irq, ast);
-+err_request_irq:
-+err_clksel:
-+	clk_disable(ast->pclk);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+err_ioremap:
-+	clk_put(ast->pclk);
-+err_pclk:
-+	clk_put(ast->osc32);
-+err_osc32:
-+	kfree(ast);
-+	return ret;
-+}
-+
-+static int __exit rtc_ast_remove(struct platform_device *pdev)
-+{
-+	struct rtc_ast *ast = platform_get_drvdata(pdev);
-+
-+	device_init_wakeup(&pdev->dev, 0);
-+
-+	clk_enable(ast->pclk);
-+	ast_writel(ast->regs, IDR, ~0UL);
-+	ast_readl(ast->regs, IMR);
-+	clk_disable(ast->pclk);
-+
-+	free_irq(platform_get_irq(pdev, 0), ast);
-+	rtc_device_unregister(ast->rtc);
-+	clk_disable(ast->osc32);
-+	iounmap(ast->regs);
-+	clk_put(ast->pclk);
-+	clk_put(ast->osc32);
-+	kfree(ast);
-+
-+	platform_set_drvdata(pdev, NULL);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver rtc_ast_driver = {
-+	.remove		= __exit_p(rtc_ast_remove),
-+	.driver		= {
-+		.name	= "rtc-ast",
-+		.owner	= THIS_MODULE,
-+	},
-+};
-+
-+static int __init rtc_ast_init(void)
-+{
-+	return platform_driver_probe(&rtc_ast_driver, rtc_ast_probe);
-+}
-+module_init(rtc_ast_init);
-+
-+static void __exit rtc_ast_exit(void)
-+{
-+	platform_driver_unregister(&rtc_ast_driver);
-+}
-+module_exit(rtc_ast_exit);
-+
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-+MODULE_DESCRIPTION("AVR32 Asynchronous Timer RTC");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
-index b9d0efb..ebfb883 100644
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -53,9 +53,14 @@ if SPI_MASTER
- 
- comment "SPI Master Controller Drivers"
- 
-+config SPI_ATMEL_HAVE_PDC
-+	def_bool y
-+	depends on (ARCH_AT91 || CPU_AT32AP700X)
-+
- config SPI_ATMEL
- 	tristate "Atmel SPI Controller"
- 	depends on (ARCH_AT91 || AVR32)
-+	depends on SPI_ATMEL_HAVE_PDC || DMA_ENGINE
- 	help
- 	  This selects a driver for the Atmel SPI Controller, present on
- 	  many AT32 (AVR32) and AT91 (ARM) chips.
-diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
-index 02f9320..5afae71 100644
---- a/drivers/spi/atmel_spi.c
-+++ b/drivers/spi/atmel_spi.c
-@@ -1,306 +1,445 @@
- /*
-  * Driver for Atmel AT32 and AT91 SPI Controllers
-  *
-- * Copyright (C) 2006 Atmel Corporation
-+ * Copyright (C) 2006-2008 Atmel Corporation
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License version 2 as
-  * published by the Free Software Foundation.
-  */
- 
--#include <linux/kernel.h>
--#include <linux/init.h>
- #include <linux/clk.h>
--#include <linux/module.h>
--#include <linux/platform_device.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
- #include <linux/err.h>
-+#include <linux/gpio.h>
-+#include <linux/init.h>
- #include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/wait.h>
-+#include <linux/workqueue.h>
-+#include <linux/spi/atmel_spi.h>
- #include <linux/spi/spi.h>
- 
--#include <asm/io.h>
--#include <mach/board.h>
--#include <mach/gpio.h>
- #include <mach/cpu.h>
- 
- #include "atmel_spi.h"
- 
--/*
-- * The core SPI transfer engine just talks to a register bank to set up
-- * DMA transfers; transfer queue progress is driven by IRQs.  The clock
-- * framework provides the base clock, subdivided for each spi_device.
-- *
-- * Newer controllers, marked with "new_1" flag, have:
-- *  - CR.LASTXFER
-- *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-- *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-- *  - SPI_CSRx.CSAAT
-- *  - SPI_CSRx.SBCR allows faster clocking
-+#define BUFFER_SIZE		PAGE_SIZE
-+#define INVALID_DMA_ADDRESS	0xffffffff
-+#define MAX_SG_SEGS		8
-+
-+/**
-+ * struct atmel_spi - SPI master controller state
-+ * @lock: Spinlock protecting the @queue, @stay and @stopping fields
-+ *	as well as the hardware registers.
-+ * @regs: Base address of the hardware registers.
-+ * @wait: Waitqueue used to wait for DMA completion or errors.
-+ * @pending: Number of DMA transfers currently pending.
-+ * @pending_bytes: Number of bytes submitted for DMA but not yet
-+ *	accounted for.
-+ * @error: Data transfer error detected by interrupt handler. When this
-+ *	is set to a nonzero value, the DMA engine is stopped, @pending
-+ *	is set to 0 and @wait is triggered.
-+ * @buffer: Scratch buffer for use when the upper layers didn't provide
-+ *	a TX or RX buffer.
-+ * @buffer_dma: DMA address of @buffer.
-+ * @buffer_size: Length of @buffer in bytes.
-+ * @queue: SPI messages queued for transfer.
-+ * @workqueue: Per-controller workqueue.
-+ * @work: Queue processing work struct.
-+ * @stay: If the last SPI message caused the SPI device to stay active,
-+ *	this points to the SPI device associated with that message. NULL
-+ *	otherwise.
-+ * @clk: Bus clock connected to the controller.
-+ * @base_hz: Base clock rate in Hz used for baud rate calculations.
-+ * @stopping: Queue is being stopped. No new messages are started.
-+ * @always_bounce: Always do transfers to/from bounce buffer.
-+ * @pdev: Platform device associated with the controller.
-  */
- struct atmel_spi {
- 	spinlock_t		lock;
--
- 	void __iomem		*regs;
--	int			irq;
--	struct clk		*clk;
--	struct platform_device	*pdev;
--	unsigned		new_1:1;
--	struct spi_device	*stay;
- 
--	u8			stopping;
--	struct list_head	queue;
--	struct spi_transfer	*current_transfer;
--	unsigned long		current_remaining_bytes;
--	struct spi_transfer	*next_transfer;
--	unsigned long		next_remaining_bytes;
-+	wait_queue_head_t	wait;
-+	int			pending;
-+	size_t			pending_bytes;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct scatterlist	tx_sg[MAX_SG_SEGS];
-+	struct scatterlist	rx_sg[MAX_SG_SEGS];
-+	unsigned int		sg_len;
-+	struct dma_async_tx_descriptor *tx_desc;
-+	struct dma_async_tx_descriptor *rx_desc;
-+	struct dma_chan		*tx_chan;
-+	struct dma_chan		*rx_chan;
-+	struct dma_client	rx_client;
-+	struct dma_client	tx_client;
-+#endif
-+	int			error;
- 
- 	void			*buffer;
- 	dma_addr_t		buffer_dma;
-+	size_t			buffer_size;
-+
-+	struct list_head	queue;
-+	struct workqueue_struct	*workqueue;
-+	struct work_struct	work;
-+	struct spi_device	*stay;
-+	struct clk		*clk;
-+	unsigned long		base_hz;
-+	bool			stopping;
-+	bool			always_bounce;
-+
-+	struct platform_device	*pdev;
-+#ifdef CONFIG_DEBUG_FS
-+	struct dentry		*debugfs_root;
-+#endif
- };
- 
--#define BUFFER_SIZE		PAGE_SIZE
--#define INVALID_DMA_ADDRESS	0xffffffff
-+/**
-+ * struct atmel_spi_device - Controller-specific per-slave state
-+ * @npcs_pin: GPIO pin ID hooked up to this SPI slave.
-+ * @csr: CSRn register value used when talking to this SPI slave.
-+ */
-+struct atmel_spi_device {
-+	unsigned int		npcs_pin;
-+	u32			csr;
-+};
- 
- /*
-- * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-- * they assume that spi slave device state will not change on deselect, so
-- * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-- * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-- * controllers have CSAAT and friends.
-- *
-- * Since the CSAAT functionality is a bit weird on newer controllers as
-- * well, we use GPIO to control nCSx pins on all controllers, updating
-- * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-- * support active-high chipselects despite the controller's belief that
-- * only active-low devices/systems exists.
-+ * Version 2 of the SPI controller has
-+ *  - CR.LASTXFER
-+ *  - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
-+ *  - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
-+ *  - SPI_CSRx.CSAAT
-+ *  - SPI_CSRx.SBCR allows faster clocking
-  *
-- * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-- * right when driven with GPIO.  ("Mode Fault does not allow more than one
-- * Master on Chip Select 0.")  No workaround exists for that ... so for
-- * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-- * and (c) will trigger that first erratum in some cases.
-+ * We can determine the controller version by reading the VERSION
-+ * register, but I haven't checked that it exists on all chips, and
-+ * this is cheaper anyway.
-  */
--
--static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
-+static bool atmel_spi_is_v2(void)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
--	int i;
--	u32 csr;
--	u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+	return !cpu_is_at91rm9200();
-+}
- 
--	/* Make sure clock polarity is correct */
--	for (i = 0; i < spi->master->num_chipselect; i++) {
--		csr = spi_readl(as, CSR0 + 4 * i);
--		if ((csr ^ cpol) & SPI_BIT(CPOL))
--			spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
--	}
-+static bool atmel_spi_xfer_is_last(struct spi_message *msg,
-+		struct spi_transfer *xfer)
-+{
-+	return &xfer->transfer_list == msg->transfers.prev;
-+}
- 
--	mr = spi_readl(as, MR);
--	mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+/*-------------------------------------------------------------------------*/
- 
--	dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
--			gpio, active ? " (high)" : "",
--			mr);
-+/*
-+ * GCC doesn't eliminate _all_ the dead code, only some of it. In
-+ * particular, the file operations appear to be difficult even if the
-+ * file operations struct itself gets eliminated.
-+ *
-+ * So let's do the CPP dance.
-+ */
-+#ifdef CONFIG_DEBUG_FS
- 
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, active);
--	spi_writel(as, MR, mr);
--}
-+#include <linux/debugfs.h>
-+#include <linux/seq_file.h>
- 
--static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
-+static int atmel_spi_queue_show(struct seq_file *s, void *v)
- {
--	unsigned gpio = (unsigned) spi->controller_data;
--	unsigned active = spi->mode & SPI_CS_HIGH;
--	u32 mr;
-+	struct atmel_spi	*as = s->private;
-+	struct spi_message	*msg;
-+	struct spi_transfer	*xfer;
- 
--	/* only deactivate *this* device; sometimes transfers to
--	 * another device may be active when this routine is called.
--	 */
--	mr = spi_readl(as, MR);
--	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
--		mr = SPI_BFINS(PCS, 0xf, mr);
--		spi_writel(as, MR, mr);
-+	spin_lock_irq(&as->lock);
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		seq_printf(s, "msg to %s:%s DMA mapped, status %d actual %u\n",
-+				msg->spi->dev.bus_id,
-+				msg->is_dma_mapped ? "" : " Not",
-+				msg->status, msg->actual_length);
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			seq_printf(s, "  t%p r%p l%u%s %u bits %u us %u Hz\n",
-+					xfer->tx_buf, xfer->rx_buf, xfer->len,
-+					xfer->cs_change ? "cs_change" : "",
-+					xfer->bits_per_word,
-+					xfer->delay_usecs,
-+					xfer->speed_hz);
-+		}
- 	}
-+	spin_unlock_irq(&as->lock);
- 
--	dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
--			gpio, active ? " (low)" : "",
--			mr);
--
--	if (!(cpu_is_at91rm9200() && spi->chip_select == 0))
--		gpio_set_value(gpio, !active);
-+	return 0;
- }
- 
--static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
--					struct spi_transfer *xfer)
-+static int atmel_spi_queue_open(struct inode *inode, struct file *file)
- {
--	return msg->transfers.prev == &xfer->transfer_list;
-+	return single_open(file, atmel_spi_queue_show, inode->i_private);
- }
- 
--static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
-+static const struct file_operations atmel_spi_queue_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_queue_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
-+
-+static void atmel_spi_show_status_reg(struct seq_file *s,
-+		const char *regname, u32 value)
- {
--	return xfer->delay_usecs == 0 && !xfer->cs_change;
-+	static const char	*sr_bit[] = {
-+		[0]	= "RDRF",
-+		[1]	= "TDRE",
-+		[2]	= "MODF",
-+		[3]	= "OVRES",
-+		[4]	= "ENDRX",
-+		[5]	= "ENDTX",
-+		[6]	= "RXBUFF",
-+		[7]	= "TXBUFE",
-+		[8]	= "NSSR",
-+		[9]	= "TXEMPTY",
-+		[16]	= "SPIENS",
-+	};
-+	unsigned int		i;
-+
-+	seq_printf(s, "%s:\t0x%08x", regname, value);
-+	for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
-+		if (value & (1 << i)) {
-+			if (sr_bit[i])
-+				seq_printf(s, " %s", sr_bit[i]);
-+			else
-+				seq_printf(s, " UNKNOWN(%u)", i);
-+		}
-+	}
-+	seq_putc(s, '\n');
- }
- 
--static void atmel_spi_next_xfer_data(struct spi_master *master,
--				struct spi_transfer *xfer,
--				dma_addr_t *tx_dma,
--				dma_addr_t *rx_dma,
--				u32 *plen)
-+static int atmel_spi_regs_show(struct seq_file *s, void *v)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	u32			len = *plen;
-+	struct atmel_spi	*as = s->private;
-+	unsigned int		i;
-+	u32			value;
-+	u32			*buf;
- 
--	/* use scratch buffer only when rx or tx data is unspecified */
--	if (xfer->rx_buf)
--		*rx_dma = xfer->rx_dma + xfer->len - len;
--	else {
--		*rx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--	}
--	if (xfer->tx_buf)
--		*tx_dma = xfer->tx_dma + xfer->len - len;
--	else {
--		*tx_dma = as->buffer_dma;
--		if (len > BUFFER_SIZE)
--			len = BUFFER_SIZE;
--		memset(as->buffer, 0, len);
--		dma_sync_single_for_device(&as->pdev->dev,
--				as->buffer_dma, len, DMA_TO_DEVICE);
--	}
-+	buf = kmalloc(0x200, GFP_KERNEL);
-+	if (!buf)
-+		return -ENOMEM;
- 
--	*plen = len;
--}
-+	/* Grab a more or less consistent snapshot */
-+	spin_lock_irq(&as->lock);
-+	memcpy_fromio(buf, as->regs, 0x200);
-+	spin_unlock_irq(&as->lock);
- 
--/*
-- * Submit next transfer for DMA.
-- * lock is held, spi irq is blocked
-- */
--static void atmel_spi_next_xfer(struct spi_master *master,
--				struct spi_message *msg)
--{
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_transfer	*xfer;
--	u32			len, remaining;
--	u32			ieval;
--	dma_addr_t		tx_dma, rx_dma;
--
--	if (!as->current_transfer)
--		xfer = list_entry(msg->transfers.next,
--				struct spi_transfer, transfer_list);
--	else if (!as->next_transfer)
--		xfer = list_entry(as->current_transfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--	else
--		xfer = NULL;
-+	value = buf[SPI_MR / 4];
-+	seq_printf(s, "MR:\t0x%08x%s%s%s%s%s%s PCS=%x DLYBCS=%u\n",
-+			value,
-+			(value & SPI_BIT(MSTR)) ? " MSTR" : "",
-+			(value & SPI_BIT(PS)) ? " PS" : "",
-+			(value & SPI_BIT(PCSDEC)) ? " PCSDEC" : "",
-+			(value & SPI_BIT(FDIV)) ? " FDIV" : "",
-+			(value & SPI_BIT(MODFDIS)) ? " MODFDIS" : "",
-+			(value & SPI_BIT(LLB)) ? " LLB" : "",
-+			SPI_BFEXT(PCS, value),
-+			SPI_BFEXT(DLYBCS, value));
-+
-+	atmel_spi_show_status_reg(s, "SR", buf[SPI_SR / 4]);
-+	atmel_spi_show_status_reg(s, "IMR", buf[SPI_IMR / 4]);
-+
-+	for (i = 0; i < 4; i++) {
-+		value = buf[SPI_CSR0 / 4 + i];
-+		seq_printf(s, "CSR%u:\t0x%08x%s%s%s\n",
-+				i, value,
-+				(value & SPI_BIT(CPOL)) ? " CPOL" : "",
-+				(value & SPI_BIT(NCPHA)) ? " NCPHA" : "",
-+				(value & SPI_BIT(CSAAT)) ? " CSAAT" : "");
-+		seq_printf(s, "\t\tBITS=%u SCBR=%u DLYBS=%u DLYBCT=%u\n",
-+				SPI_BFEXT(BITS, value) + 8,
-+				SPI_BFEXT(SCBR, value),
-+				SPI_BFEXT(DLYBS, value),
-+				SPI_BFEXT(DLYBCT, value));
-+	}
- 
--	if (xfer) {
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+	seq_printf(s, "RPR:\t0x%08x\n", buf[SPI_RPR / 4]);
-+	seq_printf(s, "RCR:\t0x%08x\n", buf[SPI_RCR / 4]);
-+	seq_printf(s, "TPR:\t0x%08x\n", buf[SPI_TPR / 4]);
-+	seq_printf(s, "TCR:\t0x%08x\n", buf[SPI_TCR / 4]);
-+	seq_printf(s, "RNPR:\t0x%08x\n", buf[SPI_RNPR / 4]);
-+	seq_printf(s, "RNCR:\t0x%08x\n", buf[SPI_RNCR / 4]);
-+	seq_printf(s, "TNPR:\t0x%08x\n", buf[SPI_TNPR / 4]);
-+	seq_printf(s, "TNCR:\t0x%08x\n", buf[SPI_TNCR / 4]);
- 
--		len = xfer->len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		remaining = xfer->len - len;
-+	value = buf[SPI_PTSR / 4];
-+	seq_printf(s, "PTSR:\t0x%08x%s%s\n", value,
-+			(value & SPI_BIT(RXTEN)) ? " RXTEN" : "",
-+			(value & SPI_BIT(TXTEN)) ? " TXTEN" : "");
- 
--		spi_writel(as, RPR, rx_dma);
--		spi_writel(as, TPR, tx_dma);
-+	kfree(buf);
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RCR, len);
--		spi_writel(as, TCR, len);
-+	return 0;
-+}
- 
--		dev_dbg(&msg->spi->dev,
--			"  start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	} else {
--		xfer = as->next_transfer;
--		remaining = as->next_remaining_bytes;
--	}
-+static int atmel_spi_regs_open(struct inode *inode, struct file *file)
-+{
-+	return single_open(file, atmel_spi_regs_show, inode->i_private);
-+}
- 
--	as->current_transfer = xfer;
--	as->current_remaining_bytes = remaining;
-+static const struct file_operations atmel_spi_regs_fops = {
-+	.owner		= THIS_MODULE,
-+	.open		= atmel_spi_regs_open,
-+	.read		= seq_read,
-+	.llseek		= seq_lseek,
-+	.release	= single_release,
-+};
- 
--	if (remaining > 0)
--		len = remaining;
--	else if (!atmel_spi_xfer_is_last(msg, xfer)
--			&& atmel_spi_xfer_can_be_chained(xfer)) {
--		xfer = list_entry(xfer->transfer_list.next,
--				struct spi_transfer, transfer_list);
--		len = xfer->len;
--	} else
--		xfer = NULL;
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
-+	struct dentry	*root;
-+	struct dentry	*node;
- 
--	as->next_transfer = xfer;
-+	root = debugfs_create_dir(as->pdev->dev.bus_id, NULL);
-+	if (IS_ERR(root))
-+		/* Debugfs not enabled */
-+		return;
-+	if (!root)
-+		/* Debugfs enabled, but failed to create directory */
-+		goto err_root;
-+
-+	node = debugfs_create_file("regs", S_IRUSR, root, as,
-+			&atmel_spi_regs_fops);
-+	if (!node)
-+		goto err;
-+	node = debugfs_create_file("queue", S_IRUSR, root, as,
-+			&atmel_spi_queue_fops);
-+	if (!node)
-+		goto err;
-+
-+	as->debugfs_root = root;
-+	return;
-+
-+err:
-+	debugfs_remove_recursive(root);
-+err_root:
-+	dev_err(&as->pdev->dev, "failed to initialize debugfs\n");
-+}
- 
--	if (xfer) {
--		u32	total;
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
-+	debugfs_remove_recursive(as->debugfs_root);
-+}
- 
--		total = len;
--		atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
--		as->next_remaining_bytes = total - len;
-+#else
-+static void atmel_spi_init_debugfs(struct atmel_spi *as)
-+{
- 
--		spi_writel(as, RNPR, rx_dma);
--		spi_writel(as, TNPR, tx_dma);
-+}
-+static void atmel_spi_cleanup_debugfs(struct atmel_spi *as)
-+{
- 
--		if (msg->spi->bits_per_word > 8)
--			len >>= 1;
--		spi_writel(as, RNCR, len);
--		spi_writel(as, TNCR, len);
-+}
-+#endif
- 
--		dev_dbg(&msg->spi->dev,
--			"  next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--		ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
--	} else {
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
--	}
-+/*
-+ * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
-+ * they assume that spi slave device state will not change on deselect, so
-+ * that automagic deselection is OK.  ("NPCSx rises if no data is to be
-+ * transmitted")  Not so!  Workaround uses nCSx pins as GPIOs; or newer
-+ * controllers have CSAAT and friends.
-+ *
-+ * Since the CSAAT functionality is a bit weird on newer controllers as
-+ * well, we use GPIO to control nCSx pins on all controllers, updating
-+ * MR.PCS to avoid confusing the controller.  Using GPIOs also lets us
-+ * support active-high chipselects despite the controller's belief that
-+ * only active-low devices/systems exists.
-+ *
-+ * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
-+ * right when driven with GPIO.  ("Mode Fault does not allow more than one
-+ * Master on Chip Select 0.")  No workaround exists for that ... so for
-+ * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
-+ * and (c) will trigger that first erratum in some cases.
-+ *
-+ * TODO: Test if the atmel_spi_is_v2() branch below works on
-+ * AT91RM9200 if we use some other register than CSR0. However, don't
-+ * do this unconditionally since AP7000 has an errata where the BITS
-+ * field in CSR0 overrides all other CSRs.
-+ */
- 
--	/* REVISIT: We're waiting for ENDRX before we start the next
--	 * transfer because we need to handle some difficult timing
--	 * issues otherwise. If we wait for ENDTX in one transfer and
--	 * then starts waiting for ENDRX in the next, it's difficult
--	 * to tell the difference between the ENDRX interrupt we're
--	 * actually waiting for and the ENDRX interrupt of the
--	 * previous transfer.
--	 *
--	 * It should be doable, though. Just not now...
--	 */
--	spi_writel(as, IER, ieval);
--	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
-+static void atmel_spi_set_csr(struct atmel_spi *as,
-+		struct spi_device *spi, u32 csr)
-+{
-+	if (atmel_spi_is_v2())
-+		spi_writel(as, CSR0, csr);
-+	else
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
- }
- 
--static void atmel_spi_next_message(struct spi_master *master)
-+static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
- {
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_device	*spi;
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
-+
-+	if (atmel_spi_is_v2()) {
-+		/*
-+		 * Always use CSR0. This ensures that the clock
-+		 * switches to the correct idle polarity before we
-+		 * toggle the CS.
-+		 */
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
-+				| SPI_BIT(MSTR));
-+		spi_readl(as, MR);
-+		dev_vdbg(&spi->dev, "activate %u%s, csr0: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				asd->csr);
-+
-+		gpio_set_value(asd->npcs_pin, active);
-+	} else {
-+		u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+		int i;
-+		u32 mr;
-+		u32 csr;
-+
-+		/* Make sure clock polarity is correct */
-+		for (i = 0; i < spi->master->num_chipselect; i++) {
-+			csr = spi_readl(as, CSR0 + 4 * i);
-+			if ((csr ^ cpol) & SPI_BIT(CPOL))
-+				spi_writel(as, CSR0 + 4 * i,
-+						csr ^ SPI_BIT(CPOL));
-+		}
- 
--	BUG_ON(as->current_transfer);
-+		mr = spi_readl(as, MR);
-+		mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
-+		dev_vdbg(&spi->dev, "activate %u%s, mr: %08x csr: %08x\n",
-+				asd->npcs_pin, active ? " (low)" : "",
-+				mr, csr);
-+		if (spi->chip_select != 0)
-+			gpio_set_value(asd->npcs_pin, active);
-+		spi_writel(as, MR, mr);
-+	}
-+}
- 
--	msg = list_entry(as->queue.next, struct spi_message, queue);
--	spi = msg->spi;
-+static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
-+{
-+	struct atmel_spi_device *asd = spi->controller_state;
-+	unsigned active = spi->mode & SPI_CS_HIGH;
-+	u32 mr;
- 
--	dev_dbg(master->dev.parent, "start message %p for %s\n",
--			msg, spi->dev.bus_id);
-+	/* only deactivate *this* device; sometimes transfers to
-+	 * another device may be active when this routine is called.
-+	 */
-+	mr = spi_readl(as, MR);
-+	if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
-+		mr = SPI_BFINS(PCS, 0xf, mr);
-+		spi_writel(as, MR, mr);
-+	}
- 
--	/* select chip if it's not still active */
--	if (as->stay) {
--		if (as->stay != spi) {
--			cs_deactivate(as, as->stay);
--			cs_activate(as, spi);
--		}
--		as->stay = NULL;
--	} else
--		cs_activate(as, spi);
-+	dev_vdbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
-+			asd->npcs_pin, active ? " (low)" : "",
-+			mr);
- 
--	atmel_spi_next_xfer(master, msg);
-+	if (atmel_spi_is_v2() || spi->chip_select != 0)
-+		gpio_set_value(asd->npcs_pin, !active);
- }
- 
- /*
-@@ -338,162 +477,460 @@ atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
- 	return 0;
- }
- 
--static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
-+static void atmel_spi_dma_unmap_xfer(struct atmel_spi *as,
- 				     struct spi_transfer *xfer)
- {
- 	if (xfer->tx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->tx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->tx_dma,
- 				 xfer->len, DMA_TO_DEVICE);
- 	if (xfer->rx_dma != INVALID_DMA_ADDRESS)
--		dma_unmap_single(master->dev.parent, xfer->rx_dma,
-+		dma_unmap_single(&as->pdev->dev, xfer->rx_dma,
- 				 xfer->len, DMA_FROM_DEVICE);
- }
- 
--static void
--atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
--		struct spi_message *msg, int status, int stay)
-+static void atmel_spi_dma_unmap_msg(struct atmel_spi *as, struct spi_message *msg)
- {
--	if (!stay || status < 0)
--		cs_deactivate(as, msg->spi);
--	else
--		as->stay = msg->spi;
--
--	list_del(&msg->queue);
--	msg->status = status;
--
--	dev_dbg(master->dev.parent,
--		"xfer complete: %u bytes transferred\n",
--		msg->actual_length);
-+	struct spi_transfer	*xfer;
- 
--	spin_unlock(&as->lock);
--	msg->complete(msg->context);
--	spin_lock(&as->lock);
-+	if (!msg->is_dma_mapped)
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list)
-+			atmel_spi_dma_unmap_xfer(as, xfer);
-+}
- 
--	as->current_transfer = NULL;
--	as->next_transfer = NULL;
-+static void atmel_spi_handle_error(struct atmel_spi *as,
-+		struct spi_message *msg, int err)
-+{
-+	unsigned int timeout;
-+
-+	/* Drain the buffers so that the hardware is ready for a new message */
-+	for (timeout = 1000; timeout; timeout--)
-+		if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
-+			break;
-+	if (!timeout)
-+		dev_warn(&msg->spi->dev,
-+			 "timeout waiting for TXEMPTY");
-+	while (spi_readl(as, SR) & SPI_BIT(RDRF))
-+		spi_readl(as, RDR);
-+
-+	/* Clear any overrun happening while cleaning up */
-+	spi_readl(as, SR);
- 
--	/* continue if needed */
--	if (list_empty(&as->queue) || as->stopping)
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--	else
--		atmel_spi_next_message(master);
-+	msg->status = err;
-+	as->error = 0;
- }
- 
--static irqreturn_t
--atmel_spi_interrupt(int irq, void *dev_id)
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
- {
--	struct spi_master	*master = dev_id;
--	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
--	struct spi_transfer	*xfer;
--	u32			status, pending, imr;
--	int			ret = IRQ_NONE;
-+	int err;
- 
--	spin_lock(&as->lock);
-+	wait_event(as->wait, as->pending == 0);
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev,
-+				"transfer error %d (%u/%u remaining)\n",
-+				err, spi_readl(as, TCR), spi_readl(as, RCR));
-+
-+		spi_writel(as, TNCR, 0);
-+		spi_writel(as, RNCR, 0);
-+		spi_writel(as, TCR, 0);
-+		spi_writel(as, RCR, 0);
- 
--	xfer = as->current_transfer;
--	msg = list_entry(as->queue.next, struct spi_message, queue);
-+		atmel_spi_handle_error(as, msg, err);
- 
--	imr = spi_readl(as, IMR);
--	status = spi_readl(as, SR);
--	pending = status & imr;
-+		return err;
-+	}
- 
--	if (pending & SPI_BIT(OVRES)) {
--		int timeout;
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
-+
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	dma_addr_t	rx_dma;
-+	dma_addr_t	tx_dma;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
- 
--		ret = IRQ_HANDLED;
-+	if (!bits)
-+		bits = spi->bits_per_word;
- 
--		spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
--				     | SPI_BIT(OVRES)));
-+	/* PDC stuff starts here */
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		wait_event(as->wait, as->pending < 2);
- 
- 		/*
--		 * When we get an overrun, we disregard the current
--		 * transfer. Data will not be copied back from any
--		 * bounce buffer and msg->actual_len will not be
--		 * updated with the last xfer.
--		 *
--		 * We will also not process any remaning transfers in
--		 * the message.
--		 *
--		 * First, stop the transfer and unmap the DMA buffers.
-+		 * This gives the RX side a slight advantage, making
-+		 * overruns less likely.
- 		 */
--		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
--		if (!msg->is_dma_mapped)
--			atmel_spi_dma_unmap_xfer(master, xfer);
-+		spi_writel(as, PTCR, SPI_BIT(TXTDIS));
-+
-+		len = xfer->len - submitted;
-+		if (xfer->rx_buf) {
-+			rx_dma = xfer->rx_dma + submitted;
-+		} else {
-+			rx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+		}
-+		if (xfer->tx_buf) {
-+			tx_dma = xfer->tx_dma + submitted;
-+		} else {
-+			tx_dma = as->buffer_dma;
-+			len = min(len, BUFFER_SIZE);
-+			memset(as->buffer, 0, len);
-+		}
-+
-+		submitted += len;
-+		if (bits > 8)
-+			len >>= 1;
-+
-+		spin_lock_irq(&as->lock);
-+		if (as->error) {
-+			spin_unlock_irq(&as->lock);
-+			atmel_spi_wait_idle(as, msg);
-+			return 0;
-+		}
-+
-+		spi_writel(as, RNPR, rx_dma);
-+		spi_writel(as, RNCR, len);
-+		spi_writel(as, TNPR, tx_dma);
-+		spi_writel(as, TNCR, len);
-+		spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
-+				| SPI_BIT(OVRES));
-+		spi_writel(as, PTCR, SPI_BIT(RXTEN) | SPI_BIT(TXTEN));
-+		as->pending++;
-+		spin_unlock_irq(&as->lock);
-+	}
-+
-+	as->pending_bytes += submitted;
- 
--		/* REVISIT: udelay in irq is unfriendly */
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
- 		if (xfer->delay_usecs)
- 			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
- 
--		dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
--			 spi_readl(as, TCR), spi_readl(as, RCR));
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
- 
--		/*
--		 * Clean up DMA registers and make sure the data
--		 * registers are empty.
--		 */
--		spi_writel(as, RNCR, 0);
--		spi_writel(as, TNCR, 0);
--		spi_writel(as, RCR, 0);
--		spi_writel(as, TCR, 0);
--		for (timeout = 1000; timeout; timeout--)
--			if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
--				break;
--		if (!timeout)
--			dev_warn(master->dev.parent,
--				 "timeout waiting for TXEMPTY");
--		while (spi_readl(as, SR) & SPI_BIT(RDRF))
--			spi_readl(as, RDR);
-+	return xfer->cs_change;
-+}
- 
--		/* Clear any overrun happening while cleaning up */
--		spi_readl(as, SR);
-+#else /* Use DMA engine framework, not PDC */
- 
--		atmel_spi_msg_done(master, as, msg, -EIO, 0);
--	} else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
--		ret = IRQ_HANDLED;
-+static void atmel_spi_dma_complete(void *param)
-+{
-+	struct atmel_spi	*as = param;
- 
--		spi_writel(as, IDR, pending);
-+	as->pending = 0;
-+	as->sg_len = 0;
-+	wake_up(&as->wait);
-+}
- 
--		if (as->current_remaining_bytes == 0) {
--			msg->actual_length += xfer->len;
--
--			if (!msg->is_dma_mapped)
--				atmel_spi_dma_unmap_xfer(master, xfer);
--
--			/* REVISIT: udelay in irq is unfriendly */
--			if (xfer->delay_usecs)
--				udelay(xfer->delay_usecs);
--
--			if (atmel_spi_xfer_is_last(msg, xfer)) {
--				/* report completed message */
--				atmel_spi_msg_done(master, as, msg, 0,
--						xfer->cs_change);
--			} else {
--				if (xfer->cs_change) {
--					cs_deactivate(as, msg->spi);
--					udelay(1);
--					cs_activate(as, msg->spi);
--				}
-+static int atmel_spi_wait_idle(struct atmel_spi *as, struct spi_message *msg)
-+{
-+	struct dma_chan			*tx_chan = as->tx_chan;
-+	struct dma_chan			*rx_chan = as->rx_chan;
-+	struct dma_device		*dma = rx_chan->device;
-+	struct dma_async_tx_descriptor	*tx_desc;
-+	struct dma_async_tx_descriptor	*rx_desc;
-+	int				err;
-+
-+	dev_vdbg(&msg->spi->dev, "wait_idle: sg_len=%u\n", as->sg_len);
-+
-+	if (!as->sg_len)
-+		return 0;
-+
-+	sg_mark_end(as->tx_sg + (as->sg_len - 1));
-+	sg_mark_end(as->rx_sg + (as->sg_len - 1));
-+	as->pending = 1;
-+	smp_wmb();
-+
-+	tx_desc = dma->device_prep_slave_sg(tx_chan,
-+			as->tx_sg, as->sg_len, DMA_TO_DEVICE,
-+			DMA_COMPL_SKIP_SRC_UNMAP | DMA_CTRL_ACK);
-+	rx_desc = dma->device_prep_slave_sg(rx_chan,
-+			as->rx_sg, as->sg_len, DMA_FROM_DEVICE,
-+			DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP
-+			| DMA_CTRL_ACK);
-+	rx_desc->callback = atmel_spi_dma_complete;
-+	rx_desc->callback_param = as;
-+	rx_desc->tx_submit(rx_desc);
-+	tx_desc->tx_submit(tx_desc);
-+	dma->device_issue_pending(rx_chan);
-+	dma->device_issue_pending(tx_chan);
-+
-+	spi_writel(as, IER, SPI_BIT(OVRES));
-+	wait_event(as->wait, !as->pending);
-+	spi_writel(as, IDR, SPI_BIT(OVRES));
-+	err = as->error;
-+	if (err) {
-+		dev_warn(&msg->spi->dev, "transfer error %d\n", err);
-+
-+		dma->device_terminate_all(tx_chan);
-+		dma->device_terminate_all(rx_chan);
-+
-+		atmel_spi_handle_error(as, msg, err);
-+
-+		return err;
-+	}
-+
-+	msg->actual_length += as->pending_bytes;
-+	as->pending_bytes = 0;
-+	sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+	sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+
-+	dev_vdbg(&msg->spi->dev, "controller idle, xfered so far: %u\n",
-+			msg->actual_length);
-+
-+	return 0;
-+}
-+
-+static int atmel_spi_submit_xfer(struct atmel_spi *as, struct spi_device *spi,
-+		struct spi_message *msg, struct spi_transfer *xfer)
-+{
-+	unsigned int	bits = xfer->bits_per_word;
-+	unsigned int	speed_hz = xfer->speed_hz;
-+	unsigned int	submitted = 0;
-+	unsigned int	i;
-+
-+	dev_vdbg(&spi->dev, "submit_xfer len %u rx %p tx %p\n",
-+			xfer->len, xfer->rx_buf, xfer->tx_buf);
-+	dev_vdbg(&spi->dev, "  csc %u bpw %u delay %u speed %u\n",
-+			xfer->cs_change, xfer->bits_per_word,
-+			xfer->delay_usecs, xfer->speed_hz);
-+
-+	if (bits || speed_hz) {
-+		struct atmel_spi_device *asd;
-+		u32 csr;
-+
-+		if (atmel_spi_wait_idle(as, msg))
-+			return 0;
-+
-+		asd = spi->controller_state;
-+		csr = asd->csr;
-+
-+		if (bits)
-+			csr = SPI_BFINS(BITS, csr, bits - 8);
-+		if (speed_hz) {
-+			u32 scbr = DIV_ROUND_UP(as->base_hz, speed_hz);
-+			csr = SPI_BFINS(SCBR, csr, scbr);
-+		}
-+
-+		atmel_spi_set_csr(as, spi, csr);
-+	}
-+
-+	if (!bits)
-+		bits = spi->bits_per_word;
-+
-+	i = as->sg_len;
-+	while (submitted < xfer->len) {
-+		unsigned long len;
-+
-+		if (i == MAX_SG_SEGS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				return 0;
-+			i = 0;
-+		}
-+
-+		len = xfer->len - submitted;
-+		if (!xfer->rx_buf || !xfer->tx_buf)
-+			len = min(len, BUFFER_SIZE);
-+
-+		if (xfer->rx_buf) {
-+			sg_set_buf(&as->rx_sg[i], xfer->rx_buf + submitted, len);
-+			as->rx_sg[i].dma_address = xfer->rx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->rx_sg[i], as->buffer, len);
-+			as->rx_sg[i].dma_address = as->buffer_dma;
-+		}
-+		if (xfer->tx_buf) {
-+			sg_set_buf(&as->tx_sg[i], xfer->tx_buf + submitted, len);
-+			as->tx_sg[i].dma_address = xfer->tx_dma + submitted;
-+		} else {
-+			sg_set_buf(&as->tx_sg[i], as->buffer, len);
-+			as->tx_sg[i].dma_address = as->buffer_dma;
-+			memset(as->buffer, 0, len);
-+		}
- 
--				/*
--				 * Not done yet. Submit the next transfer.
--				 *
--				 * FIXME handle protocol options for xfer
--				 */
--				atmel_spi_next_xfer(master, msg);
-+		submitted += len;
-+		as->sg_len = ++i;
-+	}
-+
-+	as->pending_bytes += submitted;
-+
-+	if (xfer->delay_usecs || xfer->cs_change || xfer->bits_per_word
-+			|| xfer->speed_hz) {
-+		struct atmel_spi_device	*asd = spi->controller_state;
-+		int			err;
-+
-+		err = atmel_spi_wait_idle(as, msg);
-+		if (xfer->delay_usecs)
-+			udelay(xfer->delay_usecs);
-+		atmel_spi_set_csr(as, spi, asd->csr);
-+		if (err)
-+			return 0;
-+
-+		if (xfer->cs_change && !atmel_spi_xfer_is_last(msg, xfer)) {
-+			cs_deactivate(as, spi);
-+			udelay(1);
-+			cs_activate(as, spi);
-+		}
-+	}
-+
-+	return xfer->cs_change;
-+}
-+
-+#endif /* PDC vs. DMA engine */
-+
-+static void atmel_spi_work(struct work_struct *work)
-+{
-+	struct atmel_spi	*as;
-+
-+	as = container_of(work, struct atmel_spi, work);
-+
-+	spin_lock_irq(&as->lock);
-+	while (!list_empty(&as->queue)) {
-+		struct spi_message	*msg;
-+		struct spi_transfer	*xfer;
-+		struct spi_device	*spi;
-+		int			cs_change = 0;
-+
-+		if (as->stopping)
-+			break;
-+
-+		msg = list_entry(as->queue.next, struct spi_message, queue);
-+		spin_unlock_irq(&as->lock);
-+
-+		spi = msg->spi;
-+
-+		if (as->stay) {
-+			if (as->stay != spi) {
-+				cs_deactivate(as, as->stay);
-+				cs_activate(as, spi);
- 			}
-+			as->stay = NULL;
- 		} else {
--			/*
--			 * Keep going, we still have data to send in
--			 * the current transfer.
--			 */
--			atmel_spi_next_xfer(master, msg);
-+			cs_activate(as, spi);
-+		}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+		sg_init_table(as->rx_sg, MAX_SG_SEGS);
-+		sg_init_table(as->tx_sg, MAX_SG_SEGS);
-+#endif
-+
-+		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-+			if (msg->status != -EINPROGRESS)
-+				break;
-+			cs_change = atmel_spi_submit_xfer(as, spi, msg, xfer);
-+		}
-+
-+		if (msg->status == -EINPROGRESS) {
-+			if (atmel_spi_wait_idle(as, msg))
-+				cs_change = 1;
-+			else
-+				msg->status = 0;
- 		}
-+		if (!cs_change)
-+			cs_deactivate(as, spi);
-+		else
-+			as->stay = spi;
-+
-+		atmel_spi_dma_unmap_msg(as, msg);
-+
-+		msg->complete(msg->context);
-+		spin_lock_irq(&as->lock);
-+		list_del(&msg->queue);
-+	}
-+	spin_unlock_irq(&as->lock);
-+}
-+
-+static irqreturn_t atmel_spi_interrupt(int irq, void *dev_id)
-+{
-+	struct atmel_spi	*as = dev_id;
-+	u32			status;
-+	u32			mask;
-+	u32			pending;
-+
-+	spin_lock(&as->lock);
-+
-+	status = spi_readl(as, SR);
-+	mask = spi_readl(as, IMR);
-+	pending = status & mask;
-+
-+	if (pending & SPI_BIT(OVRES)) {
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-+#endif
-+		spi_writel(as, IDR, ~0UL);
-+		as->error = -EIO;
-+		as->pending = 0;
-+#ifdef CONFIG_SPI_ATMEL_HAVE_PDC
-+	} else if (pending & SPI_BIT(RXBUFF)) {
-+		spi_writel(as, IDR, ~0UL);
-+		as->pending = 0;
-+	} else if (pending & SPI_BIT(ENDRX)) {
-+		spi_writel(as, IDR, SPI_BIT(ENDRX));
-+		as->pending--;
-+#endif
-+	} else {
-+		dev_err(&as->pdev->dev,
-+			"unexpected interrupt: SR=0x%08x MR=0x%08x\n",
-+				status, mask);
-+		spi_writel(as, IDR, pending);
- 	}
- 
-+	spi_readl(as, IMR);
-+	wake_up(&as->wait);
-+
- 	spin_unlock(&as->lock);
- 
--	return ret;
-+	return IRQ_HANDLED;
- }
- 
- /* the spi->mode bits understood by this driver: */
-@@ -502,6 +939,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
- static int atmel_spi_setup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as;
-+	struct atmel_spi_device	*asd;
- 	u32			scbr, csr;
- 	unsigned int		bits = spi->bits_per_word;
- 	unsigned long		bus_hz;
-@@ -536,21 +974,14 @@ static int atmel_spi_setup(struct spi_device *spi)
- 	}
- 
- 	/* see notes above re chipselect */
--	if (cpu_is_at91rm9200()
-+	if (!atmel_spi_is_v2()
- 			&& spi->chip_select == 0
- 			&& (spi->mode & SPI_CS_HIGH)) {
- 		dev_dbg(&spi->dev, "setup: can't be active-high\n");
- 		return -EINVAL;
- 	}
- 
--	/*
--	 * Pre-new_1 chips start out at half the peripheral
--	 * bus speed.
--	 */
--	bus_hz = clk_get_rate(as->clk);
--	if (!as->new_1)
--		bus_hz /= 2;
--
-+	bus_hz = as->base_hz;
- 	if (spi->max_speed_hz) {
- 		/*
- 		 * Calculate the lowest divider that satisfies the
-@@ -589,11 +1020,20 @@ static int atmel_spi_setup(struct spi_device *spi)
- 
- 	/* chipselect must have been muxed as GPIO (e.g. in board setup) */
- 	npcs_pin = (unsigned int)spi->controller_data;
--	if (!spi->controller_state) {
-+	asd = spi->controller_state;
-+	if (!asd) {
-+		asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
-+		if (!asd)
-+			return -ENOMEM;
-+
- 		ret = gpio_request(npcs_pin, spi->dev.bus_id);
--		if (ret)
-+		if (ret) {
-+			kfree(asd);
- 			return ret;
--		spi->controller_state = (void *)npcs_pin;
-+		}
-+
-+		asd->npcs_pin = npcs_pin;
-+		spi->controller_state = asd;
- 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
- 	} else {
- 		unsigned long		flags;
-@@ -605,11 +1045,14 @@ static int atmel_spi_setup(struct spi_device *spi)
- 		spin_unlock_irqrestore(&as->lock, flags);
- 	}
- 
-+	asd->csr = csr;
-+
- 	dev_dbg(&spi->dev,
- 		"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
- 		bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
- 
--	spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
-+	if (!atmel_spi_is_v2())
-+		spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
- 
- 	return 0;
- }
-@@ -620,74 +1063,81 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
- 	struct spi_transfer	*xfer;
- 	unsigned long		flags;
- 	struct device		*controller = spi->master->dev.parent;
-+	int			ret;
- 
- 	as = spi_master_get_devdata(spi->master);
- 
--	dev_dbg(controller, "new message %p submitted for %s\n",
-+	dev_vdbg(controller, "new message %p submitted for %s\n",
- 			msg, spi->dev.bus_id);
- 
- 	if (unlikely(list_empty(&msg->transfers)
- 			|| !spi->max_speed_hz))
- 		return -EINVAL;
- 
--	if (as->stopping)
--		return -ESHUTDOWN;
--
- 	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
- 		if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
- 			dev_dbg(&spi->dev, "missing rx or tx buf\n");
- 			return -EINVAL;
- 		}
- 
--		/* FIXME implement these protocol options!! */
--		if (xfer->bits_per_word || xfer->speed_hz) {
--			dev_dbg(&spi->dev, "no protocol options yet\n");
--			return -ENOPROTOOPT;
-+		if (xfer->bits_per_word && (xfer->bits_per_word < 8
-+					|| xfer->bits_per_word > 16)) {
-+			dev_dbg(&spi->dev, "unsupported bits_per_word\n");
-+			return -EINVAL;
-+		}
-+		if (xfer->speed_hz) {
-+			unsigned long divider;
-+			divider = DIV_ROUND_UP(as->base_hz, xfer->speed_hz);
-+
-+			if (divider > 255) {
-+				dev_dbg(&spi->dev, "speed_hz too low\n");
-+				return -EINVAL;
-+			}
- 		}
- 
- 		/*
- 		 * DMA map early, for performance (empties dcache ASAP) and
- 		 * better fault reporting.  This is a DMA-only driver.
--		 *
--		 * NOTE that if dma_unmap_single() ever starts to do work on
--		 * platforms supported by this driver, we would need to clean
--		 * up mappings for previously-mapped transfers.
- 		 */
- 		if (!msg->is_dma_mapped) {
--			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
-+			if (atmel_spi_dma_map_xfer(as, xfer) < 0) {
-+				/* Ick */
-+				while (xfer->transfer_list.prev != &msg->transfers) {
-+					xfer = list_entry(xfer->transfer_list.prev,
-+							struct spi_transfer,
-+							transfer_list);
-+					atmel_spi_dma_unmap_xfer(as, xfer);
-+				}
-+
- 				return -ENOMEM;
-+			}
- 		}
- 	}
- 
--#ifdef VERBOSE
--	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
--		dev_dbg(controller,
--			"  xfer %p: len %u tx %p/%08x rx %p/%08x\n",
--			xfer, xfer->len,
--			xfer->tx_buf, xfer->tx_dma,
--			xfer->rx_buf, xfer->rx_dma);
--	}
--#endif
--
- 	msg->status = -EINPROGRESS;
- 	msg->actual_length = 0;
- 
- 	spin_lock_irqsave(&as->lock, flags);
--	list_add_tail(&msg->queue, &as->queue);
--	if (!as->current_transfer)
--		atmel_spi_next_message(spi->master);
-+	if (as->stopping) {
-+		ret = -ESHUTDOWN;
-+	} else {
-+		list_add_tail(&msg->queue, &as->queue);
-+		queue_work(as->workqueue, &as->work);
-+		ret = 0;
-+	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
--	return 0;
-+	return ret;
- }
- 
- static void atmel_spi_cleanup(struct spi_device *spi)
- {
- 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
-+	struct atmel_spi_device	*asd = spi->controller_state;
- 	unsigned		gpio = (unsigned) spi->controller_data;
- 	unsigned long		flags;
- 
--	if (!spi->controller_state)
-+	if (!asd)
- 		return;
- 
- 	spin_lock_irqsave(&as->lock, flags);
-@@ -697,14 +1147,131 @@ static void atmel_spi_cleanup(struct spi_device *spi)
- 	}
- 	spin_unlock_irqrestore(&as->lock, flags);
- 
-+	spi->controller_state = NULL;
- 	gpio_free(gpio);
-+	kfree(asd);
-+}
-+
-+static void atmel_spi_stop_queue(struct atmel_spi *as)
-+{
-+	struct spi_message	*msg;
-+
-+	/*
-+	 * Prevent any new messages from being submitted, cancel any
-+	 * submitted but not-yet-started messages, and wait for any
-+	 * ongoing messages to complete.
-+	 */
-+	as->stopping = true;
-+	smp_wmb();
-+	cancel_work_sync(&as->work);
-+
-+	/* Terminate anything that was left over */
-+	list_for_each_entry(msg, &as->queue, queue) {
-+		atmel_spi_dma_unmap_msg(as, msg);
-+		msg->status = -ESHUTDOWN;
-+		msg->complete(msg->context);
-+	}
-+}
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+static enum dma_state_client atmel_spi_dma_chan_avail(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (!*pchan) {
-+		as->stopping = false;
-+		*pchan = chan;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_chan_removed(struct atmel_spi *as,
-+		struct dma_chan *chan, struct dma_chan **pchan)
-+{
-+	enum dma_state_client ret = DMA_NAK;
-+
-+	if (chan == *pchan) {
-+		atmel_spi_stop_queue(as);
-+		*pchan = NULL;
-+		ret = DMA_ACK;
-+	}
-+
-+	return ret;
- }
- 
-+static enum dma_state_client atmel_spi_dma_rx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, rx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA RX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->rx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static enum dma_state_client atmel_spi_dma_tx_event(struct dma_client *client,
-+		struct dma_chan *chan, enum dma_state state)
-+{
-+	struct atmel_spi	*as;
-+	enum dma_state_client	ret = DMA_NAK;
-+
-+	as = container_of(client, struct atmel_spi, tx_client);
-+
-+	switch (state) {
-+	case DMA_RESOURCE_AVAILABLE:
-+		ret = atmel_spi_dma_chan_avail(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev,
-+					"Using %s for DMA TX transfers\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	case DMA_RESOURCE_REMOVED:
-+		ret = atmel_spi_dma_chan_removed(as, chan, &as->tx_chan);
-+		if (ret == DMA_ACK)
-+			dev_info(&as->pdev->dev, "Lost %s, queue stopped\n",
-+					chan->dev.bus_id);
-+		break;
-+
-+	default:
-+		break;
-+	}
-+
-+	return ret;
-+}
-+#endif
-+
- /*-------------------------------------------------------------------------*/
- 
- static int __init atmel_spi_probe(struct platform_device *pdev)
- {
- 	struct resource		*regs;
-+	struct resource		*buf;
-+	struct atmel_spi_pdata	*pdata;
- 	int			irq;
- 	struct clk		*clk;
- 	int			ret;
-@@ -719,6 +1286,14 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	if (irq < 0)
- 		return irq;
- 
-+	pdata = pdev->dev.platform_data;
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	if (!pdata) {
-+		dev_dbg(&pdev->dev, "no platform data\n");
-+		return -ENXIO;
-+	}
-+#endif
-+
- 	clk = clk_get(&pdev->dev, "spi_clk");
- 	if (IS_ERR(clk))
- 		return PTR_ERR(clk);
-@@ -738,31 +1313,65 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 
- 	as = spi_master_get_devdata(master);
- 
--	/*
--	 * Scratch buffer is used for throwaway rx and tx data.
--	 * It's coherent to minimize dcache pollution.
--	 */
--	as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
--					&as->buffer_dma, GFP_KERNEL);
--	if (!as->buffer)
--		goto out_free;
-+	buf = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (buf) {
-+		as->buffer_dma = buf->start;
-+		as->buffer_size
-+			= rounddown_pow_of_two(buf->end - buf->start + 1);
-+		if (as->buffer_size) {
-+			as->buffer = (void __force *)ioremap(buf->start,
-+					as->buffer_size);
-+			if (as->buffer)
-+				as->always_bounce = true;
-+		}
-+	}
-+
-+	if (!as->buffer) {
-+		/*
-+		 * Scratch buffer is used for throwaway rx and tx data.
-+		 * It's coherent to minimize dcache pollution.
-+		 */
-+		as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
-+						&as->buffer_dma, GFP_KERNEL);
-+		if (!as->buffer)
-+			goto out_free;
-+	}
- 
- 	spin_lock_init(&as->lock);
-+	init_waitqueue_head(&as->wait);
- 	INIT_LIST_HEAD(&as->queue);
-+	INIT_WORK(&as->work, atmel_spi_work);
- 	as->pdev = pdev;
-+	as->clk = clk;
- 	as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
- 	if (!as->regs)
- 		goto out_free_buffer;
--	as->irq = irq;
--	as->clk = clk;
--	if (!cpu_is_at91rm9200())
--		as->new_1 = 1;
- 
--	ret = request_irq(irq, atmel_spi_interrupt, 0,
--			pdev->dev.bus_id, master);
-+	ret = request_irq(irq, atmel_spi_interrupt, 0, pdev->dev.bus_id, as);
- 	if (ret)
- 		goto out_unmap_regs;
- 
-+	as->workqueue = create_singlethread_workqueue(pdev->dev.bus_id);
-+	if (!as->workqueue)
-+		goto out_free_irq;
-+
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	as->rx_client.event_callback = atmel_spi_dma_rx_event;
-+	dma_cap_set(DMA_SLAVE, as->rx_client.cap_mask);
-+	as->rx_client.slave = pdata->rx_dma_slave;
-+	pdata->rx_dma_slave->rx_reg = regs->start + SPI_RDR + 3;
-+
-+	as->tx_client.event_callback = atmel_spi_dma_tx_event;
-+	dma_cap_set(DMA_SLAVE, as->tx_client.cap_mask);
-+	as->tx_client.slave = pdata->tx_dma_slave;
-+	pdata->tx_dma_slave->tx_reg = regs->start + SPI_TDR + 3;
-+
-+	dma_async_client_register(&as->rx_client);
-+	dma_async_client_register(&as->tx_client);
-+	dma_async_client_chan_request(&as->rx_client);
-+	dma_async_client_chan_request(&as->tx_client);
-+#endif
-+
- 	/* Initialize the hardware */
- 	clk_enable(clk);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
-@@ -770,9 +1379,19 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
- 	spi_writel(as, CR, SPI_BIT(SPIEN));
- 
-+	/* v1 chips start out at half the peripheral bus speed. */
-+	as->base_hz = clk_get_rate(clk);
-+	if (!atmel_spi_is_v2())
-+		as->base_hz /= 2;
-+
- 	/* go! */
- 	dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
- 			(unsigned long)regs->start, irq);
-+	if (as->always_bounce)
-+		dev_info(&pdev->dev, "Using bounce buffer at 0x%08x len %zu\n",
-+				as->buffer_dma, as->buffer_size);
-+
-+	atmel_spi_init_debugfs(as);
- 
- 	ret = spi_register_master(master);
- 	if (ret)
-@@ -781,9 +1400,16 @@ static int __init atmel_spi_probe(struct platform_device *pdev)
- 	return 0;
- 
- out_reset_hw:
-+	atmel_spi_cleanup_debugfs(as);
- 	spi_writel(as, CR, SPI_BIT(SWRST));
- 	clk_disable(clk);
--	free_irq(irq, master);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+out_free_irq:
-+	free_irq(irq, as);
- out_unmap_regs:
- 	iounmap(as->regs);
- out_free_buffer:
-@@ -799,33 +1425,34 @@ static int __exit atmel_spi_remove(struct platform_device *pdev)
- {
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
--	struct spi_message	*msg;
- 
--	/* reset the hardware and block queue progress */
--	spin_lock_irq(&as->lock);
--	as->stopping = 1;
--	spi_writel(as, CR, SPI_BIT(SWRST));
--	spi_readl(as, SR);
--	spin_unlock_irq(&as->lock);
-+	/* Stop the queue */
-+	atmel_spi_stop_queue(as);
- 
--	/* Terminate remaining queued transfers */
--	list_for_each_entry(msg, &as->queue, queue) {
--		/* REVISIT unmapping the dma is a NOP on ARM and AVR32
--		 * but we shouldn't depend on that...
--		 */
--		msg->status = -ESHUTDOWN;
--		msg->complete(msg->context);
--	}
-+	atmel_spi_cleanup_debugfs(as);
- 
--	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
--			as->buffer_dma);
-+	/* Shut down the hardware */
-+	spi_writel(as, CR, SPI_BIT(SWRST));
-+	spi_readl(as, SR);
- 
-+	/* Clean up */
-+	spi_unregister_master(master);
-+	free_irq(platform_get_irq(pdev, 0), as);
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	dma_async_client_unregister(&as->tx_client);
-+	dma_async_client_unregister(&as->rx_client);
-+#endif
-+	destroy_workqueue(as->workqueue);
-+	if (as->always_bounce)
-+		iounmap((void __iomem __force *)as->buffer);
-+	else
-+		dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
-+				as->buffer_dma);
-+	iounmap(as->regs);
- 	clk_disable(as->clk);
- 	clk_put(as->clk);
--	free_irq(as->irq, master);
--	iounmap(as->regs);
- 
--	spi_unregister_master(master);
-+	spi_master_put(master);
- 
- 	return 0;
- }
-@@ -837,7 +1464,9 @@ static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
- 	struct spi_master	*master = platform_get_drvdata(pdev);
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
-+	atmel_spi_stop_queue(as);
- 	clk_disable(as->clk);
-+
- 	return 0;
- }
- 
-@@ -847,6 +1476,9 @@ static int atmel_spi_resume(struct platform_device *pdev)
- 	struct atmel_spi	*as = spi_master_get_devdata(master);
- 
- 	clk_enable(as->clk);
-+	as->stopping = false;
-+	smp_wmb();
-+
- 	return 0;
- }
- 
-@@ -868,7 +1500,12 @@ static struct platform_driver atmel_spi_driver = {
- 
- static int __init atmel_spi_init(void)
- {
--	return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	int ret;
-+
-+	ret = platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
-+	if (ret)
-+		pr_notice("atmel_spi probe failed: %d\n", ret);
-+	return ret;
- }
- module_init(atmel_spi_init);
- 
-@@ -879,6 +1516,6 @@ static void __exit atmel_spi_exit(void)
- module_exit(atmel_spi_exit);
- 
- MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
--MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen at atmel.com>");
--MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen at atmel.com>");
-+MODULE_LICENSE("GPL v2");
- MODULE_ALIAS("platform:atmel_spi");
-diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
-index bcefbdd..6882a7d 100644
---- a/drivers/usb/Kconfig
-+++ b/drivers/usb/Kconfig
-@@ -37,6 +37,8 @@ config USB_ARCH_HAS_OHCI
- 	default y if ARCH_EP93XX
- 	default y if ARCH_AT91
- 	default y if ARCH_PNX4008
-+	# AVR32
-+	default y if AVR32
- 	# PPC:
- 	default y if STB03xxx
- 	default y if PPC_MPC52xx
-@@ -55,6 +57,7 @@ config USB_ARCH_HAS_EHCI
- 	default y if PPC_83xx
- 	default y if SOC_AU1200
- 	default y if ARCH_IXP4XX
-+	default y if AVR32
- 	default PCI
- 
- # ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
-diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
-index 228797e..8c48773 100644
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -73,12 +73,12 @@ config USB_EHCI_TT_NEWSCHED
- 
- config USB_EHCI_BIG_ENDIAN_MMIO
- 	bool
--	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_BIG_ENDIAN_DESC
- 	bool
--	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX)
-+	depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || AVR32)
- 	default y
- 
- config USB_EHCI_FSL
-@@ -208,17 +208,19 @@ config USB_OHCI_HCD_SSB
- config USB_OHCI_BIG_ENDIAN_DESC
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_BIG_ENDIAN_MMIO
- 	bool
- 	depends on USB_OHCI_HCD
-+	default y if AVR32
- 	default n
- 
- config USB_OHCI_LITTLE_ENDIAN
- 	bool
- 	depends on USB_OHCI_HCD
--	default n if STB03xxx || PPC_MPC52xx
-+	default n if STB03xxx || PPC_MPC52xx || AVR32
- 	default y
- 
- config USB_UHCI_HCD
-diff --git a/drivers/usb/host/ehci-avr32.c b/drivers/usb/host/ehci-avr32.c
-new file mode 100644
-index 0000000..7cd0591
---- /dev/null
-+++ b/drivers/usb/host/ehci-avr32.c
-@@ -0,0 +1,213 @@
-+/*
-+ * AVR32 EHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ehci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ehci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+}
-+
-+static int ehci_avr32_setup(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
-+	int		ret;
-+
-+	ehci_avr32_start_clocks(dev);
-+
-+	ehci->caps = hcd->regs;
-+	ehci->regs = hcd->regs
-+		+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
-+	dbg_hcs_params(ehci, "reset");
-+	dbg_hcc_params(ehci, "reset");
-+
-+	/* cache this readonly data; minimize chip reads */
-+	ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
-+
-+	ret = ehci_halt(ehci);
-+	if (ret)
-+		goto err;
-+
-+	/* data structure init */
-+	ret = ehci_init(hcd);
-+	if (ret)
-+		goto err;
-+
-+	ehci->sbrn = 0x20;
-+	ehci_port_power(ehci, 0);
-+
-+	return 0;
-+
-+err:
-+	ehci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ehci_avr32_shutdown(struct usb_hcd *hcd)
-+{
-+	ehci_shutdown(hcd);
-+	ehci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ehci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (EHCI)",
-+	.hcd_priv_size		= sizeof(struct ehci_hcd),
-+
-+	.irq			= ehci_irq,
-+	.flags			= HCD_MEMORY | HCD_USB2,
-+
-+	.reset			= ehci_avr32_setup,
-+	.start			= ehci_run,
-+	.stop			= ehci_stop,
-+	.shutdown		= ehci_avr32_shutdown,
-+
-+	.urb_enqueue		= ehci_urb_enqueue,
-+	.urb_dequeue		= ehci_urb_dequeue,
-+	.endpoint_disable	= ehci_endpoint_disable,
-+
-+	.get_frame_number	= ehci_get_frame,
-+
-+	.hub_status_data	= ehci_hub_status_data,
-+	.hub_control		= ehci_hub_control,
-+	.bus_suspend		= ehci_bus_suspend,
-+	.bus_resume		= ehci_bus_resume,
-+	.relinquish_port	= ehci_relinquish_port,
-+	.port_handed_over	= ehci_port_handed_over,
-+};
-+
-+static int ehci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*reg_res;
-+	struct usb_hcd		*hcd;
-+	struct ehci_hcd		*ehci;
-+	int			irq;
-+	int			ret;
-+
-+	reg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!reg_res) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+
-+	if (!request_mem_region(reg_res->start,
-+				reg_res->end - reg_res->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+
-+	hcd = usb_create_hcd(&ehci_avr32_hc_driver, &pdev->dev, "ehci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = reg_res->start;
-+	hcd->rsrc_len = reg_res->end - reg_res->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ehci = hcd_to_ehci(hcd);
-+	ehci->big_endian_mmio = 1;
-+	ehci->big_endian_desc = 1;
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(reg_res->start, reg_res->end - reg_res->start + 1);
-+err_request_mmio:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ehci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ehci_avr32_suspend	NULL
-+#define ehci_avr32_resume	NULL
-+
-+static struct platform_driver ehci_hcd_avr32_driver = {
-+	.probe		= ehci_avr32_probe,
-+	.remove		= ehci_avr32_remove,
-+	.suspend	= ehci_avr32_suspend,
-+	.resume		= ehci_avr32_resume,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.driver		= {
-+		.name	= "ehci",
-+	},
-+};
-diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
-index 86e38b0..15e3956 100644
---- a/drivers/usb/host/ehci-hcd.c
-+++ b/drivers/usb/host/ehci-hcd.c
-@@ -1015,6 +1015,11 @@ MODULE_LICENSE ("GPL");
- #define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ehci-avr32.c"
-+#define PLATFORM_DRIVER		ehci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_PPC_PS3
- #include "ehci-ps3.c"
- #define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
-diff --git a/drivers/usb/host/ohci-avr32.c b/drivers/usb/host/ohci-avr32.c
-new file mode 100644
-index 0000000..67f25d6
---- /dev/null
-+++ b/drivers/usb/host/ohci-avr32.c
-@@ -0,0 +1,208 @@
-+/*
-+ * AVR32 OHCI bus and power management glue
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/platform_device.h>
-+
-+/* Grr! The core layer doesn't let us keep private data anywhere! */
-+static struct clk	*ohci_clk;
-+static struct clk	*utmi_clk;
-+static struct clk	*hclk;
-+
-+static void ohci_avr32_start_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "starting clocks...\n");
-+
-+	clk_enable(ohci_clk);
-+	clk_enable(utmi_clk);
-+	clk_enable(hclk);
-+}
-+
-+static void ohci_avr32_stop_clocks(struct device *dev)
-+{
-+	dev_vdbg(dev, "stopping clocks...\n");
-+
-+	clk_disable(hclk);
-+	clk_disable(utmi_clk);
-+	clk_disable(ohci_clk);
-+}
-+
-+static int ohci_avr32_start(struct usb_hcd *hcd)
-+{
-+	struct device	*dev = hcd->self.controller;
-+	struct ohci_hcd	*ohci = hcd_to_ohci(hcd);
-+	int		ret;
-+
-+	ohci_avr32_start_clocks(dev);
-+
-+	ret = ohci_init(ohci);
-+	if (ret)
-+		goto err_ohci_init;
-+
-+	ret = ohci_run(ohci);
-+	if (likely(!ret))
-+		return 0;
-+
-+	ohci_stop(hcd);
-+
-+err_ohci_init:
-+	ohci_avr32_stop_clocks(dev);
-+	return ret;
-+}
-+
-+static void ohci_avr32_stop(struct usb_hcd *hcd)
-+{
-+	ohci_stop(hcd);
-+	ohci_avr32_stop_clocks(hcd->self.controller);
-+}
-+
-+static const struct hc_driver ohci_avr32_hc_driver = {
-+	.description		= hcd_name,
-+	.product_desc		= "AVR32 USBH (OHCI)",
-+	.hcd_priv_size		= sizeof(struct ohci_hcd),
-+
-+	.irq			= ohci_irq,
-+	.flags			= HCD_USB11 | HCD_MEMORY,
-+
-+	.start			= ohci_avr32_start,
-+	.stop			= ohci_avr32_stop,
-+	.shutdown		= ohci_shutdown,
-+
-+	.urb_enqueue		= ohci_urb_enqueue,
-+	.urb_dequeue		= ohci_urb_dequeue,
-+	.endpoint_disable	= ohci_endpoint_disable,
-+	.get_frame_number	= ohci_get_frame,
-+	.hub_status_data	= ohci_hub_status_data,
-+	.hub_control		= ohci_hub_control,
-+#ifdef CONFIG_PM
-+	.bus_suspend		= ohci_bus_suspend,
-+	.bus_resume		= ohci_bus_resume,
-+#endif
-+	.start_port_reset	= ohci_start_port_reset,
-+};
-+
-+static int ohci_avr32_probe(struct platform_device *pdev)
-+{
-+	struct resource		*regs;
-+	struct usb_hcd		*hcd;
-+	int			irq;
-+	int			ret;
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "no MMIO resource\n");
-+		return -ENXIO;
-+	}
-+
-+	irq = platform_get_irq(pdev, 0);
-+	if (irq < 0) {
-+		dev_dbg(&pdev->dev, "no IRQ resource\n");
-+		return -ENXIO;
-+	}
-+
-+	hclk = clk_get(&pdev->dev, "hclk");
-+	if (IS_ERR(hclk)) {
-+		dev_dbg(&pdev->dev, "no HSB clock\n");
-+		return -ENXIO;
-+	}
-+	utmi_clk = clk_get(&pdev->dev, "utmi_clk");
-+	if (IS_ERR(utmi_clk)) {
-+		dev_dbg(&pdev->dev, "no UTMI clock\n");
-+		ret = -ENXIO;
-+		goto err_utmi_clk;
-+	}
-+	ohci_clk = clk_get(&pdev->dev, "ohci_clk");
-+	if (IS_ERR(ohci_clk)) {
-+		dev_dbg(&pdev->dev, "no OHCI clock\n");
-+		ret = -ENXIO;
-+		goto err_ohci_clk;
-+	}
-+
-+	if (!request_mem_region(regs->start, regs->end - regs->start + 1,
-+				hcd_name)) {
-+		dev_dbg(&pdev->dev, "config regs busy\n");
-+		ret = -EBUSY;
-+		goto err_request_mmio;
-+	}
-+
-+	ret = -ENOMEM;
-+	hcd = usb_create_hcd(&ohci_avr32_hc_driver, &pdev->dev, "ohci-avr32");
-+	if (!hcd) {
-+		dev_dbg(&pdev->dev, "failed to create hcd\n");
-+		goto err_create_hcd;
-+	}
-+
-+	hcd->rsrc_start = regs->start;
-+	hcd->rsrc_len = regs->end - regs->start + 1;
-+	hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
-+	if (!hcd->regs) {
-+		dev_dbg(&pdev->dev, "failed to map registers\n");
-+		goto err_ioremap;
-+	}
-+
-+	ohci_hcd_init(hcd_to_ohci(hcd));
-+
-+	ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
-+	if (ret)
-+		goto err_add_hcd;
-+
-+	return 0;
-+
-+err_add_hcd:
-+	iounmap(hcd->regs);
-+err_ioremap:
-+	usb_put_hcd(hcd);
-+err_create_hcd:
-+	release_mem_region(regs->start, regs->end - regs->start + 1);
-+err_request_mmio:
-+	clk_put(ohci_clk);
-+err_ohci_clk:
-+	clk_put(utmi_clk);
-+err_utmi_clk:
-+	clk_put(hclk);
-+
-+	return ret;
-+}
-+
-+static int ohci_avr32_remove(struct platform_device *pdev)
-+{
-+	struct usb_hcd	*hcd = platform_get_drvdata(pdev);
-+
-+	platform_set_drvdata(pdev, NULL);
-+	usb_remove_hcd(hcd);
-+	iounmap(hcd->regs);
-+	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
-+	usb_put_hcd(hcd);
-+	clk_put(utmi_clk);
-+	clk_put(ohci_clk);
-+	clk_put(hclk);
-+
-+	return 0;
-+}
-+
-+/* FIXME */
-+#define ohci_avr32_suspend	NULL
-+#define ohci_avr32_resume	NULL
-+
-+static struct platform_driver ohci_hcd_avr32_driver = {
-+	.probe		= ohci_avr32_probe,
-+	.remove		= ohci_avr32_remove,
-+	.shutdown	= usb_hcd_platform_shutdown,
-+	.suspend	= ohci_avr32_suspend,
-+	.resume		= ohci_avr32_resume,
-+	.driver		= {
-+		.owner	= THIS_MODULE,
-+		.name	= "ohci",
-+	},
-+};
-+MODULE_ALIAS("platform:ohci");
-diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
-index 8bec02c..43bed29 100644
---- a/drivers/usb/host/ohci-hcd.c
-+++ b/drivers/usb/host/ohci-hcd.c
-@@ -1045,6 +1045,11 @@ MODULE_LICENSE ("GPL");
- #define PLATFORM_DRIVER		ohci_hcd_at91_driver
- #endif
- 
-+#ifdef CONFIG_AVR32
-+#include "ohci-avr32.c"
-+#define PLATFORM_DRIVER		ohci_hcd_avr32_driver
-+#endif
-+
- #ifdef CONFIG_ARCH_PNX4008
- #include "ohci-pnx4008.c"
- #define PLATFORM_DRIVER		usb_hcd_pnx4008_driver
-diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h
-index faf622e..d77ea5c 100644
---- a/drivers/usb/host/ohci.h
-+++ b/drivers/usb/host/ohci.h
-@@ -654,8 +654,10 @@ static inline u32 hc32_to_cpup (const struct ohci_hcd *ohci, const __hc32 *x)
-  * some big-endian SOC implementations.  Same thing happens with PSW access.
-  */
- 
--#ifdef CONFIG_PPC_MPC52xx
-+#if defined(CONFIG_PPC_MPC52xx)
- #define big_endian_frame_no_quirk(ohci)	(ohci->flags & OHCI_QUIRK_FRAME_NO)
-+#elif defined(CONFIG_AVR32)
-+#define big_endian_frame_no_quirk(ohci)	1
- #else
- #define big_endian_frame_no_quirk(ohci)	0
- #endif
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index 70d135e..9f8e70b 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -938,6 +938,15 @@ config FB_ATMEL
- 	help
- 	  This enables support for the AT91/AT32 LCD Controller.
- 
-+config FB_ATMEL_MPOP
-+	tristate "AT32 MPOP support"
-+	depends on FB && AVR32 && FB_ATMEL
-+	select FB_CFB_FILLRECT
-+	select FB_CFB_COPYAREA
-+	select FB_CFB_IMAGEBLIT
-+	help
-+	  This enables support for the AT32 MPOP module.
-+
- config FB_INTSRAM
- 	bool "Frame Buffer in internal SRAM"
- 	depends on FB_ATMEL && ARCH_AT91SAM9261
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index a6b5529..edc0656 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -89,6 +89,7 @@ obj-$(CONFIG_FB_SA1100)           += sa1100fb.o
- obj-$(CONFIG_FB_HIT)              += hitfb.o
- obj-$(CONFIG_FB_EPSON1355)	  += epson1355fb.o
- obj-$(CONFIG_FB_ATMEL)		  += atmel_lcdfb.o
-+obj-$(CONFIG_FB_ATMEL_MPOP)	  += atmel_mpopfb.o
- obj-$(CONFIG_FB_PVR2)             += pvr2fb.o
- obj-$(CONFIG_FB_VOODOO1)          += sstfb.o
- obj-$(CONFIG_FB_ARMCLCD)	  += amba-clcd.o
-diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
-index 75dac57..993d79e 100644
---- a/drivers/video/atmel_lcdfb.c
-+++ b/drivers/video/atmel_lcdfb.c
-@@ -178,7 +178,7 @@ static void init_contrast(struct atmel_lcdfb_info *sinfo)
- static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
- 	.type		= FB_TYPE_PACKED_PIXELS,
- 	.visual		= FB_VISUAL_TRUECOLOR,
--	.xpanstep	= 0,
-+	.xpanstep	= 1,
- 	.ypanstep	= 1,
- 	.ywrapstep	= 0,
- 	.accel		= FB_ACCEL_NONE,
-@@ -239,7 +239,7 @@ static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
- }
- 
- static void atmel_lcdfb_update_dma(struct fb_info *info,
--			       struct fb_var_screeninfo *var)
-+                                   struct fb_var_screeninfo *var)
- {
- 	struct atmel_lcdfb_info *sinfo = info->par;
- 	struct fb_fix_screeninfo *fix = &info->fix;
-@@ -251,6 +251,8 @@ static void atmel_lcdfb_update_dma(struct fb_info *info,
- 	dma_addr &= ~3UL;
- 
- 	/* Set framebuffer DMA base address and pixel offset */
-+	dev_dbg(info->device, "%s:\n", __func__);
-+        dev_dbg(info->device, "  *setting dma addr: 0x%lx \n", dma_addr); 
- 	lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
- 
- 	atmel_lcdfb_update_dma2d(sinfo, var);
-@@ -482,6 +484,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
- 	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
- 		 info->var.xres, info->var.yres,
- 		 info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * bpp:        %u\n", info->var.bits_per_pixel);
- 
- 	atmel_lcdfb_stop_nowait(sinfo);
- 
-@@ -583,7 +586,12 @@ static int atmel_lcdfb_set_par(struct fb_info *info)
- 	lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
- 	/* Enable FIFO & DMA errors */
- 	lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
--
-+        
-+        /* !!!HACK for logging end of frame and underruns 
-+           when connected to MPOP. */
-+        if( info->var.bits_per_pixel == 32 )
-+          lcdc_writel(sinfo, ATMEL_LCDC_IER, 0x70);
-+        
- 	/* ...wait for DMA engine to become idle... */
- 	while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
- 		msleep(10);
-@@ -684,7 +692,7 @@ static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
- }
- 
- static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
--			       struct fb_info *info)
-+                                   struct fb_info *info)
- {
- 	dev_dbg(info->device, "%s\n", __func__);
- 
-@@ -816,7 +824,8 @@ static int __init atmel_lcdfb_probe(struct platform_device *pdev)
- 	info->fix = atmel_lcdfb_fix;
- 
- 	/* Enable LCDC Clocks */
--	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()) {
-+	if (cpu_is_at91sam9261() || cpu_is_at32ap7000()
-+			|| cpu_is_at32ap7200()) {
- 		sinfo->bus_clk = clk_get(dev, "hck1");
- 		if (IS_ERR(sinfo->bus_clk)) {
- 			ret = PTR_ERR(sinfo->bus_clk);
-diff --git a/drivers/video/atmel_mpopfb.c b/drivers/video/atmel_mpopfb.c
-new file mode 100644
-index 0000000..0a07f7b
---- /dev/null
-+++ b/drivers/video/atmel_mpopfb.c
-@@ -0,0 +1,1127 @@
-+/*
-+ *  Driver for AT91/AT32 LCD Controller
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License.  See the file COPYING in the main directory of this archive for
-+ * more details.
-+ */
-+
-+#define DEBUG
-+
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+
-+#include <mach/board.h>
-+#include <mach/cpu.h>
-+
-+#include <video/atmel_lcdc.h>
-+#include <video/atmel_mpop.h>
-+
-+#define mpop_readl(sinfo, reg)		__raw_readl((sinfo)->mmio+(reg))
-+#define mpop_writel(sinfo, reg, val)	__raw_writel((val), (sinfo)->mmio+(reg))
-+
-+#define	ATMEL_MPOPFB_FBINFO_DEFAULT	(FBINFO_DEFAULT \
-+                                         | FBINFO_PARTIAL_PAN_OK        \
-+                                         | FBINFO_HWACCEL_XPAN          \
-+                                         | FBINFO_HWACCEL_YPAN)
-+
-+static struct atmel_mpopfb_rgbconv_coeffs atmel_mpop_ycrcb2rgb_coeffs = {
-+	.r1 = 298,
-+	.r2 = 0,
-+	.r3 = 409,
-+	.r4 = -56992,
-+	.g1 = 298,
-+	.g2 = -100,
-+	.g3 = -208,
-+	.g4 = 34784,
-+	.b1 = 298,
-+	.b2 = 516,
-+	.b3 = 0,
-+	.b4 = -70688,
-+};
-+
-+static struct fb_fix_screeninfo atmel_mpopfb_fix __initdata = {
-+	.type		= FB_TYPE_PLANES,
-+	.visual		= FB_VISUAL_TRUECOLOR,
-+	.xpanstep	= 16,
-+	.ypanstep	= 1,
-+	.ywrapstep	= 1,
-+	.accel		= FB_ACCEL_NONE,
-+};
-+
-+static void atmel_mpopfb_update_sar(struct fb_info *info,
-+		struct fb_var_screeninfo *var)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_fix_screeninfo *fix = &info->fix;
-+	u32 y_sar, u_sar, v_sar, o1_sar, o2_sar, cursor_sar, next_sar;
-+
-+	u32 chroma_xres_virtual;
-+	u32 chroma_yres_virtual;
-+	u32 chroma_xres;
-+	u32 chroma_yres;
-+	u32 chroma_xoffset;
-+	u32 chroma_yoffset;
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual / 2;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres / 2;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset / 2;
-+		break;
-+	case 16:
-+		chroma_xres_virtual = var->xres_virtual / 2;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres / 2;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset / 2;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	case 24:
-+		chroma_xres_virtual = var->xres_virtual;
-+		chroma_yres_virtual = var->yres_virtual;
-+		chroma_xres = var->xres;
-+		chroma_yres = var->yres;
-+		chroma_xoffset = var->xoffset;
-+		chroma_yoffset = var->yoffset;
-+		break;
-+	}
-+
-+	/* Setup pointer to YUV planes in YUV framebuffer. */
-+	y_sar = fix->smem_start + var->xoffset
-+		+ var->yoffset * var->xres_virtual;
-+	u_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ chroma_xoffset + chroma_yoffset * chroma_xres_virtual;
-+	v_sar = u_sar + chroma_xres_virtual * chroma_yres_virtual;
-+	next_sar = fix->smem_start + var->xres_virtual * var->yres_virtual
-+		+ 2 * chroma_xres_virtual * chroma_yres_virtual;
-+	o1_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize;
-+	o2_sar = next_sar;
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		next_sar += sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize
-+			* sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize;
-+	cursor_sar = next_sar;
-+
-+	if (sinfo->baseimg_info.flip) {
-+		/* If we flip we must start with the last line in the frame. */
-+		y_sar += var->xres_virtual * (var->yres - 1);
-+		u_sar += chroma_xres_virtual * (chroma_yres - 1);
-+		v_sar += chroma_xres_virtual * (chroma_yres - 1);
-+	}
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * y_sar = 0x%x\n", y_sar);
-+	dev_dbg(info->device, "  * u_sar = 0x%x\n", u_sar);
-+	dev_dbg(info->device, "  * v_sar = 0x%x\n", v_sar);
-+	dev_dbg(info->device, "  * o1_sar = 0x%x\n", o1_sar);
-+	dev_dbg(info->device, "  * o2_sar = 0x%x\n", o2_sar);
-+	dev_dbg(info->device, "  * cursor_sar = 0x%x\n", cursor_sar);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_Y_SAR, y_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_U_SAR, u_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_V_SAR, v_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SAR, o1_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SAR, o2_sar);
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SAR, cursor_sar);
-+}
-+
-+static void atmel_mpopfb_free_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+
-+	dma_free_writecombine(info->device, info->fix.smem_len,
-+			(void __force *)info->screen_base,
-+			info->fix.smem_start);
-+}
-+
-+/**
-+ *	atmel_mpopfb_alloc_video_memory - Allocate framebuffer memory
-+ *	@sinfo: the frame buffer to allocate memory for
-+ */
-+static int atmel_mpopfb_alloc_video_memory(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	info->fix.smem_len = (var->xres_virtual * var->yres_virtual
-+			* ((var->bits_per_pixel + 7) / 8));
-+
-+	info->screen_base
-+		= (void __iomem __force *)dma_alloc_writecombine(info->device,
-+				info->fix.smem_len,
-+				(dma_addr_t *)&info->fix.smem_start,
-+				GFP_KERNEL);
-+
-+	if (!info->screen_base)
-+		return -ENOMEM;
-+
-+	return 0;
-+}
-+
-+/**
-+ *      atmel_mpopfb_check_var - Validates a var passed in.
-+ *      @var: frame buffer variable screen structure
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Checks to see if the hardware supports the state requested by
-+ *	var passed in. This function does not alter the hardware
-+ *	state!!!  This means the data stored in struct fb_info and
-+ *	struct atmel_mpopfb_info do not change. This includes the var
-+ *	inside of struct fb_info.  Do NOT change these. This function
-+ *	can be called on its own if we intent to only test a mode and
-+ *	not actually set it. The stuff in modedb.c is a example of
-+ *	this. If the var passed in is slightly off by what the
-+ *	hardware can support then we alter the var PASSED in to what
-+ *	we can do. If the hardware doesn't support mode change a
-+ *	-EINVAL will be returned by the upper layers. You don't need
-+ *	to implement this function then. If you hardware doesn't
-+ *	support changing the resolution then this function is not
-+ *	needed. In this case the driver would just provide a var that
-+ *	represents the static state the screen is in.
-+ *
-+ *	Returns negative errno on error, or zero on success.
-+ */
-+static int atmel_mpopfb_check_var(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	struct device *dev = info->device;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(dev, "%s:\n", __func__);
-+	dev_dbg(dev, "  resolution: %ux%u\n", var->xres, var->yres);
-+	dev_dbg(dev, "  offset: (%u,%u)\n", var->xoffset, var->yoffset);
-+	dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
-+
-+	/*
-+	 *  FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
-+	 *  as FB_VMODE_SMOOTH_XPAN is only used internally
-+	 */
-+
-+	if (var->vmode & FB_VMODE_CONUPDATE) {
-+		var->vmode |= FB_VMODE_YWRAP;
-+		var->xoffset = info->var.xoffset;
-+		var->yoffset = info->var.yoffset;
-+	}
-+
-+	/* Horizontal size must be a multiple of 16 pixels */
-+
-+	/*
-+	 *  Some very basic checks
-+	 */
-+	if (!var->xres)
-+		var->xres = 1;
-+	if (!var->yres)
-+		var->yres = 1;
-+	if (var->xres > var->xres_virtual)
-+		var->xres_virtual = var->xres;
-+	if (var->yres > var->yres_virtual)
-+		var->yres_virtual = var->yres;
-+	if (var->bits_per_pixel > 16)
-+		var->bits_per_pixel = 24;
-+	else if (var->bits_per_pixel > 12)
-+		var->bits_per_pixel = 16;
-+	else
-+		var->bits_per_pixel = 12;
-+
-+	/* Horizontal size and offset must be a multiple of 16 pixels */
-+	var->xres = (var->xres + 15) & ~15UL;
-+	var->xres_virtual = (var->xres_virtual + 15) & ~15UL;
-+	var->xoffset = (var->xoffset + 15) & ~15UL;
-+
-+	if (var->xres_virtual < var->xoffset + var->xres)
-+		var->xres_virtual = var->xoffset + var->xres;
-+	if (var->yres_virtual < var->yoffset + var->yres)
-+		var->yres_virtual = var->yoffset + var->yres;
-+
-+	/* Check that the scaled image will fit into the LCD display. */
-+	if (sinfo->baseimg_info.xsize > lcdc_info->var.xres) {
-+		dev_err(dev, "baseimage is wider than screen: %d > %d\n",
-+			sinfo->baseimg_info.xsize, lcdc_info->var.xres);
-+		return -EINVAL;
-+	}
-+
-+	if (sinfo->baseimg_info.ysize > lcdc_info->var.yres) {
-+		dev_err(dev, "baseimage is higher than screen: %d > %d\n",
-+			sinfo->baseimg_info.ysize, lcdc_info->var.yres);
-+		return -EINVAL;
-+	}
-+
-+	/* Check that it is possible to scale to given size. */
-+	if (ATMEL_MPOP_CALC_SCALE(var->xres, sinfo->baseimg_info.xsize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->xres,
-+					sinfo->baseimg_info.xsize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from width %d to %d Max %s\n",
-+			var->xres, sinfo->baseimg_info.xsize,
-+			ATMEL_MPOP_CALC_SCALE(var->xres,
-+					      sinfo->baseimg_info.xsize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	if (ATMEL_MPOP_CALC_SCALE(var->yres, sinfo->baseimg_info.ysize) == 0
-+			|| (ATMEL_MPOP_CALC_SCALE(var->yres,
-+					sinfo->baseimg_info.ysize)
-+				> (4 << ATMEL_MPOP_RESIZE_FRAC_BITS))) {
-+		dev_err(dev, "cannot scale from height %d to %d Max %s\n",
-+			var->yres, sinfo->baseimg_info.ysize,
-+			ATMEL_MPOP_CALC_SCALE(var->yres,
-+					      sinfo->baseimg_info.ysize)
-+			? "downscale factor is 4!"
-+			: "upscale factor is 32");
-+		return -EINVAL;
-+	}
-+
-+	var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
-+	var->transp.msb_right = 0;
-+	var->transp.offset = var->transp.length = 0;
-+
-+	switch (var->bits_per_pixel) {
-+	case 12:
-+	case 16:
-+	case 24:
-+		var->red.offset = 0;
-+		var->green.offset = 8;
-+		var->blue.offset = 16;
-+		var->red.length = var->green.length = var->blue.length = 8;
-+		break;
-+	default:
-+		dev_err(dev, "color depth %d not supported\n",
-+			var->bits_per_pixel);
-+		return -EINVAL;
-+	}
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running) {
-+		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
-+
-+		/* Enable all error interrupts. */
-+		mpop_writel(sinfo, ATMEL_MPOP_INTEN, 0x7);
-+
-+		/*
-+		 * Enable the MPOP. When the LCD controller starts
-+		 * reading from the slave interface it will start
-+		 * generating a frame.
-+		 */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+			    ATMEL_MPOP_CR_EN_MASK
-+			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
-+
-+		sinfo->running = 1;
-+	}
-+}
-+
-+static void atmel_mpopfb_stop(struct atmel_mpopfb_info *sinfo)
-+{
-+	if (!sinfo->running)
-+		/* Not running. Already stopped. */
-+		return;
-+
-+	dev_dbg(sinfo->info->device, "Stopping MPOP.\n");
-+
-+	/* Disable the MPOP. This will force the MPOP to be reset. */
-+	mpop_writel(sinfo, ATMEL_MPOP_CR, 0);
-+
-+	/* Disable all interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTDIS, ~0UL);
-+
-+	/* Looks like we stopped the MPOP... */
-+	dev_dbg(sinfo->info->device, "MPOP stopped.\n");
-+
-+	sinfo->running = 0;
-+}
-+
-+static void atmel_mpopfb_connect_to_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Connecting MPOP to LCDC:\n");
-+
-+	/* Start the mpop if it is not running. */
-+	atmel_mpopfb_start(sinfo);
-+
-+	if (sinfo->connected_to_lcdc)
-+		/* Already connected. */
-+		return;
-+
-+	/*
-+	 * Set framebuffer pointer in LCDC to point to the slave
-+	 * interface of the MPOP.
-+	 */
-+	dev_dbg(sinfo->info->device, "  * Attaching to LCDC.\n");
-+	sinfo->lcdc_old_smem_start = lcdc_info->fix.smem_start;
-+	lcdc_info->fix.smem_start = (unsigned long)sinfo->slave_base;
-+	sinfo->lcdc_old_bits_per_pixel = lcdc_info->var.bits_per_pixel;
-+	lcdc_info->var.bits_per_pixel = 32;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 1;
-+}
-+
-+static void atmel_mpopfb_disconnect_from_lcdc(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+
-+	dev_dbg(sinfo->info->device, "Disconnecting MPOP from LCDC:\n");
-+
-+	if (!sinfo->connected_to_lcdc)
-+		/* Already disconnected. */
-+		return;
-+
-+	/* Restore lcdc's old framebuffer pointer and pixel-format. */
-+	lcdc_info->fix.smem_start = sinfo->lcdc_old_smem_start;
-+	lcdc_info->var.bits_per_pixel = sinfo->lcdc_old_bits_per_pixel;
-+
-+	/* Force the LCDC to change the configuration. */
-+	lcdc_info->fbops->fb_set_par(lcdc_info);
-+
-+	sinfo->connected_to_lcdc = 0;
-+
-+	/* We must stop the mpop to reset it. */
-+	atmel_mpopfb_stop(sinfo);
-+}
-+
-+static void atmel_mpopfb_put_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	dev_dbg(sinfo->info->device, "Overlay palette = :\n");
-+	for (i = 0; i < 256; i++) {
-+		dev_dbg(sinfo->info->device, "%d -> 0x%x\n", i,
-+			*((int *)&palette->entry[i]));
-+		mpop_writel(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i,
-+			    *((int *)&palette->entry[i]));
-+	}
-+}
-+
-+static void atmel_mpopfb_get_overlay_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_overlay_palette *palette)
-+{
-+	int i;
-+
-+	for (i = 0; i < 256; i++)
-+		*((int *)&palette->entry[i]) =
-+		    mpop_readl(sinfo, ATMEL_MPOP_PALETTEDATA + 4 * i);
-+}
-+
-+static void atmel_mpopfb_put_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i,
-+				*((int *)&palette->entry[i]));
-+}
-+
-+static void atmel_mpopfb_get_cursor_palette(struct atmel_mpopfb_info *sinfo,
-+		struct atmel_mpopfb_cursor_palette *palette)
-+{
-+	int i;
-+	for (i = 0; i < 4; i++)
-+		*((int *)&palette->entry[i])
-+			= mpop_readl(sinfo, ATMEL_MPOP_CURSOR_P0 + 4 * i);
-+}
-+
-+/**
-+ *      atmel_mpopfb_set_par - Alters the hardware state.
-+ *      @info: frame buffer structure that represents a single frame buffer
-+ *
-+ *	Using the fb_var_screeninfo in fb_info we set the resolution
-+ *	of the this particular framebuffer. This function alters the
-+ *	par AND the fb_fix_screeninfo stored in fb_info. It doesn't
-+ *	not alter var in fb_info since we are using that data. This
-+ *	means we depend on the data in var inside fb_info to be
-+ *	supported by the hardware.  atmel_lcdfb_check_var is always called
-+ *	before atmel_lcdfb_set_par to ensure this.  Again if you can't
-+ *	change the resolution you don't need this function.
-+ *
-+ */
-+static int atmel_mpopfb_set_par(struct fb_info *info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct fb_info *lcdc_info = platform_get_drvdata(sinfo->lcdc_pdev);
-+	struct fb_var_screeninfo *var = &info->var;
-+
-+	u32 yuv_format;
-+	u32 xscale, yscale;
-+
-+	dev_dbg(info->device, "%s:\n", __func__);
-+	dev_dbg(info->device, "  * resolution: %ux%u (%ux%u virtual)\n",
-+			info->var.xres, info->var.yres,
-+			info->var.xres_virtual, info->var.yres_virtual);
-+	dev_dbg(info->device, "  * offset: (%u,%u)\n",
-+			info->var.xoffset, info->var.yoffset);
-+	dev_dbg(info->device, "  * bpp: %u\n", info->var.bits_per_pixel);
-+
-+	/* Setup the output picture size. We must use the size of the lcdcfb. */
-+	dev_dbg(info->device, "  * output frame resolution: %ux%u \n",
-+			lcdc_info->var.xres, lcdc_info->var.yres);
-+	mpop_writel(sinfo, ATMEL_MPOP_DISP_MAX_COORD,
-+			((lcdc_info->var.xres - 1) << ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET)
-+			| ((lcdc_info->var.yres - 1) << ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup base picture. */
-+
-+	switch (var->bits_per_pixel) {
-+	default:
-+	case 12:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_420;
-+		break;
-+	case 16:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_422;
-+		break;
-+	case 24:
-+		yuv_format = ATMEL_MPOP_YUVFORMAT_444;
-+		break;
-+	}
-+
-+	xscale = ATMEL_MPOP_CALC_SCALE(info->var.xres, sinfo->baseimg_info.xsize);
-+	yscale = ATMEL_MPOP_CALC_SCALE(info->var.yres, sinfo->baseimg_info.ysize);
-+
-+	dev_dbg(info->device, "  * baseimg output size = %ux%u \n",
-+			sinfo->baseimg_info.xsize, sinfo->baseimg_info.ysize);
-+	dev_dbg(info->device, "  * resize scales = %ux%u \n", xscale, yscale);
-+	dev_dbg(info->device, "  * yuv format = %u \n", yuv_format);
-+	mpop_writel(sinfo, ATMEL_MPOP_YCR,
-+			yuv_format << ATMEL_MPOP_YCR_YUVFORMAT_OFFSET
-+			| xscale << ATMEL_MPOP_YCR_XRESIZE_OFFSET
-+			| yscale << ATMEL_MPOP_YCR_YRESIZE_OFFSET);
-+
-+	/* Setup conversion coefficients. */
-+	mpop_writel(sinfo, ATMEL_MPOP_R2R1,
-+			((sinfo->rgbconv_coeffs.r1 << ATMEL_MPOP_R1_OFFSET) & ATMEL_MPOP_R1_MASK)
-+			| ((sinfo->rgbconv_coeffs.r2 << ATMEL_MPOP_R2_OFFSET) & ATMEL_MPOP_R2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_R4R3,
-+			((sinfo->rgbconv_coeffs.r3 << ATMEL_MPOP_R3_OFFSET) & ATMEL_MPOP_R3_MASK)
-+			| ((sinfo->rgbconv_coeffs.r4 << ATMEL_MPOP_R4_OFFSET) & ATMEL_MPOP_R4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G2G1,
-+			((sinfo->rgbconv_coeffs.g1 << ATMEL_MPOP_G1_OFFSET) & ATMEL_MPOP_G1_MASK)
-+			| ((sinfo->rgbconv_coeffs.g2 << ATMEL_MPOP_G2_OFFSET) & ATMEL_MPOP_G2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_G4G3,
-+			((sinfo->rgbconv_coeffs.g3 << ATMEL_MPOP_G3_OFFSET) & ATMEL_MPOP_G3_MASK)
-+			| ((sinfo->rgbconv_coeffs.g4 << ATMEL_MPOP_G4_OFFSET) & ATMEL_MPOP_G4_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B2B1,
-+			((sinfo->rgbconv_coeffs.b1 << ATMEL_MPOP_B1_OFFSET) & ATMEL_MPOP_B1_MASK)
-+			| ((sinfo->rgbconv_coeffs.b2 << ATMEL_MPOP_B2_OFFSET) & ATMEL_MPOP_B2_MASK));
-+	mpop_writel(sinfo, ATMEL_MPOP_B4B3,
-+			((sinfo->rgbconv_coeffs.b3 << ATMEL_MPOP_B3_OFFSET) & ATMEL_MPOP_B3_MASK)
-+			| ((sinfo->rgbconv_coeffs.b4 << ATMEL_MPOP_B4_OFFSET) & ATMEL_MPOP_B4_MASK));
-+
-+	info->fix.line_length = info->var.xres_virtual;
-+	info->fix.visual = FB_VISUAL_TRUECOLOR;
-+
-+	/* Setup stride. We can flip the image by negating the 
-+	   stride, but we must then set the SAR registers to point
-+	   to the last line in the image. */
-+	if (sinfo->baseimg_info.flip) {
-+		dev_dbg(info->device, "  * flip \n");
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, -info->var.xres_virtual);
-+	} else
-+		mpop_writel(sinfo, ATMEL_MPOP_STRIDE, info->var.xres_virtual);
-+
-+	/* Setup input image size. */
-+	mpop_writel(sinfo, ATMEL_MPOP_YUV_MAX_COORD,
-+			((info->var.xres - 1) << ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET)
-+			| ((info->var.yres - 1) << ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET));
-+
-+	/* Setup size and position of output base image after scaling. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_SIZE,
-+			sinfo->baseimg_info.xsize << ATMEL_MPOP_RGB_SIZE_X_OFFSET
-+			| sinfo->baseimg_info.ysize << ATMEL_MPOP_RGB_SIZE_Y_OFFSET);
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_POS,
-+			(sinfo->baseimg_info.xpos << ATMEL_MPOP_RGB_POS_X_OFFSET)
-+			| (sinfo->baseimg_info.ypos << ATMEL_MPOP_RGB_POS_Y_OFFSET));
-+
-+	dev_dbg(info->device, "  * baseimg pos: (%u,%u) \n",
-+			sinfo->baseimg_info.xpos, sinfo->baseimg_info.ypos);
-+
-+	/* Setup Word Transfer Count. */
-+	mpop_writel(sinfo, ATMEL_MPOP_RGB_WTC,
-+			DIV_ROUND_UP(info->var.xres * info->var.yres
-+				* var->bits_per_pixel, 32));
-+
-+	/* Set overlay parameters. */
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize << ATMEL_MPOP_O1_SIZE_O1_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize << ATMEL_MPOP_O1_SIZE_O1_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O1_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].xsize
-+			 * sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize << ATMEL_MPOP_O2_SIZE_O2_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize << ATMEL_MPOP_O2_SIZE_O2_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_O2_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].xsize *
-+				sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].ysize, 4));
-+
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_SIZE,
-+			(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X)
-+			| (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize << ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y));
-+	mpop_writel(sinfo, ATMEL_MPOP_CURSOR_WTC,
-+			DIV_ROUND_UP(sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].xsize
-+				* sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].ysize, 16));
-+
-+	/* Enable base overlay + any other enabled overlays. */
-+	mpop_writel(sinfo, ATMEL_MPOP_OCR, ATMEL_MPOP_OCR_RGBEN_MASK);
-+
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_CURSOREN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O1EN_MASK);
-+	if (sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled)
-+		mpop_writel(sinfo, ATMEL_MPOP_OCR,
-+				mpop_readl(sinfo, ATMEL_MPOP_OCR)
-+				| ATMEL_MPOP_OCR_O2EN_MASK);
-+
-+	/* Set background to black. */
-+	mpop_writel(sinfo, ATMEL_MPOP_BGCOLOR, 0);
-+
-+	/* Setup source address registers */
-+	atmel_mpopfb_update_sar(info, &info->var);
-+
-+	dev_dbg(info->device, "  * DONE\n");
-+
-+	return 0;
-+}
-+
-+static int atmel_mpopfb_pan_display(struct fb_var_screeninfo *var,
-+		struct fb_info *info)
-+{
-+	dev_dbg(info->device, "%s\n", __func__);
-+
-+	/* Change source address registers to reflect the panning. */
-+	atmel_mpopfb_update_sar(info, var);
-+
-+	return 0;
-+}
-+
-+static void atmel_mpopfb_put_overlay_info(struct fb_info *info,
-+		struct atmel_mpopfb_overlay_info overlay_info)
-+{
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	/* We can update the position now since it is double buffered. */
-+	switch (overlay_info.overlay) {
-+	case ATMEL_MPOPFB_OVERLAY1:
-+		mpop_writel(sinfo, ATMEL_MPOP_O1_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O1_POS_O1_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O1_POS_O1_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_OVERLAY2:
-+		mpop_writel(sinfo, ATMEL_MPOP_O2_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_O2_POS_O2_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_O2_POS_O2_POS_Y));
-+		break;
-+	case ATMEL_MPOPFB_CURSOR:
-+		mpop_writel(sinfo, ATMEL_MPOP_CURSOR_POS,
-+			(overlay_info.xpos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X)
-+			| (overlay_info.ypos << ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y));
-+		break;
-+	default:
-+		dev_warn(info->device, "Unknown overlay type: %d\n",
-+				overlay_info.overlay);
-+		return;
-+	}
-+
-+	/* Copy the overlay info to the mpopfb info structure. */
-+	sinfo->overlay_info[overlay_info.overlay] = overlay_info;
-+}
-+
-+static int atmel_mpopfb_ioctl(struct fb_info *info,
-+		unsigned int cmd, unsigned long arg)
-+{
-+	void __user *argp = (void __user *)arg;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	struct atmel_mpopfb_overlay_info overlay_info;
-+
-+	switch (cmd) {
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_overlay_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE:{
-+			struct atmel_mpopfb_overlay_palette palette;
-+			atmel_mpopfb_get_overlay_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			if (copy_from_user(&palette, argp, sizeof(palette)))
-+				return -EFAULT;
-+			atmel_mpopfb_put_cursor_palette(sinfo, &palette);
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOGET_CURSOR_PALETTE:{
-+			struct atmel_mpopfb_cursor_palette palette;
-+			atmel_mpopfb_get_cursor_palette(sinfo, &palette);
-+			if (copy_to_user(argp, &palette, sizeof(palette)))
-+				return -EFAULT;
-+			return 0;
-+		}
-+	case ATMEL_MPOP_FBIOPUT_OVERLAY_INFO:
-+		if (copy_from_user(&overlay_info, argp, sizeof(overlay_info)))
-+			return -EFAULT;
-+		atmel_mpopfb_put_overlay_info(info, overlay_info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOPUT_BASEIMG_INFO:
-+		if (copy_from_user(&sinfo->baseimg_info, argp,
-+					sizeof(sinfo->baseimg_info)))
-+			return -EFAULT;
-+
-+		/* Check that new baseimg parameters are sane. */
-+		if (atmel_mpopfb_check_var(&info->var, info))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		atmel_mpopfb_set_par(info);
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_BASEIMG_INFO:
-+		return copy_to_user(argp, &sinfo->baseimg_info,
-+				sizeof(sinfo->baseimg_info)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS:
-+		if (copy_from_user(&sinfo->rgbconv_coeffs, argp,
-+					sizeof(sinfo->rgbconv_coeffs)))
-+			return -EFAULT;
-+
-+		/* Update hardware configuration. */
-+		if (atmel_mpopfb_set_par(info))
-+			return -EFAULT;
-+
-+		return 0;
-+	case ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS:
-+		return copy_to_user(argp, &sinfo->rgbconv_coeffs,
-+				sizeof(sinfo->rgbconv_coeffs)) ? -EFAULT : 0;
-+	case ATMEL_MPOP_FBIO_CONNECT_TO_LCDC:
-+		atmel_mpopfb_connect_to_lcdc(sinfo);
-+		return 0;
-+	case ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC:
-+		atmel_mpopfb_disconnect_from_lcdc(sinfo);
-+		return 0;
-+	default:
-+		return -EINVAL;
-+	}
-+
-+	/* Force MPOP to be updated with any new parameters. */
-+	atmel_mpopfb_set_par(info);
-+}
-+
-+static int atmel_mpopfb_setcolreg(unsigned int regno, unsigned int red,
-+				  unsigned int green, unsigned int blue,
-+				  unsigned int transp, struct fb_info *info)
-+{
-+	return 0;
-+}
-+
-+static struct fb_ops atmel_mpopfb_ops = {
-+	.owner		= THIS_MODULE,
-+	.fb_check_var	= atmel_mpopfb_check_var,
-+	.fb_set_par	= atmel_mpopfb_set_par,
-+	.fb_setcolreg	= atmel_mpopfb_setcolreg,
-+	.fb_pan_display	= atmel_mpopfb_pan_display,
-+	.fb_imageblit	= cfb_imageblit,
-+	.fb_ioctl	= atmel_mpopfb_ioctl,
-+	.fb_fillrect	= cfb_fillrect,
-+	.fb_copyarea	= cfb_copyarea,
-+};
-+
-+static irqreturn_t atmel_mpopfb_interrupt(int irq, void *dev_id)
-+{
-+	struct fb_info *info = dev_id;
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+	u32 status;
-+
-+	/* Check which interrupt we have. */
-+	status = mpop_readl(sinfo, ATMEL_MPOP_INTSTATUS);
-+
-+	/* Clear interrupts. */
-+	mpop_writel(sinfo, ATMEL_MPOP_INTCLEAR, status);
-+
-+	if (status & ATMEL_MPOP_EOP) {
-+		/* End Of Picture. Start new picture. */
-+		mpop_writel(sinfo, ATMEL_MPOP_CR,
-+				ATMEL_MPOP_CR_START_MASK
-+				| mpop_readl(sinfo, ATMEL_MPOP_CR));
-+	} else if (status & ATMEL_MPOP_OUT) {
-+		dev_err(info->dev,
-+			"MPOP Output DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OUT_BEAR));
-+	} else if (status & ATMEL_MPOP_YUV) {
-+		dev_err(info->dev,
-+			"MPOP YUV Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_YUV_BEAR));
-+	} else if (status & ATMEL_MPOP_OVERLAY) {
-+		dev_err(info->dev,
-+			"MPOP Overlay Picture Fetch DMA interface Bus Error (address=0x%x)!\n",
-+			mpop_readl(sinfo, ATMEL_MPOP_OVERLAY_BEAR));
-+	}
-+
-+	dev_dbg(info->device, "%s\n", __func__);
-+	dev_dbg(info->device, "  * status: 0x%x \n", status);
-+
-+	return IRQ_HANDLED;
-+}
-+
-+static int __init atmel_mpopfb_init_fbinfo(struct atmel_mpopfb_info *sinfo)
-+{
-+	struct fb_info *info = sinfo->info;
-+	int ret = 0;
-+
-+	info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
-+
-+	dev_info(info->device,
-+			"%luKiB frame buffer at %08lx (mapped at %p)\n",
-+			(unsigned long)info->fix.smem_len / 1024,
-+			(unsigned long)info->fix.smem_start, info->screen_base);
-+
-+	return ret;
-+}
-+
-+static void atmel_mpopfb_start_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_enable(sinfo->mpop_hclk);
-+	clk_enable(sinfo->mpop_pclk);
-+}
-+
-+static void atmel_mpopfb_stop_clock(struct atmel_mpopfb_info *sinfo)
-+{
-+	clk_disable(sinfo->mpop_hclk);
-+	clk_disable(sinfo->mpop_pclk);
-+}
-+
-+static int __init atmel_mpopfb_probe(struct platform_device *pdev)
-+{
-+	struct device			*dev = &pdev->dev;
-+	struct fb_info			*info;
-+	struct fb_info			*lcdc_info;
-+	struct atmel_mpopfb_info	*sinfo;
-+	struct atmel_mpopfb_info	*pdata_sinfo;
-+	struct resource			*regs = NULL;
-+	struct resource			*slave = NULL;
-+	struct resource			*map = NULL;
-+	int				ret;
-+
-+	dev_dbg(dev, "%s BEGIN\n", __func__);
-+
-+	ret = -ENOMEM;
-+	info = framebuffer_alloc(sizeof(struct atmel_mpopfb_info), dev);
-+	if (!info) {
-+		dev_err(dev, "cannot allocate memory\n");
-+		goto out;
-+	}
-+
-+	sinfo = info->par;
-+
-+	if (dev->platform_data) {
-+		pdata_sinfo = dev->platform_data;
-+		sinfo->lcdc_pdev = pdata_sinfo->lcdc_pdev;
-+		if (!sinfo->lcdc_pdev) {
-+			dev_err(dev, "cannot get hold of lcdcfb device\n");
-+			goto free_info;
-+		}
-+	} else {
-+		dev_err(dev, "cannot get default configuration\n");
-+		goto free_info;
-+	}
-+
-+	sinfo->info = info;
-+	sinfo->pdev = pdev;
-+	sinfo->running = 0;
-+	sinfo->connected_to_lcdc = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY1].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_OVERLAY2].enabled = 0;
-+	sinfo->overlay_info[ATMEL_MPOPFB_CURSOR].enabled = 0;
-+
-+	/* Setup default info */
-+
-+	/* Set fb_var_screeninfo equal to that of the lcdcfb driver. */
-+	lcdc_info = (struct fb_info *)platform_get_drvdata(sinfo->lcdc_pdev);
-+	memcpy(&info->var, &lcdc_info->var, sizeof(struct fb_var_screeninfo));
-+
-+	/* Set default position of the image on the screen to (0,0) and
-+	   no scaling */
-+	sinfo->baseimg_info.xpos = 0;
-+	sinfo->baseimg_info.ypos = 0;
-+	sinfo->baseimg_info.xsize = info->var.xres;
-+	sinfo->baseimg_info.ysize = info->var.yres;
-+
-+	/* Use YCbCr --> RGB converion per default. */
-+	memcpy(&sinfo->rgbconv_coeffs, &atmel_mpop_ycrcb2rgb_coeffs,
-+	       sizeof(struct atmel_mpopfb_rgbconv_coeffs));
-+
-+	strcpy(info->fix.id, sinfo->pdev->name);
-+	info->flags = ATMEL_MPOPFB_FBINFO_DEFAULT;
-+	info->fbops = &atmel_mpopfb_ops;
-+
-+	//memcpy(&info->monspecs, sinfo->default_monspecs, sizeof(info->monspecs));
-+	info->fix = atmel_mpopfb_fix;
-+
-+	/* Enable MPOP Clocks */
-+	sinfo->mpop_hclk = clk_get(dev, "hclk");
-+	sinfo->mpop_pclk = clk_get(dev, "pclk");
-+	if (IS_ERR(sinfo->mpop_hclk)) {
-+		ret = PTR_ERR(sinfo->mpop_hclk);
-+		goto put_bus_clk;
-+	}
-+	if (IS_ERR(sinfo->mpop_pclk)) {
-+		ret = PTR_ERR(sinfo->mpop_pclk);
-+		goto stop_clk;
-+	}
-+	atmel_mpopfb_start_clock(sinfo);
-+
-+	//ret = fb_find_mode(&info->var, info, NULL, info->monspecs.modedb,
-+	//                   info->monspecs.modedb_len, info->monspecs.modedb,
-+	//                   sinfo->default_bpp);
-+	//if (!ret) {
-+	//      dev_err(dev, "no suitable video mode found\n");
-+	//      goto stop_clk;
-+	//}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_err(dev, "resources unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+
-+	slave = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	if (!slave) {
-+		dev_err(dev, "slave interface memory resource unusable\n");
-+		ret = -ENXIO;
-+		goto stop_clk;
-+	}
-+	sinfo->slave_base = (void *)slave->start;
-+
-+	sinfo->irq_base = platform_get_irq(pdev, 0);
-+	if (sinfo->irq_base < 0) {
-+		dev_err(dev, "unable to get irq\n");
-+		ret = sinfo->irq_base;
-+		goto stop_clk;
-+	}
-+
-+	/* Initialize video memory */
-+	map = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-+	if (map) {
-+		/* use a pre-allocated memory buffer */
-+		info->fix.smem_start = map->start;
-+		info->fix.smem_len = map->end - map->start + 1;
-+		if (!request_mem_region(info->fix.smem_start,
-+					info->fix.smem_len, pdev->name)) {
-+			//ret = -EBUSY;
-+			//goto stop_clk;
-+			/* Probably in use by LCD controller. */
-+			info->screen_base = lcdc_info->screen_base;
-+		} else {
-+			info->screen_base =
-+			    ioremap(info->fix.smem_start, info->fix.smem_len);
-+			if (!info->screen_base)
-+				goto release_intmem;
-+		}
-+	} else {
-+		/* alocate memory buffer */
-+		ret = atmel_mpopfb_alloc_video_memory(sinfo);
-+		if (ret < 0) {
-+			dev_err(dev, "cannot allocate mpop framebuffer: %d\n",
-+				ret);
-+			goto stop_clk;
-+		}
-+	}
-+
-+	/* MPOP registers */
-+	info->fix.mmio_start = regs->start;
-+	info->fix.mmio_len = regs->end - regs->start + 1;
-+
-+	if (!request_mem_region(info->fix.mmio_start,
-+				info->fix.mmio_len, pdev->name)) {
-+		ret = -EBUSY;
-+		goto free_fb;
-+	}
-+
-+	sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
-+	if (!sinfo->mmio) {
-+		dev_err(dev, "cannot map MPOP registers\n");
-+		goto release_mem;
-+	}
-+
-+	/* MPOP slave interface */
-+	if (!request_mem_region(slave->start,
-+				slave->end - slave->start + 1, pdev->name)) {
-+		dev_err(dev,
-+			"error requesting memory region for MPOP slave interface\n");
-+		ret = -EBUSY;
-+		goto unmap_mmio;
-+	}
-+
-+	/* interrupt */
-+	ret =
-+	    request_irq(sinfo->irq_base, atmel_mpopfb_interrupt, 0, pdev->name,
-+			info);
-+	if (ret) {
-+		dev_err(dev, "request_irq failed: %d\n", ret);
-+		goto release_mem_slave;
-+	}
-+
-+	ret = atmel_mpopfb_init_fbinfo(sinfo);
-+	if (ret < 0) {
-+		dev_err(dev, "init fbinfo failed: %d\n", ret);
-+		goto unregister_irqs;
-+	}
-+
-+	/*
-+	 * This makes sure that our colour bitfield
-+	 * descriptors are correctly initialised.
-+	 */
-+	atmel_mpopfb_check_var(&info->var, info);
-+
-+	ret = fb_set_var(info, &info->var);
-+	if (ret) {
-+		dev_warn(dev, "unable to set display parameters\n");
-+		goto free_cmap;
-+	}
-+
-+	dev_set_drvdata(dev, info);
-+
-+	/*
-+	 * Tell the world that we're ready to go
-+	 */
-+	ret = register_framebuffer(info);
-+	if (ret < 0) {
-+		dev_err(dev, "failed to register framebuffer device: %d\n",
-+			ret);
-+		goto free_cmap;
-+	}
-+
-+	dev_info(dev, "fb%d: Atmel MPOP at 0x%08lx (mapped at %p), irq %lu\n",
-+		 info->node, info->fix.mmio_start, sinfo->mmio,
-+		 sinfo->irq_base);
-+
-+	return 0;
-+
-+free_cmap:
-+	fb_dealloc_cmap(&info->cmap);
-+unregister_irqs:
-+	free_irq(sinfo->irq_base, info);
-+release_mem_slave:
-+	release_mem_region(slave->start, slave->end - slave->start + 1);
-+unmap_mmio:
-+	iounmap(sinfo->mmio);
-+release_mem:
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+free_fb:
-+	if (map)
-+		iounmap(info->screen_base);
-+	else
-+		atmel_mpopfb_free_video_memory(sinfo);
-+
-+release_intmem:
-+	if (map)
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+stop_clk:
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+put_bus_clk:
-+	if (sinfo->mpop_pclk)
-+		clk_put(sinfo->mpop_pclk);
-+free_info:
-+	framebuffer_release(info);
-+out:
-+	dev_dbg(dev, "%s FAILED\n", __func__);
-+	return ret;
-+}
-+
-+static int __exit atmel_mpopfb_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct fb_info *info = dev_get_drvdata(dev);
-+	struct atmel_mpopfb_info *sinfo = info->par;
-+
-+	if (!sinfo)
-+		return 0;
-+
-+	unregister_framebuffer(info);
-+	atmel_mpopfb_stop_clock(sinfo);
-+	clk_put(sinfo->mpop_hclk);
-+	clk_put(sinfo->mpop_pclk);
-+	fb_dealloc_cmap(&info->cmap);
-+	free_irq(sinfo->irq_base, info);
-+	iounmap(sinfo->mmio);
-+	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-+	if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
-+		iounmap(info->screen_base);
-+		release_mem_region(info->fix.smem_start, info->fix.smem_len);
-+	} else {
-+		atmel_mpopfb_free_video_memory(sinfo);
-+	}
-+
-+	dev_set_drvdata(dev, NULL);
-+	framebuffer_release(info);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver atmel_mpopfb_driver = {
-+	.remove = __exit_p(atmel_mpopfb_remove),
-+	.driver.name = "atmel_mpopfb",
-+	.driver.owner = THIS_MODULE,
-+};
-+
-+static int __init atmel_mpopfb_init(void)
-+{
-+	return platform_driver_probe(&atmel_mpopfb_driver, atmel_mpopfb_probe);
-+}
-+
-+static void __exit atmel_mpopfb_exit(void)
-+{
-+	platform_driver_unregister(&atmel_mpopfb_driver);
-+}
-+
-+module_init(atmel_mpopfb_init);
-+module_exit(atmel_mpopfb_exit);
-+
-+MODULE_DESCRIPTION("AT32 MPOP framebuffer driver");
-+MODULE_AUTHOR("Ronny Pedersen <rpedersen at atmel.com>");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
-index c510367..55a3a34 100644
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -221,12 +221,12 @@ config DAVINCI_WATCHDOG
- 
- # AVR32 Architecture
- 
--config AT32AP700X_WDT
--	tristate "AT32AP700x watchdog"
--	depends on CPU_AT32AP700X
-+config AT32_WDT
-+	tristate "AVR32 On-Chip Watchdog Timer"
-+	depends on AVR32
- 	help
--	  Watchdog timer embedded into AT32AP700x devices. This will reboot
--	  your system when the timeout is reached.
-+	  Watchdog timer embedded into AT32AP700x and similar devices.
-+	  This will reboot your system when the timeout is reached.
- 
- # BLACKFIN Architecture
- 
-diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
-index e0ef123..7db92cd 100644
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -43,7 +43,7 @@ obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
- # ARM26 Architecture
- 
- # AVR32 Architecture
--obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
-+obj-$(CONFIG_AT32_WDT) += at32_wdt.o
- 
- # BLACKFIN Architecture
- obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o
-diff --git a/drivers/watchdog/at32_wdt.c b/drivers/watchdog/at32_wdt.c
-new file mode 100644
-index 0000000..bbdb997
---- /dev/null
-+++ b/drivers/watchdog/at32_wdt.c
-@@ -0,0 +1,620 @@
-+/*
-+ * Watchdog driver for Atmel AVR32 devices
-+ *
-+ * Copyright (C) 2005-2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ *
-+ * AT32AP700x Errata: WDT Clear is blocked after WDT Reset
-+ *
-+ * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-+ * register, preventing the program to clear the next Watchdog Timer Reset.
-+ *
-+ * If you still want to use the WDT after a WDT reset a small code can be
-+ * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-+ * and use a GPIO pin to reset the system. This method requires that one of the
-+ * GPIO pins are available and connected externally to the RESET_N pin. After
-+ * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-+ * the pin tristated with pullup.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/platform_device.h>
-+#include <linux/watchdog.h>
-+#include <linux/uaccess.h>
-+#include <linux/io.h>
-+#include <linux/log2.h>
-+#include <linux/spinlock.h>
-+
-+#include <mach/cpu.h>
-+#include <mach/pm.h>
-+
-+/*
-+ * AT32AP700x uses a 16-bit prescaler. This limits the timeout range
-+ * somewhat. Later chips use a 32-bit prescaler.
-+ */
-+#define TIMEOUT_MIN		1
-+#ifdef CONFIG_CPU_AT32AP700X
-+# define TIMEOUT_MAX		2
-+# define TIMEOUT_DEFAULT	TIMEOUT_MAX
-+#else
-+# define TIMEOUT_MAX		131072
-+# define TIMEOUT_DEFAULT	64
-+#endif
-+
-+/* module parameters */
-+static int timeout =  TIMEOUT_DEFAULT;
-+module_param(timeout, int, 0);
-+MODULE_PARM_DESC(timeout,
-+		"Timeout value. Any power of two between 1 and "
-+		__MODULE_STRING(TIMEOUT_MAX) " seconds. (default="
-+		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
-+
-+static int nowayout = WATCHDOG_NOWAYOUT;
-+module_param(nowayout, int, 0);
-+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
-+		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
-+
-+/* Watchdog registers and write/read macro */
-+#define WDT_CTRL		0x00
-+#define WDT_CTRL_EN		   0
-+#define WDT_CTRL_PSEL		   8
-+#define WDT_CTRL_CEN		  16
-+#define WDT_CTRL_CSEL		  17
-+#define WDT_CTRL_KEY		  24
-+
-+#define WDT_CLR			0x04
-+
-+#define WDT_BIT(name)		(1 << WDT_##name)
-+#define WDT_BF(name, value)	((value) << WDT_##name)
-+
-+#define wdt_readl(dev, reg)				\
-+	__raw_readl((dev)->regs + WDT_##reg)
-+#define wdt_writel(dev, reg, value)			\
-+	__raw_writel((value), (dev)->regs + WDT_##reg)
-+
-+struct wdt_at32 {
-+	void __iomem		*regs;
-+	struct clk		*pclk;
-+	struct clk		*src_clk;
-+	spinlock_t		io_lock;
-+	int			timeout;
-+	int			boot_status;
-+	unsigned long		users;
-+	struct miscdevice	miscdev;
-+};
-+
-+static struct wdt_at32 *wdt;
-+static char expect_release;
-+
-+static inline void wdt_clk_enable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_enable(w->pclk);
-+}
-+
-+static inline void wdt_clk_disable(struct wdt_at32 *w)
-+{
-+	if (!cpu_is_at32ap7000())
-+		clk_disable(w->pclk);
-+}
-+
-+static inline int at32_wdt_version(void)
-+{
-+	if (cpu_is_at32ap7000())
-+		return 1;
-+	if (cpu_is_at32ap7200())
-+		return 3;
-+
-+	BUG();
-+}
-+
-+static unsigned long at32_wdt_calc_psel(int timeout)
-+{
-+	if (at32_wdt_version() == 1)
-+		/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
-+		return (timeout > 1) ? 0xf : 0xe;
-+
-+	return order_base_2(timeout) + 14;
-+}
-+
-+/*
-+ * Disable the watchdog.
-+ */
-+static inline void at32_wdt_stop(void)
-+{
-+	unsigned long ctrl;
-+	unsigned long ctrl_mask = 0;
-+
-+	switch (at32_wdt_version()) {
-+	case 3:
-+		ctrl_mask |= (1 << WDT_CTRL_CEN) | (1 << WDT_CTRL_CSEL);
-+		/* fall through */
-+	case 2:
-+		ctrl_mask |= 0x1f << WDT_CTRL_PSEL;
-+		break;
-+	case 1:
-+		ctrl_mask |= 0x0f << WDT_CTRL_PSEL;
-+		break;
-+	}
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	ctrl = wdt_readl(wdt, CTRL);
-+	ctrl &= ctrl_mask;
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Enable and reset the watchdog.
-+ */
-+static inline void at32_wdt_start(void)
-+{
-+	unsigned long psel;
-+	unsigned long ctrl;
-+
-+	psel = at32_wdt_calc_psel(wdt->timeout);
-+	ctrl = WDT_BIT(CTRL_EN) | WDT_BF(CTRL_PSEL, psel);
-+
-+	if (at32_wdt_version() >= 3)
-+		ctrl |= wdt_readl(wdt, CTRL)
-+			& (WDT_BIT(CTRL_CSEL) | WDT_BIT(CTRL_CEN));
-+
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0x55));
-+	wdt_writel(wdt, CTRL, ctrl | WDT_BF(CTRL_KEY, 0xaa));
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Pat the watchdog timer.
-+ */
-+static inline void at32_wdt_pat(void)
-+{
-+	wdt_clk_enable(wdt);
-+	spin_lock(&wdt->io_lock);
-+	wdt_writel(wdt, CLR, 0x42);
-+	spin_unlock(&wdt->io_lock);
-+	wdt_clk_disable(wdt);
-+}
-+
-+/*
-+ * Watchdog device is opened, and watchdog starts running.
-+ */
-+static int at32_wdt_open(struct inode *inode, struct file *file)
-+{
-+	if (test_and_set_bit(1, &wdt->users))
-+		return -EBUSY;
-+
-+	at32_wdt_start();
-+	return nonseekable_open(inode, file);
-+}
-+
-+/*
-+ * Close the watchdog device.
-+ */
-+static int at32_wdt_close(struct inode *inode, struct file *file)
-+{
-+	if (expect_release == 42) {
-+		at32_wdt_stop();
-+	} else {
-+		dev_dbg(wdt->miscdev.parent,
-+			"unexpected close, not stopping watchdog!\n");
-+		at32_wdt_pat();
-+	}
-+	clear_bit(1, &wdt->users);
-+	expect_release = 0;
-+	return 0;
-+}
-+
-+/*
-+ * Change the watchdog time interval.
-+ */
-+static int at32_wdt_settimeout(int time)
-+{
-+	/*
-+	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max
-+	 * prescaler is 2 ^ 16 (or 2 ^ 32) allowing up to TIMEOUT_MAX
-+	 * seconds timeout.
-+	 */
-+	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX)
-+			|| !is_power_of_2(time))
-+		return -EINVAL;
-+
-+	/*
-+	 * Set new watchdog time. It will be used when at32_wdt_start() is
-+	 * called.
-+	 */
-+	wdt->timeout = time;
-+	return 0;
-+}
-+
-+/*
-+ * Get the watchdog status.
-+ */
-+static int at32_wdt_get_status(void)
-+{
-+	int rcause;
-+	int status = 0;
-+
-+	rcause = at32_get_reset_cause();
-+
-+	switch (rcause) {
-+	case AT32_RCAUSE_BOD:
-+		status = WDIOF_POWERUNDER;
-+		break;
-+	case AT32_RCAUSE_EXT:
-+		status = WDIOF_EXTERN1;
-+		break;
-+	case AT32_RCAUSE_JTAG:
-+	case AT32_RCAUSE_JTAGHARD:
-+	case AT32_RCAUSE_OCDRST:
-+		status = WDIOF_EXTERN2;
-+		break;
-+	case AT32_RCAUSE_WDT:
-+		status = WDIOF_CARDRESET;
-+		break;
-+	case AT32_RCAUSE_POR:
-+	case AT32_RCAUSE_NTAE:
-+	case AT32_RCAUSE_SLEEP:
-+	case AT32_RCAUSE_CPUERR:
-+	default:
-+		break;
-+	}
-+
-+	return status;
-+}
-+
-+static struct watchdog_info at32_wdt_info = {
-+	.identity	= "at32 watchdog",
-+	.options	= WDIOF_SETTIMEOUT |
-+			  WDIOF_KEEPALIVEPING |
-+			  WDIOF_MAGICCLOSE,
-+};
-+
-+/*
-+ * Handle commands from user-space.
-+ */
-+static long at32_wdt_ioctl(struct file *file,
-+				unsigned int cmd, unsigned long arg)
-+{
-+	int ret = -ENOTTY;
-+	int time;
-+	void __user *argp = (void __user *)arg;
-+	int __user *p = argp;
-+
-+	switch (cmd) {
-+	case WDIOC_GETSUPPORT:
-+		ret = copy_to_user(argp, &at32_wdt_info,
-+				sizeof(at32_wdt_info)) ? -EFAULT : 0;
-+		break;
-+	case WDIOC_GETSTATUS:
-+		ret = put_user(0, p);
-+		break;
-+	case WDIOC_GETBOOTSTATUS:
-+		ret = put_user(wdt->boot_status, p);
-+		break;
-+	case WDIOC_SETOPTIONS:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		if (time & WDIOS_DISABLECARD)
-+			at32_wdt_stop();
-+		if (time & WDIOS_ENABLECARD)
-+			at32_wdt_start();
-+		ret = 0;
-+		break;
-+	case WDIOC_KEEPALIVE:
-+		at32_wdt_pat();
-+		ret = 0;
-+		break;
-+	case WDIOC_SETTIMEOUT:
-+		ret = get_user(time, p);
-+		if (ret)
-+			break;
-+		ret = at32_wdt_settimeout(time);
-+		if (ret)
-+			break;
-+		/* Enable new time value */
-+		at32_wdt_start();
-+		/* fall through */
-+	case WDIOC_GETTIMEOUT:
-+		ret = put_user(wdt->timeout, p);
-+		break;
-+	}
-+
-+	return ret;
-+}
-+
-+static ssize_t at32_wdt_write(struct file *file, const char __user *data,
-+				size_t len, loff_t *ppos)
-+{
-+	/* See if we got the magic character 'V' and reload the timer */
-+	if (len) {
-+		if (!nowayout) {
-+			size_t i;
-+
-+			/*
-+			 * note: just in case someone wrote the magic
-+			 * character five months ago...
-+			 */
-+			expect_release = 0;
-+
-+			/*
-+			 * scan to see whether or not we got the magic
-+			 * character
-+			 */
-+			for (i = 0; i != len; i++) {
-+				char c;
-+				if (get_user(c, data + i))
-+					return -EFAULT;
-+				if (c == 'V')
-+					expect_release = 42;
-+			}
-+		}
-+		/* someone wrote to us, we should pat the watchdog */
-+		at32_wdt_pat();
-+	}
-+	return len;
-+}
-+
-+static const struct file_operations at32_wdt_fops = {
-+	.owner		= THIS_MODULE,
-+	.llseek		= no_llseek,
-+	.unlocked_ioctl	= at32_wdt_ioctl,
-+	.open		= at32_wdt_open,
-+	.release	= at32_wdt_close,
-+	.write		= at32_wdt_write,
-+};
-+
-+static int __init at32_wdt_enable_source_clock(struct platform_device *pdev)
-+{
-+	struct clk	*clk;
-+	unsigned int	csel;
-+	u32		ctrl;
-+
-+	/* Only v3+ have selectable source clock */
-+	if (at32_wdt_version() < 3)
-+		return 0;
-+
-+	csel = 1;
-+
-+	/*
-+	 * Prefer the much more accurate crystal oscillator in favor
-+	 * of the RC oscillator.
-+	 */
-+	clk = clk_get(NULL, "osc32");
-+	if (IS_ERR(clk)) {
-+		csel = 0;
-+		clk = clk_get(NULL, "rcosc");
-+	}
-+	if (IS_ERR(clk)) {
-+		dev_dbg(&pdev->dev, "No source clock\n");
-+		return -ENXIO;
-+	}
-+
-+	clk_enable(clk);
-+
-+	dev_info(&pdev->dev, "Using 32 kHz %s oscillator\n",
-+			csel ? "crystal" : "RC");
-+
-+	wdt_clk_enable(wdt);
-+	ctrl = (csel << WDT_CTRL_CSEL) | (1 << WDT_CTRL_CEN);
-+
-+	/*
-+	 * Make sure the WDT is disabled, and disable any clocks that
-+	 * may have been selected earlier.
-+	 */
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	/* Select the new clock */
-+	wdt_writel(wdt, CTRL, ctrl | (0x55 << WDT_CTRL_KEY));
-+	wdt_writel(wdt, CTRL, ctrl | (0xaa << WDT_CTRL_KEY));
-+
-+	/* Wait for the new clock to become usable */
-+	while (!(wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN)))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+	return 0;
-+}
-+
-+static void at32_wdt_disable_source_clock(void)
-+{
-+	wdt_clk_enable(wdt);
-+
-+	wdt_writel(wdt, CTRL, 0x55 << WDT_CTRL_KEY);
-+	wdt_writel(wdt, CTRL, 0xaa << WDT_CTRL_KEY);
-+
-+	/* Wait for the clock to become properly deselected */
-+	while (wdt_readl(wdt, CTRL) & (1 << WDT_CTRL_CEN))
-+		cpu_relax();
-+
-+	wdt_clk_disable(wdt);
-+}
-+
-+static int __init at32_wdt_probe(struct platform_device *pdev)
-+{
-+	struct resource	*regs;
-+	int ret;
-+
-+	if (wdt) {
-+		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
-+		return -EBUSY;
-+	}
-+
-+	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (!regs) {
-+		dev_dbg(&pdev->dev, "missing mmio resource\n");
-+		return -ENXIO;
-+	}
-+
-+	wdt = kzalloc(sizeof(struct wdt_at32), GFP_KERNEL);
-+	if (!wdt) {
-+		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
-+		return -ENOMEM;
-+	}
-+
-+	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+	if (!wdt->regs) {
-+		ret = -ENOMEM;
-+		dev_dbg(&pdev->dev, "could not map I/O memory\n");
-+		goto err_free;
-+	}
-+
-+	if (!cpu_is_at32ap7000()) {
-+		wdt->pclk = clk_get(&pdev->dev, "pclk");
-+		if (IS_ERR(wdt->pclk)) {
-+			dev_dbg(&pdev->dev, "no peripheral clock\n");
-+			ret = -ENXIO;
-+			goto err_iounmap;
-+		}
-+	}
-+
-+	ret = at32_wdt_enable_source_clock(pdev);
-+	if (ret)
-+		goto err_put_clk;
-+
-+	spin_lock_init(&wdt->io_lock);
-+	wdt->boot_status = at32_wdt_get_status();
-+
-+	/* Work-around for watchdog silicon errata. */
-+	if (cpu_is_at32ap7000()
-+			&& (wdt->boot_status & WDIOF_CARDRESET)) {
-+		dev_info(&pdev->dev, "CPU must be reset with external "
-+				"reset or POR due to silicon errata.\n");
-+		ret = -EIO;
-+		goto err_disable_source_clock;
-+	} else {
-+		wdt->users = 0;
-+	}
-+	wdt->miscdev.minor = WATCHDOG_MINOR;
-+	wdt->miscdev.name = "watchdog";
-+	wdt->miscdev.fops = &at32_wdt_fops;
-+
-+	if (at32_wdt_settimeout(timeout)) {
-+		at32_wdt_settimeout(TIMEOUT_DEFAULT);
-+		dev_dbg(&pdev->dev,
-+			"default timeout invalid, set to %d sec.\n",
-+			TIMEOUT_DEFAULT);
-+	}
-+
-+	ret = misc_register(&wdt->miscdev);
-+	if (ret) {
-+		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
-+		goto err_iounmap;
-+	}
-+
-+	platform_set_drvdata(pdev, wdt);
-+	wdt->miscdev.parent = &pdev->dev;
-+	dev_info(&pdev->dev,
-+		"AT32 WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
-+		wdt->regs, wdt->timeout, nowayout);
-+
-+	return 0;
-+
-+err_disable_source_clock:
-+	at32_wdt_disable_source_clock();
-+err_put_clk:
-+	if (!cpu_is_at32ap7000())
-+		clk_put(wdt->pclk);
-+err_iounmap:
-+	iounmap(wdt->regs);
-+err_free:
-+	kfree(wdt);
-+	wdt = NULL;
-+	return ret;
-+}
-+
-+static int __exit at32_wdt_remove(struct platform_device *pdev)
-+{
-+	if (wdt && platform_get_drvdata(pdev) == wdt) {
-+		/* Stop the timer before we leave */
-+		if (!nowayout) {
-+			at32_wdt_stop();
-+			at32_wdt_disable_source_clock();
-+		}
-+
-+		misc_deregister(&wdt->miscdev);
-+		if (!cpu_is_at32ap7000())
-+			clk_put(wdt->pclk);
-+		iounmap(wdt->regs);
-+		kfree(wdt);
-+		wdt = NULL;
-+		platform_set_drvdata(pdev, NULL);
-+	}
-+	return 0;
-+}
-+
-+static void at32_wdt_shutdown(struct platform_device *pdev)
-+{
-+	at32_wdt_stop();
-+}
-+
-+#ifdef CONFIG_PM
-+static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
-+{
-+	at32_wdt_stop();
-+	return 0;
-+}
-+
-+static int at32_wdt_resume(struct platform_device *pdev)
-+{
-+	if (wdt->users)
-+		at32_wdt_start();
-+	return 0;
-+}
-+#else
-+#define at32_wdt_suspend NULL
-+#define at32_wdt_resume NULL
-+#endif
-+
-+/* work with hotplug and coldplug */
-+MODULE_ALIAS("platform:at32_wdt");
-+
-+static struct platform_driver at32_wdt_driver = {
-+	.remove		= __exit_p(at32_wdt_remove),
-+	.suspend	= at32_wdt_suspend,
-+	.resume		= at32_wdt_resume,
-+	.driver		= {
-+		.name	= "at32_wdt",
-+		.owner	= THIS_MODULE,
-+	},
-+	.shutdown	= at32_wdt_shutdown,
-+};
-+
-+static int __init at32_wdt_init(void)
-+{
-+	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
-+}
-+module_init(at32_wdt_init);
-+
-+static void __exit at32_wdt_exit(void)
-+{
-+	platform_driver_unregister(&at32_wdt_driver);
-+}
-+module_exit(at32_wdt_exit);
-+
-+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt at atmel.com>");
-+MODULE_DESCRIPTION("Watchdog driver for Atmel AVR32 devices");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c
-deleted file mode 100644
-index e8ae638..0000000
---- a/drivers/watchdog/at32ap700x_wdt.c
-+++ /dev/null
-@@ -1,449 +0,0 @@
--/*
-- * Watchdog driver for Atmel AT32AP700X devices
-- *
-- * Copyright (C) 2005-2006 Atmel Corporation
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- *
-- *
-- * Errata: WDT Clear is blocked after WDT Reset
-- *
-- * A watchdog timer event will, after reset, block writes to the WDT_CLEAR
-- * register, preventing the program to clear the next Watchdog Timer Reset.
-- *
-- * If you still want to use the WDT after a WDT reset a small code can be
-- * insterted at the startup checking the AVR32_PM.rcause register for WDT reset
-- * and use a GPIO pin to reset the system. This method requires that one of the
-- * GPIO pins are available and connected externally to the RESET_N pin. After
-- * the GPIO pin has pulled down the reset line the GPIO will be reset and leave
-- * the pin tristated with pullup.
-- */
--
--#include <linux/init.h>
--#include <linux/kernel.h>
--#include <linux/module.h>
--#include <linux/moduleparam.h>
--#include <linux/miscdevice.h>
--#include <linux/fs.h>
--#include <linux/platform_device.h>
--#include <linux/watchdog.h>
--#include <linux/uaccess.h>
--#include <linux/io.h>
--#include <linux/spinlock.h>
--
--#define TIMEOUT_MIN		1
--#define TIMEOUT_MAX		2
--#define TIMEOUT_DEFAULT		TIMEOUT_MAX
--
--/* module parameters */
--static int timeout =  TIMEOUT_DEFAULT;
--module_param(timeout, int, 0);
--MODULE_PARM_DESC(timeout,
--		"Timeout value. Limited to be 1 or 2 seconds. (default="
--		__MODULE_STRING(TIMEOUT_DEFAULT) ")");
--
--static int nowayout = WATCHDOG_NOWAYOUT;
--module_param(nowayout, int, 0);
--MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
--		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
--
--/* Watchdog registers and write/read macro */
--#define WDT_CTRL		0x00
--#define WDT_CTRL_EN		   0
--#define WDT_CTRL_PSEL		   8
--#define WDT_CTRL_KEY		  24
--
--#define WDT_CLR			0x04
--
--#define WDT_RCAUSE		0x10
--#define WDT_RCAUSE_POR		   0
--#define WDT_RCAUSE_EXT		   2
--#define WDT_RCAUSE_WDT		   3
--#define WDT_RCAUSE_JTAG		   4
--#define WDT_RCAUSE_SERP		   5
--
--#define WDT_BIT(name)		(1 << WDT_##name)
--#define WDT_BF(name, value)	((value) << WDT_##name)
--
--#define wdt_readl(dev, reg)				\
--	__raw_readl((dev)->regs + WDT_##reg)
--#define wdt_writel(dev, reg, value)			\
--	__raw_writel((value), (dev)->regs + WDT_##reg)
--
--struct wdt_at32ap700x {
--	void __iomem		*regs;
--	spinlock_t		io_lock;
--	int			timeout;
--	int			boot_status;
--	unsigned long		users;
--	struct miscdevice	miscdev;
--};
--
--static struct wdt_at32ap700x *wdt;
--static char expect_release;
--
--/*
-- * Disable the watchdog.
-- */
--static inline void at32_wdt_stop(void)
--{
--	unsigned long psel;
--
--	spin_lock(&wdt->io_lock);
--	psel = wdt_readl(wdt, CTRL) & WDT_BF(CTRL_PSEL, 0x0f);
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, psel | WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Enable and reset the watchdog.
-- */
--static inline void at32_wdt_start(void)
--{
--	/* 0xf is 2^16 divider = 2 sec, 0xe is 2^15 divider = 1 sec */
--	unsigned long psel = (wdt->timeout > 1) ? 0xf : 0xe;
--
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0x55));
--	wdt_writel(wdt, CTRL, WDT_BIT(CTRL_EN)
--			| WDT_BF(CTRL_PSEL, psel)
--			| WDT_BF(CTRL_KEY, 0xaa));
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Pat the watchdog timer.
-- */
--static inline void at32_wdt_pat(void)
--{
--	spin_lock(&wdt->io_lock);
--	wdt_writel(wdt, CLR, 0x42);
--	spin_unlock(&wdt->io_lock);
--}
--
--/*
-- * Watchdog device is opened, and watchdog starts running.
-- */
--static int at32_wdt_open(struct inode *inode, struct file *file)
--{
--	if (test_and_set_bit(1, &wdt->users))
--		return -EBUSY;
--
--	at32_wdt_start();
--	return nonseekable_open(inode, file);
--}
--
--/*
-- * Close the watchdog device.
-- */
--static int at32_wdt_close(struct inode *inode, struct file *file)
--{
--	if (expect_release == 42) {
--		at32_wdt_stop();
--	} else {
--		dev_dbg(wdt->miscdev.parent,
--			"unexpected close, not stopping watchdog!\n");
--		at32_wdt_pat();
--	}
--	clear_bit(1, &wdt->users);
--	expect_release = 0;
--	return 0;
--}
--
--/*
-- * Change the watchdog time interval.
-- */
--static int at32_wdt_settimeout(int time)
--{
--	/*
--	 * All counting occurs at 1 / SLOW_CLOCK (32 kHz) and max prescaler is
--	 * 2 ^ 16 allowing up to 2 seconds timeout.
--	 */
--	if ((time < TIMEOUT_MIN) || (time > TIMEOUT_MAX))
--		return -EINVAL;
--
--	/*
--	 * Set new watchdog time. It will be used when at32_wdt_start() is
--	 * called.
--	 */
--	wdt->timeout = time;
--	return 0;
--}
--
--/*
-- * Get the watchdog status.
-- */
--static int at32_wdt_get_status(void)
--{
--	int rcause;
--	int status = 0;
--
--	rcause = wdt_readl(wdt, RCAUSE);
--
--	switch (rcause) {
--	case WDT_BIT(RCAUSE_EXT):
--		status = WDIOF_EXTERN1;
--		break;
--	case WDT_BIT(RCAUSE_WDT):
--		status = WDIOF_CARDRESET;
--		break;
--	case WDT_BIT(RCAUSE_POR):  /* fall through */
--	case WDT_BIT(RCAUSE_JTAG): /* fall through */
--	case WDT_BIT(RCAUSE_SERP): /* fall through */
--	default:
--		break;
--	}
--
--	return status;
--}
--
--static struct watchdog_info at32_wdt_info = {
--	.identity	= "at32ap700x watchdog",
--	.options	= WDIOF_SETTIMEOUT |
--			  WDIOF_KEEPALIVEPING |
--			  WDIOF_MAGICCLOSE,
--};
--
--/*
-- * Handle commands from user-space.
-- */
--static long at32_wdt_ioctl(struct file *file,
--				unsigned int cmd, unsigned long arg)
--{
--	int ret = -ENOTTY;
--	int time;
--	void __user *argp = (void __user *)arg;
--	int __user *p = argp;
--
--	switch (cmd) {
--	case WDIOC_GETSUPPORT:
--		ret = copy_to_user(argp, &at32_wdt_info,
--				sizeof(at32_wdt_info)) ? -EFAULT : 0;
--		break;
--	case WDIOC_GETSTATUS:
--		ret = put_user(0, p);
--		break;
--	case WDIOC_GETBOOTSTATUS:
--		ret = put_user(wdt->boot_status, p);
--		break;
--	case WDIOC_SETOPTIONS:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		if (time & WDIOS_DISABLECARD)
--			at32_wdt_stop();
--		if (time & WDIOS_ENABLECARD)
--			at32_wdt_start();
--		ret = 0;
--		break;
--	case WDIOC_KEEPALIVE:
--		at32_wdt_pat();
--		ret = 0;
--		break;
--	case WDIOC_SETTIMEOUT:
--		ret = get_user(time, p);
--		if (ret)
--			break;
--		ret = at32_wdt_settimeout(time);
--		if (ret)
--			break;
--		/* Enable new time value */
--		at32_wdt_start();
--		/* fall through */
--	case WDIOC_GETTIMEOUT:
--		ret = put_user(wdt->timeout, p);
--		break;
--	}
--
--	return ret;
--}
--
--static ssize_t at32_wdt_write(struct file *file, const char __user *data,
--				size_t len, loff_t *ppos)
--{
--	/* See if we got the magic character 'V' and reload the timer */
--	if (len) {
--		if (!nowayout) {
--			size_t i;
--
--			/*
--			 * note: just in case someone wrote the magic
--			 * character five months ago...
--			 */
--			expect_release = 0;
--
--			/*
--			 * scan to see whether or not we got the magic
--			 * character
--			 */
--			for (i = 0; i != len; i++) {
--				char c;
--				if (get_user(c, data + i))
--					return -EFAULT;
--				if (c == 'V')
--					expect_release = 42;
--			}
--		}
--		/* someone wrote to us, we should pat the watchdog */
--		at32_wdt_pat();
--	}
--	return len;
--}
--
--static const struct file_operations at32_wdt_fops = {
--	.owner		= THIS_MODULE,
--	.llseek		= no_llseek,
--	.unlocked_ioctl	= at32_wdt_ioctl,
--	.open		= at32_wdt_open,
--	.release	= at32_wdt_close,
--	.write		= at32_wdt_write,
--};
--
--static int __init at32_wdt_probe(struct platform_device *pdev)
--{
--	struct resource	*regs;
--	int ret;
--
--	if (wdt) {
--		dev_dbg(&pdev->dev, "only 1 wdt instance supported.\n");
--		return -EBUSY;
--	}
--
--	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--	if (!regs) {
--		dev_dbg(&pdev->dev, "missing mmio resource\n");
--		return -ENXIO;
--	}
--
--	wdt = kzalloc(sizeof(struct wdt_at32ap700x), GFP_KERNEL);
--	if (!wdt) {
--		dev_dbg(&pdev->dev, "no memory for wdt structure\n");
--		return -ENOMEM;
--	}
--
--	wdt->regs = ioremap(regs->start, regs->end - regs->start + 1);
--	if (!wdt->regs) {
--		ret = -ENOMEM;
--		dev_dbg(&pdev->dev, "could not map I/O memory\n");
--		goto err_free;
--	}
--
--	spin_lock_init(&wdt->io_lock);
--	wdt->boot_status = at32_wdt_get_status();
--
--	/* Work-around for watchdog silicon errata. */
--	if (wdt->boot_status & WDIOF_CARDRESET) {
--		dev_info(&pdev->dev, "CPU must be reset with external "
--				"reset or POR due to silicon errata.\n");
--		ret = -EIO;
--		goto err_iounmap;
--	} else {
--		wdt->users = 0;
--	}
--	wdt->miscdev.minor = WATCHDOG_MINOR;
--	wdt->miscdev.name = "watchdog";
--	wdt->miscdev.fops = &at32_wdt_fops;
--
--	if (at32_wdt_settimeout(timeout)) {
--		at32_wdt_settimeout(TIMEOUT_DEFAULT);
--		dev_dbg(&pdev->dev,
--			"default timeout invalid, set to %d sec.\n",
--			TIMEOUT_DEFAULT);
--	}
--
--	ret = misc_register(&wdt->miscdev);
--	if (ret) {
--		dev_dbg(&pdev->dev, "failed to register wdt miscdev\n");
--		goto err_iounmap;
--	}
--
--	platform_set_drvdata(pdev, wdt);
--	wdt->miscdev.parent = &pdev->dev;
--	dev_info(&pdev->dev,
--		"AT32AP700X WDT at 0x%p, timeout %d sec (nowayout=%d)\n",
--		wdt->regs, wdt->timeout, nowayout);
--
--	return 0;
--
--err_iounmap:
--	iounmap(wdt->regs);
--err_free:
--	kfree(wdt);
--	wdt = NULL;
--	return ret;
--}
--
--static int __exit at32_wdt_remove(struct platform_device *pdev)
--{
--	if (wdt && platform_get_drvdata(pdev) == wdt) {
--		/* Stop the timer before we leave */
--		if (!nowayout)
--			at32_wdt_stop();
--
--		misc_deregister(&wdt->miscdev);
--		iounmap(wdt->regs);
--		kfree(wdt);
--		wdt = NULL;
--		platform_set_drvdata(pdev, NULL);
--	}
--	return 0;
--}
--
--static void at32_wdt_shutdown(struct platform_device *pdev)
--{
--	at32_wdt_stop();
--}
--
--#ifdef CONFIG_PM
--static int at32_wdt_suspend(struct platform_device *pdev, pm_message_t message)
--{
--	at32_wdt_stop();
--	return 0;
--}
--
--static int at32_wdt_resume(struct platform_device *pdev)
--{
--	if (wdt->users)
--		at32_wdt_start();
--	return 0;
--}
--#else
--#define at32_wdt_suspend NULL
--#define at32_wdt_resume NULL
--#endif
--
--/* work with hotplug and coldplug */
--MODULE_ALIAS("platform:at32_wdt");
--
--static struct platform_driver at32_wdt_driver = {
--	.remove		= __exit_p(at32_wdt_remove),
--	.suspend	= at32_wdt_suspend,
--	.resume		= at32_wdt_resume,
--	.driver		= {
--		.name	= "at32_wdt",
--		.owner	= THIS_MODULE,
--	},
--	.shutdown	= at32_wdt_shutdown,
--};
--
--static int __init at32_wdt_init(void)
--{
--	return platform_driver_probe(&at32_wdt_driver, at32_wdt_probe);
--}
--module_init(at32_wdt_init);
--
--static void __exit at32_wdt_exit(void)
--{
--	platform_driver_unregister(&at32_wdt_driver);
--}
--module_exit(at32_wdt_exit);
--
--MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt at atmel.com>");
--MODULE_DESCRIPTION("Watchdog driver for Atmel AT32AP700X");
--MODULE_LICENSE("GPL");
--MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-diff --git a/include/linux/Kbuild b/include/linux/Kbuild
-index b68ec09..e69646d 100644
---- a/include/linux/Kbuild
-+++ b/include/linux/Kbuild
-@@ -23,6 +23,7 @@ header-y += atmapi.h
- header-y += atmarp.h
- header-y += atmbr2684.h
- header-y += atmclip.h
-+header-y += atmel_mpopfb.h
- header-y += atm_eni.h
- header-y += atm_he.h
- header-y += atm_idt77105.h
-diff --git a/include/linux/atmel_mpopfb.h b/include/linux/atmel_mpopfb.h
-new file mode 100644
-index 0000000..cd12e16
---- /dev/null
-+++ b/include/linux/atmel_mpopfb.h
-@@ -0,0 +1,112 @@
-+/*
-+ *  Header file for AT32 MPOP FB Driver
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOPFB_H__
-+#define __ATMEL_MPOPFB_H__
-+
-+#include <linux/fb.h>
-+#include <linux/ioctl.h>
-+
-+/* Coefficients for conversion to rgb. */
-+struct atmel_mpopfb_rgbconv_coeffs {
-+	int r1, r2, r3, r4;
-+	int g1, g2, g3, g4;
-+	int b1, b2, b3, b4;
-+};
-+
-+struct atmel_mpopfb_baseimg_info {
-+	/* Position of the mpop base image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+
-+	/* The size of the base image after scaling. */
-+	unsigned xsize;
-+	unsigned ysize;
-+
-+	/* Signal that we should flip the video. */
-+	int flip;
-+
-+};
-+
-+enum atmel_mpopfb_overlay_type {
-+	ATMEL_MPOPFB_OVERLAY1 = 0,
-+	ATMEL_MPOPFB_OVERLAY2 = 1,
-+	ATMEL_MPOPFB_CURSOR = 2
-+};
-+
-+struct atmel_mpopfb_overlay_info {
-+	/* Position of the mpop overlay image
-+	   in the image sent to the LCD. */
-+	unsigned xpos;
-+	unsigned ypos;
-+	/* The size of the overlay image. */
-+	unsigned xsize;
-+	unsigned ysize;
-+	/* Signal which overlay this info is for. */
-+	enum atmel_mpopfb_overlay_type overlay;
-+	/* Signal if the overlay is enabled. */
-+	unsigned enabled;
-+};
-+
-+struct atmel_mpopfb_overlay_palette_entry {
-+	unsigned char alpha;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_cursor_palette_entry {
-+	unsigned char:6;
-+	unsigned char invert:1;
-+	unsigned char visible:1;
-+	unsigned char red;
-+	unsigned char green;
-+	unsigned char blue;
-+};
-+
-+struct atmel_mpopfb_overlay_palette {
-+	struct atmel_mpopfb_overlay_palette_entry entry[256];
-+};
-+
-+struct atmel_mpopfb_cursor_palette {
-+	struct atmel_mpopfb_cursor_palette_entry entry[4];
-+};
-+
-+#define ATMEL_MPOP_FBIOPUT_BASEIMG_INFO        _IOW('x',0,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOGET_BASEIMG_INFO        _IOR('x',1,struct atmel_mpopfb_baseimg_info)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_INFO        _IOW('x',2,struct atmel_mpopfb_overlay_info)
-+#define ATMEL_MPOP_FBIO_CONNECT_TO_LCDC        _IO( 'x',4)
-+#define ATMEL_MPOP_FBIO_DISCONNECT_FROM_LCDC   _IO( 'x',5)
-+#define ATMEL_MPOP_FBIOPUT_RGBCONV_COEFFS      _IOW('x',6,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOGET_RGBCONV_COEFFS      _IOR('x',7,struct atmel_mpopfb_rgbconv_coeffs)
-+#define ATMEL_MPOP_FBIOPUT_OVERLAY_PALETTE     _IOW('x',8,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOGET_OVERLAY_PALETTE     _IOR('x',9,struct atmel_mpopfb_overlay_palette)
-+#define ATMEL_MPOP_FBIOPUT_CURSOR_PALETTE      _IOW('x',10,struct atmel_mpopfb_cursor_palette)
-+#define ATMEL_MPOP_FBIOGET_CURSOR_PALETTE      _IOR('x',11,struct atmel_mpopfb_cursor_palette)
-+
-+#define ATMEL_MPOP_RESIZE_FRAC_BITS 5
-+#define ATMEL_MPOP_SCALE_FRAC_DIV(a,b)  ((((a) << ATMEL_MPOP_RESIZE_FRAC_BITS))/(b))
-+#define ATMEL_MPOP_CALC_SCALE(from_res,to_res)  ATMEL_MPOP_SCALE_FRAC_DIV(from_res, to_res)
-+
-+#define ATMEL_MPOP_COEFF_FRAC_BITS 8
-+
-+#endif
-diff --git a/include/linux/atmel_pdca.h b/include/linux/atmel_pdca.h
-new file mode 100644
-index 0000000..a2ee314
---- /dev/null
-+++ b/include/linux/atmel_pdca.h
-@@ -0,0 +1,120 @@
-+/*
-+ * Driver for the Atmel PDCA Peripheral DMA Controller
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ATMEL_PDCA_H
-+#define __ATMEL_PDCA_H
-+
-+#include <linux/dmaengine.h>
-+#include <linux/interrupt.h>
-+#include <linux/kernel.h>
-+#include <linux/list.h>
-+
-+struct pdca_pdata {
-+	unsigned int		nr_channels;
-+};
-+
-+struct pdca_slave {
-+	struct dma_slave	slave;
-+	u8			tx_periph_id;
-+	u8			rx_periph_id;
-+};
-+
-+struct pdca_desc {
-+	/* This controller does not support hardware descriptors */
-+	struct scatterlist	*sg;
-+	int			sg_len;
-+	u8			reg_width;
-+	u8			periph_id;
-+
-+	struct list_head	desc_node;
-+	struct dma_async_tx_descriptor txd;
-+};
-+
-+struct pdca_chan {
-+	struct list_head	freelist;
-+	struct list_head	queue;
-+
-+	spinlock_t		lock;
-+	void __iomem		*regs;
-+
-+	struct scatterlist	*cur_sg;
-+	struct scatterlist	*next_sg;
-+
-+	struct tasklet_struct	tasklet;
-+
-+	dma_cookie_t		completed;
-+	struct dma_chan		chan;
-+	struct pdca_slave	*pslave;
-+	unsigned int		descs_allocated;
-+	bool			enabled;
-+};
-+
-+struct pdca_dev {
-+	struct clk		*hclk;
-+	struct clk		*pclk;
-+	struct dma_device	dma;
-+	void __iomem		*regs;
-+
-+	struct pdca_chan	chan[];
-+};
-+
-+static inline struct pdca_slave *dma_to_pdca_slave(struct dma_slave *slave)
-+{
-+	return container_of(slave, struct pdca_slave, slave);
-+}
-+
-+static inline struct pdca_desc *txd_to_pdca_desc(
-+		struct dma_async_tx_descriptor *txd)
-+{
-+	return container_of(txd, struct pdca_desc, txd);
-+}
-+
-+static inline struct pdca_chan *dma_to_pdca_chan(struct dma_chan *chan)
-+{
-+	return container_of(chan, struct pdca_chan, chan);
-+}
-+
-+static inline struct pdca_dev *dma_to_pdca_dev(struct dma_device *dma)
-+{
-+	return container_of(dma, struct pdca_dev, dma);
-+}
-+
-+/* PDCA per-channel register definitions */
-+#define PDCA_MAR		0x0000	/* Memory Address */
-+#define PDCA_PSR		0x0004	/* Peripheral Select */
-+#define PDCA_TCR		0x0008	/* Transfer Counter */
-+#define PDCA_MARR		0x000c	/* Memory Address Reload */
-+#define PDCA_TCRR		0x0010	/* Transfer Counter Reload */
-+#define PDCA_CR			0x0014	/* Control */
-+# define PDCA_CR_TEN		(  1 <<  0)	/* Transfer Enable */
-+# define PDCA_CR_TDIS		(  1 <<  1)	/* Transfer Disable */
-+# define PDCA_CR_ECLR		(  1 <<  8)	/* Error Clear */
-+#define PDCA_MR			0x0018	/* Mode */
-+# define PDCA_SIZE_BYTE		(  0 <<  0)	/* 8 bits per transfer */
-+# define PDCA_SIZE_HWORD	(  1 <<  0)	/* 16 bits per transfer */
-+# define PDCA_SIZE_WORD		(  2 <<  0)	/* 32 bits per transfer */
-+#define PDCA_SR			0x001c	/* Status */
-+# define PDCA_SR_TEN		(  1 <<  0)	/* Transfer Enabled */
-+#define PDCA_IER		0x0020	/* Interrupt Enable */
-+#define PDCA_IDR		0x0024	/* Interrupt Disable */
-+#define PDCA_IMR		0x0028	/* Interrupt Mask */
-+#define PDCA_ISR		0x002c	/* Interrupt Status */
-+# define PDCA_RCZ		(  1 <<  0)	/* Reload Counter Zero */
-+# define PDCA_TRC		(  1 <<  1)	/* Transfer Complete */
-+# define PDCA_TERR		(  1 <<  2)	/* Transfer Error */
-+
-+/* Address space occupied by one channel */
-+#define PDCA_CHAN_SIZE		0x40
-+
-+#define pdca_readl(base, reg)				\
-+	__raw_readl((base) + PDCA_##reg)
-+#define pdca_writel(base, reg, value)			\
-+	__raw_writel((value), (base) + PDCA_##reg)
-+
-+#endif /* __ATMEL_PDCA_H */
-diff --git a/include/linux/spi/atmel_spi.h b/include/linux/spi/atmel_spi.h
-new file mode 100644
-index 0000000..88ae568
---- /dev/null
-+++ b/include/linux/spi/atmel_spi.h
-@@ -0,0 +1,20 @@
-+/*
-+ * Driver for Atmel AT32 and AT91 SPI Controllers
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __LINUX_SPI_ATMEL_SPI_H
-+#define __LINUX_SPI_ATMEL_SPI_H
-+
-+struct atmel_spi_pdata {
-+#ifndef CONFIG_SPI_ATMEL_HAVE_PDC
-+	struct dma_slave	*rx_dma_slave;
-+	struct dma_slave	*tx_dma_slave;
-+#endif
-+};
-+
-+#endif /* __LINUX_SPI_ATMEL_SPI_H */
-diff --git a/include/video/atmel_mpop.h b/include/video/atmel_mpop.h
-new file mode 100644
-index 0000000..60270b8
---- /dev/null
-+++ b/include/video/atmel_mpop.h
-@@ -0,0 +1,820 @@
-+/*
-+ *  Header file for AT32 MPOP Controller
-+ *
-+ *  Data structure and register user interface
-+ *
-+ *  Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-+ */
-+#ifndef __ATMEL_MPOP_H__
-+#define __ATMEL_MPOP_H__
-+
-+#include <linux/atmel_mpopfb.h>
-+
-+/* MPOP Controller info data structure */
-+struct atmel_mpopfb_info {
-+	spinlock_t lock;
-+	struct fb_info *info;
-+	void __iomem *mmio;
-+	unsigned long irq_base;
-+	void *slave_base;
-+
-+	struct platform_device *pdev;
-+	struct platform_device *lcdc_pdev;
-+	struct clk *mpop_hclk;
-+	struct clk *mpop_pclk;
-+	unsigned int running;
-+	unsigned int connected_to_lcdc;
-+	unsigned long lcdc_old_smem_start;
-+	unsigned long lcdc_old_bits_per_pixel;
-+	struct atmel_mpopfb_baseimg_info baseimg_info;
-+	struct atmel_mpopfb_overlay_info overlay_info[3];
-+	struct atmel_mpopfb_rgbconv_coeffs rgbconv_coeffs;
-+};
-+
-+/* TODO! Clean up these defines.... */
-+#define ATMEL_MPOP_B                                                 0
-+#define ATMEL_MPOP_B1                                                0
-+#define ATMEL_MPOP_B1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B1_OFFSET                                         0
-+#define ATMEL_MPOP_B1_SIZE                                          12
-+#define ATMEL_MPOP_B2                                               12
-+#define ATMEL_MPOP_B2B1                                     0x00000024
-+#define ATMEL_MPOP_B2B1_B1                                           0
-+#define ATMEL_MPOP_B2B1_B1_MASK                             0x00000fff
-+#define ATMEL_MPOP_B2B1_B1_OFFSET                                    0
-+#define ATMEL_MPOP_B2B1_B1_SIZE                                     12
-+#define ATMEL_MPOP_B2B1_B2                                          12
-+#define ATMEL_MPOP_B2B1_B2_MASK                             0x00fff000
-+#define ATMEL_MPOP_B2B1_B2_OFFSET                                   12
-+#define ATMEL_MPOP_B2B1_B2_SIZE                                     12
-+#define ATMEL_MPOP_B2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_B2_OFFSET                                        12
-+#define ATMEL_MPOP_B2_SIZE                                          12
-+#define ATMEL_MPOP_B3                                                0
-+#define ATMEL_MPOP_B3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_B3_OFFSET                                         0
-+#define ATMEL_MPOP_B3_SIZE                                          12
-+#define ATMEL_MPOP_B4                                               12
-+#define ATMEL_MPOP_B4B3                                     0x00000028
-+#define ATMEL_MPOP_B4B3_B3                                           0
-+#define ATMEL_MPOP_B4B3_B3_MASK                             0x00000fff
-+#define ATMEL_MPOP_B4B3_B3_OFFSET                                    0
-+#define ATMEL_MPOP_B4B3_B3_SIZE                                     12
-+#define ATMEL_MPOP_B4B3_B4                                          12
-+#define ATMEL_MPOP_B4B3_B4_MASK                             0xfffff000
-+#define ATMEL_MPOP_B4B3_B4_OFFSET                                   12
-+#define ATMEL_MPOP_B4B3_B4_SIZE                                     20
-+#define ATMEL_MPOP_B4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_B4_OFFSET                                        12
-+#define ATMEL_MPOP_B4_SIZE                                          20
-+#define ATMEL_MPOP_BGCOLOR                                  0x00000090
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR                                   0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_MASK                     0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_OFFSET                            0
-+#define ATMEL_MPOP_BGCOLOR_BGCOLOR_SIZE                             32
-+#define ATMEL_MPOP_BGCOLOR_MASK                             0xffffffff
-+#define ATMEL_MPOP_BGCOLOR_OFFSET                                    0
-+#define ATMEL_MPOP_BGCOLOR_SIZE                                     32
-+#define ATMEL_MPOP_BGR                                               6
-+#define ATMEL_MPOP_BGR_MASK                                 0x00000040
-+#define ATMEL_MPOP_BGR_OFFSET                                        6
-+#define ATMEL_MPOP_BGR_SIZE                                          1
-+#define ATMEL_MPOP_B_MASK                                   0x000000ff
-+#define ATMEL_MPOP_B_OFFSET                                          0
-+#define ATMEL_MPOP_B_SIZE                                            8
-+#define ATMEL_MPOP_CACHEDIS                                          8
-+#define ATMEL_MPOP_CACHEDIS_MASK                            0x00000100
-+#define ATMEL_MPOP_CACHEDIS_OFFSET                                   8
-+#define ATMEL_MPOP_CACHEDIS_SIZE                                     1
-+#define ATMEL_MPOP_CR                                       0x00000000
-+#define ATMEL_MPOP_CR_CACHEDIS                                       8
-+#define ATMEL_MPOP_CR_CACHEDIS_MASK                         0x00000100
-+#define ATMEL_MPOP_CR_CACHEDIS_OFFSET                                8
-+#define ATMEL_MPOP_CR_CACHEDIS_SIZE                                  1
-+#define ATMEL_MPOP_CR_EN                                             0
-+#define ATMEL_MPOP_CR_EN_MASK                               0x00000001
-+#define ATMEL_MPOP_CR_EN_OFFSET                                      0
-+#define ATMEL_MPOP_CR_EN_SIZE                                        1
-+#define ATMEL_MPOP_CR_OUT_BGR                                        3
-+#define ATMEL_MPOP_CR_OUT_BGR_MASK                          0x00000008
-+#define ATMEL_MPOP_CR_OUT_BGR_OFFSET                                 3
-+#define ATMEL_MPOP_CR_OUT_BGR_SIZE                                   1
-+#define ATMEL_MPOP_CR_OUT_CTRL                                       2
-+#define ATMEL_MPOP_CR_OUT_CTRL_MASK                         0x00000004
-+#define ATMEL_MPOP_CR_OUT_CTRL_OFFSET                                2
-+#define ATMEL_MPOP_CR_OUT_CTRL_SIZE                                  1
-+#define ATMEL_MPOP_CR_START                                          1
-+#define ATMEL_MPOP_CR_START_MASK                            0x00000002
-+#define ATMEL_MPOP_CR_START_OFFSET                                   1
-+#define ATMEL_MPOP_CR_START_SIZE                                     1
-+#define ATMEL_MPOP_CURSOREN                                          0
-+#define ATMEL_MPOP_CURSOREN_MASK                            0x00000001
-+#define ATMEL_MPOP_CURSOREN_OFFSET                                   0
-+#define ATMEL_MPOP_CURSOREN_SIZE                                     1
-+#define ATMEL_MPOP_CURSOR_P0                                0x00000080
-+#define ATMEL_MPOP_CURSOR_P0_B                                       0
-+#define ATMEL_MPOP_CURSOR_P0_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P0_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P0_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_G                                       8
-+#define ATMEL_MPOP_CURSOR_P0_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P0_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P0_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P0_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P0_R                                      16
-+#define ATMEL_MPOP_CURSOR_P0_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P0_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P0_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P0_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P1                                0x00000084
-+#define ATMEL_MPOP_CURSOR_P1_B                                       0
-+#define ATMEL_MPOP_CURSOR_P1_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P1_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P1_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_G                                       8
-+#define ATMEL_MPOP_CURSOR_P1_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P1_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P1_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P1_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P1_R                                      16
-+#define ATMEL_MPOP_CURSOR_P1_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P1_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P1_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P1_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P2                                0x00000088
-+#define ATMEL_MPOP_CURSOR_P2_B                                       0
-+#define ATMEL_MPOP_CURSOR_P2_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P2_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P2_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_G                                       8
-+#define ATMEL_MPOP_CURSOR_P2_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P2_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P2_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P2_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P2_R                                      16
-+#define ATMEL_MPOP_CURSOR_P2_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P2_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P2_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P2_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_P3                                0x0000008c
-+#define ATMEL_MPOP_CURSOR_P3_B                                       0
-+#define ATMEL_MPOP_CURSOR_P3_B_MASK                         0x000000ff
-+#define ATMEL_MPOP_CURSOR_P3_B_OFFSET                                0
-+#define ATMEL_MPOP_CURSOR_P3_B_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_G                                       8
-+#define ATMEL_MPOP_CURSOR_P3_G_MASK                         0x0000ff00
-+#define ATMEL_MPOP_CURSOR_P3_G_OFFSET                                8
-+#define ATMEL_MPOP_CURSOR_P3_G_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_INVERT                                 25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_MASK                    0x02000000
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_OFFSET                          25
-+#define ATMEL_MPOP_CURSOR_P3_INVERT_SIZE                             1
-+#define ATMEL_MPOP_CURSOR_P3_R                                      16
-+#define ATMEL_MPOP_CURSOR_P3_R_MASK                         0x00ff0000
-+#define ATMEL_MPOP_CURSOR_P3_R_OFFSET                               16
-+#define ATMEL_MPOP_CURSOR_P3_R_SIZE                                  8
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE                                24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_MASK                   0x01000000
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_OFFSET                         24
-+#define ATMEL_MPOP_CURSOR_P3_VISIBLE_SIZE                            1
-+#define ATMEL_MPOP_CURSOR_POS                               0x00000058
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X                          11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_MASK             0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_OFFSET                   11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_X_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y                           0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_MASK             0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_OFFSET                    0
-+#define ATMEL_MPOP_CURSOR_POS_CURSOR_POS_Y_SIZE                     11
-+#define ATMEL_MPOP_CURSOR_POS_X                                     11
-+#define ATMEL_MPOP_CURSOR_POS_X_MASK                        0x003ff800
-+#define ATMEL_MPOP_CURSOR_POS_X_OFFSET                              11
-+#define ATMEL_MPOP_CURSOR_POS_X_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_POS_Y                                      0
-+#define ATMEL_MPOP_CURSOR_POS_Y_MASK                        0x000007ff
-+#define ATMEL_MPOP_CURSOR_POS_Y_OFFSET                               0
-+#define ATMEL_MPOP_CURSOR_POS_Y_SIZE                                11
-+#define ATMEL_MPOP_CURSOR_SAR                               0x00000048
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR                             0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_SAR_CURSOR_SAR_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_SAR_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_SAR_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_SAR_SIZE                                  32
-+#define ATMEL_MPOP_CURSOR_SIZE                              0x0000006c
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X                        11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_MASK           0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_OFFSET                 11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_X_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y                         0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_MASK           0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_OFFSET                  0
-+#define ATMEL_MPOP_CURSOR_SIZE_CURSOR_SIZE_Y_SIZE                   11
-+#define ATMEL_MPOP_CURSOR_SIZE_X                                    11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_MASK                       0x003ff800
-+#define ATMEL_MPOP_CURSOR_SIZE_X_OFFSET                             11
-+#define ATMEL_MPOP_CURSOR_SIZE_X_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_SIZE_Y                                     0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_MASK                       0x000007ff
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_OFFSET                              0
-+#define ATMEL_MPOP_CURSOR_SIZE_Y_SIZE                               11
-+#define ATMEL_MPOP_CURSOR_WTC                               0x0000007c
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC                             0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_MASK               0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_OFFSET                      0
-+#define ATMEL_MPOP_CURSOR_WTC_CURSOR_WTC_SIZE                       32
-+#define ATMEL_MPOP_CURSOR_WTC_MASK                          0xffffffff
-+#define ATMEL_MPOP_CURSOR_WTC_OFFSET                                 0
-+#define ATMEL_MPOP_CURSOR_WTC_SIZE                                  32
-+#define ATMEL_MPOP_DISP_MAX_COORD                           0x00000010
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X                  11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_MASK     0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_OFFSET           11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_X_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y                   0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_MASK     0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_OFFSET            0
-+#define ATMEL_MPOP_DISP_MAX_COORD_DISP_MAX_COORD_Y_SIZE             11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X                                 11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_MASK                    0x003ff800
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_OFFSET                          11
-+#define ATMEL_MPOP_DISP_MAX_COORD_X_SIZE                            11
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y                                  0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_MASK                    0x000007ff
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_OFFSET                           0
-+#define ATMEL_MPOP_DISP_MAX_COORD_Y_SIZE                            11
-+#define ATMEL_MPOP_EN                                                0
-+#define ATMEL_MPOP_EN_MASK                                  0x00000001
-+#define ATMEL_MPOP_EN_OFFSET                                         0
-+#define ATMEL_MPOP_EN_SIZE                                           1
-+#define ATMEL_MPOP_EOP                                               3
-+#define ATMEL_MPOP_EOP_MASK                                 0x00000008
-+#define ATMEL_MPOP_EOP_OFFSET                                        3
-+#define ATMEL_MPOP_EOP_SIZE                                          1
-+#define ATMEL_MPOP_G                                                 8
-+#define ATMEL_MPOP_G1                                                0
-+#define ATMEL_MPOP_G1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G1_OFFSET                                         0
-+#define ATMEL_MPOP_G1_SIZE                                          12
-+#define ATMEL_MPOP_G2                                               12
-+#define ATMEL_MPOP_G2G1                                     0x0000001c
-+#define ATMEL_MPOP_G2G1_G1                                           0
-+#define ATMEL_MPOP_G2G1_G1_MASK                             0x00000fff
-+#define ATMEL_MPOP_G2G1_G1_OFFSET                                    0
-+#define ATMEL_MPOP_G2G1_G1_SIZE                                     12
-+#define ATMEL_MPOP_G2G1_G2                                          12
-+#define ATMEL_MPOP_G2G1_G2_MASK                             0x00fff000
-+#define ATMEL_MPOP_G2G1_G2_OFFSET                                   12
-+#define ATMEL_MPOP_G2G1_G2_SIZE                                     12
-+#define ATMEL_MPOP_G2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_G2_OFFSET                                        12
-+#define ATMEL_MPOP_G2_SIZE                                          12
-+#define ATMEL_MPOP_G3                                                0
-+#define ATMEL_MPOP_G3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_G3_OFFSET                                         0
-+#define ATMEL_MPOP_G3_SIZE                                          12
-+#define ATMEL_MPOP_G4                                               12
-+#define ATMEL_MPOP_G4G3                                     0x00000020
-+#define ATMEL_MPOP_G4G3_G3                                           0
-+#define ATMEL_MPOP_G4G3_G3_MASK                             0x00000fff
-+#define ATMEL_MPOP_G4G3_G3_OFFSET                                    0
-+#define ATMEL_MPOP_G4G3_G3_SIZE                                     12
-+#define ATMEL_MPOP_G4G3_G4                                          12
-+#define ATMEL_MPOP_G4G3_G4_MASK                             0xfffff000
-+#define ATMEL_MPOP_G4G3_G4_OFFSET                                   12
-+#define ATMEL_MPOP_G4G3_G4_SIZE                                     20
-+#define ATMEL_MPOP_G4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_G4_OFFSET                                        12
-+#define ATMEL_MPOP_G4_SIZE                                          20
-+#define ATMEL_MPOP_G_MASK                                   0x0000ff00
-+#define ATMEL_MPOP_G_OFFSET                                          8
-+#define ATMEL_MPOP_G_SIZE                                            8
-+#define ATMEL_MPOP_INTCLEAR                                 0x000000b0
-+#define ATMEL_MPOP_INTCLEAR_EOP                                      3
-+#define ATMEL_MPOP_INTCLEAR_EOP_MASK                        0x00000008
-+#define ATMEL_MPOP_INTCLEAR_EOP_OFFSET                               3
-+#define ATMEL_MPOP_INTCLEAR_EOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OUT                                      2
-+#define ATMEL_MPOP_INTCLEAR_OUT_MASK                        0x00000004
-+#define ATMEL_MPOP_INTCLEAR_OUT_OFFSET                               2
-+#define ATMEL_MPOP_INTCLEAR_OUT_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY                                  1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_MASK                    0x00000002
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_OFFSET                           1
-+#define ATMEL_MPOP_INTCLEAR_OVERLAY_SIZE                             1
-+#define ATMEL_MPOP_INTCLEAR_SOP                                      4
-+#define ATMEL_MPOP_INTCLEAR_SOP_MASK                        0x00000010
-+#define ATMEL_MPOP_INTCLEAR_SOP_OFFSET                               4
-+#define ATMEL_MPOP_INTCLEAR_SOP_SIZE                                 1
-+#define ATMEL_MPOP_INTCLEAR_YUV                                      0
-+#define ATMEL_MPOP_INTCLEAR_YUV_MASK                        0x00000001
-+#define ATMEL_MPOP_INTCLEAR_YUV_OFFSET                               0
-+#define ATMEL_MPOP_INTCLEAR_YUV_SIZE                                 1
-+#define ATMEL_MPOP_INTDIS                                   0x000000a4
-+#define ATMEL_MPOP_INTDIS_EOP                                        3
-+#define ATMEL_MPOP_INTDIS_EOP_MASK                          0x00000008
-+#define ATMEL_MPOP_INTDIS_EOP_OFFSET                                 3
-+#define ATMEL_MPOP_INTDIS_EOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OUT                                        2
-+#define ATMEL_MPOP_INTDIS_OUT_MASK                          0x00000004
-+#define ATMEL_MPOP_INTDIS_OUT_OFFSET                                 2
-+#define ATMEL_MPOP_INTDIS_OUT_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_OVERLAY                                    1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_MASK                      0x00000002
-+#define ATMEL_MPOP_INTDIS_OVERLAY_OFFSET                             1
-+#define ATMEL_MPOP_INTDIS_OVERLAY_SIZE                               1
-+#define ATMEL_MPOP_INTDIS_SOP                                        4
-+#define ATMEL_MPOP_INTDIS_SOP_MASK                          0x00000010
-+#define ATMEL_MPOP_INTDIS_SOP_OFFSET                                 4
-+#define ATMEL_MPOP_INTDIS_SOP_SIZE                                   1
-+#define ATMEL_MPOP_INTDIS_YUV                                        0
-+#define ATMEL_MPOP_INTDIS_YUV_MASK                          0x00000001
-+#define ATMEL_MPOP_INTDIS_YUV_OFFSET                                 0
-+#define ATMEL_MPOP_INTDIS_YUV_SIZE                                   1
-+#define ATMEL_MPOP_INTEN                                    0x000000a0
-+#define ATMEL_MPOP_INTEN_EOP                                         3
-+#define ATMEL_MPOP_INTEN_EOP_MASK                           0x00000008
-+#define ATMEL_MPOP_INTEN_EOP_OFFSET                                  3
-+#define ATMEL_MPOP_INTEN_EOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OUT                                         2
-+#define ATMEL_MPOP_INTEN_OUT_MASK                           0x00000004
-+#define ATMEL_MPOP_INTEN_OUT_OFFSET                                  2
-+#define ATMEL_MPOP_INTEN_OUT_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_OVERLAY                                     1
-+#define ATMEL_MPOP_INTEN_OVERLAY_MASK                       0x00000002
-+#define ATMEL_MPOP_INTEN_OVERLAY_OFFSET                              1
-+#define ATMEL_MPOP_INTEN_OVERLAY_SIZE                                1
-+#define ATMEL_MPOP_INTEN_SOP                                         4
-+#define ATMEL_MPOP_INTEN_SOP_MASK                           0x00000010
-+#define ATMEL_MPOP_INTEN_SOP_OFFSET                                  4
-+#define ATMEL_MPOP_INTEN_SOP_SIZE                                    1
-+#define ATMEL_MPOP_INTEN_YUV                                         0
-+#define ATMEL_MPOP_INTEN_YUV_MASK                           0x00000001
-+#define ATMEL_MPOP_INTEN_YUV_OFFSET                                  0
-+#define ATMEL_MPOP_INTEN_YUV_SIZE                                    1
-+#define ATMEL_MPOP_INTMASK                                  0x000000a8
-+#define ATMEL_MPOP_INTMASK_EOP                                       3
-+#define ATMEL_MPOP_INTMASK_EOP_MASK                         0x00000008
-+#define ATMEL_MPOP_INTMASK_EOP_OFFSET                                3
-+#define ATMEL_MPOP_INTMASK_EOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OUT                                       2
-+#define ATMEL_MPOP_INTMASK_OUT_MASK                         0x00000004
-+#define ATMEL_MPOP_INTMASK_OUT_OFFSET                                2
-+#define ATMEL_MPOP_INTMASK_OUT_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_OVERLAY                                   1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_MASK                     0x00000002
-+#define ATMEL_MPOP_INTMASK_OVERLAY_OFFSET                            1
-+#define ATMEL_MPOP_INTMASK_OVERLAY_SIZE                              1
-+#define ATMEL_MPOP_INTMASK_SOP                                       4
-+#define ATMEL_MPOP_INTMASK_SOP_MASK                         0x00000010
-+#define ATMEL_MPOP_INTMASK_SOP_OFFSET                                4
-+#define ATMEL_MPOP_INTMASK_SOP_SIZE                                  1
-+#define ATMEL_MPOP_INTMASK_YUV                                       0
-+#define ATMEL_MPOP_INTMASK_YUV_MASK                         0x00000001
-+#define ATMEL_MPOP_INTMASK_YUV_OFFSET                                0
-+#define ATMEL_MPOP_INTMASK_YUV_SIZE                                  1
-+#define ATMEL_MPOP_INTSTATUS                                0x000000ac
-+#define ATMEL_MPOP_INTSTATUS_EOP                                     3
-+#define ATMEL_MPOP_INTSTATUS_EOP_MASK                       0x00000008
-+#define ATMEL_MPOP_INTSTATUS_EOP_OFFSET                              3
-+#define ATMEL_MPOP_INTSTATUS_EOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OUT                                     2
-+#define ATMEL_MPOP_INTSTATUS_OUT_MASK                       0x00000004
-+#define ATMEL_MPOP_INTSTATUS_OUT_OFFSET                              2
-+#define ATMEL_MPOP_INTSTATUS_OUT_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY                                 1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_MASK                   0x00000002
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_OFFSET                          1
-+#define ATMEL_MPOP_INTSTATUS_OVERLAY_SIZE                            1
-+#define ATMEL_MPOP_INTSTATUS_SOP                                     4
-+#define ATMEL_MPOP_INTSTATUS_SOP_MASK                       0x00000010
-+#define ATMEL_MPOP_INTSTATUS_SOP_OFFSET                              4
-+#define ATMEL_MPOP_INTSTATUS_SOP_SIZE                                1
-+#define ATMEL_MPOP_INTSTATUS_YUV                                     0
-+#define ATMEL_MPOP_INTSTATUS_YUV_MASK                       0x00000001
-+#define ATMEL_MPOP_INTSTATUS_YUV_OFFSET                              0
-+#define ATMEL_MPOP_INTSTATUS_YUV_SIZE                                1
-+#define ATMEL_MPOP_INVERT                                           25
-+#define ATMEL_MPOP_INVERT_MASK                              0x02000000
-+#define ATMEL_MPOP_INVERT_OFFSET                                    25
-+#define ATMEL_MPOP_INVERT_SIZE                                       1
-+#define ATMEL_MPOP_MSTR_PTR                                 0x0000000c
-+#define ATMEL_MPOP_MSTR_PTR_MASK                            0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR                                 0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_MASK                   0xffffffff
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_OFFSET                          0
-+#define ATMEL_MPOP_MSTR_PTR_MSTR_PTR_SIZE                           32
-+#define ATMEL_MPOP_MSTR_PTR_OFFSET                                   0
-+#define ATMEL_MPOP_MSTR_PTR_SIZE                                    32
-+#define ATMEL_MPOP_O1EN                                              1
-+#define ATMEL_MPOP_O1EN_MASK                                0x00000002
-+#define ATMEL_MPOP_O1EN_OFFSET                                       1
-+#define ATMEL_MPOP_O1EN_SIZE                                         1
-+#define ATMEL_MPOP_O1_POS                                   0x00000050
-+#define ATMEL_MPOP_O1_POS_O1_POS_X                                  11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O1_POS_O1_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y                                   0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O1_POS_O1_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O1_POS_X                                         11
-+#define ATMEL_MPOP_O1_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O1_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O1_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O1_POS_Y                                          0
-+#define ATMEL_MPOP_O1_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O1_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O1_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O1_SAR                                   0x00000040
-+#define ATMEL_MPOP_O1_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR                                     0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O1_SAR_O1_SAR_SIZE                               32
-+#define ATMEL_MPOP_O1_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O1_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O1_SIZE                                  0x00000064
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X                                11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y                                 0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O1_SIZE_O1_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O1_SIZE_X                                        11
-+#define ATMEL_MPOP_O1_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O1_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O1_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O1_SIZE_Y                                         0
-+#define ATMEL_MPOP_O1_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O1_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O1_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O1_WTC                                   0x00000074
-+#define ATMEL_MPOP_O1_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC                                     0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O1_WTC_O1_WTC_SIZE                               32
-+#define ATMEL_MPOP_O1_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O1_WTC_SIZE                                      32
-+#define ATMEL_MPOP_O2EN                                              2
-+#define ATMEL_MPOP_O2EN_MASK                                0x00000004
-+#define ATMEL_MPOP_O2EN_OFFSET                                       2
-+#define ATMEL_MPOP_O2EN_SIZE                                         1
-+#define ATMEL_MPOP_O2_POS                                   0x00000054
-+#define ATMEL_MPOP_O2_POS_O2_POS_X                                  11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_OFFSET                           11
-+#define ATMEL_MPOP_O2_POS_O2_POS_X_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y                                   0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_OFFSET                            0
-+#define ATMEL_MPOP_O2_POS_O2_POS_Y_SIZE                             11
-+#define ATMEL_MPOP_O2_POS_X                                         11
-+#define ATMEL_MPOP_O2_POS_X_MASK                            0x003ff800
-+#define ATMEL_MPOP_O2_POS_X_OFFSET                                  11
-+#define ATMEL_MPOP_O2_POS_X_SIZE                                    11
-+#define ATMEL_MPOP_O2_POS_Y                                          0
-+#define ATMEL_MPOP_O2_POS_Y_MASK                            0x000007ff
-+#define ATMEL_MPOP_O2_POS_Y_OFFSET                                   0
-+#define ATMEL_MPOP_O2_POS_Y_SIZE                                    11
-+#define ATMEL_MPOP_O2_SAR                                   0x00000044
-+#define ATMEL_MPOP_O2_SAR_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR                                     0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_OFFSET                              0
-+#define ATMEL_MPOP_O2_SAR_O2_SAR_SIZE                               32
-+#define ATMEL_MPOP_O2_SAR_OFFSET                                     0
-+#define ATMEL_MPOP_O2_SAR_SIZE                                      32
-+#define ATMEL_MPOP_O2_SIZE                                  0x00000068
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X                                11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_OFFSET                         11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_X_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y                                 0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_OFFSET                          0
-+#define ATMEL_MPOP_O2_SIZE_O2_SIZE_Y_SIZE                           11
-+#define ATMEL_MPOP_O2_SIZE_X                                        11
-+#define ATMEL_MPOP_O2_SIZE_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_O2_SIZE_X_OFFSET                                 11
-+#define ATMEL_MPOP_O2_SIZE_X_SIZE                                   11
-+#define ATMEL_MPOP_O2_SIZE_Y                                         0
-+#define ATMEL_MPOP_O2_SIZE_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_O2_SIZE_Y_OFFSET                                  0
-+#define ATMEL_MPOP_O2_SIZE_Y_SIZE                                   11
-+#define ATMEL_MPOP_O2_WTC                                   0x00000078
-+#define ATMEL_MPOP_O2_WTC_MASK                              0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC                                     0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_MASK                       0xffffffff
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_OFFSET                              0
-+#define ATMEL_MPOP_O2_WTC_O2_WTC_SIZE                               32
-+#define ATMEL_MPOP_O2_WTC_OFFSET                                     0
-+#define ATMEL_MPOP_O2_WTC_SIZE                                      32
-+#define ATMEL_MPOP_OCR                                      0x00000008
-+#define ATMEL_MPOP_OCR_BGR                                           6
-+#define ATMEL_MPOP_OCR_BGR_MASK                             0x00000040
-+#define ATMEL_MPOP_OCR_BGR_OFFSET                                    6
-+#define ATMEL_MPOP_OCR_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OCR_CURSOREN                                      0
-+#define ATMEL_MPOP_OCR_CURSOREN_MASK                        0x00000001
-+#define ATMEL_MPOP_OCR_CURSOREN_OFFSET                               0
-+#define ATMEL_MPOP_OCR_CURSOREN_SIZE                                 1
-+#define ATMEL_MPOP_OCR_O1EN                                          1
-+#define ATMEL_MPOP_OCR_O1EN_MASK                            0x00000002
-+#define ATMEL_MPOP_OCR_O1EN_OFFSET                                   1
-+#define ATMEL_MPOP_OCR_O1EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_O2EN                                          2
-+#define ATMEL_MPOP_OCR_O2EN_MASK                            0x00000004
-+#define ATMEL_MPOP_OCR_O2EN_OFFSET                                   2
-+#define ATMEL_MPOP_OCR_O2EN_SIZE                                     1
-+#define ATMEL_MPOP_OCR_RGBEN                                         3
-+#define ATMEL_MPOP_OCR_RGBEN_MASK                           0x00000008
-+#define ATMEL_MPOP_OCR_RGBEN_OFFSET                                  3
-+#define ATMEL_MPOP_OCR_RGBEN_SIZE                                    1
-+#define ATMEL_MPOP_OCR_RGBFORM                                       5
-+#define ATMEL_MPOP_OCR_RGBFORM_MASK                         0x00000020
-+#define ATMEL_MPOP_OCR_RGBFORM_OFFSET                                5
-+#define ATMEL_MPOP_OCR_RGBFORM_SIZE                                  1
-+#define ATMEL_MPOP_OCR_RGBSRC                                        4
-+#define ATMEL_MPOP_OCR_RGBSRC_MASK                          0x00000010
-+#define ATMEL_MPOP_OCR_RGBSRC_OFFSET                                 4
-+#define ATMEL_MPOP_OCR_RGBSRC_SIZE                                   1
-+#define ATMEL_MPOP_OUT                                               2
-+#define ATMEL_MPOP_OUT_BEAR                                 0x0000009c
-+#define ATMEL_MPOP_OUT_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR                                 0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_OUT_BEAR_OUT_BEAR_SIZE                           32
-+#define ATMEL_MPOP_OUT_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_OUT_BGR                                           3
-+#define ATMEL_MPOP_OUT_BGR_MASK                             0x00000008
-+#define ATMEL_MPOP_OUT_BGR_OFFSET                                    3
-+#define ATMEL_MPOP_OUT_BGR_SIZE                                      1
-+#define ATMEL_MPOP_OUT_CTRL                                          2
-+#define ATMEL_MPOP_OUT_CTRL_MASK                            0x00000004
-+#define ATMEL_MPOP_OUT_CTRL_OFFSET                                   2
-+#define ATMEL_MPOP_OUT_CTRL_SIZE                                     1
-+#define ATMEL_MPOP_OUT_MASK                                 0x00000004
-+#define ATMEL_MPOP_OUT_OFFSET                                        2
-+#define ATMEL_MPOP_OUT_SIZE                                          1
-+#define ATMEL_MPOP_OVERLAY                                           1
-+#define ATMEL_MPOP_OVERLAY_BEAR                             0x00000098
-+#define ATMEL_MPOP_OVERLAY_BEAR_MASK                        0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OFFSET                               0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR                         0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_MASK           0xffffffff
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_OFFSET                  0
-+#define ATMEL_MPOP_OVERLAY_BEAR_OVERLAY_BEAR_SIZE                   32
-+#define ATMEL_MPOP_OVERLAY_BEAR_SIZE                                32
-+#define ATMEL_MPOP_OVERLAY_MASK                             0x00000002
-+#define ATMEL_MPOP_OVERLAY_OFFSET                                    1
-+#define ATMEL_MPOP_OVERLAY_SIZE                                      1
-+#define ATMEL_MPOP_PALETTEDATA                              0x00000400
-+#define ATMEL_MPOP_R                                                16
-+#define ATMEL_MPOP_R1                                                0
-+#define ATMEL_MPOP_R1_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R1_OFFSET                                         0
-+#define ATMEL_MPOP_R1_SIZE                                          12
-+#define ATMEL_MPOP_R2                                               12
-+#define ATMEL_MPOP_R2R1                                     0x00000014
-+#define ATMEL_MPOP_R2R1_R1                                           0
-+#define ATMEL_MPOP_R2R1_R1_MASK                             0x00000fff
-+#define ATMEL_MPOP_R2R1_R1_OFFSET                                    0
-+#define ATMEL_MPOP_R2R1_R1_SIZE                                     12
-+#define ATMEL_MPOP_R2R1_R2                                          12
-+#define ATMEL_MPOP_R2R1_R2_MASK                             0x00fff000
-+#define ATMEL_MPOP_R2R1_R2_OFFSET                                   12
-+#define ATMEL_MPOP_R2R1_R2_SIZE                                     12
-+#define ATMEL_MPOP_R2_MASK                                  0x00fff000
-+#define ATMEL_MPOP_R2_OFFSET                                        12
-+#define ATMEL_MPOP_R2_SIZE                                          12
-+#define ATMEL_MPOP_R3                                                0
-+#define ATMEL_MPOP_R3_MASK                                  0x00000fff
-+#define ATMEL_MPOP_R3_OFFSET                                         0
-+#define ATMEL_MPOP_R3_SIZE                                          12
-+#define ATMEL_MPOP_R4                                               12
-+#define ATMEL_MPOP_R4R3                                     0x00000018
-+#define ATMEL_MPOP_R4R3_R3                                           0
-+#define ATMEL_MPOP_R4R3_R3_MASK                             0x00000fff
-+#define ATMEL_MPOP_R4R3_R3_OFFSET                                    0
-+#define ATMEL_MPOP_R4R3_R3_SIZE                                     12
-+#define ATMEL_MPOP_R4R3_R4                                          12
-+#define ATMEL_MPOP_R4R3_R4_MASK                             0xfffff000
-+#define ATMEL_MPOP_R4R3_R4_OFFSET                                   12
-+#define ATMEL_MPOP_R4R3_R4_SIZE                                     20
-+#define ATMEL_MPOP_R4_MASK                                  0xfffff000
-+#define ATMEL_MPOP_R4_OFFSET                                        12
-+#define ATMEL_MPOP_R4_SIZE                                          20
-+#define ATMEL_MPOP_RGBEN                                             3
-+#define ATMEL_MPOP_RGBEN_MASK                               0x00000008
-+#define ATMEL_MPOP_RGBEN_OFFSET                                      3
-+#define ATMEL_MPOP_RGBEN_SIZE                                        1
-+#define ATMEL_MPOP_RGBFORM                                           5
-+#define ATMEL_MPOP_RGBFORM_MASK                             0x00000020
-+#define ATMEL_MPOP_RGBFORM_OFFSET                                    5
-+#define ATMEL_MPOP_RGBFORM_SIZE                                      1
-+#define ATMEL_MPOP_RGBSRC                                            4
-+#define ATMEL_MPOP_RGBSRC_MASK                              0x00000010
-+#define ATMEL_MPOP_RGBSRC_OFFSET                                     4
-+#define ATMEL_MPOP_RGBSRC_SIZE                                       1
-+#define ATMEL_MPOP_RGB_POS                                  0x0000004c
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X                                11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_MASK                   0x003ff800
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_OFFSET                         11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_X_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y                                 0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_MASK                   0x000007ff
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_OFFSET                          0
-+#define ATMEL_MPOP_RGB_POS_RGB_POS_Y_SIZE                           11
-+#define ATMEL_MPOP_RGB_POS_X                                        11
-+#define ATMEL_MPOP_RGB_POS_X_MASK                           0x003ff800
-+#define ATMEL_MPOP_RGB_POS_X_OFFSET                                 11
-+#define ATMEL_MPOP_RGB_POS_X_SIZE                                   11
-+#define ATMEL_MPOP_RGB_POS_Y                                         0
-+#define ATMEL_MPOP_RGB_POS_Y_MASK                           0x000007ff
-+#define ATMEL_MPOP_RGB_POS_Y_OFFSET                                  0
-+#define ATMEL_MPOP_RGB_POS_Y_SIZE                                   11
-+#define ATMEL_MPOP_RGB_SAR                                  0x0000003c
-+#define ATMEL_MPOP_RGB_SAR_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR                                   0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_OFFSET                            0
-+#define ATMEL_MPOP_RGB_SAR_RGB_SAR_SIZE                             32
-+#define ATMEL_MPOP_RGB_SAR_SIZE                                     32
-+#define ATMEL_MPOP_RGB_SIZE                                 0x00000060
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X                              11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_MASK                 0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_OFFSET                       11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_X_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y                               0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_MASK                 0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_OFFSET                        0
-+#define ATMEL_MPOP_RGB_SIZE_RGB_SIZE_Y_SIZE                         11
-+#define ATMEL_MPOP_RGB_SIZE_X                                       11
-+#define ATMEL_MPOP_RGB_SIZE_X_MASK                          0x003ff800
-+#define ATMEL_MPOP_RGB_SIZE_X_OFFSET                                11
-+#define ATMEL_MPOP_RGB_SIZE_X_SIZE                                  11
-+#define ATMEL_MPOP_RGB_SIZE_Y                                        0
-+#define ATMEL_MPOP_RGB_SIZE_Y_MASK                          0x000007ff
-+#define ATMEL_MPOP_RGB_SIZE_Y_OFFSET                                 0
-+#define ATMEL_MPOP_RGB_SIZE_Y_SIZE                                  11
-+#define ATMEL_MPOP_RGB_WTC                                  0x00000070
-+#define ATMEL_MPOP_RGB_WTC_MASK                             0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_OFFSET                                    0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC                                   0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_MASK                     0xffffffff
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_OFFSET                            0
-+#define ATMEL_MPOP_RGB_WTC_RGB_WTC_SIZE                             32
-+#define ATMEL_MPOP_RGB_WTC_SIZE                                     32
-+#define ATMEL_MPOP_R_MASK                                   0x00ff0000
-+#define ATMEL_MPOP_R_OFFSET                                         16
-+#define ATMEL_MPOP_R_SIZE                                            8
-+#define ATMEL_MPOP_SOP                                               4
-+#define ATMEL_MPOP_SOP_MASK                                 0x00000010
-+#define ATMEL_MPOP_SOP_OFFSET                                        4
-+#define ATMEL_MPOP_SOP_SIZE                                          1
-+#define ATMEL_MPOP_START                                             1
-+#define ATMEL_MPOP_START_MASK                               0x00000002
-+#define ATMEL_MPOP_START_OFFSET                                      1
-+#define ATMEL_MPOP_START_SIZE                                        1
-+#define ATMEL_MPOP_STRIDE                                   0x0000002c
-+#define ATMEL_MPOP_STRIDE_MASK                              0xffffffff
-+#define ATMEL_MPOP_STRIDE_OFFSET                                     0
-+#define ATMEL_MPOP_STRIDE_SIZE                                      32
-+#define ATMEL_MPOP_STRIDE_STRIDE                                     0
-+#define ATMEL_MPOP_STRIDE_STRIDE_MASK                       0xffffffff
-+#define ATMEL_MPOP_STRIDE_STRIDE_OFFSET                              0
-+#define ATMEL_MPOP_STRIDE_STRIDE_SIZE                               32
-+#define ATMEL_MPOP_U_SAR                                    0x00000034
-+#define ATMEL_MPOP_U_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_U_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_U_SAR_SIZE                                       32
-+#define ATMEL_MPOP_U_SAR_U_SAR                                       0
-+#define ATMEL_MPOP_U_SAR_U_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_U_SAR_U_SAR_OFFSET                                0
-+#define ATMEL_MPOP_U_SAR_U_SAR_SIZE                                 32
-+#define ATMEL_MPOP_VISIBLE                                          24
-+#define ATMEL_MPOP_VISIBLE_MASK                             0x01000000
-+#define ATMEL_MPOP_VISIBLE_OFFSET                                   24
-+#define ATMEL_MPOP_VISIBLE_SIZE                                      1
-+#define ATMEL_MPOP_V_SAR                                    0x00000038
-+#define ATMEL_MPOP_V_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_V_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_V_SAR_SIZE                                       32
-+#define ATMEL_MPOP_V_SAR_V_SAR                                       0
-+#define ATMEL_MPOP_V_SAR_V_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_V_SAR_V_SAR_OFFSET                                0
-+#define ATMEL_MPOP_V_SAR_V_SAR_SIZE                                 32
-+#define ATMEL_MPOP_XRESIZE                                          16
-+#define ATMEL_MPOP_XRESIZE_MASK                             0x00ff0000
-+#define ATMEL_MPOP_XRESIZE_OFFSET                                   16
-+#define ATMEL_MPOP_XRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YCR                                      0x00000004
-+#define ATMEL_MPOP_YCR_XRESIZE                                      16
-+#define ATMEL_MPOP_YCR_XRESIZE_MASK                         0x00ff0000
-+#define ATMEL_MPOP_YCR_XRESIZE_OFFSET                               16
-+#define ATMEL_MPOP_YCR_XRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YRESIZE                                       8
-+#define ATMEL_MPOP_YCR_YRESIZE_MASK                         0x0000ff00
-+#define ATMEL_MPOP_YCR_YRESIZE_OFFSET                                8
-+#define ATMEL_MPOP_YCR_YRESIZE_SIZE                                  8
-+#define ATMEL_MPOP_YCR_YUVFORMAT                                     0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_MASK                       0x00000003
-+#define ATMEL_MPOP_YCR_YUVFORMAT_OFFSET                              0
-+#define ATMEL_MPOP_YCR_YUVFORMAT_SIZE                                2
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_420              0x00000002
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_422              0x00000001
-+#define ATMEL_MPOP_YCR_YUVFORMAT_YUVFORMAT_444              0x00000000
-+#define ATMEL_MPOP_YRESIZE                                           8
-+#define ATMEL_MPOP_YRESIZE_MASK                             0x0000ff00
-+#define ATMEL_MPOP_YRESIZE_OFFSET                                    8
-+#define ATMEL_MPOP_YRESIZE_SIZE                                      8
-+#define ATMEL_MPOP_YUV                                               0
-+#define ATMEL_MPOP_YUVFORMAT                                         0
-+#define ATMEL_MPOP_YUVFORMAT_420                            0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_422                            0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_444                            0x00000000
-+#define ATMEL_MPOP_YUVFORMAT_MASK                           0x00000003
-+#define ATMEL_MPOP_YUVFORMAT_OFFSET                                  0
-+#define ATMEL_MPOP_YUVFORMAT_SIZE                                    2
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_420                  0x00000002
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_422                  0x00000001
-+#define ATMEL_MPOP_YUVFORMAT_YUVFORMAT_444                  0x00000000
-+#define ATMEL_MPOP_YUV_BEAR                                 0x00000094
-+#define ATMEL_MPOP_YUV_BEAR_MASK                            0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_OFFSET                                   0
-+#define ATMEL_MPOP_YUV_BEAR_SIZE                                    32
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR                                 0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_MASK                   0xffffffff
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_OFFSET                          0
-+#define ATMEL_MPOP_YUV_BEAR_YUV_BEAR_SIZE                           32
-+#define ATMEL_MPOP_YUV_MASK                                 0x00000001
-+#define ATMEL_MPOP_YUV_MAX_COORD                            0x0000005c
-+#define ATMEL_MPOP_YUV_MAX_COORD_X                                  11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_MASK                     0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_OFFSET                           11
-+#define ATMEL_MPOP_YUV_MAX_COORD_X_SIZE                             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y                                   0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X                    11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_MASK       0x003ff800
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_OFFSET             11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_X_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y                     0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_MASK       0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_OFFSET              0
-+#define ATMEL_MPOP_YUV_MAX_COORD_YUV_MAX_COORD_Y_SIZE               11
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_MASK                     0x000007ff
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_OFFSET                            0
-+#define ATMEL_MPOP_YUV_MAX_COORD_Y_SIZE                             11
-+#define ATMEL_MPOP_YUV_OFFSET                                        0
-+#define ATMEL_MPOP_YUV_SIZE                                          1
-+#define ATMEL_MPOP_Y_SAR                                    0x00000030
-+#define ATMEL_MPOP_Y_SAR_MASK                               0xffffffff
-+#define ATMEL_MPOP_Y_SAR_OFFSET                                      0
-+#define ATMEL_MPOP_Y_SAR_SIZE                                       32
-+#define ATMEL_MPOP_Y_SAR_Y_SAR                                       0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_MASK                         0xffffffff
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_OFFSET                                0
-+#define ATMEL_MPOP_Y_SAR_Y_SAR_SIZE                                 32
-+
-+#endif /* __ATMEL_MPOP_H__ */
-diff --git a/localversion-atmel b/localversion-atmel
-new file mode 100644
-index 0000000..b90deba
---- /dev/null
-+++ b/localversion-atmel
-@@ -0,0 +1 @@
-+.atmel.1
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-200-avr32-remove.note.gnu.build-id-section.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-200-avr32-remove.note.gnu.build-id-section.patch
deleted file mode 100644
index 6921de2..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-200-avr32-remove.note.gnu.build-id-section.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 474d77e07d5adfe7976b6f3ed131660867489778 Mon Sep 17 00:00:00 2001
-From: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-Date: Wed, 26 Nov 2008 11:38:35 +0100
-Subject: [PATCH 1/3] avr32: remove .note.gnu.build-id section when making vmlinux.bin
-
-This patch will remove the section .note.gnu.build-id added in binutils
-2.18 from the vmlinux.bin binary. Not removing this section results in a
-huge multiple gigabyte binary and likewize large uImage.
-
-Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-
-diff --git a/arch/avr32/boot/images/Makefile b/arch/avr32/boot/images/Makefile
-index 219720a..1848bf0 100644
---- a/arch/avr32/boot/images/Makefile
-+++ b/arch/avr32/boot/images/Makefile
-@@ -10,7 +10,7 @@ MKIMAGE		:= $(srctree)/scripts/mkuboot.sh
- 
- extra-y		:= vmlinux.bin vmlinux.gz
- 
--OBJCOPYFLAGS_vmlinux.bin := -O binary
-+OBJCOPYFLAGS_vmlinux.bin := -O binary -R .note.gnu.build-id
- $(obj)/vmlinux.bin: vmlinux FORCE
- 	$(call if_changed,objcopy)
- 
--- 
-1.5.6.3
-
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-201-avr32-atmel_mpopfb-disable-debug.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-201-avr32-atmel_mpopfb-disable-debug.patch
deleted file mode 100644
index 6cc4b67..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-201-avr32-atmel_mpopfb-disable-debug.patch
+++ /dev/null
@@ -1,23 +0,0 @@
-From f26e2224d46430ac4f6c0ddeb518f5766ba62b16 Mon Sep 17 00:00:00 2001
-From: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-Date: Wed, 26 Nov 2008 14:10:45 +0100
-Subject: [PATCH 2/3] atmel_mpopfb: remove define DEBUG to disable debug output
-
-Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-
-diff --git a/drivers/video/atmel_mpopfb.c b/drivers/video/atmel_mpopfb.c
-index 0a07f7b..3b4b668 100644
---- a/drivers/video/atmel_mpopfb.c
-+++ b/drivers/video/atmel_mpopfb.c
-@@ -8,8 +8,6 @@
-  * more details.
-  */
- 
--#define DEBUG
--
- #include <linux/clk.h>
- #include <linux/delay.h>
- #include <linux/dma-mapping.h>
--- 
-1.5.6.3
-
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
deleted file mode 100644
index d09823e..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-202-avr32-atmel_mpopfb-add-signal-to-disable-line-caching.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From 86fd2e3e74a191ae43122ac18f62f5163c577d4b Mon Sep 17 00:00:00 2001
-From: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-Date: Wed, 26 Nov 2008 14:11:59 +0100
-Subject: [PATCH 3/3] atmel_mpopfb: add signal to disable line caching and set correct output
-
-This patch adds a signal to disable line caching, due to an errata in
-silicon revision A. It also sets the output from MPOP to BGR to match
-big endian framebuffer memory.
-
-Signed-off-by: Hans-Christian Egtvedt <hans-christian.egtvedt at atmel.com>
-
-diff --git a/drivers/video/atmel_mpopfb.c b/drivers/video/atmel_mpopfb.c
-index 3b4b668..350303b 100644
---- a/drivers/video/atmel_mpopfb.c
-+++ b/drivers/video/atmel_mpopfb.c
-@@ -313,6 +313,10 @@ static int atmel_mpopfb_check_var(struct fb_var_screeninfo *var,
- static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
- {
- 	if (!sinfo->running) {
-+		unsigned int line_cache_disable =
-+			sinfo->baseimg_info.line_cache_disable ?
-+			ATMEL_MPOP_CR_CACHEDIS_MASK : 0;
-+
- 		dev_dbg(sinfo->info->device, "  * Starting MPOP.\n");
- 
- 		/* Enable all error interrupts. */
-@@ -323,9 +327,9 @@ static void atmel_mpopfb_start(struct atmel_mpopfb_info *sinfo)
- 		 * reading from the slave interface it will start
- 		 * generating a frame.
- 		 */
--		mpop_writel(sinfo, ATMEL_MPOP_CR,
--			    ATMEL_MPOP_CR_EN_MASK
--			    /*| ATMEL_MPOP_CR_OUT_BGR_MASK */ );
-+		mpop_writel(sinfo, ATMEL_MPOP_CR, ATMEL_MPOP_CR_EN_MASK
-+				| line_cache_disable
-+				| ATMEL_MPOP_CR_OUT_BGR_MASK);
- 
- 		sinfo->running = 1;
- 	}
-diff --git a/include/linux/atmel_mpopfb.h b/include/linux/atmel_mpopfb.h
-index cd12e16..d0f2505 100644
---- a/include/linux/atmel_mpopfb.h
-+++ b/include/linux/atmel_mpopfb.h
-@@ -42,9 +42,11 @@ struct atmel_mpopfb_baseimg_info {
- 	unsigned xsize;
- 	unsigned ysize;
- 
--	/* Signal that we should flip the video. */
-+	/* Signal for flipping the video. */
- 	int flip;
- 
-+	/* Signal for disabling the line cache. */
-+	int line_cache_disable;
- };
- 
- enum atmel_mpopfb_overlay_type {
--- 
-1.5.6.3
-
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-203-avr32-fix-arch-header-byteorder.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-203-avr32-fix-arch-header-byteorder.patch
deleted file mode 100644
index ac990f9..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-203-avr32-fix-arch-header-byteorder.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-Index: linux-2.6.27.6/arch/avr32/include/asm/byteorder.h
-===================================================================
---- linux-2.6.27.6.orig/arch/avr32/include/asm/byteorder.h	2008-11-28 16:47:15.000000000 +0100
-+++ linux-2.6.27.6/arch/avr32/include/asm/byteorder.h	2008-11-28 16:47:31.000000000 +0100
-@@ -7,8 +7,9 @@
- #include <asm/types.h>
- #include <linux/compiler.h>
- 
--#define __BIG_ENDIAN
-+#define __BIG_ENDIAN 4321
- #define __SWAB_64_THRU_32__
-+#define __BYTEORDER_HAS_U64__
- 
- #ifdef __CHECKER__
- extern unsigned long __builtin_bswap_32(unsigned long x);
-@@ -33,5 +34,5 @@
- #define __arch_swab32 __arch_swab32
- #endif
- 
--#include <linux/byteorder.h>
-+#include <linux/byteorder/big_endian.h>
- #endif /* __ASM_AVR32_BYTEORDER_H */
-Index: linux-2.6.27.6/arch/avr32/mach-at32ap/include/mach/io.h
-===================================================================
---- linux-2.6.27.6.orig/arch/avr32/mach-at32ap/include/mach/io.h	2008-11-28 16:47:58.000000000 +0100
-+++ linux-2.6.27.6/arch/avr32/mach-at32ap/include/mach/io.h	2008-11-28 16:48:15.000000000 +0100
-@@ -1,7 +1,7 @@
- #ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
- #define __ASM_AVR32_ARCH_AT32AP_IO_H
- 
--#include <linux/swab.h>
-+#include <linux/byteorder/swabb.h>
- 
- #if defined(CONFIG_AP700X_32_BIT_SMC)
- # define __swizzle_addr_b(addr)	(addr ^ 3UL)
diff --git a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch b/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
deleted file mode 100644
index 2392cbb..0000000
--- a/target/device/Atmel/arch-avr32/kernel-patches-2.6.27.6/linux-2.6.27.6-204-avr32-ap700x-fix-det_pin-for-nand-flash.patch
+++ /dev/null
@@ -1,31 +0,0 @@
---- a/arch/avr32/boards/atstk1000/atstk1002.c
-+++ b/arch/avr32/boards/atstk1000/atstk1002.c
-@@ -99,6 +99,7 @@ static struct mtd_partition *nand_part_i
- static struct atmel_nand_data atstk1006_nand_data __initdata = {
- 	.cle		= 21,
- 	.ale		= 22,
-+	.det_pin	= GPIO_PIN_NONE,
- 	.rdy_pin	= GPIO_PIN_PB(30),
- 	.enable_pin	= GPIO_PIN_PB(29),
- 	.partition_info	= nand_part_info,
---- a/arch/avr32/mach-at32ap/at32ap700x.c
-+++ b/arch/avr32/mach-at32ap/at32ap700x.c
-@@ -1969,13 +1969,14 @@ at32_add_device_nand(unsigned int id, st
- 		goto fail;
- 
- 	hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
--	if (data->enable_pin)
-+
-+	if (gpio_is_valid(data->enable_pin))
- 		at32_select_gpio(data->enable_pin,
- 				AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
--	if (data->rdy_pin)
--		at32_select_gpio(data->rdy_pin, 0);
--	if (data->det_pin)
-+	if (gpio_is_valid(data->det_pin))
- 		at32_select_gpio(data->det_pin, 0);
-+	if (gpio_is_valid(data->rdy_pin))
-+		at32_select_gpio(data->rdy_pin, 0);
- 
- 	platform_device_add(pdev);
- 	return pdev;
diff --git a/target/device/Atmel/misc-patches/README b/target/device/Atmel/misc-patches/README
deleted file mode 100644
index cf51054..0000000
--- a/target/device/Atmel/misc-patches/README
+++ /dev/null
@@ -1,2 +0,0 @@
-Copy these patches to kernel-patches, or u-boot for whatever board you are using them on.
- 
diff --git a/target/device/Atmel/misc-patches/u-boot-1.3.0-200MHz-ngw100.patch b/target/device/Atmel/misc-patches/u-boot-1.3.0-200MHz-ngw100.patch
deleted file mode 100644
index 9749041..0000000
--- a/target/device/Atmel/misc-patches/u-boot-1.3.0-200MHz-ngw100.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/include/configs/atngw100.h	2008-03-02 10:17:04.000000000 -0500
-+++ b/include/configs/atngw100.h	2008-03-02 10:22:46.000000000 -0500
-@@ -42,7 +42,7 @@
- #define CFG_POWER_MANAGER		1
- #define CFG_OSC0_HZ			20000000
- #define CFG_PLL0_DIV			1
--#define CFG_PLL0_MUL			7
-+#define CFG_PLL0_MUL			10
- #define CFG_PLL0_SUPPRESS_CYCLES	16
- #define CFG_CLKDIV_CPU			0
- #define CFG_CLKDIV_HSB			1
-@@ -56,7 +56,7 @@
-  *
-  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
-  */
--#define CFG_PLL0_OPT			0x04
-+#define CFG_PLL0_OPT			0x06
- 
- #define CONFIG_USART1			1
- 
diff --git a/target/device/Atmel/misc-patches/u-boot-1.3.0-64MB-sdram-ngw100.patch b/target/device/Atmel/misc-patches/u-boot-1.3.0-64MB-sdram-ngw100.patch
deleted file mode 100644
index b04bbf9..0000000
--- a/target/device/Atmel/misc-patches/u-boot-1.3.0-64MB-sdram-ngw100.patch
+++ /dev/null
@@ -1,11 +0,0 @@
---- a/board/atmel/atngw100/atngw100.c	2008-03-02 10:17:04.000000000 -0500
-+++ b/board/atmel/atngw100/atngw100.c	2008-03-02 10:21:23.000000000 -0500
-@@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
- static const struct sdram_info sdram = {
- 	.phys_addr	= CFG_SDRAM_BASE,
- 	.row_bits	= 13,
--	.col_bits	= 9,
-+	.col_bits	= 10,
- 	.bank_bits	= 2,
- 	.cas		= 3,
- 	.twr		= 2,
diff --git a/target/device/Atmel/root/device_table.txt b/target/device/Atmel/root/device_table.txt
deleted file mode 100644
index 8b46ca0..0000000
--- a/target/device/Atmel/root/device_table.txt
+++ /dev/null
@@ -1,162 +0,0 @@
-# When building a target filesystem, it is desirable to not have to
-# become root and then run 'mknod' a thousand times.  Using a device 
-# table you can create device nodes and directories "on the fly".
-#
-# This is a sample device table file for use with genext2fs.  You can
-# do all sorts of interesting things with a device table file.  For
-# example, if you want to adjust the permissions on a particular file
-# you can just add an entry like:
-#   /sbin/foobar        f       2755    0       0       -       -       -       -       -
-# and (assuming the file /sbin/foobar exists) it will be made setuid
-# root (regardless of what its permissions are on the host filesystem.
-# Furthermore, you can use a single table entry to create a many device
-# minors.  For example, if I wanted to create /dev/hda and /dev/hda[0-15]
-# I could just use the following two table entries:
-#   /dev/hda    b       640     0       0       3       0       0       0       -
-#   /dev/hda    b       640     0       0       3       1       1       1       15
-# 
-# Device table entries take the form of:
-# <name>    <type>      <mode>  <uid>   <gid>   <major> <minor> <start> <inc>   <count>
-# where name is the file name,  type can be one of: 
-#       f       A regular file
-#       d       Directory
-#       c       Character special device file
-#       b       Block special device file
-#       p       Fifo (named pipe)
-# uid is the user id for the target file, gid is the group id for the
-# target file.  The rest of the entries (major, minor, etc) apply only 
-# to device special files.
-
-# Have fun
-# -Erik Andersen <andersen at codepoet.org>
-#
-
-#<name>		<type>	<mode>	<uid>	<gid>	<major>	<minor>	<start>	<inc>	<count>
-/dev		d	755	0	0	-	-	-	-	-
-/dev/pts	d	755	0	0	-	-	-	-	-
-/tmp		d	1777	0	0	-	-	-	-	-
-/etc		d	755	0	0	-	-	-	-	-
-/home/default	d	2755	1000	1000	-	-	-	-	-
-#<name>					<type>	<mode>	<uid>	<gid>	<major>	<minor>	<start>	<inc>	<count>
-/bin/busybox				f	4755	0	0	-	-	-	-	-
-/etc/shadow				f	600	0	0	-	-	-	-	-
-/etc/passwd				f	644	0	0	-	-	-	-	-
-/etc/network/if-up.d			d	755	0	0	-	-	-	-	-
-/etc/network/if-pre-up.d		d	755	0	0	-	-	-	-	-
-/etc/network/if-down.d			d	755	0	0	-	-	-	-	-
-/etc/network/if-post-down.d		d	755	0	0	-	-	-	-	-
-/usr/share/udhcpc/default.script	f	755	0	0	-	-	-	-	-
-# uncomment this to allow starting x as non-root
-#/usr/X11R6/bin/Xfbdev		f	4755	0	0	-	-	-	-	-
-# Normal system devices
-/dev/mem	c	640	0	0	1	1	0	0	-
-/dev/kmem	c	640	0	0	1	2	0	0	-
-/dev/null	c	666	0	0	1	3	0	0	-
-/dev/zero	c	666	0	0	1	5	0	0	-
-/dev/random	c	666	0	0	1	8	0	0	-
-/dev/urandom	c	666	0	0	1	9	0	0	-
-/dev/ram	b	640	0	0	1	1	0	0	-
-/dev/ram	b	640	0	0	1	0	0	1	4
-/dev/loop	b	640	0	0	7	0	0	1	2
-/dev/rtc	c	640	0	0	10	135	-	-	-
-/dev/console	c	666	0	0	5	1	-	-	-
-/dev/tty	c	666	0	0	5	0	-	-	-
-/dev/tty	c	666	0	0	4	0	0	1	8
-/dev/ttyp	c	666	0	0	3	0	0	1	10
-/dev/ptyp	c       666     0       0       2       0       0       1       10
-/dev/ptmx	c	666	0	0	5	2	-	-	-
-/dev/ttyP	c	666	0	0	57	0	0	1	4
-/dev/ttyS	c	666	0	0	4	64	0	1	4
-/dev/fb		c	640	0	5	29	0	0	32	4
-#/dev/ttySA	c	666	0	0	204	5	0	1	3
-/dev/psaux	c	666	0	0	10	1	0	0	-
-#/dev/ppp	c	666	0	0	108	0	-	-	-
-
-# MTD stuff
-/dev/mtd	c	640	0	0	90	0	0	2	4
-/dev/mtdblock	b	640	0	0	31	0	0	1	4
-
-#Tun/tap driver
-/dev/net	d	755	0	0	-	-	-	-	-
-/dev/net/tun	c	660	0	0	10	200	-	-	-
-
-# Audio stuff
-#/dev/audio	c	666	0	29	14	4	-	-	-
-#/dev/audio1	c	666	0	29	14	20	-	-	-
-#/dev/dsp	c	666	0	29	14	3	-	-	-
-#/dev/dsp1	c	666	0	29	14	19	-	-	-
-#/dev/sndstat	c	666	0	29	14	6	-	-	-
-
-# User-mode Linux stuff
-/dev/ubda	b	640	0	0	98	0	0	0	-
-/dev/ubda	b	640	0	0	98	1	1	1	15
-
-# IDE Devices
-/dev/hda	b	640	0	0	3	0	0	0	-
-/dev/hda	b	640	0	0	3	1	1	1	15
-/dev/hdb	b	640	0	0	3	64	0	0	-
-/dev/hdb	b	640	0	0	3	65	1	1	15
-#/dev/hdc	b	640	0	0	22	0	0	0	-
-#/dev/hdc	b	640	0	0	22	1	1	1	15
-#/dev/hdd	b	640	0	0	22	64	0	0	-
-#/dev/hdd	b	640	0	0	22	65	1	1	15
-#/dev/hde	b	640	0	0	33	0	0	0	-
-#/dev/hde	b	640	0	0	33	1	1	1	15
-#/dev/hdf	b	640	0	0	33	64	0	0	-
-#/dev/hdf	b	640	0	0	33	65	1	1	15
-#/dev/hdg	b	640	0	0	34	0	0	0	-
-#/dev/hdg	b	640	0	0	34	1	1	1	15
-#/dev/hdh	b	640	0	0	34	64	0	0	-
-#/dev/hdh	b	640	0	0	34	65	1	1	15
-
-# SCSI Devices
-#/dev/sda	b	640	0	0	8	0	0	0	-
-#/dev/sda	b	640	0	0	8	1	1	1	15
-#/dev/sdb	b	640	0	0	8	16	0	0	-
-#/dev/sdb	b	640	0	0	8	17	1	1	15
-#/dev/sdc	b	640	0	0	8	32	0	0	-
-#/dev/sdc	b	640	0	0	8	33	1	1	15
-#/dev/sdd	b	640	0	0	8	48	0	0	-
-#/dev/sdd	b	640	0	0	8	49	1	1	15
-#/dev/sde	b	640	0	0	8	64	0	0	-
-#/dev/sde	b	640	0	0	8	65	1	1	15
-#/dev/sdf	b	640	0	0	8	80	0	0	-
-#/dev/sdf	b	640	0	0	8	81	1	1	15
-#/dev/sdg	b	640	0	0	8	96	0	0	-
-#/dev/sdg	b	640	0	0	8	97	1	1	15
-#/dev/sdh	b	640	0	0	8	112	0	0	-
-#/dev/sdh	b	640	0	0	8	113	1	1	15
-#/dev/sg	c	640	0	0	21	0	0	1	15
-#/dev/scd	b	640	0	0	11	0	0	1	15
-#/dev/st	c	640	0	0	9	0	0	1	8
-#/dev/nst	c	640	0	0	9	128	0	1	8
-#/dev/st	c	640	0	0	9	32	1	1	4
-#/dev/st	c	640	0	0	9	64	1	1	4
-#/dev/st	c	640	0	0	9	96	1	1	4
-
-# Floppy disk devices
-#/dev/fd	b	640	0	0	2	0	0	1	2
-#/dev/fd0d360	b	640	0	0	2	4	0	0	-
-#/dev/fd1d360	b	640	0	0	2	5	0	0	-
-#/dev/fd0h1200	b	640	0	0	2	8	0	0	-
-#/dev/fd1h1200	b	640	0	0	2	9	0	0	-
-#/dev/fd0u1440	b	640	0	0	2	28	0	0	-
-#/dev/fd1u1440	b	640	0	0	2	29	0	0	-
-#/dev/fd0u2880	b	640	0	0	2	32	0	0	-
-#/dev/fd1u2880	b	640	0	0	2	33	0	0	-
-
-# All the proprietary cdrom devices in the world
-#/dev/aztcd	b	640	0	0	29	0	0	0	-
-#/dev/bpcd	b	640	0	0	41	0	0	0	-
-#/dev/capi20	c	640	0	0	68	0	0	1	2
-#/dev/cdu31a	b	640	0	0	15	0	0	0	-
-#/dev/cdu535	b	640	0	0	24	0	0	0	-
-#/dev/cm206cd	b	640	0	0	32	0	0	0	-
-#/dev/sjcd	b	640	0	0	18	0	0	0	-
-#/dev/sonycd	b	640	0	0	15	0	0	0	-
-#/dev/gscd	b	640	0	0	16	0	0	0	-
-#/dev/sbpcd	b	640	0	0	25	0	0	0	-
-#/dev/sbpcd	b	640	0	0	25	0	0	1	4
-#/dev/mcd	b	640	0	0	23	0	0	0	-
-#/dev/optcd	b	640	0	0	17	0	0	0	-
-
diff --git a/target/device/Atmel/root/skel.patch b/target/device/Atmel/root/skel.patch
deleted file mode 100644
index fce5ca9..0000000
--- a/target/device/Atmel/root/skel.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-diff -urN target_skeleton_atmel/etc/group target_skeleton/etc/group
---- target_skeleton_atmel/etc/group	2006-11-01 21:24:48.000000000 +0100
-+++ target_skeleton/etc/group	2007-04-05 12:37:05.000000000 +0200
-@@ -8,6 +8,8 @@
- wheel:x:10:root
- utmp:x:43:
- staff:x:50:
-+haldaemon:x:68:
-+dbus:x:81:
- nobody:x:99:
- nogroup:x:99:
- users:x:100:
-diff -urN target_skeleton_atmel/etc/inittab target_skeleton/etc/inittab
---- target_skeleton_atmel/etc/inittab	2006-11-01 21:24:48.000000000 +0100
-+++ target_skeleton/etc/inittab	2007-04-05 12:37:05.000000000 +0200
-@@ -24,17 +24,17 @@
- ::sysinit:/etc/init.d/rcS
- 
- # Set up a couple of getty's
--#tty1::respawn:/sbin/getty 38400 tty1
--#tty2::respawn:/sbin/getty 38400 tty2
-+tty1::respawn:/sbin/getty 38400 tty1
-+tty2::respawn:/sbin/getty 38400 tty2
- 
- # Put a getty on the serial port
--ttyS0::respawn:/sbin/getty -L ttyS0 115200 vt100
-+#ttyS0::respawn:/sbin/getty -L ttyS0 115200 vt100
- 
- # Logging junk
- null::sysinit:/bin/touch /var/log/messages
- null::respawn:/sbin/syslogd -n -m 0
- null::respawn:/sbin/klogd -n
--#tty3::respawn:/usr/bin/tail -f /var/log/messages
-+tty3::respawn:/usr/bin/tail -f /var/log/messages
- 
- # Stuff to do for the 3-finger salute
- ::ctrlaltdel:/sbin/reboot
-diff -urN target_skeleton_atmel/etc/passwd target_skeleton/etc/passwd
---- target_skeleton_atmel/etc/passwd	2006-11-01 21:24:48.000000000 +0100
-+++ target_skeleton/etc/passwd	2007-04-05 12:37:05.000000000 +0200
-@@ -8,6 +8,8 @@
- www-data:x:33:33:www-data:/var/www:/bin/sh
- backup:x:34:34:backup:/var/backups:/bin/sh
- operator:x:37:37:Operator:/var:/bin/sh
--sshd:x:103:99:Operator:/var:/bin/sh
-+haldaemon:x:68:68:hald:/:/bin/sh
-+dbus:x:81:81:dbus:/var/run/dbus:/bin/sh
- nobody:x:99:99:nobody:/home:/bin/sh
-+sshd:x:103:99:Operator:/var:/bin/sh
- default:x:1000:1000:Default non-root user:/home/default:/bin/sh
-Filerna target_skeleton_atmel/etc/random-seed och target_skeleton/etc/random-seed skiljer
-diff -urN target_skeleton_atmel/etc/resolv.conf target_skeleton/etc/resolv.conf
---- target_skeleton_atmel/etc/resolv.conf	2006-11-01 21:24:48.000000000 +0100
-+++ target_skeleton/etc/resolv.conf	1970-01-01 01:00:00.000000000 +0100
-@@ -1,2 +0,0 @@
--domain dev.null
--nameserver 127.0.0.1
-diff -urN target_skeleton_atmel/root/.bashrc target_skeleton/root/.bashrc
---- target_skeleton_atmel/root/.bashrc	2006-11-01 21:24:49.000000000 +0100
-+++ target_skeleton/root/.bashrc	2007-04-05 12:37:04.000000000 +0200
-@@ -37,8 +37,8 @@
-     alias ps1='ps faxo "%U %t %p %a" '
-     alias af='ps af'
-     alias cls='clear'
--    alias ll='/bin/ls -laFh'
--    alias ls='/bin/ls -F'
-+    alias ll='/bin/ls --color=tty -laFh'
-+    alias ls='/bin/ls --color=tty -F'
-     alias df='df -h'
-     alias indent='indent -bad -bap -bbo -nbc -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli0 -cp33 -cs -d0 -di1 -nfc1 -nfca -hnl -i4 -ip0 -l75 -lp -npcs -npsl -nsc -nsob -nss -ts4 '
-     #alias bc='bc -l'
diff --git a/target/device/Atmel/root/skel.tar.gz b/target/device/Atmel/root/skel.tar.gz
deleted file mode 100644
index dacbf6c486bf9952465269195036333db4900cb1..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 629
zcmV-*0*d_~iwFStk!wQ$1MQn(ZsITyMmY*Ms6DpF=Lr<GsD(sH==s;4ux__fcN1Dq
zSm}Fzf*_I&j~S20(6{aQu&Ikl#1Qh;#$Y~Pf3q>s1&(CdrpMO#Xg1qWd0xV07 at K~(
z-8ARNLq8nOU)}ew*UKBZUjGyN?0<JW*ZdC5^lvFL1)}8NlZ)`Lf%rd+`}O^M@{t4O
z`;!0Q;a`K||1>tcN at Ixs82{?u8s{k5>3d?Mi^)GdbbXs<)?UuzP-$-PpZq_!r$faA
zFfaa%WlDEN$^R)CApSKF|F6g0`uRVv|G_#l<$p);uYveKovZEvX8C8&*0Xn0{8M!B
zuYve)yY>BF^FJFu`A7V#ApWJysyD_=|EWeajzg67ANxNY#D8D63A8Bwt;D~_{!a%{
zKh$ji&9DD*|7VJSLj0>B{>M|d{`zl;WAM at NwEn}t3gZ7V^y~Zgfdf-+{3ZX+TKLzX
z_^;Rln4kaC{y#r&gYnq^sZjh^ECCj+|DMHvVEEUd_^((4F7q$(PY&^~!n^<Hrmu7e
zFvov6|6!Z`%lQxd*GK%nHFr_}c}n~K>-j&U{!^j&U%mdj`gcLrf8>81{_x-JPy1u@
z<70^bW#|9-sV(Kk#E;MB6Yzia-|k;3jj`N+h{W)(!3Y0OwZ^!?e+Uu&H7Nf3%a?EM
zyWHTP4Z*(##sAQ??Q5MemiuSx;9rH}zv4%IOa6~o|5YgdE7ks)8{(f3|2l~O$HUt_
z^nc|1&zb4>|M>rp3dR3j)&K0u{;%f5GVnk7 at 5W*6{@;82<NOZ*000000000000000
P_zu4S6ZkOH08jt`S-Np2

diff --git a/target/device/Atmel/root/target_skeleton/bin/.empty b/target/device/Atmel/root/target_skeleton/bin/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/boot/.empty b/target/device/Atmel/root/target_skeleton/boot/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/config/.empty b/target/device/Atmel/root/target_skeleton/config/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/dev/.empty b/target/device/Atmel/root/target_skeleton/dev/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/etc/TZ b/target/device/Atmel/root/target_skeleton/etc/TZ
deleted file mode 100644
index 9fcb2a3..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/TZ
+++ /dev/null
@@ -1 +0,0 @@
-MST7MDT
diff --git a/target/device/Atmel/root/target_skeleton/etc/fstab b/target/device/Atmel/root/target_skeleton/etc/fstab
deleted file mode 100644
index 4302748..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/fstab
+++ /dev/null
@@ -1,9 +0,0 @@
-# /etc/fstab: static file system information.
-#
-# <file system>	<mount pt>	<type>	<options>         			<dump> <pass>
-/dev/root			/			ext2		rw,noauto				0		1
-proc				/proc		proc		defaults					0		0
-devpts			/dev/pts		devpts	defaults,gid=5,mode=620	0		0
-tmpfs			/tmp			tmpfs	defaults					0		0
-sysfs			/sys			sysfs	defaults					0		0	
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/group b/target/device/Atmel/root/target_skeleton/etc/group
deleted file mode 100644
index f78c22c..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/group
+++ /dev/null
@@ -1,16 +0,0 @@
-root:x:0:
-daemon:x:1:
-bin:x:2:
-sys:x:3:
-adm:x:4:
-tty:x:5:
-disk:x:6:
-wheel:x:10:root
-utmp:x:43:
-staff:x:50:
-haldaemon:x:68:
-dbus:x:81:
-nobody:x:99:
-nogroup:x:99:
-users:x:100:
-default:x:1000:
diff --git a/target/device/Atmel/root/target_skeleton/etc/hostname b/target/device/Atmel/root/target_skeleton/etc/hostname
deleted file mode 100644
index 5b26b35..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/hostname
+++ /dev/null
@@ -1 +0,0 @@
-buildroot
diff --git a/target/device/Atmel/root/target_skeleton/etc/hosts b/target/device/Atmel/root/target_skeleton/etc/hosts
deleted file mode 100644
index ba712fe..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/hosts
+++ /dev/null
@@ -1 +0,0 @@
-127.0.0.1	localhost
diff --git a/target/device/Atmel/root/target_skeleton/etc/init.d/S20urandom b/target/device/Atmel/root/target_skeleton/etc/init.d/S20urandom
deleted file mode 100755
index f73cea5..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/init.d/S20urandom
+++ /dev/null
@@ -1,54 +0,0 @@
-#! /bin/sh
-#
-# urandom	This script saves the random seed between reboots.
-#		It is called from the boot, halt and reboot scripts.
-#
-# Version:	@(#)urandom  1.33  22-Jun-1998  miquels at cistron.nl
-#
-
-[ -c /dev/urandom ] || exit 0
-#. /etc/default/rcS
-
-case "$1" in
-	start|"")
-		if [ "$VERBOSE" != no ]
-		then
-			echo -n "Initializing random number generator... "
-		fi
-		# Load and then save 512 bytes,
-		# which is the size of the entropy pool
-		if [ -f /etc/random-seed ]
-		then
-			cat /etc/random-seed >/dev/urandom
-		fi
-		# check for read only file system
-		if ! touch /etc/random-seed 2>/dev/null
-		then
-			echo "read-only file system detected...done"
-			exit
-		fi
-		rm -f /etc/random-seed
-		umask 077
-		dd if=/dev/urandom of=/etc/random-seed count=1 \
-			>/dev/null 2>&1 || echo "urandom start: failed."
-		umask 022
-		[ "$VERBOSE" != no ] && echo "done."
-		;;
-	stop)
-		if ! touch /etc/random-seed 2>/dev/null
-                then
-                        exit
-                fi
-		# Carry a random seed from shut-down to start-up;
-		# see documentation in linux/drivers/char/random.c
-		[ "$VERBOSE" != no ] && echo -n "Saving random seed... "
-		umask 077
-		dd if=/dev/urandom of=/etc/random-seed count=1 \
-			>/dev/null 2>&1 || echo "urandom stop: failed."
-		[ "$VERBOSE" != no ] && echo "done."
-		;;
-	*)
-		echo "Usage: urandom {start|stop}" >&2
-		exit 1
-		;;
-esac
diff --git a/target/device/Atmel/root/target_skeleton/etc/init.d/S40network b/target/device/Atmel/root/target_skeleton/etc/init.d/S40network
deleted file mode 100755
index d835d9c..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/init.d/S40network
+++ /dev/null
@@ -1,35 +0,0 @@
-#!/bin/sh
-#
-# Start the network....
-#
-
-start() {
- 	echo "Starting network..."
-	/sbin/ifup -a
-}	
-stop() {
-	echo -n "Stopping network..."
-	/sbin/ifdown -a
-}
-restart() {
-	stop
-	start
-}	
-
-case "$1" in
-  start)
-  	start
-	;;
-  stop)
-  	stop
-	;;
-  restart|reload)
-  	restart
-	;;
-  *)
-	echo $"Usage: $0 {start|stop|restart}"
-	exit 1
-esac
-
-exit $?
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/init.d/rcS b/target/device/Atmel/root/target_skeleton/etc/init.d/rcS
deleted file mode 100755
index de41153..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/init.d/rcS
+++ /dev/null
@@ -1,27 +0,0 @@
-#!/bin/sh
-
-
-# Start all init scripts in /etc/init.d
-# executing them in numerical order.
-#
-for i in /etc/init.d/S??* ;do
-
-     # Ignore dangling symlinks (if any).
-     [ ! -f "$i" ] && continue
-
-     case "$i" in
-	*.sh)
-	    # Source shell script for speed.
-	    (
-		trap - INT QUIT TSTP
-		set start
-		. $i
-	    )
-	    ;;
-	*)
-	    # No sh extension, so fork subprocess.
-	    $i start
-	    ;;
-    esac
-done
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/inittab b/target/device/Atmel/root/target_skeleton/etc/inittab
deleted file mode 100644
index 2e3b9a4..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/inittab
+++ /dev/null
@@ -1,45 +0,0 @@
-# /etc/inittab
-#
-# Copyright (C) 2001 Erik Andersen <andersen at codepoet.org>
-#
-# Note: BusyBox init doesn't support runlevels.  The runlevels field is
-# completely ignored by BusyBox init. If you want runlevels, use
-# sysvinit.
-#
-# Format for each entry: <id>:<runlevels>:<action>:<process>
-#
-# id        == tty to run on, or empty for /dev/console
-# runlevels == ignored
-# action    == one of sysinit, respawn, askfirst, wait, and once
-# process   == program to run
-
-# Startup the system
-null::sysinit:/bin/mount -o remount,rw /
-null::sysinit:/bin/mount -t proc proc /proc
-null::sysinit:/bin/mount -a
-null::sysinit:/bin/hostname -F /etc/hostname
-# now run any rc scripts
-::sysinit:/etc/init.d/rcS
-
-# Set up a couple of getty's
-#tty1::respawn:/sbin/getty 38400 tty1
-#tty2::respawn:/sbin/getty 38400 tty2
-
-# Put a getty on the serial port
-ttyS0::respawn:/sbin/getty -L ttyS0 115200 vt100
-
-# Logging junk
-null::sysinit:/bin/touch /var/log/messages
-null::respawn:/sbin/syslogd -n -m 0
-null::respawn:/sbin/klogd -n
-tty3::respawn:/usr/bin/tail -f /var/log/messages
-
-# Stuff to do for the 3-finger salute
-::ctrlaltdel:/sbin/reboot
-
-# Stuff to do before rebooting
-null::shutdown:/usr/bin/killall klogd
-null::shutdown:/usr/bin/killall syslogd
-null::shutdown:/bin/umount -a -r
-null::shutdown:/sbin/swapoff -a
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/inputrc b/target/device/Atmel/root/target_skeleton/etc/inputrc
deleted file mode 100644
index 2f1cb60..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/inputrc
+++ /dev/null
@@ -1,44 +0,0 @@
-# /etc/inputrc - global inputrc for libreadline
-# See readline(3readline) and `info readline' for more information.
-
-# Be 8 bit clean.
-set input-meta on
-set output-meta on
-set bell-style visible
-
-# To allow the use of 8bit-characters like the german umlauts, comment out
-# the line below. However this makes the meta key not work as a meta key,
-# which is annoying to those which don't need to type in 8-bit characters.
-
-# set convert-meta off
-
-"\e0d": backward-word
-"\e0c": forward-word
-"\e[h": beginning-of-line
-"\e[f": end-of-line
-"\e[1~": beginning-of-line
-"\e[4~": end-of-line
-#"\e[5~": beginning-of-history
-#"\e[6~": end-of-history
-"\e[3~": delete-char
-"\e[2~": quoted-insert
-
-# Common standard keypad and cursor
-# (codes courtsey Werner Fink, <werner at suse.de>)
-#"\e[1~": history-search-backward
-"\e[2~": yank
-"\e[3~": delete-char
-#"\e[4~": set-mark
-"\e[5~": history-search-backward
-"\e[6~": history-search-forward
-# Normal keypad and cursor of xterm
-"\e[F": end-of-line
-"\e[H": beginning-of-line
-# Application keypad and cursor of xterm
-"\eOA": previous-history
-"\eOC": forward-char
-"\eOB": next-history
-"\eOD": backward-char
-"\eOF": end-of-line
-"\eOH": beginning-of-line
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/issue b/target/device/Atmel/root/target_skeleton/etc/issue
deleted file mode 100644
index 90f1779..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/issue
+++ /dev/null
@@ -1,3 +0,0 @@
-
-Welcome to Buildroot
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/ld.so.conf b/target/device/Atmel/root/target_skeleton/etc/ld.so.conf
deleted file mode 100644
index 83327c0..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/ld.so.conf
+++ /dev/null
@@ -1 +0,0 @@
-include /etc/ld.so.conf.d/*.conf
diff --git a/target/device/Atmel/root/target_skeleton/etc/ld.so.conf.d/.empty b/target/device/Atmel/root/target_skeleton/etc/ld.so.conf.d/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/etc/network/interfaces b/target/device/Atmel/root/target_skeleton/etc/network/interfaces
deleted file mode 100644
index 218b82c..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/network/interfaces
+++ /dev/null
@@ -1,4 +0,0 @@
-# Configure Loopback
-auto lo
-iface lo inet loopback
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/passwd b/target/device/Atmel/root/target_skeleton/etc/passwd
deleted file mode 100644
index 377d4df..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/passwd
+++ /dev/null
@@ -1,15 +0,0 @@
-root:x:0:0:root:/root:/bin/sh
-daemon:x:1:1:daemon:/usr/sbin:/bin/sh
-bin:x:2:2:bin:/bin:/bin/sh
-sys:x:3:3:sys:/dev:/bin/sh
-sync:x:4:100:sync:/bin:/bin/sync
-mail:x:8:8:mail:/var/spool/mail:/bin/sh
-proxy:x:13:13:proxy:/bin:/bin/sh
-www-data:x:33:33:www-data:/var/www:/bin/sh
-backup:x:34:34:backup:/var/backups:/bin/sh
-operator:x:37:37:Operator:/var:/bin/sh
-haldaemon:x:68:68:hald:/:/bin/sh
-dbus:x:81:81:dbus:/var/run/dbus:/bin/sh
-nobody:x:99:99:nobody:/home:/bin/sh
-sshd:x:103:99:Operator:/var:/bin/sh
-default:x:1000:1000:Default non-root user:/home/default:/bin/sh
diff --git a/target/device/Atmel/root/target_skeleton/etc/profile b/target/device/Atmel/root/target_skeleton/etc/profile
deleted file mode 100644
index cc2e0be..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/profile
+++ /dev/null
@@ -1,48 +0,0 @@
-# ~/.bashrc: executed by bash(1) for non-login interactive shells.
-
-export PATH=\
-/bin:\
-/sbin:\
-/usr/bin:\
-/usr/sbin:\
-/usr/bin/X11:\
-/usr/local/bin
-
-# If running interactively, then:
-if [ "$PS1" ]; then
-
-    if [ "$BASH" ]; then
-	export PS1="[\u@\h \W]\\$ "
-	alias ll='/bin/ls --color=tty -laFh'
-	alias ls='/bin/ls --color=tty -F'
-	export LS_COLORS='no=00:fi=00:di=01;34:ln=01;36:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.bz2=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.jpg=01;35:*.jpeg=01;35:*.png=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.mpg=01;35:*.mpeg=01;35:*.avi=01;35:*.fli=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:';
-    else
-      if [ "`id -u`" -eq 0 ]; then 
-	export PS1='# '
-      else
-	export PS1='$ '
-      fi
-    fi
-
-    export USER=`id -un`
-    export LOGNAME=$USER
-    export HOSTNAME=`/bin/hostname`
-    export HISTSIZE=1000
-    export HISTFILESIZE=1000
-    export PAGER='/bin/more '
-    export EDITOR='/bin/vi'
-    export INPUTRC=/etc/inputrc
-    export DMALLOC_OPTIONS=debug=0x34f47d83,inter=100,log=logfile
-
-    ### Some aliases
-    alias ps2='ps facux '
-    alias ps1='ps faxo "%U %t %p %a" '
-    alias af='ps af'
-    alias cls='clear'
-    alias df='df -h'
-    alias indent='indent -bad -bap -bbo -nbc -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli0 -cp33 -cs -d0 -di1 -nfc1 -nfca -hnl -i4 -ip0 -l75 -lp -npcs -npsl -nsc -nsob -nss -ts4 '
-    #alias bc='bc -l'
-    alias minicom='minicom -c on'
-    alias calc='calc -Cd '
-    alias bc='calc -Cd '
-fi;
diff --git a/target/device/Atmel/root/target_skeleton/etc/protocols b/target/device/Atmel/root/target_skeleton/etc/protocols
deleted file mode 100644
index 1ac8a40..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/protocols
+++ /dev/null
@@ -1,31 +0,0 @@
-# /etc/protocols:
-# $Id: protocols,v 1.1 2004/10/09 02:49:18 andersen Exp $
-#
-# Internet (IP) protocols
-#
-#	from: @(#)protocols	5.1 (Berkeley) 4/17/89
-#
-# Updated for NetBSD based on RFC 1340, Assigned Numbers (July 1992).
-
-ip	0	IP		# internet protocol, pseudo protocol number
-icmp	1	ICMP		# internet control message protocol
-igmp	2	IGMP		# Internet Group Management
-ggp	3	GGP		# gateway-gateway protocol
-ipencap	4	IP-ENCAP	# IP encapsulated in IP (officially ``IP'')
-st	5	ST		# ST datagram mode
-tcp	6	TCP		# transmission control protocol
-egp	8	EGP		# exterior gateway protocol
-pup	12	PUP		# PARC universal packet protocol
-udp	17	UDP		# user datagram protocol
-hmp	20	HMP		# host monitoring protocol
-xns-idp	22	XNS-IDP		# Xerox NS IDP
-rdp	27	RDP		# "reliable datagram" protocol
-iso-tp4	29	ISO-TP4		# ISO Transport Protocol class 4
-xtp	36	XTP		# Xpress Tranfer Protocol
-ddp	37	DDP		# Datagram Delivery Protocol
-idpr-cmtp	39	IDPR-CMTP	# IDPR Control Message Transport
-rspf	73	RSPF		#Radio Shortest Path First.
-vmtp	81	VMTP		# Versatile Message Transport
-ospf	89	OSPFIGP		# Open Shortest Path First IGP
-ipip	94	IPIP		# Yet Another IP encapsulation
-encap	98	ENCAP		# Yet Another IP encapsulation
diff --git a/target/device/Atmel/root/target_skeleton/etc/random-seed b/target/device/Atmel/root/target_skeleton/etc/random-seed
deleted file mode 100644
index f26038adc5d057a0b9d6ce5d3cda02ccb4a4d12e..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 512
zcmV+b0{{Iq0UOB42;n<rZ7)sf8Kr=fg87_s+y&vLYgGJP-sY`OWMEj0aQ&I{*g5$)
zH?Zu5*rX8>4xpAvJIL$H4mg*!B4&9jh)7+B2j-fX7o at K*bzj;pJ$FwoQzl&MuZ^Wy
zrYS)x9vq<)#e~&1uB|_ITW-fntEg1^KXs3>vvgL7?_kg!+6=fg{S7mwkr$#pm<zB(
zu)oAUWFK-u-)cWcuSL*8$Q<cmC?ll~NEK at l5k|75(YzZ_p!I6FJ}YI_3>PZ13liCc
zi|M+im&71p*p+Z|7f(m-aedNFtEezFN<xKEd-wQ71%XuGfKr+6VcDycMQ(v6+Z0G|
z-MPjg at JHu%y(|h1cTa=a4(m?GyU)ZD-T+-vLXX}cCXyn}vCXC3Hn1ft`zDTL(};Rr
z?3wX?Eh5%n+AXAeDtXvl!o>-nZHytAhV~}?OM$-f$(%cG(ioV{==Ub4mfZP}OaJJ7
z25tvCcku=>;L?}O-dvK9`}<^gmg at IrnfQm#P>RRF|C9c;GDgEg_bw26{dkIVt1`{`
z3#ol{Q_FL91TBD~{uZn<gw?^=VUuSaIf)=p`07n=>RRZ(Otf!KXM&;q)8B<Q8(T)k
z?Z}a{1Jyf~bQPL{qVQk6jFNfBr)0;57HwN`o6Kw{wdPGHUWrfsJ}0VmW|Tr22whlO
C+W_DI

diff --git a/target/device/Atmel/root/target_skeleton/etc/securetty b/target/device/Atmel/root/target_skeleton/etc/securetty
deleted file mode 100644
index 81616f3..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/securetty
+++ /dev/null
@@ -1,12 +0,0 @@
-tty1
-tty2
-tty3
-tty4
-tty5
-tty6
-tty7
-tty8
-ttyS0
-ttyS1
-ttyS2
-ttyS3
diff --git a/target/device/Atmel/root/target_skeleton/etc/services b/target/device/Atmel/root/target_skeleton/etc/services
deleted file mode 100644
index b287b63..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/services
+++ /dev/null
@@ -1,302 +0,0 @@
-# /etc/services:
-# $Id: services,v 1.1 2004/10/09 02:49:18 andersen Exp $
-#
-# Network services, Internet style
-#
-# Note that it is presently the policy of IANA to assign a single well-known
-# port number for both TCP and UDP; hence, most entries here have two entries
-# even if the protocol doesn't support UDP operations.
-# Updated from RFC 1700, ``Assigned Numbers'' (October 1994).  Not all ports
-# are included, only the more common ones.
-
-tcpmux		1/tcp				# TCP port service multiplexer
-echo		7/tcp
-echo		7/udp
-discard		9/tcp		sink null
-discard		9/udp		sink null
-systat		11/tcp		users
-daytime		13/tcp
-daytime		13/udp
-netstat		15/tcp
-qotd		17/tcp		quote
-msp		18/tcp				# message send protocol
-msp		18/udp				# message send protocol
-chargen		19/tcp		ttytst source
-chargen		19/udp		ttytst source
-ftp-data	20/tcp
-ftp		21/tcp
-fsp		21/udp		fspd
-ssh		22/tcp				# SSH Remote Login Protocol
-ssh		22/udp				# SSH Remote Login Protocol
-telnet		23/tcp
-# 24 - private
-smtp		25/tcp		mail
-# 26 - unassigned
-time		37/tcp		timserver
-time		37/udp		timserver
-rlp		39/udp		resource	# resource location
-nameserver	42/tcp		name		# IEN 116
-whois		43/tcp		nicname
-re-mail-ck	50/tcp				# Remote Mail Checking Protocol
-re-mail-ck	50/udp				# Remote Mail Checking Protocol
-domain		53/tcp		nameserver	# name-domain server
-domain		53/udp		nameserver
-mtp		57/tcp				# deprecated
-bootps		67/tcp				# BOOTP server
-bootps		67/udp
-bootpc		68/tcp				# BOOTP client
-bootpc		68/udp
-tftp		69/udp
-gopher		70/tcp				# Internet Gopher
-gopher		70/udp
-rje		77/tcp		netrjs
-finger		79/tcp
-www		80/tcp		http		# WorldWideWeb HTTP
-www		80/udp				# HyperText Transfer Protocol
-link		87/tcp		ttylink
-kerberos	88/tcp		kerberos5 krb5	# Kerberos v5
-kerberos	88/udp		kerberos5 krb5	# Kerberos v5
-supdup		95/tcp
-# 100 - reserved
-hostnames	101/tcp		hostname	# usually from sri-nic
-iso-tsap	102/tcp		tsap		# part of ISODE.
-csnet-ns	105/tcp		cso-ns		# also used by CSO name server
-csnet-ns	105/udp		cso-ns
-# unfortunately the poppassd (Eudora) uses a port which has already
-# been assigned to a different service. We list the poppassd as an
-# alias here. This should work for programs asking for this service.
-# (due to a bug in inetd the 3com-tsmux line is disabled)
-#3com-tsmux	106/tcp		poppassd
-#3com-tsmux	106/udp		poppassd
-rtelnet		107/tcp				# Remote Telnet
-rtelnet		107/udp
-pop-2		109/tcp		postoffice	# POP version 2
-pop-2		109/udp
-pop-3		110/tcp				# POP version 3
-pop-3		110/udp
-sunrpc		111/tcp		portmapper	# RPC 4.0 portmapper TCP
-sunrpc		111/udp		portmapper	# RPC 4.0 portmapper UDP
-auth		113/tcp		authentication tap ident
-sftp		115/tcp
-uucp-path	117/tcp
-nntp		119/tcp		readnews untp	# USENET News Transfer Protocol
-ntp		123/tcp
-ntp		123/udp				# Network Time Protocol
-netbios-ns	137/tcp				# NETBIOS Name Service
-netbios-ns	137/udp
-netbios-dgm	138/tcp				# NETBIOS Datagram Service
-netbios-dgm	138/udp
-netbios-ssn	139/tcp				# NETBIOS session service
-netbios-ssn	139/udp
-imap2		143/tcp				# Interim Mail Access Proto v2
-imap2		143/udp
-snmp		161/udp				# Simple Net Mgmt Proto
-snmp-trap	162/udp		snmptrap	# Traps for SNMP
-cmip-man	163/tcp				# ISO mgmt over IP (CMOT)
-cmip-man	163/udp
-cmip-agent	164/tcp
-cmip-agent	164/udp
-xdmcp		177/tcp				# X Display Mgr. Control Proto
-xdmcp		177/udp
-nextstep	178/tcp		NeXTStep NextStep	# NeXTStep window
-nextstep	178/udp		NeXTStep NextStep	# server
-bgp		179/tcp				# Border Gateway Proto.
-bgp		179/udp
-prospero	191/tcp				# Cliff Neuman's Prospero
-prospero	191/udp
-irc		194/tcp				# Internet Relay Chat
-irc		194/udp
-smux		199/tcp				# SNMP Unix Multiplexer
-smux		199/udp
-at-rtmp		201/tcp				# AppleTalk routing
-at-rtmp		201/udp
-at-nbp		202/tcp				# AppleTalk name binding
-at-nbp		202/udp
-at-echo		204/tcp				# AppleTalk echo
-at-echo		204/udp
-at-zis		206/tcp				# AppleTalk zone information
-at-zis		206/udp
-qmtp		209/tcp				# The Quick Mail Transfer Protocol
-qmtp		209/udp				# The Quick Mail Transfer Protocol
-z3950		210/tcp		wais		# NISO Z39.50 database
-z3950		210/udp		wais
-ipx		213/tcp				# IPX
-ipx		213/udp
-imap3		220/tcp				# Interactive Mail Access
-imap3		220/udp				# Protocol v3
-ulistserv	372/tcp				# UNIX Listserv
-ulistserv	372/udp
-https		443/tcp				# MCom
-https		443/udp				# MCom
-snpp		444/tcp				# Simple Network Paging Protocol
-snpp		444/udp				# Simple Network Paging Protocol
-saft		487/tcp				# Simple Asynchronous File Transfer
-saft		487/udp				# Simple Asynchronous File Transfer
-npmp-local	610/tcp		dqs313_qmaster	# npmp-local / DQS
-npmp-local	610/udp		dqs313_qmaster	# npmp-local / DQS
-npmp-gui	611/tcp		dqs313_execd	# npmp-gui / DQS
-npmp-gui	611/udp		dqs313_execd	# npmp-gui / DQS
-hmmp-ind	612/tcp		dqs313_intercell# HMMP Indication / DQS
-hmmp-ind	612/udp		dqs313_intercell# HMMP Indication / DQS
-#
-# UNIX specific services
-#
-exec		512/tcp
-biff		512/udp		comsat
-login		513/tcp
-who		513/udp		whod
-shell		514/tcp		cmd		# no passwords used
-syslog		514/udp
-printer		515/tcp		spooler		# line printer spooler
-talk		517/udp
-ntalk		518/udp
-route		520/udp		router routed	# RIP
-timed		525/udp		timeserver
-tempo		526/tcp		newdate
-courier		530/tcp		rpc
-conference	531/tcp		chat
-netnews		532/tcp		readnews
-netwall		533/udp				# -for emergency broadcasts
-uucp		540/tcp		uucpd		# uucp daemon
-afpovertcp	548/tcp				# AFP over TCP
-afpovertcp	548/udp				# AFP over TCP
-remotefs	556/tcp		rfs_server rfs	# Brunhoff remote filesystem
-klogin		543/tcp				# Kerberized `rlogin' (v5)
-kshell		544/tcp		krcmd		# Kerberized `rsh' (v5)
-kerberos-adm	749/tcp				# Kerberos `kadmin' (v5)
-#
-webster		765/tcp				# Network dictionary
-webster		765/udp
-#
-# From ``Assigned Numbers'':
-#
-#> The Registered Ports are not controlled by the IANA and on most systems
-#> can be used by ordinary user processes or programs executed by ordinary
-#> users.
-#
-#> Ports are used in the TCP [45,106] to name the ends of logical
-#> connections which carry long term conversations.  For the purpose of
-#> providing services to unknown callers, a service contact port is
-#> defined.  This list specifies the port used by the server process as its
-#> contact port.  While the IANA can not control uses of these ports it
-#> does register or list uses of these ports as a convienence to the
-#> community.
-#
-nfsdstatus	1110/tcp
-nfsd-keepalive	1110/udp
-
-ingreslock	1524/tcp
-ingreslock	1524/udp
-prospero-np	1525/tcp			# Prospero non-privileged
-prospero-np	1525/udp
-datametrics	1645/tcp	old-radius	# datametrics / old radius entry
-datametrics	1645/udp	old-radius	# datametrics / old radius entry
-sa-msg-port	1646/tcp	old-radacct	# sa-msg-port / old radacct entry
-sa-msg-port	1646/udp	old-radacct	# sa-msg-port / old radacct entry
-radius		1812/tcp			# Radius
-radius		1812/udp			# Radius
-radacct		1813/tcp			# Radius Accounting
-radacct		1813/udp			# Radius Accounting
-nfsd		2049/tcp	nfs
-nfsd		2049/udp	nfs
-cvspserver	2401/tcp			# CVS client/server operations
-cvspserver	2401/udp			# CVS client/server operations
-mysql		3306/tcp			# MySQL
-mysql		3306/udp			# MySQL
-rfe		5002/tcp			# Radio Free Ethernet
-rfe		5002/udp			# Actually uses UDP only
-cfengine	5308/tcp			# CFengine
-cfengine	5308/udp			# CFengine
-bbs		7000/tcp			# BBS service
-#
-#
-# Kerberos (Project Athena/MIT) services
-# Note that these are for Kerberos v4, and are unofficial.  Sites running
-# v4 should uncomment these and comment out the v5 entries above.
-#
-kerberos4	750/udp		kerberos-iv kdc	# Kerberos (server) udp
-kerberos4	750/tcp		kerberos-iv kdc	# Kerberos (server) tcp
-kerberos_master	751/udp				# Kerberos authentication
-kerberos_master	751/tcp				# Kerberos authentication
-passwd_server	752/udp				# Kerberos passwd server
-krb_prop	754/tcp				# Kerberos slave propagation
-krbupdate	760/tcp		kreg		# Kerberos registration
-kpasswd		761/tcp		kpwd		# Kerberos "passwd"
-kpop		1109/tcp			# Pop with Kerberos
-knetd		2053/tcp			# Kerberos de-multiplexor
-zephyr-srv	2102/udp			# Zephyr server
-zephyr-clt	2103/udp			# Zephyr serv-hm connection
-zephyr-hm	2104/udp			# Zephyr hostmanager
-eklogin		2105/tcp			# Kerberos encrypted rlogin
-#
-# Unofficial but necessary (for NetBSD) services
-#
-supfilesrv	871/tcp				# SUP server
-supfiledbg	1127/tcp			# SUP debugging
-#
-# Datagram Delivery Protocol services
-#
-rtmp		1/ddp				# Routing Table Maintenance Protocol
-nbp		2/ddp				# Name Binding Protocol
-echo		4/ddp				# AppleTalk Echo Protocol
-zip		6/ddp				# Zone Information Protocol
-#
-# Services added for the Debian GNU/Linux distribution
-poppassd	106/tcp				# Eudora
-poppassd	106/udp				# Eudora
-mailq		174/tcp				# Mailer transport queue for Zmailer
-mailq		174/tcp				# Mailer transport queue for Zmailer
-omirr		808/tcp		omirrd		# online mirror
-omirr		808/udp		omirrd		# online mirror
-rmtcfg		1236/tcp			# Gracilis Packeten remote config server
-xtel		1313/tcp			# french minitel
-coda_opcons	1355/udp			# Coda opcons            (Coda fs)
-coda_venus	1363/udp			# Coda venus             (Coda fs)
-coda_auth	1357/udp			# Coda auth              (Coda fs)
-coda_udpsrv	1359/udp			# Coda udpsrv            (Coda fs)
-coda_filesrv	1361/udp			# Coda filesrv           (Coda fs)
-codacon		1423/tcp	venus.cmu	# Coda Console           (Coda fs)
-coda_aux1	1431/tcp			# coda auxiliary service (Coda fs)
-coda_aux1	1431/udp			# coda auxiliary service (Coda fs)
-coda_aux2	1433/tcp			# coda auxiliary service (Coda fs)
-coda_aux2	1433/udp			# coda auxiliary service (Coda fs)
-coda_aux3	1435/tcp			# coda auxiliary service (Coda fs)
-coda_aux3	1435/udp			# coda auxiliary service (Coda fs)
-cfinger		2003/tcp			# GNU Finger
-afbackup	2988/tcp			# Afbackup system
-afbackup	2988/udp			# Afbackup system
-icp		3130/tcp			# Internet Cache Protocol (Squid)
-icp		3130/udp			# Internet Cache Protocol (Squid)
-postgres	5432/tcp			# POSTGRES
-postgres	5432/udp			# POSTGRES
-fax		4557/tcp			# FAX transmission service        (old)
-hylafax		4559/tcp			# HylaFAX client-server protocol  (new)
-noclog		5354/tcp			# noclogd with TCP (nocol)
-noclog		5354/udp			# noclogd with UDP (nocol)
-hostmon		5355/tcp			# hostmon uses TCP (nocol)
-hostmon		5355/udp			# hostmon uses TCP (nocol)
-ircd		6667/tcp			# Internet Relay Chat
-ircd		6667/udp			# Internet Relay Chat
-webcache	8080/tcp			# WWW caching service
-webcache	8080/udp			# WWW caching service
-tproxy		8081/tcp			# Transparent Proxy
-tproxy		8081/udp			# Transparent Proxy
-mandelspawn	9359/udp	mandelbrot	# network mandelbrot
-amanda		10080/udp			# amanda backup services
-amandaidx	10082/tcp			# amanda backup services
-amidxtape	10083/tcp			# amanda backup services
-isdnlog		20011/tcp			# isdn logging system
-isdnlog		20011/udp			# isdn logging system
-vboxd		20012/tcp			# voice box system
-vboxd		20012/udp			# voice box system
-binkp           24554/tcp			# Binkley
-binkp           24554/udp			# Binkley
-asp		27374/tcp			# Address Search Protocol
-asp		27374/udp			# Address Search Protocol
-tfido           60177/tcp			# Ifmail
-tfido           60177/udp			# Ifmail
-fido            60179/tcp			# Ifmail
-fido            60179/udp			# Ifmail
-
-# Local services
-
diff --git a/target/device/Atmel/root/target_skeleton/etc/shadow b/target/device/Atmel/root/target_skeleton/etc/shadow
deleted file mode 100644
index 4941a1a..0000000
--- a/target/device/Atmel/root/target_skeleton/etc/shadow
+++ /dev/null
@@ -1,12 +0,0 @@
-root::10933:0:99999:7:::
-bin:*:10933:0:99999:7:::
-daemon:*:10933:0:99999:7:::
-adm:*:10933:0:99999:7:::
-lp:*:10933:0:99999:7:::
-sync:*:10933:0:99999:7:::
-shutdown:*:10933:0:99999:7:::
-halt:*:10933:0:99999:7:::
-uucp:*:10933:0:99999:7:::
-operator:*:10933:0:99999:7:::
-nobody:*:10933:0:99999:7:::
-default::10933:0:99999:7:::
diff --git a/target/device/Atmel/root/target_skeleton/home/.empty b/target/device/Atmel/root/target_skeleton/home/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/lib/.empty b/target/device/Atmel/root/target_skeleton/lib/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/mnt/.empty b/target/device/Atmel/root/target_skeleton/mnt/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/opt/.empty b/target/device/Atmel/root/target_skeleton/opt/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/proc/.empty b/target/device/Atmel/root/target_skeleton/proc/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/root/.bash_history b/target/device/Atmel/root/target_skeleton/root/.bash_history
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/root/.bash_logout b/target/device/Atmel/root/target_skeleton/root/.bash_logout
deleted file mode 100644
index 77ef1f9..0000000
--- a/target/device/Atmel/root/target_skeleton/root/.bash_logout
+++ /dev/null
@@ -1,7 +0,0 @@
-# ~/.bash_logout: executed by bash(1) when login shell exits.
-
-# when leaving the console clear the screen to increase privacy
-
-case "`tty`" in
-    /dev/tty[0-9]*) clear
-esac
diff --git a/target/device/Atmel/root/target_skeleton/root/.bash_profile b/target/device/Atmel/root/target_skeleton/root/.bash_profile
deleted file mode 100644
index 27bf149..0000000
--- a/target/device/Atmel/root/target_skeleton/root/.bash_profile
+++ /dev/null
@@ -1,15 +0,0 @@
-# .bash_profile
-
-export PATH=\
-/bin:\
-/sbin:\
-/usr/bin:\
-/usr/sbin:\
-/usr/bin/X11:\
-/usr/local/bin
-
-umask 022
-
-if [ -f ~/.bashrc ]; then
-    source ~/.bashrc
-fi
diff --git a/target/device/Atmel/root/target_skeleton/root/.bashrc b/target/device/Atmel/root/target_skeleton/root/.bashrc
deleted file mode 100644
index d13c8f9..0000000
--- a/target/device/Atmel/root/target_skeleton/root/.bashrc
+++ /dev/null
@@ -1,48 +0,0 @@
-# ~/.bashrc: executed by bash(1) for non-login interactive shells.
-
-export PATH=\
-/bin:\
-/sbin:\
-/usr/bin:\
-/usr/sbin:\
-/usr/bin/X11:\
-/usr/local/bin
-
-# If running interactively, then:
-if [ "$PS1" ]; then
-
-    if [ "$BASH" ]; then
-	export PS1="[\u@\h \W]\\$ "
-    else
-      if [ "`id -u`" -eq 0 ]; then 
-	export PS1='# '
-      else
-	export PS1='$ '
-      fi
-    fi
-
-    export USER=`id -un`
-    export LOGNAME=$USER
-    export HOSTNAME=`/bin/hostname`
-    export HISTSIZE=1000
-    export HISTFILESIZE=1000
-    export PAGER='/bin/more '
-    export EDITOR='/bin/vi'
-    export INPUTRC=/etc/inputrc
-    export DMALLOC_OPTIONS=debug=0x34f47d83,inter=100,log=logfile
-    export LS_COLORS='no=00:fi=00:di=01;34:ln=01;36:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.bz2=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.jpg=01;35:*.jpeg=01;35:*.png=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.mpg=01;35:*.mpeg=01;35:*.avi=01;35:*.fli=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:';
-
-    ### Some aliases
-    alias ps2='ps facux '
-    alias ps1='ps faxo "%U %t %p %a" '
-    alias af='ps af'
-    alias cls='clear'
-    alias ll='/bin/ls --color=tty -laFh'
-    alias ls='/bin/ls --color=tty -F'
-    alias df='df -h'
-    alias indent='indent -bad -bap -bbo -nbc -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli0 -cp33 -cs -d0 -di1 -nfc1 -nfca -hnl -i4 -ip0 -l75 -lp -npcs -npsl -nsc -nsob -nss -ts4 '
-    #alias bc='bc -l'
-    alias minicom='minicom -c on'
-    alias calc='calc -Cd '
-    alias bc='calc -Cd '
-fi;
diff --git a/target/device/Atmel/root/target_skeleton/root/.empty b/target/device/Atmel/root/target_skeleton/root/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/sbin/.empty b/target/device/Atmel/root/target_skeleton/sbin/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/sys/.empty b/target/device/Atmel/root/target_skeleton/sys/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/tmp/.empty b/target/device/Atmel/root/target_skeleton/tmp/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/bin/.empty b/target/device/Atmel/root/target_skeleton/usr/bin/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/include/.empty b/target/device/Atmel/root/target_skeleton/usr/include/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/lib/.empty b/target/device/Atmel/root/target_skeleton/usr/lib/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/man/.empty b/target/device/Atmel/root/target_skeleton/usr/man/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/sbin/.empty b/target/device/Atmel/root/target_skeleton/usr/sbin/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/usr/share/udhcpc/default.script b/target/device/Atmel/root/target_skeleton/usr/share/udhcpc/default.script
deleted file mode 100755
index a52a7f8..0000000
--- a/target/device/Atmel/root/target_skeleton/usr/share/udhcpc/default.script
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-
-# udhcpc script edited by Tim Riker <Tim at Rikers.org>
-
-[ -z "$1" ] && echo "Error: should be called from udhcpc" && exit 1
-
-RESOLV_CONF="/etc/resolv.conf"
-[ -n "$broadcast" ] && BROADCAST="broadcast $broadcast"
-[ -n "$subnet" ] && NETMASK="netmask $subnet"
-
-case "$1" in
-	deconfig)
-		/sbin/ifconfig $interface 0.0.0.0
-		;;
-
-	renew|bound)
-		/sbin/ifconfig $interface $ip $BROADCAST $NETMASK
-
-		if [ -n "$router" ] ; then
-			echo "deleting routers"
-			while route del default gw 0.0.0.0 dev $interface ; do
-				:
-			done
-
-			for i in $router ; do
-				route add default gw $i dev $interface
-			done
-		fi
-
-		echo -n > $RESOLV_CONF
-		[ -n "$domain" ] && echo search $domain >> $RESOLV_CONF
-		for i in $dns ; do
-			echo adding dns $i
-			echo nameserver $i >> $RESOLV_CONF
-		done
-		;;
-esac
-
-exit 0
diff --git a/target/device/Atmel/root/target_skeleton/usr/src/.empty b/target/device/Atmel/root/target_skeleton/usr/src/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/cache/.empty b/target/device/Atmel/root/target_skeleton/var/cache/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/lib/pcmcia/.empty b/target/device/Atmel/root/target_skeleton/var/lib/pcmcia/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/lock/.empty b/target/device/Atmel/root/target_skeleton/var/lock/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/log/.empty b/target/device/Atmel/root/target_skeleton/var/log/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/pcmcia/.empty b/target/device/Atmel/root/target_skeleton/var/pcmcia/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/run/.empty b/target/device/Atmel/root/target_skeleton/var/run/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/spool/.empty b/target/device/Atmel/root/target_skeleton/var/spool/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/target_skeleton/var/tmp/.empty b/target/device/Atmel/root/target_skeleton/var/tmp/.empty
deleted file mode 100644
index e69de29..0000000
diff --git a/target/device/Atmel/root/uClibc.config b/target/device/Atmel/root/uClibc.config
deleted file mode 100644
index aec16bf..0000000
--- a/target/device/Atmel/root/uClibc.config
+++ /dev/null
@@ -1,167 +0,0 @@
-#
-# Automatically generated make config: don't edit
-#
-# TARGET_alpha is not set
-TARGET_arm=y
-# TARGET_bfin is not set
-# TARGET_cris is not set
-# TARGET_e1 is not set
-# TARGET_frv is not set
-# TARGET_h8300 is not set
-# TARGET_i386 is not set
-# TARGET_i960 is not set
-# TARGET_m68k is not set
-# TARGET_microblaze is not set
-# TARGET_mips is not set
-# TARGET_nios is not set
-# TARGET_nios2 is not set
-# TARGET_powerpc is not set
-# TARGET_sh is not set
-# TARGET_sh64 is not set
-# TARGET_sparc is not set
-# TARGET_v850 is not set
-# TARGET_x86_64 is not set
-
-#
-# Target Architecture Features and Options
-#
-HAVE_ELF=y
-ARCH_SUPPORTS_LITTLE_ENDIAN=y
-TARGET_ARCH="arm"
-ARCH_SUPPORTS_BIG_ENDIAN=y
-CONFIG_GENERIC_ARM=y
-# CONFIG_ARM610 is not set
-# CONFIG_ARM710 is not set
-# CONFIG_ARM720T is not set
-# CONFIG_ARM920T is not set
-# CONFIG_ARM922T is not set
-# CONFIG_ARM926T is not set
-# CONFIG_ARM1136JF_S is not set
-# CONFIG_ARM_SA110 is not set
-# CONFIG_ARM_SA1100 is not set
-# CONFIG_ARM_XSCALE is not set
-ARCH_LITTLE_ENDIAN=y
-# ARCH_BIG_ENDIAN is not set
-# ARCH_HAS_NO_MMU is not set
-ARCH_HAS_MMU=y
-UCLIBC_HAS_FLOATS=y
-HAS_FPU=y
-DO_C99_MATH=y
-KERNEL_SOURCE="/home/ulf/projects/AT91RM9200/buildroot/toolchain_build_arm/linux"
-C_SYMBOL_PREFIX=""
-HAVE_DOT_CONFIG=y
-
-#
-# General Library Settings
-#
-# HAVE_NO_PIC is not set
-DOPIC=y
-# HAVE_NO_SHARED is not set
-HAVE_SHARED=y
-# ARCH_HAS_NO_LDSO is not set
-BUILD_UCLIBC_LDSO=y
-# FORCE_SHAREABLE_TEXT_SEGMENTS is not set
-LDSO_LDD_SUPPORT=y
-LDSO_CACHE_SUPPORT=y
-# LDSO_PRELOAD_FILE_SUPPORT is not set
-LDSO_BASE_FILENAME="ld.so"
-# LDSO_RUNPATH is not set
-# DL_FINI_CRT_COMPAT is not set
-UCLIBC_CTOR_DTOR=y
-# HAS_NO_THREADS is not set
-UCLIBC_HAS_THREADS=y
-PTHREADS_DEBUG_SUPPORT=y
-UCLIBC_HAS_LFS=y
-# UCLIBC_STATIC_LDCONFIG is not set
-# MALLOC is not set
-# MALLOC_SIMPLE is not set
-MALLOC_STANDARD=y
-MALLOC_GLIBC_COMPAT=y
-UCLIBC_DYNAMIC_ATEXIT=y
-HAS_SHADOW=y
-# UNIX98PTY_ONLY is not set
-ASSUME_DEVPTS=y
-UCLIBC_HAS_TM_EXTENSIONS=y
-UCLIBC_HAS_TZ_CACHING=y
-UCLIBC_HAS_TZ_FILE=y
-UCLIBC_HAS_TZ_FILE_READ_MANY=y
-UCLIBC_TZ_FILE_PATH="/etc/TZ"
-
-#
-# Networking Support
-#
-UCLIBC_HAS_IPV6=y
-UCLIBC_HAS_RPC=y
-UCLIBC_HAS_FULL_RPC=y
-
-#
-# String and Stdio Support
-#
-UCLIBC_HAS_STRING_GENERIC_OPT=y
-UCLIBC_HAS_STRING_ARCH_OPT=y
-UCLIBC_HAS_CTYPE_TABLES=y
-UCLIBC_HAS_CTYPE_SIGNED=y
-# UCLIBC_HAS_CTYPE_UNSAFE is not set
-UCLIBC_HAS_CTYPE_CHECKED=y
-# UCLIBC_HAS_CTYPE_ENFORCED is not set
-UCLIBC_HAS_WCHAR=y
-# UCLIBC_HAS_LOCALE is not set
-UCLIBC_HAS_HEXADECIMAL_FLOATS=y
-UCLIBC_HAS_GLIBC_CUSTOM_PRINTF=y
-UCLIBC_PRINTF_SCANF_POSITIONAL_ARGS=9
-UCLIBC_HAS_SCANF_GLIBC_A_FLAG=y
-# UCLIBC_HAS_STDIO_BUFSIZ_NONE is not set
-# UCLIBC_HAS_STDIO_BUFSIZ_256 is not set
-# UCLIBC_HAS_STDIO_BUFSIZ_512 is not set
-# UCLIBC_HAS_STDIO_BUFSIZ_1024 is not set
-# UCLIBC_HAS_STDIO_BUFSIZ_2048 is not set
-UCLIBC_HAS_STDIO_BUFSIZ_4096=y
-# UCLIBC_HAS_STDIO_BUFSIZ_8192 is not set
-UCLIBC_HAS_STDIO_BUILTIN_BUFFER_NONE=y
-# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_4 is not set
-# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_8 is not set
-# UCLIBC_HAS_STDIO_SHUTDOWN_ON_ABORT is not set
-UCLIBC_HAS_STDIO_GETC_MACRO=y
-UCLIBC_HAS_STDIO_PUTC_MACRO=y
-UCLIBC_HAS_STDIO_AUTO_RW_TRANSITION=y
-# UCLIBC_HAS_FOPEN_LARGEFILE_MODE is not set
-UCLIBC_HAS_FOPEN_EXCLUSIVE_MODE=y
-UCLIBC_HAS_GLIBC_CUSTOM_STREAMS=y
-UCLIBC_HAS_PRINTF_M_SPEC=y
-UCLIBC_HAS_ERRNO_MESSAGES=y
-# UCLIBC_HAS_SYS_ERRLIST is not set
-UCLIBC_HAS_SIGNUM_MESSAGES=y
-# UCLIBC_HAS_SYS_SIGLIST is not set
-UCLIBC_HAS_GNU_GETOPT=y
-
-#
-# Big and Tall
-#
-UCLIBC_HAS_REGEX=y
-# UCLIBC_HAS_WORDEXP is not set
-UCLIBC_HAS_FTW=y
-UCLIBC_HAS_GLOB=y
-
-#
-# Library Installation Options
-#
-SHARED_LIB_LOADER_PREFIX="/lib"
-RUNTIME_PREFIX="/"
-DEVEL_PREFIX="/usr/"
-
-#
-# uClibc security related options
-#
-# UCLIBC_SECURITY is not set
-
-#
-# uClibc development/debugging options
-#
-CROSS_COMPILER_PREFIX="/usr/local/arm/gcc-3.4.4-uclibc/bin/arm-linux-uclibc-"
-# DODEBUG is not set
-# DODEBUG_PT is not set
-# DOASSERTS is not set
-# SUPPORT_LD_DEBUG is not set
-# SUPPORT_LD_DEBUG_EARLY is not set
-WARNINGS="-Wall"
-# UCLIBC_MJN3_ONLY is not set
-- 
1.7.0.4

